nios_system |

2016.12.22.10:06:15 | Datasheet

Overview

clk_0 | nios_system

Processor
nios2_processor Nios II 13.0
All Components
nios2_processor altera_nios2_qsys 13.0
onchip_memory altera_avalon_onchip_memory2 13.0.1.99.2
jtag_uart altera_avalon_jtag_uart 13.0.1.99.2
LEDs altera_avalon_pio 13.0.1.99.2
LEDRs altera_avalon_pio 13.0.1.99.2
switches altera_avalon_pio 13.0.1.99.2
push_switches altera_avalon_pio 13.0.1.99.2
hex0 altera_avalon_pio 13.0.1.99.2
hex1 altera_avalon_pio 13.0.1.99.2
hex2 altera_avalon_pio 13.0.1.99.2
hex3 altera_avalon_pio 13.0.1.99.2
hex4 altera_avalon_pio 13.0.1.99.2
hex5 altera_avalon_pio 13.0.1.99.2
hex6 altera_avalon_pio 13.0.1.99.2
hex7 altera_avalon_pio 13.0.1.99.2
lcd_16207_0 altera_avalon_lcd_16207 13.0.1.99.2
lcd_on altera_avalon_pio 13.0.1.99.2
lcd_blon altera_avalon_pio 13.0.1.99.2
Memory Map

| nios2_processor
data_master | instruction_master
nios2_processor |  |
jtag_debug_module | 0x00040800 | 0x00040800
onchip_memory |  |
s1 | 0x00000000 | 0x00000000
jtag_uart |  |
avalon_jtag_slave | 0x00041100 |
LEDs |  |
s1 | 0x000410f0 |
LEDRs |  |
s1 | 0x000410e0 |
switches |  |
s1 | 0x000410d0 |
push_switches |  |
s1 | 0x000410c0 |
hex0 |  |
s1 | 0x000410b0 |
hex1 |  |
s1 | 0x000410a0 |
hex2 |  |
s1 | 0x00041090 |
hex3 |  |
s1 | 0x00041080 |
hex4 |  |
s1 | 0x00041070 |
hex5 |  |
s1 | 0x00041060 |
hex6 |  |
s1 | 0x00041050 |
hex7 |  |
s1 | 0x00041040 |
lcd_16207_0 |  |
control_slave | 0x00041030 |
lcd_on |  |
s1 | 0x00041010 |
lcd_blon |  |
s1 | 0x00041020 |

## clk_0

clock_source v13.0

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## nios2_processor

altera_nios2_qsys v13.0

clk_0 | clk | nios2_processor
clk
clk_reset
reset_n
|  | jtag_debug_module_reset | onchip_memory
|  | reset1
|  | instruction_master
|  | s1
|  | data_master
|  | s1
|  | jtag_debug_module_reset | jtag_uart
|  | reset
|  | d_irq
|  | irq
|  | data_master
|  | avalon_jtag_slave
|  | jtag_debug_module_reset | LEDs
|  | reset
|  | data_master
|  | s1
|  | data_master | LEDRs
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | jtag_debug_module_reset | switches
|  | reset
|  | data_master
|  | s1
|  | data_master | push_switches
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | hex0
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | hex1
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | hex2
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | hex3
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | hex4
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | hex5
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | hex6
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | data_master | hex7
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | jtag_debug_module_reset | lcd_16207_0
|  | reset
|  | data_master
|  | control_slave
|  | data_master | lcd_on
|  | s1
|  | jtag_debug_module_reset
|  | reset
|  | jtag_debug_module_reset | lcd_blon
|  | reset
|  | data_master
|  | s1

## Parameters

setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_export_large_RAMs | false
setting_asic_enabled | false
setting_asic_synopsys_translate_on_off | false
setting_oci_export_jtag_signals | false
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
muldiv_divider | false
mpu_useLimit | false
mpu_enabled | false
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
manuallyAssignCpuID | true
debug_triggerArming | true
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
dcache_omitDataMaster | false
cpuReset | false
is_hardcopy_compatible | false
setting_shadowRegisterSets | 0
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mmu_TLBMissExcOffset | 0
debug_jtagInstanceID | 0
resetOffset | 0
exceptionOffset | 32
cpuID | 0
cpuID_stored | 0
breakOffset | 32
userDefinedSettings |
resetSlave | onchip_memory.s1
mmu_TLBMissExcSlave | None
exceptionSlave | onchip_memory.s1
breakSlave | nios2_processor.jtag_debug_module
setting_perfCounterWidth | 32
setting_interruptControllerType | Internal
setting_branchPredictionType | Automatic
setting_bhtPtrSz | 8
muldiv_multiplierType | EmbeddedMulFast
mpu_minInstRegionSize | 12
mpu_minDataRegionSize | 12
mmu_uitlbNumEntries | 4
mmu_udtlbNumEntries | 6
mmu_tlbPtrSz | 7
mmu_tlbNumWays | 16
mmu_processIDNumBits | 8
impl | Tiny
icache_size | 4096
icache_tagramBlockType | Automatic
icache_ramBlockType | Automatic
icache_numTCIM | 0
icache_burstType | None
dcache_bursts | false
dcache_victim_buf_impl | ram
debug_level | Level1
debug_OCIOnchipTrace | _128
dcache_size | 2048
dcache_tagramBlockType | Automatic
dcache_ramBlockType | Automatic
dcache_numTCDM | 0
dcache_lineSize | 32
setting_exportvectors | false
setting_ecc_present | false
regfile_ramBlockType | Automatic
ocimem_ramBlockType | Automatic
mmu_ramBlockType | Automatic
bht_ramBlockType | Automatic
resetAbsoluteAddr | 0
exceptionAbsoluteAddr | 32
breakAbsoluteAddr | 264224
mmu_TLBMissExcAbsAddr | 0
dcache_bursts_derived | false
dcache_size_derived | 2048
dcache_lineSize_derived | 32
translate_on | "synthesis translate_on"
translate_off | "synthesis translate_off"
instAddrWidth | 19
dataAddrWidth | 19
tightlyCoupledDataMaster0AddrWidth | 1
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster3AddrWidth | 1
instSlaveMapParam | <address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='nios2_processor.jtag_debug_module' start='0x40800' end='0x41000' /></address-map>

dataSlaveMapParam

<address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='nios2_processor.jtag_debug_module' start='0x40800' end='0x41000' /><slave name='lcd_on.s1' start='0x41010' end='0x41020' /><slave name='lcd_blon.s1' start='0x41020' end='0x41030' /><slave name='lcd_16207_0.control_slave' start='0x41030' end='0x41040' /><slave name='hex7.s1' start='0x41040' end='0x41050' /><slave name='hex6.s1' start='0x41050' end='0x41060' /><slave name='hex5.s1' start='0x41060' end='0x41070' /><slave name='hex4.s1' start='0x41070' end='0x41080' /><slave name='hex3.s1' start='0x41080' end='0x41090' /><slave name='hex2.s1' start='0x41090' end='0x410A0' /><slave name='hex1.s1' start='0x410A0' end='0x410B0' /><slave name='hex0.s1' start='0x410B0' end='0x410C0' /><slave name='push_switches.s1' start='0x410C0' end='0x410D0' /><slave name='switches.s1' start='0x410D0' end='0x410E0' /><slave name='LEDRs.s1' start='0x410E0' end='0x410F0' /><slave name='LEDs.s1' start='0x410F0' end='0x41100' /><slave name='jtag_uart.avalon_jtag_slave' start='0x41100' end='0x41108' /></address-map>

clockFrequency | 50000000
deviceFamilyName | CYCLONEIVE
internalIrqMaskSystemInfo | 32
customInstSlavesSystemInfo | <info/>

deviceFeaturesSystemInfo

ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1

tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster3MapParam |
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster3MapParam |
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIG_ENDIAN | 0
BREAK_ADDR | 0x00040820
CPU_FREQ | 50000000u
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x00000000
CPU_IMPLEMENTATION | "tiny"
DATA_ADDR_WIDTH | 19
DCACHE_LINE_SIZE | 0
DCACHE_LINE_SIZE_LOG2 | 0
DCACHE_SIZE | 0
EXCEPTION_ADDR | 0x00000020
FLUSHDA_SUPPORTED |
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 0
HARDWARE_MULX_PRESENT | 0
HAS_DEBUG_CORE | 1
HAS_DEBUG_STUB |
HAS_JMPI_INSTRUCTION |
ICACHE_LINE_SIZE | 0
ICACHE_LINE_SIZE_LOG2 | 0
ICACHE_SIZE | 0
INST_ADDR_WIDTH | 19
RESET_ADDR | 0x00000000

## onchip_memory

altera_avalon_onchip_memory2 v13.0.1.99.2

clk_0 | clk | onchip_memory
clk1
clk_reset
reset1
nios2_processor | jtag_debug_module_reset
reset1
instruction_master
s1
data_master
s1

## Parameters

allowInSystemMemoryContentEditor | false
blockType | AUTO
dataWidth | 32
dualPort | false
initMemContent | true
initializationFileName | onchip_mem.hex
instanceID | NONE
memorySize | 204800
readDuringWriteMode | DONT_CARE
simAllowMRAMContentsFile | false
simMemInitOnlyFilename | 0
singleClockOperation | false
slave1Latency | 1
slave2Latency | 1
useNonDefaultInitFile | false
useShallowMemBlocks | false
writable | true
autoInitializationFileName | nios_system_onchip_memory
deviceFamily | CYCLONEIVE

deviceFeatures

ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1

derived_set_addr_width | 16
derived_gui_ram_block_type | Automatic
derived_is_hardcopy | false
derived_init_file_name | nios_system_onchip_memory.hex
generateLegacySim | false

## Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | nios_system_onchip_memory
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 204800
WRITABLE | 1

## jtag_uart

altera_avalon_jtag_uart v13.0.1.99.2

nios2_processor | jtag_debug_module_reset | jtag_uart
reset
d_irq
irq
data_master
avalon_jtag_slave
clk_0 | clk_reset
reset
clk
clk

## Parameters

allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | NO_INTERACTIVE_WINDOWS
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
avalonSpec | 2.0
legacySignalAllow | false
enableInteractiveInput | false
enableInteractiveOutput | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

READ_DEPTH | 64
READ_THRESHOLD | 8
WRITE_DEPTH | 64
WRITE_THRESHOLD | 8

## LEDs

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | LEDs
clk
clk_reset
reset
nios2_processor | jtag_debug_module_reset
reset
data_master
s1

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 8
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 8
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## LEDRs

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | LEDRs
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 18
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 18
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## switches

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | switches
clk
clk_reset
reset
nios2_processor | jtag_debug_module_reset
reset
data_master
s1

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 18
clockRate | 50000000
derived_has_tri | false
derived_has_out | false
derived_has_in | true
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 18
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## push_switches

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | push_switches
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 3
clockRate | 50000000
derived_has_tri | false
derived_has_out | false
derived_has_in | true
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 3
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## hex0

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | hex0
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 7
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 7
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## hex1

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | hex1
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 7
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 7
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## hex2

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | hex2
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 7
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 7
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## hex3

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | hex3
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 7
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 7
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## hex4

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | hex4
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 7
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 7
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## hex5

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | hex5
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 7
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 7
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## hex6

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | hex6
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 7
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 7
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## hex7

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | hex7
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 7
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 7
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## lcd_16207_0

altera_avalon_lcd_16207 v13.0.1.99.2

clk_0 | clk | lcd_16207_0
clk
clk_reset
reset
nios2_processor | jtag_debug_module_reset
reset
data_master
control_slave

## Parameters

deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## lcd_on

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | lcd_on
clk
clk_reset
reset
nios2_processor | data_master
s1
jtag_debug_module_reset
reset

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 1
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## lcd_blon

altera_avalon_pio v13.0.1.99.2

clk_0 | clk | lcd_blon
clk
clk_reset
reset
nios2_processor | jtag_debug_module_reset
reset
data_master
s1

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
clockRate | 50000000
derived_has_tri | false
derived_has_out | true
derived_has_in | false
derived_do_test_bench_wiring | false
derived_capture | false
derived_edge_type | NONE
derived_irq_type | NONE
derived_has_irq | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 1
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 0
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

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