
qsys_tutorial_switchs18.elf:     file format elf32-littlenios2
qsys_tutorial_switchs18.elf
architecture: nios2, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00000020

Program Header:
    LOAD off    0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12
         filesz 0x00000020 memsz 0x00000020 flags r-x
    LOAD off    0x00001020 vaddr 0x00000020 paddr 0x00000020 align 2**12
         filesz 0x00000144 memsz 0x00000144 flags r-x
    LOAD off    0x00001164 vaddr 0x00000164 paddr 0x00000168 align 2**12
         filesz 0x00000004 memsz 0x00000004 flags rw-
    LOAD off    0x0000116c vaddr 0x0000016c paddr 0x0000016c align 2**12
         filesz 0x00000000 memsz 0x0000000c flags rw-

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .entry        00000020  00000000  00000000  00001000  2**5
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .text         00000144  00000020  00000020  00001020  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rwdata       00000004  00000164  00000168  00001164  2**2
                  CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
  3 .bss          0000000c  0000016c  0000016c  0000116c  2**2
                  ALLOC, SMALL_DATA
  4 .comment      00000026  00000000  00000000  00001168  2**0
                  CONTENTS, READONLY
  5 .debug_aranges 00000108  00000000  00000000  00001190  2**3
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_pubnames 00000149  00000000  00000000  00001298  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_info   000006b7  00000000  00000000  000013e1  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_abbrev 00000398  00000000  00000000  00001a98  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_line   00000dd4  00000000  00000000  00001e30  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_frame  00000118  00000000  00000000  00002c04  2**2
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_str    000003f0  00000000  00000000  00002d1c  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_loc    00000070  00000000  00000000  0000310c  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_alt_sim_info 00000010  00000000  00000000  0000317c  2**2
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_ranges 00000020  00000000  00000000  00003190  2**3
                  CONTENTS, READONLY, DEBUGGING
 15 .thread_model 00000003  00000000  00000000  00003dc7  2**0
                  CONTENTS, READONLY
 16 .cpu          0000000f  00000000  00000000  00003dca  2**0
                  CONTENTS, READONLY
 17 .qsys         00000001  00000000  00000000  00003dd9  2**0
                  CONTENTS, READONLY
 18 .simulation_enabled 00000001  00000000  00000000  00003dda  2**0
                  CONTENTS, READONLY
 19 .stderr_dev   00000009  00000000  00000000  00003ddb  2**0
                  CONTENTS, READONLY
 20 .stdin_dev    00000009  00000000  00000000  00003de4  2**0
                  CONTENTS, READONLY
 21 .stdout_dev   00000009  00000000  00000000  00003ded  2**0
                  CONTENTS, READONLY
 22 .sopc_system_name 0000000b  00000000  00000000  00003df6  2**0
                  CONTENTS, READONLY
 23 .quartus_project_dir 00000030  00000000  00000000  00003e01  2**0
                  CONTENTS, READONLY
 24 .sopcinfo     00037346  00000000  00000000  00003e31  2**0
                  CONTENTS, READONLY
SYMBOL TABLE:
00000000 l    d  .entry	00000000 .entry
00000020 l    d  .text	00000000 .text
00000164 l    d  .rwdata	00000000 .rwdata
0000016c l    d  .bss	00000000 .bss
00000000 l    d  .comment	00000000 .comment
00000000 l    d  .debug_aranges	00000000 .debug_aranges
00000000 l    d  .debug_pubnames	00000000 .debug_pubnames
00000000 l    d  .debug_info	00000000 .debug_info
00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
00000000 l    d  .debug_line	00000000 .debug_line
00000000 l    d  .debug_frame	00000000 .debug_frame
00000000 l    d  .debug_str	00000000 .debug_str
00000000 l    d  .debug_loc	00000000 .debug_loc
00000000 l    d  .debug_alt_sim_info	00000000 .debug_alt_sim_info
00000000 l    d  .debug_ranges	00000000 .debug_ranges
00000058 l       .text	00000000 alt_after_alt_main
00000000 l    df *ABS*	00000000 hello_world_small.c
00000000 l    df *ABS*	00000000 alt_load.c
00000078 l     F .text	00000020 alt_load_section
00000000 l    df *ABS*	00000000 alt_main.c
00000000 l    df *ABS*	00000000 alt_sys_init.c
00000000 l    df *ABS*	00000000 alt_dcache_flush_all.c
00000000 l    df *ABS*	00000000 alt_icache_flush_all.c
00000000 l    df *ABS*	00000000 altera_nios2_qsys_irq.c
00000104 g     F .text	0000002c alt_main
00000168 g       *ABS*	00000000 __flash_rwdata_start
00000164 g     O .rwdata	00000004 jtag_uart
00000000 g     F .entry	0000000c __reset
00000020 g       *ABS*	00000000 __flash_exceptions_start
00000170 g     O .bss	00000004 alt_argv
00008164 g       *ABS*	00000000 _gp
00000178 g       *ABS*	00000000 __bss_end
00000154 g     F .text	00000004 alt_dcache_flush_all
00000168 g       *ABS*	00000000 __ram_rwdata_end
00000000 g       *ABS*	00000000 __alt_mem_onchip_memory
00000164 g       *ABS*	00000000 __ram_rodata_end
00000178 g       *ABS*	00000000 end
00001000 g       *ABS*	00000000 __alt_stack_pointer
00000020 g     F .text	0000003c _start
00000130 g     F .text	00000004 alt_sys_init
00000164 g       *ABS*	00000000 __ram_rwdata_start
00000164 g       *ABS*	00000000 __ram_rodata_start
00000178 g       *ABS*	00000000 __alt_stack_base
0000016c g       *ABS*	00000000 __bss_start
0000005c g     F .text	0000001c main
00000174 g     O .bss	00000004 alt_envp
00000164 g       *ABS*	00000000 __flash_rodata_start
00000134 g     F .text	00000020 alt_irq_init
0000016c g     O .bss	00000004 alt_argc
00000020 g       *ABS*	00000000 __ram_exceptions_start
00000168 g       *ABS*	00000000 _edata
00000178 g       *ABS*	00000000 _end
00000020 g       *ABS*	00000000 __ram_exceptions_end
0000015c g     F .text	00000008 altera_nios2_qsys_irq_init
0000000c g       .entry	00000000 exit
00001000 g       *ABS*	00000000 __alt_data_end
0000000c g       .entry	00000000 _exit
00000158 g     F .text	00000004 alt_icache_flush_all
00000098 g     F .text	0000006c alt_load



Disassembly of section .entry:

00000000 <__reset>:
 * Jump to the _start entry point in the .text section if reset code
 * is allowed or if optimizing for RTL simulation.
 */
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
    /* Jump to the _start entry point in the .text section. */
    movhi r1, %hi(_start)
   0:	00400034 	movhi	at,0
    ori r1, r1, %lo(_start)
   4:	08400814 	ori	at,at,32
    jmp r1
   8:	0800683a 	jmp	at

0000000c <_exit>:
	...

Disassembly of section .text:

00000020 <_start>:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0)    
    /*
     * Now that the caches are initialized, set up the stack pointer.
     * The value provided by the linker is assumed to be correctly aligned.
     */
    movhi sp, %hi(__alt_stack_pointer)
  20:	06c00034 	movhi	sp,0
    ori sp, sp, %lo(__alt_stack_pointer)
  24:	dec40014 	ori	sp,sp,4096

    /* Set up the global pointer. */
    movhi gp, %hi(_gp)
  28:	06800034 	movhi	gp,0
    ori gp, gp, %lo(_gp)
  2c:	d6a05914 	ori	gp,gp,33124
 */
#ifndef ALT_SIM_OPTIMIZE
    /* Log that the BSS is about to be cleared. */
    ALT_LOG_PUTS(alt_log_msg_bss)

    movhi r2, %hi(__bss_start)
  30:	00800034 	movhi	r2,0
    ori r2, r2, %lo(__bss_start)
  34:	10805b14 	ori	r2,r2,364

    movhi r3, %hi(__bss_end)
  38:	00c00034 	movhi	r3,0
    ori r3, r3, %lo(__bss_end)
  3c:	18c05e14 	ori	r3,r3,376

    beq r2, r3, 1f
  40:	10c00326 	beq	r2,r3,50 <_start+0x30>

0:
    stw zero, (r2)
  44:	10000015 	stw	zero,0(r2)
    addi r2, r2, 4
  48:	10800104 	addi	r2,r2,4
    bltu r2, r3, 0b
  4c:	10fffd36 	bltu	r2,r3,44 <_start+0x24>
     * section aren't defined until alt_load() has been called).
     */
    mov   et, zero
#endif

    call alt_load
  50:	00000980 	call	98 <alt_load>

    /* Log that alt_main is about to be called. */
    ALT_LOG_PUTS(alt_log_msg_alt_main)

    /* Call the C entry point. It should never return. */
    call alt_main
  54:	00001040 	call	104 <alt_main>

00000058 <alt_after_alt_main>:

    /* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
    br alt_after_alt_main
  58:	003fff06 	br	58 <alt_after_alt_main>

0000005c <main>:
	int data;
	switches_t sw;
} sw_t;

void main()
{
  5c:	01080004 	movi	r4,8192
  60:	00c80404 	movi	r3,8208
	while(1) {
		sw_t s;
		s.data = *switches;
  64:	20800017 	ldw	r2,0(r4)
		*ledrs = s.sw.code;
  68:	1004d2ba 	srli	r2,r2,10
  6c:	10803fcc 	andi	r2,r2,255
  70:	18800015 	stw	r2,0(r3)
  74:	003ffb06 	br	64 <main+0x8>

00000078 <alt_load_section>:

static void ALT_INLINE alt_load_section (alt_u32* from, 
                                         alt_u32* to, 
                                         alt_u32* end)
{
  if (to != from)
  78:	2900051e 	bne	r5,r4,90 <alt_load_section+0x18>
  7c:	f800283a 	ret
  {
    while( to != end )
    {
      *to++ = *from++;
  80:	20800017 	ldw	r2,0(r4)
  84:	21000104 	addi	r4,r4,4
  88:	28800015 	stw	r2,0(r5)
  8c:	29400104 	addi	r5,r5,4
                                         alt_u32* to, 
                                         alt_u32* end)
{
  if (to != from)
  {
    while( to != end )
  90:	29bffb1e 	bne	r5,r6,80 <alt_load_section+0x8>
  94:	f800283a 	ret

00000098 <alt_load>:
 * there is no bootloader, so this application is responsible for loading to
 * RAM any sections that are required.
 */  

void alt_load (void)
{
  98:	deffff04 	addi	sp,sp,-4
  /* 
   * Copy the .rwdata section. 
   */

  alt_load_section (&__flash_rwdata_start, 
  9c:	01000034 	movhi	r4,0
  a0:	21005a04 	addi	r4,r4,360
  a4:	01400034 	movhi	r5,0
  a8:	29405904 	addi	r5,r5,356
  ac:	01800034 	movhi	r6,0
  b0:	31805a04 	addi	r6,r6,360
 * there is no bootloader, so this application is responsible for loading to
 * RAM any sections that are required.
 */  

void alt_load (void)
{
  b4:	dfc00015 	stw	ra,0(sp)
  /* 
   * Copy the .rwdata section. 
   */

  alt_load_section (&__flash_rwdata_start, 
  b8:	00000780 	call	78 <alt_load_section>

  /*
   * Copy the exception handler.
   */

  alt_load_section (&__flash_exceptions_start, 
  bc:	01000034 	movhi	r4,0
  c0:	21000804 	addi	r4,r4,32
  c4:	01400034 	movhi	r5,0
  c8:	29400804 	addi	r5,r5,32
  cc:	01800034 	movhi	r6,0
  d0:	31800804 	addi	r6,r6,32
  d4:	00000780 	call	78 <alt_load_section>

  /*
   * Copy the .rodata section.
   */

  alt_load_section (&__flash_rodata_start, 
  d8:	01000034 	movhi	r4,0
  dc:	21005904 	addi	r4,r4,356
  e0:	01400034 	movhi	r5,0
  e4:	29405904 	addi	r5,r5,356
  e8:	01800034 	movhi	r6,0
  ec:	31805904 	addi	r6,r6,356
  f0:	00000780 	call	78 <alt_load_section>
  
  /*
   * Now ensure that the caches are in synch.
   */
  
  alt_dcache_flush_all();
  f4:	00001540 	call	154 <alt_dcache_flush_all>
  alt_icache_flush_all();
}
  f8:	dfc00017 	ldw	ra,0(sp)
  fc:	dec00104 	addi	sp,sp,4
  /*
   * Now ensure that the caches are in synch.
   */
  
  alt_dcache_flush_all();
  alt_icache_flush_all();
 100:	00001581 	jmpi	158 <alt_icache_flush_all>

00000104 <alt_main>:
 * devices/filesystems/components in the system; and call the entry point for
 * the users application, i.e. main().
 */

void alt_main (void)
{
 104:	deffff04 	addi	sp,sp,-4
#endif

  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
  /* Initialize the interrupt controller. */
  alt_irq_init (NULL);
 108:	0009883a 	mov	r4,zero
 * devices/filesystems/components in the system; and call the entry point for
 * the users application, i.e. main().
 */

void alt_main (void)
{
 10c:	dfc00015 	stw	ra,0(sp)
#endif

  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
  /* Initialize the interrupt controller. */
  alt_irq_init (NULL);
 110:	00001340 	call	134 <alt_irq_init>
  ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n");
  ALT_SEM_CREATE (&alt_fd_list_lock, 1);

  /* Initialize the device drivers/software components. */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n");
  alt_sys_init();
 114:	00001300 	call	130 <alt_sys_init>
   */

  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");

#ifdef ALT_NO_EXIT
  main (alt_argc, alt_argv, alt_envp);
 118:	d1200217 	ldw	r4,-32760(gp)
 11c:	d1600317 	ldw	r5,-32756(gp)
 120:	d1a00417 	ldw	r6,-32752(gp)
  close(STDOUT_FILENO);
  exit (result);
#endif

  ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n");
}
 124:	dfc00017 	ldw	ra,0(sp)
 128:	dec00104 	addi	sp,sp,4
   */

  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");

#ifdef ALT_NO_EXIT
  main (alt_argc, alt_argv, alt_envp);
 12c:	000005c1 	jmpi	5c <main>

00000130 <alt_sys_init>:
 */

void alt_sys_init( void )
{
    ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart);
}
 130:	f800283a 	ret

00000134 <alt_irq_init>:
 * The "base" parameter is ignored and only
 * present for backwards-compatibility.
 */

void alt_irq_init ( const void* base )
{
 134:	deffff04 	addi	sp,sp,-4
 138:	dfc00015 	stw	ra,0(sp)
    ALTERA_NIOS2_QSYS_IRQ_INIT ( NIOS2_PROCESSOR, nios2_processor);
 13c:	000015c0 	call	15c <altera_nios2_qsys_irq_init>
 * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts.
 */
static ALT_INLINE void ALT_ALWAYS_INLINE 
       alt_irq_cpu_enable_interrupts ()
{
    NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK
 140:	00800044 	movi	r2,1
 144:	1001703a 	wrctl	status,r2
    alt_irq_cpu_enable_interrupts();
}
 148:	dfc00017 	ldw	ra,0(sp)
 14c:	dec00104 	addi	sp,sp,4
 150:	f800283a 	ret

00000154 <alt_dcache_flush_all>:
  for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE)
  { 
    __asm__ volatile ("flushd (%0)" :: "r" (i));
  }
#endif /* NIOS2_DCACHE_SIZE > 0 */
}
 154:	f800283a 	ret

00000158 <alt_icache_flush_all>:
void alt_icache_flush_all (void)
{
#if NIOS2_ICACHE_SIZE > 0
  alt_icache_flush (0, NIOS2_ICACHE_SIZE);
#endif
}
 158:	f800283a 	ret

0000015c <altera_nios2_qsys_irq_init>:
 * To initialize the internal interrupt controller, just clear the IENABLE
 * register so that all possible IRQs are disabled.
 */
void altera_nios2_qsys_irq_init(void) 
{
    NIOS2_WRITE_IENABLE(0);
 15c:	000170fa 	wrctl	ienable,zero
}
 160:	f800283a 	ret
