
qsys_tutorial_key3.elf:     file format elf32-littlenios2
qsys_tutorial_key3.elf
architecture: nios2, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x00000020

Program Header:
    LOAD off    0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12
         filesz 0x00000020 memsz 0x00000020 flags r-x
    LOAD off    0x00001020 vaddr 0x00000020 paddr 0x00000020 align 2**12
         filesz 0x000001b8 memsz 0x000001b8 flags r-x
    LOAD off    0x000011d8 vaddr 0x000001d8 paddr 0x000001dc align 2**12
         filesz 0x00000004 memsz 0x00000004 flags rw-
    LOAD off    0x000011e0 vaddr 0x000001e0 paddr 0x000001e0 align 2**12
         filesz 0x00000000 memsz 0x0000000c flags rw-

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .entry        00000020  00000000  00000000  00001000  2**5
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .text         000001b8  00000020  00000020  00001020  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rwdata       00000004  000001d8  000001dc  000011d8  2**2
                  CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
  3 .bss          0000000c  000001e0  000001e0  000011e0  2**2
                  ALLOC, SMALL_DATA
  4 .comment      00000026  00000000  00000000  000011dc  2**0
                  CONTENTS, READONLY
  5 .debug_aranges 00000108  00000000  00000000  00001208  2**3
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_pubnames 00000149  00000000  00000000  00001310  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_info   000006dd  00000000  00000000  00001459  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_abbrev 000003ba  00000000  00000000  00001b36  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_line   00000e24  00000000  00000000  00001ef0  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_frame  00000118  00000000  00000000  00002d14  2**2
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_str    000003ed  00000000  00000000  00002e2c  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_loc    000000b7  00000000  00000000  00003219  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_alt_sim_info 00000010  00000000  00000000  000032d0  2**2
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_ranges 00000020  00000000  00000000  000032e0  2**3
                  CONTENTS, READONLY, DEBUGGING
 15 .thread_model 00000003  00000000  00000000  00003f17  2**0
                  CONTENTS, READONLY
 16 .cpu          0000000f  00000000  00000000  00003f1a  2**0
                  CONTENTS, READONLY
 17 .qsys         00000001  00000000  00000000  00003f29  2**0
                  CONTENTS, READONLY
 18 .simulation_enabled 00000001  00000000  00000000  00003f2a  2**0
                  CONTENTS, READONLY
 19 .stderr_dev   00000009  00000000  00000000  00003f2b  2**0
                  CONTENTS, READONLY
 20 .stdin_dev    00000009  00000000  00000000  00003f34  2**0
                  CONTENTS, READONLY
 21 .stdout_dev   00000009  00000000  00000000  00003f3d  2**0
                  CONTENTS, READONLY
 22 .sopc_system_name 0000000b  00000000  00000000  00003f46  2**0
                  CONTENTS, READONLY
 23 .quartus_project_dir 00000030  00000000  00000000  00003f51  2**0
                  CONTENTS, READONLY
 24 .sopcinfo     0003d17e  00000000  00000000  00003f81  2**0
                  CONTENTS, READONLY
SYMBOL TABLE:
00000000 l    d  .entry	00000000 .entry
00000020 l    d  .text	00000000 .text
000001d8 l    d  .rwdata	00000000 .rwdata
000001e0 l    d  .bss	00000000 .bss
00000000 l    d  .comment	00000000 .comment
00000000 l    d  .debug_aranges	00000000 .debug_aranges
00000000 l    d  .debug_pubnames	00000000 .debug_pubnames
00000000 l    d  .debug_info	00000000 .debug_info
00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
00000000 l    d  .debug_line	00000000 .debug_line
00000000 l    d  .debug_frame	00000000 .debug_frame
00000000 l    d  .debug_str	00000000 .debug_str
00000000 l    d  .debug_loc	00000000 .debug_loc
00000000 l    d  .debug_alt_sim_info	00000000 .debug_alt_sim_info
00000000 l    d  .debug_ranges	00000000 .debug_ranges
00000058 l       .text	00000000 alt_after_alt_main
00000000 l    df *ABS*	00000000 hello_world_small.c
00000000 l    df *ABS*	00000000 alt_load.c
000000ec l     F .text	00000020 alt_load_section
00000000 l    df *ABS*	00000000 alt_main.c
00000000 l    df *ABS*	00000000 alt_sys_init.c
00000000 l    df *ABS*	00000000 alt_dcache_flush_all.c
00000000 l    df *ABS*	00000000 alt_icache_flush_all.c
00000000 l    df *ABS*	00000000 altera_nios2_qsys_irq.c
00000178 g     F .text	0000002c alt_main
000001dc g       *ABS*	00000000 __flash_rwdata_start
000001d8 g     O .rwdata	00000004 jtag_uart
00000000 g     F .entry	0000000c __reset
00000020 g       *ABS*	00000000 __flash_exceptions_start
000001e4 g     O .bss	00000004 alt_argv
000081d8 g       *ABS*	00000000 _gp
000001ec g       *ABS*	00000000 __bss_end
000001c8 g     F .text	00000004 alt_dcache_flush_all
000001dc g       *ABS*	00000000 __ram_rwdata_end
00000000 g       *ABS*	00000000 __alt_mem_onchip_memory
000001d8 g       *ABS*	00000000 __ram_rodata_end
000001ec g       *ABS*	00000000 end
00001000 g       *ABS*	00000000 __alt_stack_pointer
00000020 g     F .text	0000003c _start
000001a4 g     F .text	00000004 alt_sys_init
000001d8 g       *ABS*	00000000 __ram_rwdata_start
000001d8 g       *ABS*	00000000 __ram_rodata_start
000001ec g       *ABS*	00000000 __alt_stack_base
000001e0 g       *ABS*	00000000 __bss_start
0000005c g     F .text	00000090 main
000001e8 g     O .bss	00000004 alt_envp
000001d8 g       *ABS*	00000000 __flash_rodata_start
000001a8 g     F .text	00000020 alt_irq_init
000001e0 g     O .bss	00000004 alt_argc
00000020 g       *ABS*	00000000 __ram_exceptions_start
000001dc g       *ABS*	00000000 _edata
000001ec g       *ABS*	00000000 _end
00000020 g       *ABS*	00000000 __ram_exceptions_end
000001d0 g     F .text	00000008 altera_nios2_qsys_irq_init
0000000c g       .entry	00000000 exit
00001000 g       *ABS*	00000000 __alt_data_end
0000000c g       .entry	00000000 _exit
000001cc g     F .text	00000004 alt_icache_flush_all
0000010c g     F .text	0000006c alt_load



Disassembly of section .entry:

00000000 <__reset>:
 * Jump to the _start entry point in the .text section if reset code
 * is allowed or if optimizing for RTL simulation.
 */
#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE)
    /* Jump to the _start entry point in the .text section. */
    movhi r1, %hi(_start)
   0:	00400034 	movhi	at,0
    ori r1, r1, %lo(_start)
   4:	08400814 	ori	at,at,32
    jmp r1
   8:	0800683a 	jmp	at

0000000c <_exit>:
	...

Disassembly of section .text:

00000020 <_start>:
#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0)    
    /*
     * Now that the caches are initialized, set up the stack pointer.
     * The value provided by the linker is assumed to be correctly aligned.
     */
    movhi sp, %hi(__alt_stack_pointer)
  20:	06c00034 	movhi	sp,0
    ori sp, sp, %lo(__alt_stack_pointer)
  24:	dec40014 	ori	sp,sp,4096

    /* Set up the global pointer. */
    movhi gp, %hi(_gp)
  28:	06800034 	movhi	gp,0
    ori gp, gp, %lo(_gp)
  2c:	d6a07614 	ori	gp,gp,33240
 */
#ifndef ALT_SIM_OPTIMIZE
    /* Log that the BSS is about to be cleared. */
    ALT_LOG_PUTS(alt_log_msg_bss)

    movhi r2, %hi(__bss_start)
  30:	00800034 	movhi	r2,0
    ori r2, r2, %lo(__bss_start)
  34:	10807814 	ori	r2,r2,480

    movhi r3, %hi(__bss_end)
  38:	00c00034 	movhi	r3,0
    ori r3, r3, %lo(__bss_end)
  3c:	18c07b14 	ori	r3,r3,492

    beq r2, r3, 1f
  40:	10c00326 	beq	r2,r3,50 <_start+0x30>

0:
    stw zero, (r2)
  44:	10000015 	stw	zero,0(r2)
    addi r2, r2, 4
  48:	10800104 	addi	r2,r2,4
    bltu r2, r3, 0b
  4c:	10fffd36 	bltu	r2,r3,44 <_start+0x24>
     * section aren't defined until alt_load() has been called).
     */
    mov   et, zero
#endif

    call alt_load
  50:	000010c0 	call	10c <alt_load>

    /* Log that alt_main is about to be called. */
    ALT_LOG_PUTS(alt_log_msg_alt_main)

    /* Call the C entry point. It should never return. */
    call alt_main
  54:	00001780 	call	178 <alt_main>

00000058 <alt_after_alt_main>:

    /* Wait in infinite loop in case alt_main does return. */
alt_after_alt_main:
    br alt_after_alt_main
  58:	003fff06 	br	58 <alt_after_alt_main>

0000005c <main>:
{
	int buf = 0;
	unsigned char status = 0;
	while(1) {
		sw_t s;
		s.data = *switches;
  5c:	00880404 	movi	r2,8208
  60:	10c00017 	ldw	r3,0(r2)
  64:	00000d06 	br	9c <main+0x40>
  68:	01400084 	movi	r5,2
  6c:	00880404 	movi	r2,8208

		switch (status) {
  70:	29003fcc 	andi	r4,r5,255
  74:	00c00044 	movi	r3,1
{
	int buf = 0;
	unsigned char status = 0;
	while(1) {
		sw_t s;
		s.data = *switches;
  78:	10800017 	ldw	r2,0(r2)

		switch (status) {
  7c:	20c00e26 	beq	r4,r3,b8 <main+0x5c>
			break;
		case 1:
			if (*push_switches == 7) status = 2;
			break;
		case 2:
			*ledrs += buf;
  80:	01880804 	movi	r6,8224
	unsigned char status = 0;
	while(1) {
		sw_t s;
		s.data = *switches;

		switch (status) {
  84:	000b883a 	mov	r5,zero
  88:	20c00336 	bltu	r4,r3,98 <main+0x3c>
  8c:	00800084 	movi	r2,2
  90:	20801126 	beq	r4,r2,d8 <main+0x7c>
  94:	003ff506 	br	6c <main+0x10>
  98:	1007883a 	mov	r3,r2
		case 0:
			if (*push_switches != 7) status = 1;
  9c:	00880004 	movi	r2,8192
  a0:	10800003 	ldbu	r2,0(r2)
			buf = s.sw.code;
  a4:	1806d2ba 	srli	r3,r3,10
		sw_t s;
		s.data = *switches;

		switch (status) {
		case 0:
			if (*push_switches != 7) status = 1;
  a8:	108001d8 	cmpnei	r2,r2,7
  ac:	100b883a 	mov	r5,r2
			buf = s.sw.code;
  b0:	19c03fcc 	andi	r7,r3,255
  b4:	003fed06 	br	6c <main+0x10>
			break;
		case 1:
			if (*push_switches == 7) status = 2;
  b8:	00880004 	movi	r2,8192
  bc:	10800003 	ldbu	r2,0(r2)
  c0:	00c001c4 	movi	r3,7
  c4:	10803fcc 	andi	r2,r2,255
  c8:	1080201c 	xori	r2,r2,128
  cc:	10bfe004 	addi	r2,r2,-128
  d0:	10ffe61e 	bne	r2,r3,6c <main+0x10>
  d4:	003fe406 	br	68 <main+0xc>
			break;
		case 2:
			*ledrs += buf;
  d8:	30800017 	ldw	r2,0(r6)
  dc:	000b883a 	mov	r5,zero
  e0:	11c5883a 	add	r2,r2,r7
  e4:	30800015 	stw	r2,0(r6)
  e8:	003fe006 	br	6c <main+0x10>

000000ec <alt_load_section>:

static void ALT_INLINE alt_load_section (alt_u32* from, 
                                         alt_u32* to, 
                                         alt_u32* end)
{
  if (to != from)
  ec:	2900051e 	bne	r5,r4,104 <alt_load_section+0x18>
  f0:	f800283a 	ret
  {
    while( to != end )
    {
      *to++ = *from++;
  f4:	20800017 	ldw	r2,0(r4)
  f8:	21000104 	addi	r4,r4,4
  fc:	28800015 	stw	r2,0(r5)
 100:	29400104 	addi	r5,r5,4
                                         alt_u32* to, 
                                         alt_u32* end)
{
  if (to != from)
  {
    while( to != end )
 104:	29bffb1e 	bne	r5,r6,f4 <alt_load_section+0x8>
 108:	f800283a 	ret

0000010c <alt_load>:
 * there is no bootloader, so this application is responsible for loading to
 * RAM any sections that are required.
 */  

void alt_load (void)
{
 10c:	deffff04 	addi	sp,sp,-4
  /* 
   * Copy the .rwdata section. 
   */

  alt_load_section (&__flash_rwdata_start, 
 110:	01000034 	movhi	r4,0
 114:	21007704 	addi	r4,r4,476
 118:	01400034 	movhi	r5,0
 11c:	29407604 	addi	r5,r5,472
 120:	01800034 	movhi	r6,0
 124:	31807704 	addi	r6,r6,476
 * there is no bootloader, so this application is responsible for loading to
 * RAM any sections that are required.
 */  

void alt_load (void)
{
 128:	dfc00015 	stw	ra,0(sp)
  /* 
   * Copy the .rwdata section. 
   */

  alt_load_section (&__flash_rwdata_start, 
 12c:	00000ec0 	call	ec <alt_load_section>

  /*
   * Copy the exception handler.
   */

  alt_load_section (&__flash_exceptions_start, 
 130:	01000034 	movhi	r4,0
 134:	21000804 	addi	r4,r4,32
 138:	01400034 	movhi	r5,0
 13c:	29400804 	addi	r5,r5,32
 140:	01800034 	movhi	r6,0
 144:	31800804 	addi	r6,r6,32
 148:	00000ec0 	call	ec <alt_load_section>

  /*
   * Copy the .rodata section.
   */

  alt_load_section (&__flash_rodata_start, 
 14c:	01000034 	movhi	r4,0
 150:	21007604 	addi	r4,r4,472
 154:	01400034 	movhi	r5,0
 158:	29407604 	addi	r5,r5,472
 15c:	01800034 	movhi	r6,0
 160:	31807604 	addi	r6,r6,472
 164:	00000ec0 	call	ec <alt_load_section>
  
  /*
   * Now ensure that the caches are in synch.
   */
  
  alt_dcache_flush_all();
 168:	00001c80 	call	1c8 <alt_dcache_flush_all>
  alt_icache_flush_all();
}
 16c:	dfc00017 	ldw	ra,0(sp)
 170:	dec00104 	addi	sp,sp,4
  /*
   * Now ensure that the caches are in synch.
   */
  
  alt_dcache_flush_all();
  alt_icache_flush_all();
 174:	00001cc1 	jmpi	1cc <alt_icache_flush_all>

00000178 <alt_main>:
 * devices/filesystems/components in the system; and call the entry point for
 * the users application, i.e. main().
 */

void alt_main (void)
{
 178:	deffff04 	addi	sp,sp,-4
#endif

  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
  /* Initialize the interrupt controller. */
  alt_irq_init (NULL);
 17c:	0009883a 	mov	r4,zero
 * devices/filesystems/components in the system; and call the entry point for
 * the users application, i.e. main().
 */

void alt_main (void)
{
 180:	dfc00015 	stw	ra,0(sp)
#endif

  /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n");
  /* Initialize the interrupt controller. */
  alt_irq_init (NULL);
 184:	00001a80 	call	1a8 <alt_irq_init>
  ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n");
  ALT_SEM_CREATE (&alt_fd_list_lock, 1);

  /* Initialize the device drivers/software components. */
  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n");
  alt_sys_init();
 188:	00001a40 	call	1a4 <alt_sys_init>
   */

  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");

#ifdef ALT_NO_EXIT
  main (alt_argc, alt_argv, alt_envp);
 18c:	d1200217 	ldw	r4,-32760(gp)
 190:	d1600317 	ldw	r5,-32756(gp)
 194:	d1a00417 	ldw	r6,-32752(gp)
  close(STDOUT_FILENO);
  exit (result);
#endif

  ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n");
}
 198:	dfc00017 	ldw	ra,0(sp)
 19c:	dec00104 	addi	sp,sp,4
   */

  ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n");

#ifdef ALT_NO_EXIT
  main (alt_argc, alt_argv, alt_envp);
 1a0:	000005c1 	jmpi	5c <main>

000001a4 <alt_sys_init>:
 */

void alt_sys_init( void )
{
    ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart);
}
 1a4:	f800283a 	ret

000001a8 <alt_irq_init>:
 * The "base" parameter is ignored and only
 * present for backwards-compatibility.
 */

void alt_irq_init ( const void* base )
{
 1a8:	deffff04 	addi	sp,sp,-4
 1ac:	dfc00015 	stw	ra,0(sp)
    ALTERA_NIOS2_QSYS_IRQ_INIT ( NIOS2_PROCESSOR, nios2_processor);
 1b0:	00001d00 	call	1d0 <altera_nios2_qsys_irq_init>
 * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts.
 */
static ALT_INLINE void ALT_ALWAYS_INLINE 
       alt_irq_cpu_enable_interrupts ()
{
    NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK
 1b4:	00800044 	movi	r2,1
 1b8:	1001703a 	wrctl	status,r2
    alt_irq_cpu_enable_interrupts();
}
 1bc:	dfc00017 	ldw	ra,0(sp)
 1c0:	dec00104 	addi	sp,sp,4
 1c4:	f800283a 	ret

000001c8 <alt_dcache_flush_all>:
  for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE)
  { 
    __asm__ volatile ("flushd (%0)" :: "r" (i));
  }
#endif /* NIOS2_DCACHE_SIZE > 0 */
}
 1c8:	f800283a 	ret

000001cc <alt_icache_flush_all>:
void alt_icache_flush_all (void)
{
#if NIOS2_ICACHE_SIZE > 0
  alt_icache_flush (0, NIOS2_ICACHE_SIZE);
#endif
}
 1cc:	f800283a 	ret

000001d0 <altera_nios2_qsys_irq_init>:
 * To initialize the internal interrupt controller, just clear the IENABLE
 * register so that all possible IRQs are disabled.
 */
void altera_nios2_qsys_irq_init(void) 
{
    NIOS2_WRITE_IENABLE(0);
 1d0:	000170fa 	wrctl	ienable,zero
}
 1d4:	f800283a 	ret
