datasheet for nios

diff --git a/.qsys_edit/filters.xml b/.qsys_edit/filters.xml new file mode 100644 index 0000000..519c8a6 --- /dev/null +++ b/.qsys_edit/filters.xml @@ -0,0 +1,2 @@ + + diff --git a/.qsys_edit/preferences.xml b/.qsys_edit/preferences.xml new file mode 100644 index 0000000..cc21c5e --- /dev/null +++ b/.qsys_edit/preferences.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/app_software/.cproject b/app_software/.cproject new file mode 100644 index 0000000..d07a4c4 --- /dev/null +++ b/app_software/.cproject @@ -0,0 +1,481 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/app_software/.project b/app_software/.project new file mode 100644 index 0000000..b583772 --- /dev/null +++ b/app_software/.project @@ -0,0 +1,90 @@ + + + qsys_turorial_green + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://qsys_turorial_green} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUICustomAppNature + + diff --git a/app_software/lights.c b/app_software/lights.c new file mode 100644 index 0000000..763f1ed --- /dev/null +++ b/app_software/lights.c @@ -0,0 +1,7 @@ +#define switches (volatile char *) 0x0002000 +#define leds (char *) 0x0002010 + +void main() +{ + while(1) *leds = *switches; +} \ No newline at end of file diff --git a/db/a_dpfifo_q131.tdf b/db/a_dpfifo_q131.tdf new file mode 100644 index 0000000..e177be3 --- /dev/null +++ b/db/a_dpfifo_q131.tdf @@ -0,0 +1,79 @@ +--a_dpfifo ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" +--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION a_fefifo_7cf (aclr, clock, rreq, sclr, wreq) +RETURNS ( empty, full, usedw_out[5..0]); +FUNCTION dpram_nl21 (data[7..0], inclock, outclock, outclocken, rdaddress[5..0], wraddress[5..0], wren) +RETURNS ( q[7..0]); +FUNCTION cntr_1ob (aclr, clock, cnt_en, sclr) +RETURNS ( q[5..0]); + +--synthesis_resources = lut 18 M9K 1 reg 20 +SUBDESIGN a_dpfifo_q131 +( + aclr : input; + clock : input; + data[7..0] : input; + empty : output; + full : output; + q[7..0] : output; + rreq : input; + sclr : input; + usedw[5..0] : output; + wreq : input; +) +VARIABLE + fifo_state : a_fefifo_7cf; + FIFOram : dpram_nl21; + rd_ptr_count : cntr_1ob; + wr_ptr : cntr_1ob; + rd_ptr[5..0] : WIRE; + valid_rreq : WIRE; + valid_wreq : WIRE; + +BEGIN + fifo_state.aclr = aclr; + fifo_state.clock = clock; + fifo_state.rreq = rreq; + fifo_state.sclr = sclr; + fifo_state.wreq = wreq; + FIFOram.data[] = data[]; + FIFOram.inclock = clock; + FIFOram.outclock = clock; + FIFOram.outclocken = (valid_rreq # sclr); + FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]); + FIFOram.wraddress[] = wr_ptr.q[]; + FIFOram.wren = valid_wreq; + rd_ptr_count.aclr = aclr; + rd_ptr_count.clock = clock; + rd_ptr_count.cnt_en = valid_rreq; + rd_ptr_count.sclr = sclr; + wr_ptr.aclr = aclr; + wr_ptr.clock = clock; + wr_ptr.cnt_en = valid_wreq; + wr_ptr.sclr = sclr; + empty = fifo_state.empty; + full = fifo_state.full; + q[] = FIFOram.q[]; + rd_ptr[] = rd_ptr_count.q[]; + usedw[] = fifo_state.usedw_out[]; + valid_rreq = rreq; + valid_wreq = wreq; +END; +--VALID FILE diff --git a/db/a_fefifo_7cf.tdf b/db/a_fefifo_7cf.tdf new file mode 100644 index 0000000..3398db0 --- /dev/null +++ b/db/a_fefifo_7cf.tdf @@ -0,0 +1,90 @@ +--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=64 lpm_widthad=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock empty full rreq sclr usedw_out wreq +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cntr_do7 (aclr, clock, cnt_en, sclr, updown) +RETURNS ( q[5..0]); + +--synthesis_resources = lut 6 reg 8 +SUBDESIGN a_fefifo_7cf +( + aclr : input; + clock : input; + empty : output; + full : output; + rreq : input; + sclr : input; + usedw_out[5..0] : output; + wreq : input; +) +VARIABLE + b_full : dffe; + b_non_empty : dffe; + count_usedw : cntr_do7; + equal_af1w[5..0] : WIRE; + equal_one[5..0] : WIRE; + is_almost_empty0 : WIRE; + is_almost_empty1 : WIRE; + is_almost_empty2 : WIRE; + is_almost_empty3 : WIRE; + is_almost_empty4 : WIRE; + is_almost_empty5 : WIRE; + is_almost_full0 : WIRE; + is_almost_full1 : WIRE; + is_almost_full2 : WIRE; + is_almost_full3 : WIRE; + is_almost_full4 : WIRE; + is_almost_full5 : WIRE; + usedw[5..0] : WIRE; + valid_rreq : WIRE; + valid_wreq : WIRE; + +BEGIN + b_full.clk = clock; + b_full.clrn = (! aclr); + b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full5 & wreq) & (! rreq))))); + b_non_empty.clk = clock; + b_non_empty.clrn = (! aclr); + b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty5 & rreq) & (! wreq)))))); + count_usedw.aclr = aclr; + count_usedw.clock = clock; + count_usedw.cnt_en = (valid_wreq $ valid_rreq); + count_usedw.sclr = sclr; + count_usedw.updown = valid_wreq; + empty = (! b_non_empty.q); + equal_af1w[] = ( B"0", B"0", B"0", B"0", B"0", B"0"); + equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"0"); + full = b_full.q; + is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]); + is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0); + is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1); + is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2); + is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3); + is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4); + is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]); + is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0); + is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1); + is_almost_full3 = ((usedw[3..3] $ equal_af1w[3..3]) & is_almost_full2); + is_almost_full4 = ((usedw[4..4] $ equal_af1w[4..4]) & is_almost_full3); + is_almost_full5 = ((usedw[5..5] $ equal_af1w[5..5]) & is_almost_full4); + usedw[] = count_usedw.q[]; + usedw_out[] = usedw[]; + valid_rreq = rreq; + valid_wreq = wreq; +END; +--VALID FILE diff --git a/db/altsyncram_0rh1.tdf b/db/altsyncram_0rh1.tdf new file mode 100644 index 0000000..660af43 --- /dev/null +++ b/db/altsyncram_0rh1.tdf @@ -0,0 +1,1042 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_rf_ram_a.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_0rh1 +( + address_a[4..0] : input; + address_b[4..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[4..0] : WIRE; + address_b_wire[4..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_1rh1.tdf b/db/altsyncram_1rh1.tdf new file mode 100644 index 0000000..987a124 --- /dev/null +++ b/db/altsyncram_1rh1.tdf @@ -0,0 +1,1042 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_rf_ram_b.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_1rh1 +( + address_a[4..0] : input; + address_b[4..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[4..0] : WIRE; + address_b_wire[4..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_4891.tdf b/db/altsyncram_4891.tdf new file mode 100644 index 0000000..f9cb0e6 --- /dev/null +++ b/db/altsyncram_4891.tdf @@ -0,0 +1,819 @@ +--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_ociram_default_contents.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 address_a byteena_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_4891 +( + address_a[7..0] : input; + byteena_a[3..0] : input; + clock0 : input; + data_a[31..0] : input; + q_a[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[7..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + ram_block1a[31..0].portawe = wren_a; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[31..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_4ed1.tdf b/db/altsyncram_4ed1.tdf new file mode 100644 index 0000000..edb6130 --- /dev/null +++ b/db/altsyncram_4ed1.tdf @@ -0,0 +1,5470 @@ +--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=51200 NUMWORDS_A=51200 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=16 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_qsa (data[2..0], enable) +RETURNS ( eq[6..0]); +FUNCTION mux_nob (data[223..0], sel[2..0]) +RETURNS ( result[31..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 168 M9K 200 reg 3 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_4ed1 +( + address_a[15..0] : input; + byteena_a[3..0] : input; + clock0 : input; + clocken0 : input; + data_a[31..0] : input; + q_a[31..0] : output; + wren_a : input; +) +VARIABLE + address_reg_a[2..0] : dffe; + decode3 : decode_qsa; + mux2 : mux_nob; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a32 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a33 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a34 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a35 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a36 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a37 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a38 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a39 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a40 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a41 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a42 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a43 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a44 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a45 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a46 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a47 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a48 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a49 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a50 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a51 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a52 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a53 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a54 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a55 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a56 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a57 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a58 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a59 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a60 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a61 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a62 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a63 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a64 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a65 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a66 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a67 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a68 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a69 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a70 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a71 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a72 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a73 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a74 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a75 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a76 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a77 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a78 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a79 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a80 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a81 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a82 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a83 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a84 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a85 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a86 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a87 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a88 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a89 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a90 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a91 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a92 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a93 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a94 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a95 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a96 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a97 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a98 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a99 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a100 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a101 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a102 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a103 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a104 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a105 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a106 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a107 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a108 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a109 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a110 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a111 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a112 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a113 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a114 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a115 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a116 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a117 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a118 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a119 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a120 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a121 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a122 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a123 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a124 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a125 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a126 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a127 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a128 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a129 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a130 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a131 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a132 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a133 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a134 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a135 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a136 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a137 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a138 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a139 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a140 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a141 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a142 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a143 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a144 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a145 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a146 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a147 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a148 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a149 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a150 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a151 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a152 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a153 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a154 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a155 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a156 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a157 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a158 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a159 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a160 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a161 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a162 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a163 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a164 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a165 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a166 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a167 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a168 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a169 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a170 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a171 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a172 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a173 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a174 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a175 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a176 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a177 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a178 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a179 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a180 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a181 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a182 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a183 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a184 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a185 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a186 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a187 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a188 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a189 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a190 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a191 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a192 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a193 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a194 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a195 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a196 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a197 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a198 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a199 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a200 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a201 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a202 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a203 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a204 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a205 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a206 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a207 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a208 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a209 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a210 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a211 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a212 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a213 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a214 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a215 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a216 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a217 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a218 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a219 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a220 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a221 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a222 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a223 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[2..0] : WIRE; + address_a_wire[15..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + address_reg_a[].ena = clocken0; + decode3.data[2..0] = address_a_wire[15..13]; + decode3.enable = wren_a; + mux2.data[] = ( ram_block1a[223..0].portadataout[0..0]); + mux2.sel[] = address_reg_a[].q; + ram_block1a[223..0].clk0 = clock0; + ram_block1a[223..0].ena0 = clocken0; + ram_block1a[191..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[223..192].portaaddr[] = ( address_a_wire[10..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[39..32].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[47..40].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[55..48].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[63..56].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[71..64].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[79..72].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[87..80].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[95..88].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[103..96].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[111..104].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[119..112].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[127..120].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[135..128].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[143..136].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[151..144].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[159..152].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[167..160].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[175..168].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[183..176].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[191..184].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[199..192].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[207..200].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[215..208].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[223..216].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[32].portadatain[] = ( data_a[0..0]); + ram_block1a[33].portadatain[] = ( data_a[1..1]); + ram_block1a[34].portadatain[] = ( data_a[2..2]); + ram_block1a[35].portadatain[] = ( data_a[3..3]); + ram_block1a[36].portadatain[] = ( data_a[4..4]); + ram_block1a[37].portadatain[] = ( data_a[5..5]); + ram_block1a[38].portadatain[] = ( data_a[6..6]); + ram_block1a[39].portadatain[] = ( data_a[7..7]); + ram_block1a[40].portadatain[] = ( data_a[8..8]); + ram_block1a[41].portadatain[] = ( data_a[9..9]); + ram_block1a[42].portadatain[] = ( data_a[10..10]); + ram_block1a[43].portadatain[] = ( data_a[11..11]); + ram_block1a[44].portadatain[] = ( data_a[12..12]); + ram_block1a[45].portadatain[] = ( data_a[13..13]); + ram_block1a[46].portadatain[] = ( data_a[14..14]); + ram_block1a[47].portadatain[] = ( data_a[15..15]); + ram_block1a[48].portadatain[] = ( data_a[16..16]); + ram_block1a[49].portadatain[] = ( data_a[17..17]); + ram_block1a[50].portadatain[] = ( data_a[18..18]); + ram_block1a[51].portadatain[] = ( data_a[19..19]); + ram_block1a[52].portadatain[] = ( data_a[20..20]); + ram_block1a[53].portadatain[] = ( data_a[21..21]); + ram_block1a[54].portadatain[] = ( data_a[22..22]); + ram_block1a[55].portadatain[] = ( data_a[23..23]); + ram_block1a[56].portadatain[] = ( data_a[24..24]); + ram_block1a[57].portadatain[] = ( data_a[25..25]); + ram_block1a[58].portadatain[] = ( data_a[26..26]); + ram_block1a[59].portadatain[] = ( data_a[27..27]); + ram_block1a[60].portadatain[] = ( data_a[28..28]); + ram_block1a[61].portadatain[] = ( data_a[29..29]); + ram_block1a[62].portadatain[] = ( data_a[30..30]); + ram_block1a[63].portadatain[] = ( data_a[31..31]); + ram_block1a[64].portadatain[] = ( data_a[0..0]); + ram_block1a[65].portadatain[] = ( data_a[1..1]); + ram_block1a[66].portadatain[] = ( data_a[2..2]); + ram_block1a[67].portadatain[] = ( data_a[3..3]); + ram_block1a[68].portadatain[] = ( data_a[4..4]); + ram_block1a[69].portadatain[] = ( data_a[5..5]); + ram_block1a[70].portadatain[] = ( data_a[6..6]); + ram_block1a[71].portadatain[] = ( data_a[7..7]); + ram_block1a[72].portadatain[] = ( data_a[8..8]); + ram_block1a[73].portadatain[] = ( data_a[9..9]); + ram_block1a[74].portadatain[] = ( data_a[10..10]); + ram_block1a[75].portadatain[] = ( data_a[11..11]); + ram_block1a[76].portadatain[] = ( data_a[12..12]); + ram_block1a[77].portadatain[] = ( data_a[13..13]); + ram_block1a[78].portadatain[] = ( data_a[14..14]); + ram_block1a[79].portadatain[] = ( data_a[15..15]); + ram_block1a[80].portadatain[] = ( data_a[16..16]); + ram_block1a[81].portadatain[] = ( data_a[17..17]); + ram_block1a[82].portadatain[] = ( data_a[18..18]); + ram_block1a[83].portadatain[] = ( data_a[19..19]); + ram_block1a[84].portadatain[] = ( data_a[20..20]); + ram_block1a[85].portadatain[] = ( data_a[21..21]); + ram_block1a[86].portadatain[] = ( data_a[22..22]); + ram_block1a[87].portadatain[] = ( data_a[23..23]); + ram_block1a[88].portadatain[] = ( data_a[24..24]); + ram_block1a[89].portadatain[] = ( data_a[25..25]); + ram_block1a[90].portadatain[] = ( data_a[26..26]); + ram_block1a[91].portadatain[] = ( data_a[27..27]); + ram_block1a[92].portadatain[] = ( data_a[28..28]); + ram_block1a[93].portadatain[] = ( data_a[29..29]); + ram_block1a[94].portadatain[] = ( data_a[30..30]); + ram_block1a[95].portadatain[] = ( data_a[31..31]); + ram_block1a[96].portadatain[] = ( data_a[0..0]); + ram_block1a[97].portadatain[] = ( data_a[1..1]); + ram_block1a[98].portadatain[] = ( data_a[2..2]); + ram_block1a[99].portadatain[] = ( data_a[3..3]); + ram_block1a[100].portadatain[] = ( data_a[4..4]); + ram_block1a[101].portadatain[] = ( data_a[5..5]); + ram_block1a[102].portadatain[] = ( data_a[6..6]); + ram_block1a[103].portadatain[] = ( data_a[7..7]); + ram_block1a[104].portadatain[] = ( data_a[8..8]); + ram_block1a[105].portadatain[] = ( data_a[9..9]); + ram_block1a[106].portadatain[] = ( data_a[10..10]); + ram_block1a[107].portadatain[] = ( data_a[11..11]); + ram_block1a[108].portadatain[] = ( data_a[12..12]); + ram_block1a[109].portadatain[] = ( data_a[13..13]); + ram_block1a[110].portadatain[] = ( data_a[14..14]); + ram_block1a[111].portadatain[] = ( data_a[15..15]); + ram_block1a[112].portadatain[] = ( data_a[16..16]); + ram_block1a[113].portadatain[] = ( data_a[17..17]); + ram_block1a[114].portadatain[] = ( data_a[18..18]); + ram_block1a[115].portadatain[] = ( data_a[19..19]); + ram_block1a[116].portadatain[] = ( data_a[20..20]); + ram_block1a[117].portadatain[] = ( data_a[21..21]); + ram_block1a[118].portadatain[] = ( data_a[22..22]); + ram_block1a[119].portadatain[] = ( data_a[23..23]); + ram_block1a[120].portadatain[] = ( data_a[24..24]); + ram_block1a[121].portadatain[] = ( data_a[25..25]); + ram_block1a[122].portadatain[] = ( data_a[26..26]); + ram_block1a[123].portadatain[] = ( data_a[27..27]); + ram_block1a[124].portadatain[] = ( data_a[28..28]); + ram_block1a[125].portadatain[] = ( data_a[29..29]); + ram_block1a[126].portadatain[] = ( data_a[30..30]); + ram_block1a[127].portadatain[] = ( data_a[31..31]); + ram_block1a[128].portadatain[] = ( data_a[0..0]); + ram_block1a[129].portadatain[] = ( data_a[1..1]); + ram_block1a[130].portadatain[] = ( data_a[2..2]); + ram_block1a[131].portadatain[] = ( data_a[3..3]); + ram_block1a[132].portadatain[] = ( data_a[4..4]); + ram_block1a[133].portadatain[] = ( data_a[5..5]); + ram_block1a[134].portadatain[] = ( data_a[6..6]); + ram_block1a[135].portadatain[] = ( data_a[7..7]); + ram_block1a[136].portadatain[] = ( data_a[8..8]); + ram_block1a[137].portadatain[] = ( data_a[9..9]); + ram_block1a[138].portadatain[] = ( data_a[10..10]); + ram_block1a[139].portadatain[] = ( data_a[11..11]); + ram_block1a[140].portadatain[] = ( data_a[12..12]); + ram_block1a[141].portadatain[] = ( data_a[13..13]); + ram_block1a[142].portadatain[] = ( data_a[14..14]); + ram_block1a[143].portadatain[] = ( data_a[15..15]); + ram_block1a[144].portadatain[] = ( data_a[16..16]); + ram_block1a[145].portadatain[] = ( data_a[17..17]); + ram_block1a[146].portadatain[] = ( data_a[18..18]); + ram_block1a[147].portadatain[] = ( data_a[19..19]); + ram_block1a[148].portadatain[] = ( data_a[20..20]); + ram_block1a[149].portadatain[] = ( data_a[21..21]); + ram_block1a[150].portadatain[] = ( data_a[22..22]); + ram_block1a[151].portadatain[] = ( data_a[23..23]); + ram_block1a[152].portadatain[] = ( data_a[24..24]); + ram_block1a[153].portadatain[] = ( data_a[25..25]); + ram_block1a[154].portadatain[] = ( data_a[26..26]); + ram_block1a[155].portadatain[] = ( data_a[27..27]); + ram_block1a[156].portadatain[] = ( data_a[28..28]); + ram_block1a[157].portadatain[] = ( data_a[29..29]); + ram_block1a[158].portadatain[] = ( data_a[30..30]); + ram_block1a[159].portadatain[] = ( data_a[31..31]); + ram_block1a[160].portadatain[] = ( data_a[0..0]); + ram_block1a[161].portadatain[] = ( data_a[1..1]); + ram_block1a[162].portadatain[] = ( data_a[2..2]); + ram_block1a[163].portadatain[] = ( data_a[3..3]); + ram_block1a[164].portadatain[] = ( data_a[4..4]); + ram_block1a[165].portadatain[] = ( data_a[5..5]); + ram_block1a[166].portadatain[] = ( data_a[6..6]); + ram_block1a[167].portadatain[] = ( data_a[7..7]); + ram_block1a[168].portadatain[] = ( data_a[8..8]); + ram_block1a[169].portadatain[] = ( data_a[9..9]); + ram_block1a[170].portadatain[] = ( data_a[10..10]); + ram_block1a[171].portadatain[] = ( data_a[11..11]); + ram_block1a[172].portadatain[] = ( data_a[12..12]); + ram_block1a[173].portadatain[] = ( data_a[13..13]); + ram_block1a[174].portadatain[] = ( data_a[14..14]); + ram_block1a[175].portadatain[] = ( data_a[15..15]); + ram_block1a[176].portadatain[] = ( data_a[16..16]); + ram_block1a[177].portadatain[] = ( data_a[17..17]); + ram_block1a[178].portadatain[] = ( data_a[18..18]); + ram_block1a[179].portadatain[] = ( data_a[19..19]); + ram_block1a[180].portadatain[] = ( data_a[20..20]); + ram_block1a[181].portadatain[] = ( data_a[21..21]); + ram_block1a[182].portadatain[] = ( data_a[22..22]); + ram_block1a[183].portadatain[] = ( data_a[23..23]); + ram_block1a[184].portadatain[] = ( data_a[24..24]); + ram_block1a[185].portadatain[] = ( data_a[25..25]); + ram_block1a[186].portadatain[] = ( data_a[26..26]); + ram_block1a[187].portadatain[] = ( data_a[27..27]); + ram_block1a[188].portadatain[] = ( data_a[28..28]); + ram_block1a[189].portadatain[] = ( data_a[29..29]); + ram_block1a[190].portadatain[] = ( data_a[30..30]); + ram_block1a[191].portadatain[] = ( data_a[31..31]); + ram_block1a[192].portadatain[] = ( data_a[0..0]); + ram_block1a[193].portadatain[] = ( data_a[1..1]); + ram_block1a[194].portadatain[] = ( data_a[2..2]); + ram_block1a[195].portadatain[] = ( data_a[3..3]); + ram_block1a[196].portadatain[] = ( data_a[4..4]); + ram_block1a[197].portadatain[] = ( data_a[5..5]); + ram_block1a[198].portadatain[] = ( data_a[6..6]); + ram_block1a[199].portadatain[] = ( data_a[7..7]); + ram_block1a[200].portadatain[] = ( data_a[8..8]); + ram_block1a[201].portadatain[] = ( data_a[9..9]); + ram_block1a[202].portadatain[] = ( data_a[10..10]); + ram_block1a[203].portadatain[] = ( data_a[11..11]); + ram_block1a[204].portadatain[] = ( data_a[12..12]); + ram_block1a[205].portadatain[] = ( data_a[13..13]); + ram_block1a[206].portadatain[] = ( data_a[14..14]); + ram_block1a[207].portadatain[] = ( data_a[15..15]); + ram_block1a[208].portadatain[] = ( data_a[16..16]); + ram_block1a[209].portadatain[] = ( data_a[17..17]); + ram_block1a[210].portadatain[] = ( data_a[18..18]); + ram_block1a[211].portadatain[] = ( data_a[19..19]); + ram_block1a[212].portadatain[] = ( data_a[20..20]); + ram_block1a[213].portadatain[] = ( data_a[21..21]); + ram_block1a[214].portadatain[] = ( data_a[22..22]); + ram_block1a[215].portadatain[] = ( data_a[23..23]); + ram_block1a[216].portadatain[] = ( data_a[24..24]); + ram_block1a[217].portadatain[] = ( data_a[25..25]); + ram_block1a[218].portadatain[] = ( data_a[26..26]); + ram_block1a[219].portadatain[] = ( data_a[27..27]); + ram_block1a[220].portadatain[] = ( data_a[28..28]); + ram_block1a[221].portadatain[] = ( data_a[29..29]); + ram_block1a[222].portadatain[] = ( data_a[30..30]); + ram_block1a[223].portadatain[] = ( data_a[31..31]); + ram_block1a[223..0].portare = B"11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; + ram_block1a[223..0].portawe = ( decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); + address_a_sel[2..0] = address_a[15..13]; + address_a_wire[] = address_a[]; + q_a[] = mux2.result[]; +END; +--VALID FILE diff --git a/db/altsyncram_mbd1.tdf b/db/altsyncram_mbd1.tdf new file mode 100644 index 0000000..638b810 --- /dev/null +++ b/db/altsyncram_mbd1.tdf @@ -0,0 +1,821 @@ +--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=4096 NUMWORDS_A=4096 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=12 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 16 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_mbd1 +( + address_a[11..0] : input; + byteena_a[3..0] : input; + clock0 : input; + clocken0 : input; + data_a[31..0] : input; + q_a[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[11..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].ena0 = clocken0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[11..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + ram_block1a[31..0].portawe = wren_a; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[31..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_r1m1.tdf b/db/altsyncram_r1m1.tdf new file mode 100644 index 0000000..15e2d8b --- /dev/null +++ b/db/altsyncram_r1m1.tdf @@ -0,0 +1,303 @@ +--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_r1m1 +( + address_a[5..0] : input; + address_b[5..0] : input; + clock0 : input; + clock1 : input; + clocken1 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block2a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[5..0] : WIRE; + address_b_wire[5..0] : WIRE; + +BEGIN + ram_block2a[7..0].clk0 = clock0; + ram_block2a[7..0].clk1 = clock1; + ram_block2a[7..0].ena0 = wren_a; + ram_block2a[7..0].ena1 = clocken1; + ram_block2a[7..0].portaaddr[] = ( address_a_wire[5..0]); + ram_block2a[0].portadatain[] = ( data_a[0..0]); + ram_block2a[1].portadatain[] = ( data_a[1..1]); + ram_block2a[2].portadatain[] = ( data_a[2..2]); + ram_block2a[3].portadatain[] = ( data_a[3..3]); + ram_block2a[4].portadatain[] = ( data_a[4..4]); + ram_block2a[5].portadatain[] = ( data_a[5..5]); + ram_block2a[6].portadatain[] = ( data_a[6..6]); + ram_block2a[7].portadatain[] = ( data_a[7..7]); + ram_block2a[7..0].portawe = wren_a; + ram_block2a[7..0].portbaddr[] = ( address_b_wire[5..0]); + ram_block2a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block2a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_sad1.tdf b/db/altsyncram_sad1.tdf new file mode 100644 index 0000000..674477b --- /dev/null +++ b/db/altsyncram_sad1.tdf @@ -0,0 +1,821 @@ +--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=1024 NUMWORDS_A=1024 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=10 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_sad1 +( + address_a[9..0] : input; + byteena_a[3..0] : input; + clock0 : input; + clocken0 : input; + data_a[31..0] : input; + q_a[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[9..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].ena0 = clocken0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + ram_block1a[31..0].portawe = wren_a; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[31..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/db/cntr_1ob.tdf b/db/cntr_1ob.tdf new file mode 100644 index 0000000..f20e091 --- /dev/null +++ b/db/cntr_1ob.tdf @@ -0,0 +1,97 @@ +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=6 aclr clock cnt_en q sclr +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 6 reg 6 +SUBDESIGN cntr_1ob +( + aclr : input; + clock : input; + cnt_en : input; + q[5..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[5..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[5..0] : NODE; + external_cin : WIRE; + s_val[5..0] : WIRE; + safe_q[5..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); + counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); + counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = aclr; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/db/cntr_do7.tdf b/db/cntr_do7.tdf new file mode 100644 index 0000000..cf34edf --- /dev/null +++ b/db/cntr_do7.tdf @@ -0,0 +1,98 @@ +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=6 aclr clock cnt_en q sclr updown +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 6 reg 6 +SUBDESIGN cntr_do7 +( + aclr : input; + clock : input; + cnt_en : input; + q[5..0] : output; + sclr : input; + updown : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[5..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[5..0] : NODE; + external_cin : WIRE; + s_val[5..0] : WIRE; + safe_q[5..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); + counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); + counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = aclr; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = updown; +END; +--VALID FILE diff --git a/db/decode_qsa.tdf b/db/decode_qsa.tdf new file mode 100644 index 0000000..78baf29 --- /dev/null +++ b/db/decode_qsa.tdf @@ -0,0 +1,57 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=7 LPM_WIDTH=3 data enable eq +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 8 +SUBDESIGN decode_qsa +( + data[2..0] : input; + enable : input; + eq[6..0] : output; +) +VARIABLE + data_wire[2..0] : WIRE; + enable_wire : WIRE; + eq_node[6..0] : WIRE; + eq_wire[7..0] : WIRE; + w_anode1849w[3..0] : WIRE; + w_anode1866w[3..0] : WIRE; + w_anode1876w[3..0] : WIRE; + w_anode1886w[3..0] : WIRE; + w_anode1896w[3..0] : WIRE; + w_anode1906w[3..0] : WIRE; + w_anode1916w[3..0] : WIRE; + w_anode1926w[3..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[6..0] = eq_wire[6..0]; + eq_wire[] = ( w_anode1926w[3..3], w_anode1916w[3..3], w_anode1906w[3..3], w_anode1896w[3..3], w_anode1886w[3..3], w_anode1876w[3..3], w_anode1866w[3..3], w_anode1849w[3..3]); + w_anode1849w[] = ( (w_anode1849w[2..2] & (! data_wire[2..2])), (w_anode1849w[1..1] & (! data_wire[1..1])), (w_anode1849w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode1866w[] = ( (w_anode1866w[2..2] & (! data_wire[2..2])), (w_anode1866w[1..1] & (! data_wire[1..1])), (w_anode1866w[0..0] & data_wire[0..0]), enable_wire); + w_anode1876w[] = ( (w_anode1876w[2..2] & (! data_wire[2..2])), (w_anode1876w[1..1] & data_wire[1..1]), (w_anode1876w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode1886w[] = ( (w_anode1886w[2..2] & (! data_wire[2..2])), (w_anode1886w[1..1] & data_wire[1..1]), (w_anode1886w[0..0] & data_wire[0..0]), enable_wire); + w_anode1896w[] = ( (w_anode1896w[2..2] & data_wire[2..2]), (w_anode1896w[1..1] & (! data_wire[1..1])), (w_anode1896w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode1906w[] = ( (w_anode1906w[2..2] & data_wire[2..2]), (w_anode1906w[1..1] & (! data_wire[1..1])), (w_anode1906w[0..0] & data_wire[0..0]), enable_wire); + w_anode1916w[] = ( (w_anode1916w[2..2] & data_wire[2..2]), (w_anode1916w[1..1] & data_wire[1..1]), (w_anode1916w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode1926w[] = ( (w_anode1926w[2..2] & data_wire[2..2]), (w_anode1926w[1..1] & data_wire[1..1]), (w_anode1926w[0..0] & data_wire[0..0]), enable_wire); +END; +--VALID FILE diff --git a/db/dpram_nl21.tdf b/db/dpram_nl21.tdf new file mode 100644 index 0000000..ed4cc69 --- /dev/null +++ b/db/dpram_nl21.tdf @@ -0,0 +1,48 @@ +--altdpram DEVICE_FAMILY="Cyclone IV E" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=8 WIDTHAD=6 data inclock outclock outclocken q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" +--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION altsyncram_r1m1 (address_a[5..0], address_b[5..0], clock0, clock1, clocken1, data_a[7..0], wren_a) +RETURNS ( q_b[7..0]); + +--synthesis_resources = M9K 1 +SUBDESIGN dpram_nl21 +( + data[7..0] : input; + inclock : input; + outclock : input; + outclocken : input; + q[7..0] : output; + rdaddress[5..0] : input; + wraddress[5..0] : input; + wren : input; +) +VARIABLE + altsyncram1 : altsyncram_r1m1; + +BEGIN + altsyncram1.address_a[] = wraddress[]; + altsyncram1.address_b[] = rdaddress[]; + altsyncram1.clock0 = inclock; + altsyncram1.clock1 = outclock; + altsyncram1.clocken1 = outclocken; + altsyncram1.data_a[] = data[]; + altsyncram1.wren_a = wren; + q[] = altsyncram1.q_b[]; +END; +--VALID FILE diff --git a/db/ip/nios_system/nios_system.bsf b/db/ip/nios_system/nios_system.bsf new file mode 100644 index 0000000..dac37b1 --- /dev/null +++ b/db/ip/nios_system/nios_system.bsf @@ -0,0 +1,248 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 384 792) + (text "nios_system" (rect 155 -1 206 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 776 20 788)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 160 72)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 160 152)(line_width 1)) + ) + (port + (pt 0 232) + (input) + (text "switches_export[17..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) + (text "switches_export[17..0]" (rect 4 221 136 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 160 232)(line_width 3)) + ) + (port + (pt 0 272) + (input) + (text "push_switches_export[2..0]" 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532)(pt 162 556)(line_width 1)) + (line (pt 161 572)(pt 161 596)(line_width 1)) + (line (pt 162 572)(pt 162 596)(line_width 1)) + (line (pt 161 612)(pt 161 684)(line_width 1)) + (line (pt 162 612)(pt 162 684)(line_width 1)) + (line (pt 161 700)(pt 161 724)(line_width 1)) + (line (pt 162 700)(pt 162 724)(line_width 1)) + (line (pt 161 740)(pt 161 764)(line_width 1)) + (line (pt 162 740)(pt 162 764)(line_width 1)) + (line (pt 160 32)(pt 224 32)(line_width 1)) + (line (pt 224 32)(pt 224 776)(line_width 1)) + (line (pt 160 776)(pt 224 776)(line_width 1)) + (line (pt 160 32)(pt 160 776)(line_width 1)) + (line (pt 0 0)(pt 384 0)(line_width 1)) + (line (pt 384 0)(pt 384 792)(line_width 1)) + (line (pt 0 792)(pt 384 792)(line_width 1)) + (line (pt 0 0)(pt 0 792)(line_width 1)) + ) +) diff --git a/db/ip/nios_system/nios_system.v b/db/ip/nios_system/nios_system.v new file mode 100644 index 0000000..06baee3 --- /dev/null +++ b/db/ip/nios_system/nios_system.v @@ -0,0 +1,5964 @@ +// nios_system.v + +// Generated using ACDS version 13.0sp1 232 at 2017.01.26.11:05:39 + +`timescale 1 ps / 1 ps +module nios_system ( + input wire clk_clk, // clk.clk + output wire [7:0] leds_export, // leds.export + input wire reset_reset_n, // reset.reset_n + output wire [17:0] ledrs_export, // ledrs.export + input wire [17:0] switches_export, // switches.export + input wire [2:0] push_switches_export, // push_switches.export + output wire [6:0] hex0_export, // hex0.export + output wire [6:0] hex1_export, // hex1.export + output wire [6:0] hex2_export, // hex2.export + output wire [6:0] hex3_export, // hex3.export + output wire [6:0] hex4_export, // hex4.export + output wire [6:0] hex5_export, // hex5.export + output wire [6:0] hex6_export, // hex6.export + output wire [6:0] hex7_export, // hex7.export + output wire lcd_16207_0_RS, // lcd_16207_0.RS + output wire lcd_16207_0_RW, // .RW + inout wire [7:0] lcd_16207_0_data, // .data + output wire lcd_16207_0_E, // .E + output wire lcd_on_export, // lcd_on.export + output wire lcd_blon_export // lcd_blon.export + ); + + wire nios2_processor_instruction_master_waitrequest; // nios2_processor_instruction_master_translator:av_waitrequest -> nios2_processor:i_waitrequest + wire [18:0] nios2_processor_instruction_master_address; // nios2_processor:i_address -> nios2_processor_instruction_master_translator:av_address + wire nios2_processor_instruction_master_read; // nios2_processor:i_read -> nios2_processor_instruction_master_translator:av_read + wire [31:0] nios2_processor_instruction_master_readdata; // nios2_processor_instruction_master_translator:av_readdata -> nios2_processor:i_readdata + wire nios2_processor_data_master_waitrequest; // nios2_processor_data_master_translator:av_waitrequest -> nios2_processor:d_waitrequest + wire [31:0] nios2_processor_data_master_writedata; // nios2_processor:d_writedata -> nios2_processor_data_master_translator:av_writedata + wire [18:0] nios2_processor_data_master_address; // nios2_processor:d_address -> nios2_processor_data_master_translator:av_address + wire nios2_processor_data_master_write; // nios2_processor:d_write -> nios2_processor_data_master_translator:av_write + wire nios2_processor_data_master_read; // nios2_processor:d_read -> nios2_processor_data_master_translator:av_read + wire [31:0] nios2_processor_data_master_readdata; // nios2_processor_data_master_translator:av_readdata -> nios2_processor:d_readdata + wire nios2_processor_data_master_debugaccess; // nios2_processor:jtag_debug_module_debugaccess_to_roms -> nios2_processor_data_master_translator:av_debugaccess + wire [3:0] nios2_processor_data_master_byteenable; // nios2_processor:d_byteenable -> nios2_processor_data_master_translator:av_byteenable + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_processor:jtag_debug_module_waitrequest -> nios2_processor_jtag_debug_module_translator:av_waitrequest + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_processor_jtag_debug_module_translator:av_writedata -> nios2_processor:jtag_debug_module_writedata + wire [8:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_processor_jtag_debug_module_translator:av_address -> nios2_processor:jtag_debug_module_address + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_processor_jtag_debug_module_translator:av_write -> nios2_processor:jtag_debug_module_write + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_processor_jtag_debug_module_translator:av_read -> nios2_processor:jtag_debug_module_read + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_processor:jtag_debug_module_readdata -> nios2_processor_jtag_debug_module_translator:av_readdata + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_processor_jtag_debug_module_translator:av_debugaccess -> nios2_processor:jtag_debug_module_debugaccess + wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_processor_jtag_debug_module_translator:av_byteenable -> nios2_processor:jtag_debug_module_byteenable + wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_s1_translator:av_writedata -> onchip_memory:writedata + wire [15:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // onchip_memory_s1_translator:av_address -> onchip_memory:address + wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_s1_translator:av_chipselect -> onchip_memory:chipselect + wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_s1_translator:av_clken -> onchip_memory:clken + wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // onchip_memory_s1_translator:av_write -> onchip_memory:write + wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory:readdata -> onchip_memory_s1_translator:av_readdata + wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_s1_translator:av_byteenable -> onchip_memory:byteenable + wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata + wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address + wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect + wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n + wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata + wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata + wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_writedata; // LEDRs_s1_translator:av_writedata -> LEDRs:writedata + wire [1:0] ledrs_s1_translator_avalon_anti_slave_0_address; // LEDRs_s1_translator:av_address -> LEDRs:address + wire ledrs_s1_translator_avalon_anti_slave_0_chipselect; // LEDRs_s1_translator:av_chipselect -> LEDRs:chipselect + wire ledrs_s1_translator_avalon_anti_slave_0_write; // LEDRs_s1_translator:av_write -> LEDRs:write_n + wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_readdata; // LEDRs:readdata -> LEDRs_s1_translator:av_readdata + wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address + wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata + wire [1:0] push_switches_s1_translator_avalon_anti_slave_0_address; // push_switches_s1_translator:av_address -> push_switches:address + wire [31:0] push_switches_s1_translator_avalon_anti_slave_0_readdata; // push_switches:readdata -> push_switches_s1_translator:av_readdata + wire [31:0] hex0_s1_translator_avalon_anti_slave_0_writedata; // hex0_s1_translator:av_writedata -> hex0:writedata + wire [1:0] hex0_s1_translator_avalon_anti_slave_0_address; // hex0_s1_translator:av_address -> hex0:address + wire hex0_s1_translator_avalon_anti_slave_0_chipselect; // hex0_s1_translator:av_chipselect -> hex0:chipselect + wire hex0_s1_translator_avalon_anti_slave_0_write; // hex0_s1_translator:av_write -> hex0:write_n + wire [31:0] hex0_s1_translator_avalon_anti_slave_0_readdata; // hex0:readdata -> hex0_s1_translator:av_readdata + wire [31:0] hex1_s1_translator_avalon_anti_slave_0_writedata; // hex1_s1_translator:av_writedata -> hex1:writedata + wire [1:0] hex1_s1_translator_avalon_anti_slave_0_address; // hex1_s1_translator:av_address -> hex1:address + wire hex1_s1_translator_avalon_anti_slave_0_chipselect; // hex1_s1_translator:av_chipselect -> hex1:chipselect + wire hex1_s1_translator_avalon_anti_slave_0_write; // hex1_s1_translator:av_write -> hex1:write_n + wire [31:0] hex1_s1_translator_avalon_anti_slave_0_readdata; // hex1:readdata -> hex1_s1_translator:av_readdata + wire [31:0] hex2_s1_translator_avalon_anti_slave_0_writedata; // hex2_s1_translator:av_writedata -> hex2:writedata + wire [1:0] hex2_s1_translator_avalon_anti_slave_0_address; // hex2_s1_translator:av_address -> hex2:address + wire hex2_s1_translator_avalon_anti_slave_0_chipselect; // hex2_s1_translator:av_chipselect -> hex2:chipselect + wire hex2_s1_translator_avalon_anti_slave_0_write; // hex2_s1_translator:av_write -> hex2:write_n + wire [31:0] hex2_s1_translator_avalon_anti_slave_0_readdata; // hex2:readdata -> hex2_s1_translator:av_readdata + wire [31:0] hex3_s1_translator_avalon_anti_slave_0_writedata; // hex3_s1_translator:av_writedata -> hex3:writedata + wire [1:0] hex3_s1_translator_avalon_anti_slave_0_address; // hex3_s1_translator:av_address -> hex3:address + wire hex3_s1_translator_avalon_anti_slave_0_chipselect; // hex3_s1_translator:av_chipselect -> hex3:chipselect + wire hex3_s1_translator_avalon_anti_slave_0_write; // hex3_s1_translator:av_write -> hex3:write_n + wire [31:0] hex3_s1_translator_avalon_anti_slave_0_readdata; // hex3:readdata -> hex3_s1_translator:av_readdata + wire [31:0] hex4_s1_translator_avalon_anti_slave_0_writedata; // hex4_s1_translator:av_writedata -> hex4:writedata + wire [1:0] hex4_s1_translator_avalon_anti_slave_0_address; // hex4_s1_translator:av_address -> hex4:address + wire hex4_s1_translator_avalon_anti_slave_0_chipselect; // hex4_s1_translator:av_chipselect -> hex4:chipselect + wire hex4_s1_translator_avalon_anti_slave_0_write; // hex4_s1_translator:av_write -> hex4:write_n + wire [31:0] hex4_s1_translator_avalon_anti_slave_0_readdata; // hex4:readdata -> hex4_s1_translator:av_readdata + wire [31:0] hex5_s1_translator_avalon_anti_slave_0_writedata; // hex5_s1_translator:av_writedata -> hex5:writedata + wire [1:0] hex5_s1_translator_avalon_anti_slave_0_address; // hex5_s1_translator:av_address -> hex5:address + wire hex5_s1_translator_avalon_anti_slave_0_chipselect; // hex5_s1_translator:av_chipselect -> hex5:chipselect + wire hex5_s1_translator_avalon_anti_slave_0_write; // hex5_s1_translator:av_write -> hex5:write_n + wire [31:0] hex5_s1_translator_avalon_anti_slave_0_readdata; // hex5:readdata -> hex5_s1_translator:av_readdata + wire [31:0] hex6_s1_translator_avalon_anti_slave_0_writedata; // hex6_s1_translator:av_writedata -> hex6:writedata + wire [1:0] hex6_s1_translator_avalon_anti_slave_0_address; // hex6_s1_translator:av_address -> hex6:address + wire hex6_s1_translator_avalon_anti_slave_0_chipselect; // hex6_s1_translator:av_chipselect -> hex6:chipselect + wire hex6_s1_translator_avalon_anti_slave_0_write; // hex6_s1_translator:av_write -> hex6:write_n + wire [31:0] hex6_s1_translator_avalon_anti_slave_0_readdata; // hex6:readdata -> hex6_s1_translator:av_readdata + wire [31:0] hex7_s1_translator_avalon_anti_slave_0_writedata; // hex7_s1_translator:av_writedata -> hex7:writedata + wire [1:0] hex7_s1_translator_avalon_anti_slave_0_address; // hex7_s1_translator:av_address -> hex7:address + wire hex7_s1_translator_avalon_anti_slave_0_chipselect; // hex7_s1_translator:av_chipselect -> hex7:chipselect + wire hex7_s1_translator_avalon_anti_slave_0_write; // hex7_s1_translator:av_write -> hex7:write_n + wire [31:0] hex7_s1_translator_avalon_anti_slave_0_readdata; // hex7:readdata -> hex7_s1_translator:av_readdata + wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata; // lcd_16207_0_control_slave_translator:av_writedata -> lcd_16207_0:writedata + wire [1:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address; // lcd_16207_0_control_slave_translator:av_address -> lcd_16207_0:address + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write; // lcd_16207_0_control_slave_translator:av_write -> lcd_16207_0:write + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read; // lcd_16207_0_control_slave_translator:av_read -> lcd_16207_0:read + wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata; // lcd_16207_0:readdata -> lcd_16207_0_control_slave_translator:av_readdata + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer; // lcd_16207_0_control_slave_translator:av_begintransfer -> lcd_16207_0:begintransfer + wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_writedata; // lcd_on_s1_translator:av_writedata -> lcd_on:writedata + wire [1:0] lcd_on_s1_translator_avalon_anti_slave_0_address; // lcd_on_s1_translator:av_address -> lcd_on:address + wire lcd_on_s1_translator_avalon_anti_slave_0_chipselect; // lcd_on_s1_translator:av_chipselect -> lcd_on:chipselect + wire lcd_on_s1_translator_avalon_anti_slave_0_write; // lcd_on_s1_translator:av_write -> lcd_on:write_n + wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_readdata; // lcd_on:readdata -> lcd_on_s1_translator:av_readdata + wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_writedata; // lcd_blon_s1_translator:av_writedata -> lcd_blon:writedata + wire [1:0] lcd_blon_s1_translator_avalon_anti_slave_0_address; // lcd_blon_s1_translator:av_address -> lcd_blon:address + wire lcd_blon_s1_translator_avalon_anti_slave_0_chipselect; // lcd_blon_s1_translator:av_chipselect -> lcd_blon:chipselect + wire lcd_blon_s1_translator_avalon_anti_slave_0_write; // lcd_blon_s1_translator:av_write -> lcd_blon:write_n + wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_readdata; // lcd_blon:readdata -> lcd_blon_s1_translator:av_readdata + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_instruction_master_translator:uav_waitrequest + wire [2:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_instruction_master_translator:uav_burstcount -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_processor_instruction_master_translator:uav_writedata -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_writedata + wire [18:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_address; // nios2_processor_instruction_master_translator:uav_address -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_address + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_lock; // nios2_processor_instruction_master_translator:uav_lock -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_lock + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_write; // nios2_processor_instruction_master_translator:uav_write -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_write + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_read; // nios2_processor_instruction_master_translator:uav_read -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_instruction_master_translator:uav_readdata + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_instruction_master_translator:uav_debugaccess -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_instruction_master_translator:uav_byteenable -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_instruction_master_translator:uav_readdatavalid + wire nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_data_master_translator:uav_waitrequest + wire [2:0] nios2_processor_data_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_data_master_translator:uav_burstcount -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_writedata; // nios2_processor_data_master_translator:uav_writedata -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_writedata + wire [18:0] nios2_processor_data_master_translator_avalon_universal_master_0_address; // nios2_processor_data_master_translator:uav_address -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_address + wire nios2_processor_data_master_translator_avalon_universal_master_0_lock; // nios2_processor_data_master_translator:uav_lock -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_lock + wire nios2_processor_data_master_translator_avalon_universal_master_0_write; // nios2_processor_data_master_translator:uav_write -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_write + wire nios2_processor_data_master_translator_avalon_universal_master_0_read; // nios2_processor_data_master_translator:uav_read -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_readdata; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_data_master_translator:uav_readdata + wire nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_data_master_translator:uav_debugaccess -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] nios2_processor_data_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_data_master_translator:uav_byteenable -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_byteenable + wire nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_data_master_translator:uav_readdatavalid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_processor_jtag_debug_module_translator:uav_waitrequest -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_processor_jtag_debug_module_translator:uav_burstcount + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_processor_jtag_debug_module_translator:uav_writedata + wire [18:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_processor_jtag_debug_module_translator:uav_address + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_processor_jtag_debug_module_translator:uav_write + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_processor_jtag_debug_module_translator:uav_lock + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_processor_jtag_debug_module_translator:uav_read + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_processor_jtag_debug_module_translator:uav_readdata -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_processor_jtag_debug_module_translator:uav_readdatavalid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_processor_jtag_debug_module_translator:uav_debugaccess + wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_processor_jtag_debug_module_translator:uav_byteenable + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount + wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata + wire [18:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_s1_translator:uav_address + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_s1_translator:uav_write + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_s1_translator:uav_lock + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_s1_translator:uav_read + wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess + wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount + wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata + wire [18:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read + wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess + wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata + wire [18:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess + wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDRs_s1_translator:uav_waitrequest -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDRs_s1_translator:uav_burstcount + wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDRs_s1_translator:uav_writedata + wire [18:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDRs_s1_translator:uav_address + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDRs_s1_translator:uav_write + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDRs_s1_translator:uav_lock + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDRs_s1_translator:uav_read + wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDRs_s1_translator:uav_readdata -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDRs_s1_translator:uav_readdatavalid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDRs_s1_translator:uav_debugaccess + wire [3:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDRs_s1_translator:uav_byteenable + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount + wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata + wire [18:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read + wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess + wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // push_switches_s1_translator:uav_waitrequest -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> push_switches_s1_translator:uav_burstcount + wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> push_switches_s1_translator:uav_writedata + wire [18:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> push_switches_s1_translator:uav_address + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> push_switches_s1_translator:uav_write + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> push_switches_s1_translator:uav_lock + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> push_switches_s1_translator:uav_read + wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // push_switches_s1_translator:uav_readdata -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // push_switches_s1_translator:uav_readdatavalid -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> push_switches_s1_translator:uav_debugaccess + wire [3:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> push_switches_s1_translator:uav_byteenable + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount + wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex0_s1_translator:uav_writedata + wire [18:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex0_s1_translator:uav_address + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex0_s1_translator:uav_write + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex0_s1_translator:uav_lock + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex0_s1_translator:uav_read + wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess + wire [3:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount + wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex1_s1_translator:uav_writedata + wire [18:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex1_s1_translator:uav_address + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex1_s1_translator:uav_write + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex1_s1_translator:uav_lock + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex1_s1_translator:uav_read + wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess + wire [3:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount + wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex2_s1_translator:uav_writedata + wire [18:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex2_s1_translator:uav_address + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex2_s1_translator:uav_write + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex2_s1_translator:uav_lock + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex2_s1_translator:uav_read + wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess + wire [3:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount + wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex3_s1_translator:uav_writedata + wire [18:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex3_s1_translator:uav_address + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex3_s1_translator:uav_write + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex3_s1_translator:uav_lock + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex3_s1_translator:uav_read + wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess + wire [3:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount + wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex4_s1_translator:uav_writedata + wire [18:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex4_s1_translator:uav_address + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex4_s1_translator:uav_write + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex4_s1_translator:uav_lock + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex4_s1_translator:uav_read + wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess + wire [3:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount + wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex5_s1_translator:uav_writedata + wire [18:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex5_s1_translator:uav_address + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex5_s1_translator:uav_write + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex5_s1_translator:uav_lock + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex5_s1_translator:uav_read + wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess + wire [3:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex6_s1_translator:uav_waitrequest -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex6_s1_translator:uav_burstcount + wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex6_s1_translator:uav_writedata + wire [18:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex6_s1_translator:uav_address + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex6_s1_translator:uav_write + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex6_s1_translator:uav_lock + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex6_s1_translator:uav_read + wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex6_s1_translator:uav_readdata -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex6_s1_translator:uav_readdatavalid -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex6_s1_translator:uav_debugaccess + wire [3:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex6_s1_translator:uav_byteenable + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex7_s1_translator:uav_waitrequest -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex7_s1_translator:uav_burstcount + wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex7_s1_translator:uav_writedata + wire [18:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex7_s1_translator:uav_address + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex7_s1_translator:uav_write + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex7_s1_translator:uav_lock + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex7_s1_translator:uav_read + wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex7_s1_translator:uav_readdata -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex7_s1_translator:uav_readdatavalid -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex7_s1_translator:uav_debugaccess + wire [3:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex7_s1_translator:uav_byteenable + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_16207_0_control_slave_translator:uav_waitrequest -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_16207_0_control_slave_translator:uav_burstcount + wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_16207_0_control_slave_translator:uav_writedata + wire [18:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> lcd_16207_0_control_slave_translator:uav_address + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> lcd_16207_0_control_slave_translator:uav_write + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_16207_0_control_slave_translator:uav_lock + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> lcd_16207_0_control_slave_translator:uav_read + wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_16207_0_control_slave_translator:uav_readdata -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_16207_0_control_slave_translator:uav_readdatavalid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_16207_0_control_slave_translator:uav_debugaccess + wire [3:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_16207_0_control_slave_translator:uav_byteenable + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_on_s1_translator:uav_waitrequest -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_on_s1_translator:uav_burstcount + wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_on_s1_translator:uav_writedata + wire [18:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_on_s1_translator:uav_address + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_on_s1_translator:uav_write + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_on_s1_translator:uav_lock + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_on_s1_translator:uav_read + wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_on_s1_translator:uav_readdata -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_on_s1_translator:uav_readdatavalid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_on_s1_translator:uav_debugaccess + wire [3:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_on_s1_translator:uav_byteenable + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_blon_s1_translator:uav_waitrequest -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_blon_s1_translator:uav_burstcount + wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_blon_s1_translator:uav_writedata + wire [18:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_blon_s1_translator:uav_address + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_blon_s1_translator:uav_write + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_blon_s1_translator:uav_lock + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_blon_s1_translator:uav_read + wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_blon_s1_translator:uav_readdata -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_blon_s1_translator:uav_readdatavalid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_blon_s1_translator:uav_debugaccess + wire [3:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_blon_s1_translator:uav_byteenable + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket + wire [95:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_ready + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket + wire [95:0] nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket + wire [95:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket + wire [95:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket + wire [95:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket + wire [95:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket + wire [95:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket + wire [95:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket + wire [95:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket + wire [95:0] hex0_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket + wire [95:0] hex1_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket + wire [95:0] hex2_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket + wire [95:0] hex3_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket + wire [95:0] hex4_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket + wire [95:0] hex5_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket + wire [95:0] hex6_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket + wire [95:0] hex7_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket + wire [95:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket + wire [95:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket + wire [95:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_017:sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDRs:reset_n, LEDRs_s1_translator:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, hex0:reset_n, hex0_s1_translator:reset, hex0_s1_translator_avalon_universal_slave_0_agent:reset, hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex1:reset_n, hex1_s1_translator:reset, hex1_s1_translator_avalon_universal_slave_0_agent:reset, hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex2:reset_n, hex2_s1_translator:reset, hex2_s1_translator_avalon_universal_slave_0_agent:reset, hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex3:reset_n, hex3_s1_translator:reset, hex3_s1_translator_avalon_universal_slave_0_agent:reset, hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex4:reset_n, hex4_s1_translator:reset, hex4_s1_translator_avalon_universal_slave_0_agent:reset, hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex5:reset_n, hex5_s1_translator:reset, hex5_s1_translator_avalon_universal_slave_0_agent:reset, hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex6:reset_n, hex6_s1_translator:reset, hex6_s1_translator_avalon_universal_slave_0_agent:reset, hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex7:reset_n, hex7_s1_translator:reset, hex7_s1_translator_avalon_universal_slave_0_agent:reset, hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, irq_mapper:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_16207_0:reset_n, lcd_16207_0_control_slave_translator:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_blon:reset_n, lcd_blon_s1_translator:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_on:reset_n, lcd_on_s1_translator:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_processor:reset_n, nios2_processor_data_master_translator:reset, nios2_processor_data_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_instruction_master_translator:reset, nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_jtag_debug_module_translator:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory:reset, onchip_memory_s1_translator:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, push_switches:reset_n, push_switches_s1_translator:reset, push_switches_s1_translator_avalon_universal_slave_0_agent:reset, push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset] + wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory:reset_req + wire nios2_processor_jtag_debug_module_reset_reset; // nios2_processor:jtag_debug_module_resetrequest -> rst_controller:reset_in1 + wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket + wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid + wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket + wire [95:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data + wire [17:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel + wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready + wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket + wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid + wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket + wire [95:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data + wire [17:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel + wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready + wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket + wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid + wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket + wire [95:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data + wire [17:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel + wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready + wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket + wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid + wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket + wire [95:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data + wire [17:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel + wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready + wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src13_endofpacket; // cmd_xbar_demux_001:src13_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src13_valid; // cmd_xbar_demux_001:src13_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src13_startofpacket; // cmd_xbar_demux_001:src13_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src13_data; // cmd_xbar_demux_001:src13_data -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src13_channel; // cmd_xbar_demux_001:src13_channel -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src14_endofpacket; // cmd_xbar_demux_001:src14_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src14_valid; // cmd_xbar_demux_001:src14_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src14_startofpacket; // cmd_xbar_demux_001:src14_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src14_data; // cmd_xbar_demux_001:src14_data -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src14_channel; // cmd_xbar_demux_001:src14_channel -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src15_endofpacket; // cmd_xbar_demux_001:src15_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src15_valid; // cmd_xbar_demux_001:src15_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src15_startofpacket; // cmd_xbar_demux_001:src15_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src15_data; // cmd_xbar_demux_001:src15_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src15_channel; // cmd_xbar_demux_001:src15_channel -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src16_endofpacket; // cmd_xbar_demux_001:src16_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src16_valid; // cmd_xbar_demux_001:src16_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src16_startofpacket; // cmd_xbar_demux_001:src16_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src16_data; // cmd_xbar_demux_001:src16_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src16_channel; // cmd_xbar_demux_001:src16_channel -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src17_endofpacket; // cmd_xbar_demux_001:src17_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src17_valid; // cmd_xbar_demux_001:src17_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src17_startofpacket; // cmd_xbar_demux_001:src17_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src17_data; // cmd_xbar_demux_001:src17_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src17_channel; // cmd_xbar_demux_001:src17_channel -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket + wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid + wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket + wire [95:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data + wire [17:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel + wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready + wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket + wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid + wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket + wire [95:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data + wire [17:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel + wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready + wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket + wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid + wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket + wire [95:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data + wire [17:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel + wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready + wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket + wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid + wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket + wire [95:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data + wire [17:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel + wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready + wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket + wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid + wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket + wire [95:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data + wire [17:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel + wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready + wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket + wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid + wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket + wire [95:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data + wire [17:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel + wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready + wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket + wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid + wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket + wire [95:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data + wire [17:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel + wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready + wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket + wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid + wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket + wire [95:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data + wire [17:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel + wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready + wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket + wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid + wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket + wire [95:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data + wire [17:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel + wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready + wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket + wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid + wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket + wire [95:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data + wire [17:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel + wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready + wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket + wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid + wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket + wire [95:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data + wire [17:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel + wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready + wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket + wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid + wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket + wire [95:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data + wire [17:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel + wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready + wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket + wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid + wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket + wire [95:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data + wire [17:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel + wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready + wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket + wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid + wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket + wire [95:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data + wire [17:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel + wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready + wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket + wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid + wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket + wire [95:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data + wire [17:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel + wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready + wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_001:sink13_endofpacket + wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_001:sink13_valid + wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_001:sink13_startofpacket + wire [95:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_001:sink13_data + wire [17:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_001:sink13_channel + wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_001:sink13_ready -> rsp_xbar_demux_013:src0_ready + wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_001:sink14_endofpacket + wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_001:sink14_valid + wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_001:sink14_startofpacket + wire [95:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_001:sink14_data + wire [17:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_001:sink14_channel + wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_001:sink14_ready -> rsp_xbar_demux_014:src0_ready + wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_001:sink15_endofpacket + wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_001:sink15_valid + wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_001:sink15_startofpacket + wire [95:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_001:sink15_data + wire [17:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_001:sink15_channel + wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_001:sink15_ready -> rsp_xbar_demux_015:src0_ready + wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_001:sink16_endofpacket + wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_001:sink16_valid + wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_001:sink16_startofpacket + wire [95:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_001:sink16_data + wire [17:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_001:sink16_channel + wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_001:sink16_ready -> rsp_xbar_demux_016:src0_ready + wire rsp_xbar_demux_017_src0_endofpacket; // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_001:sink17_endofpacket + wire rsp_xbar_demux_017_src0_valid; // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_001:sink17_valid + wire rsp_xbar_demux_017_src0_startofpacket; // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_001:sink17_startofpacket + wire [95:0] rsp_xbar_demux_017_src0_data; // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_001:sink17_data + wire [17:0] rsp_xbar_demux_017_src0_channel; // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_001:sink17_channel + wire rsp_xbar_demux_017_src0_ready; // rsp_xbar_mux_001:sink17_ready -> rsp_xbar_demux_017:src0_ready + wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket + wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid + wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket + wire [95:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data + wire [17:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel + wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready + wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_valid + wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [95:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_data + wire [17:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_channel + wire rsp_xbar_mux_src_ready; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready + wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket + wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid + wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket + wire [95:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data + wire [17:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel + wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready + wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_valid + wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [95:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_data + wire [17:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_channel + wire rsp_xbar_mux_001_src_ready; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready + wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready + wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket + wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid + wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket + wire [95:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data + wire [17:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel + wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready + wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_001_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready + wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket + wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid + wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket + wire [95:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data + wire [17:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel + wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready + wire cmd_xbar_demux_001_src2_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready + wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket + wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid + wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket + wire [95:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data + wire [17:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel + wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready + wire cmd_xbar_demux_001_src3_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready + wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket + wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid + wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket + wire [95:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data + wire [17:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel + wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready + wire cmd_xbar_demux_001_src4_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready + wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket + wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid + wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket + wire [95:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data + wire [17:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel + wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready + wire cmd_xbar_demux_001_src5_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready + wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket + wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid + wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket + wire [95:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data + wire [17:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel + wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready + wire cmd_xbar_demux_001_src6_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready + wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket + wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid + wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket + wire [95:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data + wire [17:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel + wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready + wire cmd_xbar_demux_001_src7_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready + wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket + wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid + wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket + wire [95:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data + wire [17:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel + wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready + wire cmd_xbar_demux_001_src8_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready + wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket + wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid + wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket + wire [95:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data + wire [17:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel + wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready + wire cmd_xbar_demux_001_src9_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready + wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket + wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid + wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket + wire [95:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data + wire [17:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel + wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready + wire cmd_xbar_demux_001_src10_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready + wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket + wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid + wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket + wire [95:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data + wire [17:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel + wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready + wire cmd_xbar_demux_001_src11_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready + wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket + wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid + wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket + wire [95:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data + wire [17:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel + wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready + wire cmd_xbar_demux_001_src12_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready + wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket + wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid + wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket + wire [95:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data + wire [17:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel + wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready + wire cmd_xbar_demux_001_src13_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src13_ready + wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket + wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid + wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket + wire [95:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data + wire [17:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel + wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready + wire cmd_xbar_demux_001_src14_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src14_ready + wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket + wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid + wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket + wire [95:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data + wire [17:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel + wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready + wire cmd_xbar_demux_001_src15_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src15_ready + wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket + wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid + wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket + wire [95:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data + wire [17:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel + wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready + wire cmd_xbar_demux_001_src16_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src16_ready + wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket + wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid + wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket + wire [95:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data + wire [17:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel + wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready + wire cmd_xbar_demux_001_src17_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src17_ready + wire id_router_017_src_endofpacket; // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket + wire id_router_017_src_valid; // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid + wire id_router_017_src_startofpacket; // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket + wire [95:0] id_router_017_src_data; // id_router_017:src_data -> rsp_xbar_demux_017:sink_data + wire [17:0] id_router_017_src_channel; // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel + wire id_router_017_src_ready; // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready + wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq + wire [31:0] nios2_processor_d_irq_irq; // irq_mapper:sender_irq -> nios2_processor:d_irq + + nios_system_nios2_processor nios2_processor ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n + .d_address (nios2_processor_data_master_address), // data_master.address + .d_byteenable (nios2_processor_data_master_byteenable), // .byteenable + .d_read (nios2_processor_data_master_read), // .read + .d_readdata (nios2_processor_data_master_readdata), // .readdata + .d_waitrequest (nios2_processor_data_master_waitrequest), // .waitrequest + .d_write (nios2_processor_data_master_write), // .write + .d_writedata (nios2_processor_data_master_writedata), // .writedata + .jtag_debug_module_debugaccess_to_roms (nios2_processor_data_master_debugaccess), // .debugaccess + .i_address (nios2_processor_instruction_master_address), // instruction_master.address + .i_read (nios2_processor_instruction_master_read), // .read + .i_readdata (nios2_processor_instruction_master_readdata), // .readdata + .i_waitrequest (nios2_processor_instruction_master_waitrequest), // .waitrequest + .d_irq (nios2_processor_d_irq_irq), // d_irq.irq + .jtag_debug_module_resetrequest (nios2_processor_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset + .jtag_debug_module_address (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address + .jtag_debug_module_byteenable (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable + .jtag_debug_module_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess + .jtag_debug_module_read (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read + .jtag_debug_module_readdata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata + .jtag_debug_module_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .jtag_debug_module_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write + .jtag_debug_module_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata + .no_ci_readra () // custom_instruction_master.readra + ); + + nios_system_onchip_memory onchip_memory ( + .clk (clk_clk), // clk1.clk + .address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // s1.address + .clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken + .chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write + .readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable + .reset (rst_controller_reset_out_reset), // reset1.reset + .reset_req (rst_controller_reset_out_reset_req) // .reset_req + ); + + nios_system_jtag_uart jtag_uart ( + .clk (clk_clk), // clk.clk + .rst_n (~rst_controller_reset_out_reset), // reset.reset_n + .av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect + .av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address + .av_read_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n + .av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n + .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_irq (irq_mapper_receiver0_irq) // irq.irq + ); + + nios_system_LEDs leds ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (leds_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~leds_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (leds_export) // external_connection.export + ); + + nios_system_LEDRs ledrs ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (ledrs_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~ledrs_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (ledrs_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (ledrs_export) // external_connection.export + ); + + nios_system_switches switches ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (switches_s1_translator_avalon_anti_slave_0_address), // s1.address + .readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .in_port (switches_export) // external_connection.export + ); + + nios_system_push_switches push_switches ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (push_switches_s1_translator_avalon_anti_slave_0_address), // s1.address + .readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .in_port (push_switches_export) // external_connection.export + ); + + nios_system_hex0 hex0 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex0_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex0_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex0_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex0_export) // external_connection.export + ); + + nios_system_hex0 hex1 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex1_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex1_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex1_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex1_export) // external_connection.export + ); + + nios_system_hex0 hex2 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex2_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex2_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex2_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex2_export) // external_connection.export + ); + + nios_system_hex0 hex3 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex3_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex3_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex3_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex3_export) // external_connection.export + ); + + nios_system_hex0 hex4 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex4_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex4_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex4_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex4_export) // external_connection.export + ); + + nios_system_hex0 hex5 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex5_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex5_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex5_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex5_export) // external_connection.export + ); + + nios_system_hex0 hex6 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex6_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex6_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex6_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex6_export) // external_connection.export + ); + + nios_system_hex0 hex7 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex7_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex7_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex7_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex7_export) // external_connection.export + ); + + nios_system_lcd_16207_0 lcd_16207_0 ( + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .clk (clk_clk), // clk.clk + .begintransfer (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer), // control_slave.begintransfer + .read (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read), // .read + .write (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write), // .write + .readdata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .writedata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .address (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address), // .address + .LCD_RS (lcd_16207_0_RS), // external.export + .LCD_RW (lcd_16207_0_RW), // .export + .LCD_data (lcd_16207_0_data), // .export + .LCD_E (lcd_16207_0_E) // .export + ); + + nios_system_lcd_on lcd_on ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (lcd_on_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~lcd_on_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (lcd_on_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (lcd_on_export) // external_connection.export + ); + + nios_system_lcd_on lcd_blon ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (lcd_blon_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~lcd_blon_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (lcd_blon_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (lcd_blon_export) // external_connection.export + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (19), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (0), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (1), + .AV_REGISTERINCOMINGSIGNALS (0) + ) nios2_processor_instruction_master_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (nios2_processor_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (nios2_processor_instruction_master_translator_avalon_universal_master_0_read), // .read + .uav_write (nios2_processor_instruction_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (nios2_processor_instruction_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (nios2_processor_instruction_master_address), // avalon_anti_master_0.address + .av_waitrequest (nios2_processor_instruction_master_waitrequest), // .waitrequest + .av_read (nios2_processor_instruction_master_read), // .read + .av_readdata (nios2_processor_instruction_master_readdata), // .readdata + .av_burstcount (1'b1), // (terminated) + .av_byteenable (4'b1111), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_readdatavalid (), // (terminated) + .av_write (1'b0), // (terminated) + .av_writedata (32'b00000000000000000000000000000000), // (terminated) + .av_lock (1'b0), // (terminated) + .av_debugaccess (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponserequest (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponserequest (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (19), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (1) + ) nios2_processor_data_master_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (nios2_processor_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (nios2_processor_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (nios2_processor_data_master_translator_avalon_universal_master_0_read), // .read + .uav_write (nios2_processor_data_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (nios2_processor_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (nios2_processor_data_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (nios2_processor_data_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (nios2_processor_data_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (nios2_processor_data_master_address), // avalon_anti_master_0.address + .av_waitrequest (nios2_processor_data_master_waitrequest), // .waitrequest + .av_byteenable (nios2_processor_data_master_byteenable), // .byteenable + .av_read (nios2_processor_data_master_read), // .read + .av_readdata (nios2_processor_data_master_readdata), // .readdata + .av_write (nios2_processor_data_master_write), // .write + .av_writedata (nios2_processor_data_master_writedata), // .writedata + .av_debugaccess (nios2_processor_data_master_debugaccess), // .debugaccess + .av_burstcount (1'b1), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_readdatavalid (), // (terminated) + .av_lock (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponserequest (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponserequest (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (9), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) nios2_processor_jtag_debug_module_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write + .av_read (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read + .av_readdata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata + .av_byteenable (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable + .av_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (16), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) onchip_memory_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable + .av_chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) leds_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (leds_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (leds_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (1), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) jtag_uart_avalon_jtag_slave_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write + .av_read (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read + .av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) ledrs_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (ledrs_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (ledrs_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (ledrs_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) switches_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write (), // (terminated) + .av_read (), // (terminated) + .av_writedata (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) push_switches_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (push_switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write (), // (terminated) + .av_read (), // (terminated) + .av_writedata (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex0_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex0_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex0_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex1_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex1_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex1_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex2_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex2_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex2_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex2_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex2_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex2_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex2_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex3_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex3_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex3_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex3_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex3_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex3_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex3_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex4_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex4_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex4_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex4_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex4_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex4_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex4_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex5_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex5_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex5_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex5_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex5_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex5_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex5_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex6_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex6_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex6_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex6_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex6_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex6_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex6_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex7_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex7_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex7_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex7_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex7_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex7_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex7_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (8), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (13), + .AV_WRITE_WAIT_CYCLES (13), + .AV_SETUP_WAIT_CYCLES (13), + .AV_DATA_HOLD_CYCLES (13) + ) lcd_16207_0_control_slave_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write), // .write + .av_read (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read), // .read + .av_readdata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_begintransfer (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer), // .begintransfer + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) lcd_on_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (lcd_on_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (lcd_on_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (lcd_on_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) lcd_blon_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (lcd_blon_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (lcd_blon_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (lcd_blon_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_BEGIN_BURST (74), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .PKT_BURST_TYPE_H (71), + .PKT_BURST_TYPE_L (70), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_TRANS_EXCLUSIVE (60), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_THREAD_ID_H (86), + .PKT_THREAD_ID_L (86), + .PKT_CACHE_H (93), + .PKT_CACHE_L (90), + .PKT_DATA_SIDEBAND_H (73), + .PKT_DATA_SIDEBAND_L (73), + .PKT_QOS_H (75), + .PKT_QOS_L (75), + .PKT_ADDR_SIDEBAND_H (72), + .PKT_ADDR_SIDEBAND_L (72), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .ST_DATA_W (96), + .ST_CHANNEL_W (18), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (1), + .BURSTWRAP_VALUE (3), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .av_address (nios2_processor_instruction_master_translator_avalon_universal_master_0_address), // av.address + .av_write (nios2_processor_instruction_master_translator_avalon_universal_master_0_write), // .write + .av_read (nios2_processor_instruction_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (nios2_processor_instruction_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid + .cp_data (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .cp_startofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .cp_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready + .rp_valid (rsp_xbar_mux_src_valid), // rp.valid + .rp_data (rsp_xbar_mux_src_data), // .data + .rp_channel (rsp_xbar_mux_src_channel), // .channel + .rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket + .rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket + .rp_ready (rsp_xbar_mux_src_ready), // .ready + .av_response (), // (terminated) + .av_writeresponserequest (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_BEGIN_BURST (74), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .PKT_BURST_TYPE_H (71), + .PKT_BURST_TYPE_L (70), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_TRANS_EXCLUSIVE (60), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_THREAD_ID_H (86), + .PKT_THREAD_ID_L (86), + .PKT_CACHE_H (93), + .PKT_CACHE_L (90), + .PKT_DATA_SIDEBAND_H (73), + .PKT_DATA_SIDEBAND_L (73), + .PKT_QOS_H (75), + .PKT_QOS_L (75), + .PKT_ADDR_SIDEBAND_H (72), + .PKT_ADDR_SIDEBAND_L (72), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .ST_DATA_W (96), + .ST_CHANNEL_W (18), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (0), + .BURSTWRAP_VALUE (7), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) nios2_processor_data_master_translator_avalon_universal_master_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .av_address (nios2_processor_data_master_translator_avalon_universal_master_0_address), // av.address + .av_write (nios2_processor_data_master_translator_avalon_universal_master_0_write), // .write + .av_read (nios2_processor_data_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (nios2_processor_data_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (nios2_processor_data_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (nios2_processor_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (nios2_processor_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (nios2_processor_data_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid + .cp_data (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .cp_startofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .cp_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready + .rp_valid (rsp_xbar_mux_001_src_valid), // rp.valid + .rp_data (rsp_xbar_mux_001_src_data), // .data + .rp_channel (rsp_xbar_mux_001_src_channel), // .channel + .rp_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket + .rp_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket + .rp_ready (rsp_xbar_mux_001_src_ready), // .ready + .av_response (), // (terminated) + .av_writeresponserequest (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_mux_src_ready), // cp.ready + .cp_valid (cmd_xbar_mux_src_valid), // .valid + .cp_data (cmd_xbar_mux_src_data), // .data + .cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_mux_src_channel), // .channel + .rf_sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) onchip_memory_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready + .cp_valid (cmd_xbar_mux_001_src_valid), // .valid + .cp_data (cmd_xbar_mux_001_src_data), // .data + .cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_mux_001_src_channel), // .channel + .rf_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) leds_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src2_valid), // .valid + .cp_data (cmd_xbar_demux_001_src2_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src2_channel), // .channel + .rf_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src3_valid), // .valid + .cp_data (cmd_xbar_demux_001_src3_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src3_channel), // .channel + .rf_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) ledrs_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src4_valid), // .valid + .cp_data (cmd_xbar_demux_001_src4_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src4_channel), // .channel + .rf_sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) switches_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src5_valid), // .valid + .cp_data (cmd_xbar_demux_001_src5_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src5_channel), // .channel + .rf_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) push_switches_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src6_valid), // .valid + .cp_data (cmd_xbar_demux_001_src6_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src6_channel), // .channel + .rf_sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex0_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src7_valid), // .valid + .cp_data (cmd_xbar_demux_001_src7_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src7_channel), // .channel + .rf_sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex1_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src8_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src8_valid), // .valid + .cp_data (cmd_xbar_demux_001_src8_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src8_channel), // .channel + .rf_sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex2_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex2_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex2_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex2_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex2_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src9_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src9_valid), // .valid + .cp_data (cmd_xbar_demux_001_src9_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src9_channel), // .channel + .rf_sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex3_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex3_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex3_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex3_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex3_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src10_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src10_valid), // .valid + .cp_data (cmd_xbar_demux_001_src10_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src10_channel), // .channel + .rf_sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex4_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex4_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex4_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex4_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex4_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src11_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src11_valid), // .valid + .cp_data (cmd_xbar_demux_001_src11_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src11_channel), // .channel + .rf_sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex5_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex5_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex5_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex5_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex5_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src12_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src12_valid), // .valid + .cp_data (cmd_xbar_demux_001_src12_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src12_channel), // .channel + .rf_sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex6_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex6_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex6_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex6_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex6_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src13_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src13_valid), // .valid + .cp_data (cmd_xbar_demux_001_src13_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src13_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src13_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src13_channel), // .channel + .rf_sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex7_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex7_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex7_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex7_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex7_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src14_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src14_valid), // .valid + .cp_data (cmd_xbar_demux_001_src14_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src14_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src14_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src14_channel), // .channel + .rf_sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src15_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src15_valid), // .valid + .cp_data (cmd_xbar_demux_001_src15_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src15_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src15_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src15_channel), // .channel + .rf_sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) lcd_on_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src16_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src16_valid), // .valid + .cp_data (cmd_xbar_demux_001_src16_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src16_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src16_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src16_channel), // .channel + .rf_sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) lcd_blon_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src17_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src17_valid), // .valid + .cp_data (cmd_xbar_demux_001_src17_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src17_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src17_channel), // .channel + .rf_sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + nios_system_addr_router addr_router ( + .sink_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready + .sink_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid + .sink_data (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .sink_startofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (addr_router_src_ready), // src.ready + .src_valid (addr_router_src_valid), // .valid + .src_data (addr_router_src_data), // .data + .src_channel (addr_router_src_channel), // .channel + .src_startofpacket (addr_router_src_startofpacket), // .startofpacket + .src_endofpacket (addr_router_src_endofpacket) // .endofpacket + ); + + nios_system_addr_router_001 addr_router_001 ( + .sink_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready + .sink_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid + .sink_data (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .sink_startofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (addr_router_001_src_ready), // src.ready + .src_valid (addr_router_001_src_valid), // .valid + .src_data (addr_router_001_src_data), // .data + .src_channel (addr_router_001_src_channel), // .channel + .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket + .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket + ); + + nios_system_id_router id_router ( + .sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_src_ready), // src.ready + .src_valid (id_router_src_valid), // .valid + .src_data (id_router_src_data), // .data + .src_channel (id_router_src_channel), // .channel + .src_startofpacket (id_router_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_src_endofpacket) // .endofpacket + ); + + nios_system_id_router id_router_001 ( + .sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_001_src_ready), // src.ready + .src_valid (id_router_001_src_valid), // .valid + .src_data (id_router_001_src_data), // .data + .src_channel (id_router_001_src_channel), // .channel + .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_002 ( + .sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_002_src_ready), // src.ready + .src_valid (id_router_002_src_valid), // .valid + .src_data (id_router_002_src_data), // .data + .src_channel (id_router_002_src_channel), // .channel + .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_003 ( + .sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_003_src_ready), // src.ready + .src_valid (id_router_003_src_valid), // .valid + .src_data (id_router_003_src_data), // .data + .src_channel (id_router_003_src_channel), // .channel + .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_004 ( + .sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_004_src_ready), // src.ready + .src_valid (id_router_004_src_valid), // .valid + .src_data (id_router_004_src_data), // .data + .src_channel (id_router_004_src_channel), // .channel + .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_005 ( + .sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_005_src_ready), // src.ready + .src_valid (id_router_005_src_valid), // .valid + .src_data (id_router_005_src_data), // .data + .src_channel (id_router_005_src_channel), // .channel + .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_006 ( + .sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_006_src_ready), // src.ready + .src_valid (id_router_006_src_valid), // .valid + .src_data (id_router_006_src_data), // .data + .src_channel (id_router_006_src_channel), // .channel + .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_007 ( + .sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_007_src_ready), // src.ready + .src_valid (id_router_007_src_valid), // .valid + .src_data (id_router_007_src_data), // .data + .src_channel (id_router_007_src_channel), // .channel + .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_008 ( + .sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_008_src_ready), // src.ready + .src_valid (id_router_008_src_valid), // .valid + .src_data (id_router_008_src_data), // .data + .src_channel (id_router_008_src_channel), // .channel + .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_009 ( + .sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_009_src_ready), // src.ready + .src_valid (id_router_009_src_valid), // .valid + .src_data (id_router_009_src_data), // .data + .src_channel (id_router_009_src_channel), // .channel + .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_010 ( + .sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_010_src_ready), // src.ready + .src_valid (id_router_010_src_valid), // .valid + .src_data (id_router_010_src_data), // .data + .src_channel (id_router_010_src_channel), // .channel + .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_011 ( + .sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_011_src_ready), // src.ready + .src_valid (id_router_011_src_valid), // .valid + .src_data (id_router_011_src_data), // .data + .src_channel (id_router_011_src_channel), // .channel + .src_startofpacket (id_router_011_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_011_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_012 ( + .sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_012_src_ready), // src.ready + .src_valid (id_router_012_src_valid), // .valid + .src_data (id_router_012_src_data), // .data + .src_channel (id_router_012_src_channel), // .channel + .src_startofpacket (id_router_012_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_012_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_013 ( + .sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_013_src_ready), // src.ready + .src_valid (id_router_013_src_valid), // .valid + .src_data (id_router_013_src_data), // .data + .src_channel (id_router_013_src_channel), // .channel + .src_startofpacket (id_router_013_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_013_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_014 ( + .sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_014_src_ready), // src.ready + .src_valid (id_router_014_src_valid), // .valid + .src_data (id_router_014_src_data), // .data + .src_channel (id_router_014_src_channel), // .channel + .src_startofpacket (id_router_014_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_014_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_015 ( + .sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_015_src_ready), // src.ready + .src_valid (id_router_015_src_valid), // .valid + .src_data (id_router_015_src_data), // .data + .src_channel (id_router_015_src_channel), // .channel + .src_startofpacket (id_router_015_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_015_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_016 ( + .sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_016_src_ready), // src.ready + .src_valid (id_router_016_src_valid), // .valid + .src_data (id_router_016_src_data), // .data + .src_channel (id_router_016_src_channel), // .channel + .src_startofpacket (id_router_016_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_016_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_017 ( + .sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_017_src_ready), // src.ready + .src_valid (id_router_017_src_valid), // .valid + .src_data (id_router_017_src_data), // .data + .src_channel (id_router_017_src_channel), // .channel + .src_startofpacket (id_router_017_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_017_src_endofpacket) // .endofpacket + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (2), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (1) + ) rst_controller ( + .reset_in0 (~reset_reset_n), // reset_in0.reset + .reset_in1 (nios2_processor_jtag_debug_module_reset_reset), // reset_in1.reset + .clk (clk_clk), // clk.clk + .reset_out (rst_controller_reset_out_reset), // reset_out.reset + .reset_req (rst_controller_reset_out_reset_req), // .reset_req + .reset_in2 (1'b0), // (terminated) + .reset_in3 (1'b0), // (terminated) + .reset_in4 (1'b0), // (terminated) + .reset_in5 (1'b0), // (terminated) + .reset_in6 (1'b0), // (terminated) + .reset_in7 (1'b0), // (terminated) + .reset_in8 (1'b0), // (terminated) + .reset_in9 (1'b0), // (terminated) + .reset_in10 (1'b0), // (terminated) + .reset_in11 (1'b0), // (terminated) + .reset_in12 (1'b0), // (terminated) + .reset_in13 (1'b0), // (terminated) + .reset_in14 (1'b0), // (terminated) + .reset_in15 (1'b0) // (terminated) + ); + + nios_system_cmd_xbar_demux cmd_xbar_demux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (addr_router_src_ready), // sink.ready + .sink_channel (addr_router_src_channel), // .channel + .sink_data (addr_router_src_data), // .data + .sink_startofpacket (addr_router_src_startofpacket), // .startofpacket + .sink_endofpacket (addr_router_src_endofpacket), // .endofpacket + .sink_valid (addr_router_src_valid), // .valid + .src0_ready (cmd_xbar_demux_src0_ready), // src0.ready + .src0_valid (cmd_xbar_demux_src0_valid), // .valid + .src0_data (cmd_xbar_demux_src0_data), // .data + .src0_channel (cmd_xbar_demux_src0_channel), // .channel + .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket + .src1_ready (cmd_xbar_demux_src1_ready), // src1.ready + .src1_valid (cmd_xbar_demux_src1_valid), // .valid + .src1_data (cmd_xbar_demux_src1_data), // .data + .src1_channel (cmd_xbar_demux_src1_channel), // .channel + .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_demux_001 cmd_xbar_demux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (addr_router_001_src_ready), // sink.ready + .sink_channel (addr_router_001_src_channel), // .channel + .sink_data (addr_router_001_src_data), // .data + .sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket + .sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket + .sink_valid (addr_router_001_src_valid), // .valid + .src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready + .src0_valid (cmd_xbar_demux_001_src0_valid), // .valid + .src0_data (cmd_xbar_demux_001_src0_data), // .data + .src0_channel (cmd_xbar_demux_001_src0_channel), // .channel + .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket + .src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready + .src1_valid (cmd_xbar_demux_001_src1_valid), // .valid + .src1_data (cmd_xbar_demux_001_src1_data), // .data + .src1_channel (cmd_xbar_demux_001_src1_channel), // .channel + .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket + .src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready + .src2_valid (cmd_xbar_demux_001_src2_valid), // .valid + .src2_data (cmd_xbar_demux_001_src2_data), // .data + .src2_channel (cmd_xbar_demux_001_src2_channel), // .channel + .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket + .src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket + .src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready + .src3_valid (cmd_xbar_demux_001_src3_valid), // .valid + .src3_data (cmd_xbar_demux_001_src3_data), // .data + .src3_channel (cmd_xbar_demux_001_src3_channel), // .channel + .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket + .src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket + .src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready + .src4_valid (cmd_xbar_demux_001_src4_valid), // .valid + .src4_data (cmd_xbar_demux_001_src4_data), // .data + .src4_channel (cmd_xbar_demux_001_src4_channel), // .channel + .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket + .src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket + .src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready + .src5_valid (cmd_xbar_demux_001_src5_valid), // .valid + .src5_data (cmd_xbar_demux_001_src5_data), // .data + .src5_channel (cmd_xbar_demux_001_src5_channel), // .channel + .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket + .src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket + .src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready + .src6_valid (cmd_xbar_demux_001_src6_valid), // .valid + .src6_data (cmd_xbar_demux_001_src6_data), // .data + .src6_channel (cmd_xbar_demux_001_src6_channel), // .channel + .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket + .src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket + .src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready + .src7_valid (cmd_xbar_demux_001_src7_valid), // .valid + .src7_data (cmd_xbar_demux_001_src7_data), // .data + .src7_channel (cmd_xbar_demux_001_src7_channel), // .channel + .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket + .src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket + .src8_ready (cmd_xbar_demux_001_src8_ready), // src8.ready + .src8_valid (cmd_xbar_demux_001_src8_valid), // .valid + .src8_data (cmd_xbar_demux_001_src8_data), // .data + .src8_channel (cmd_xbar_demux_001_src8_channel), // .channel + .src8_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket + .src8_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket + .src9_ready (cmd_xbar_demux_001_src9_ready), // src9.ready + .src9_valid (cmd_xbar_demux_001_src9_valid), // .valid + .src9_data (cmd_xbar_demux_001_src9_data), // .data + .src9_channel (cmd_xbar_demux_001_src9_channel), // .channel + .src9_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket + .src9_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket + .src10_ready (cmd_xbar_demux_001_src10_ready), // src10.ready + .src10_valid (cmd_xbar_demux_001_src10_valid), // .valid + .src10_data (cmd_xbar_demux_001_src10_data), // .data + .src10_channel (cmd_xbar_demux_001_src10_channel), // .channel + .src10_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket + .src10_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket + .src11_ready (cmd_xbar_demux_001_src11_ready), // src11.ready + .src11_valid (cmd_xbar_demux_001_src11_valid), // .valid + .src11_data (cmd_xbar_demux_001_src11_data), // .data + .src11_channel (cmd_xbar_demux_001_src11_channel), // .channel + .src11_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket + .src11_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket + .src12_ready (cmd_xbar_demux_001_src12_ready), // src12.ready + .src12_valid (cmd_xbar_demux_001_src12_valid), // .valid + .src12_data (cmd_xbar_demux_001_src12_data), // .data + .src12_channel (cmd_xbar_demux_001_src12_channel), // .channel + .src12_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket + .src12_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket + .src13_ready (cmd_xbar_demux_001_src13_ready), // src13.ready + .src13_valid (cmd_xbar_demux_001_src13_valid), // .valid + .src13_data (cmd_xbar_demux_001_src13_data), // .data + .src13_channel (cmd_xbar_demux_001_src13_channel), // .channel + .src13_startofpacket (cmd_xbar_demux_001_src13_startofpacket), // .startofpacket + .src13_endofpacket (cmd_xbar_demux_001_src13_endofpacket), // .endofpacket + .src14_ready (cmd_xbar_demux_001_src14_ready), // src14.ready + .src14_valid (cmd_xbar_demux_001_src14_valid), // .valid + .src14_data (cmd_xbar_demux_001_src14_data), // .data + .src14_channel (cmd_xbar_demux_001_src14_channel), // .channel + .src14_startofpacket (cmd_xbar_demux_001_src14_startofpacket), // .startofpacket + .src14_endofpacket (cmd_xbar_demux_001_src14_endofpacket), // .endofpacket + .src15_ready (cmd_xbar_demux_001_src15_ready), // src15.ready + .src15_valid (cmd_xbar_demux_001_src15_valid), // .valid + .src15_data (cmd_xbar_demux_001_src15_data), // .data + .src15_channel (cmd_xbar_demux_001_src15_channel), // .channel + .src15_startofpacket (cmd_xbar_demux_001_src15_startofpacket), // .startofpacket + .src15_endofpacket (cmd_xbar_demux_001_src15_endofpacket), // .endofpacket + .src16_ready (cmd_xbar_demux_001_src16_ready), // src16.ready + .src16_valid (cmd_xbar_demux_001_src16_valid), // .valid + .src16_data (cmd_xbar_demux_001_src16_data), // .data + .src16_channel (cmd_xbar_demux_001_src16_channel), // .channel + .src16_startofpacket (cmd_xbar_demux_001_src16_startofpacket), // .startofpacket + .src16_endofpacket (cmd_xbar_demux_001_src16_endofpacket), // .endofpacket + .src17_ready (cmd_xbar_demux_001_src17_ready), // src17.ready + .src17_valid (cmd_xbar_demux_001_src17_valid), // .valid + .src17_data (cmd_xbar_demux_001_src17_data), // .data + .src17_channel (cmd_xbar_demux_001_src17_channel), // .channel + .src17_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket + .src17_endofpacket (cmd_xbar_demux_001_src17_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_mux cmd_xbar_mux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (cmd_xbar_mux_src_ready), // src.ready + .src_valid (cmd_xbar_mux_src_valid), // .valid + .src_data (cmd_xbar_mux_src_data), // .data + .src_channel (cmd_xbar_mux_src_channel), // .channel + .src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket + .sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready + .sink0_valid (cmd_xbar_demux_src0_valid), // .valid + .sink0_channel (cmd_xbar_demux_src0_channel), // .channel + .sink0_data (cmd_xbar_demux_src0_data), // .data + .sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket + .sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready + .sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid + .sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel + .sink1_data (cmd_xbar_demux_001_src0_data), // .data + .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_mux cmd_xbar_mux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (cmd_xbar_mux_001_src_ready), // src.ready + .src_valid (cmd_xbar_mux_001_src_valid), // .valid + .src_data (cmd_xbar_mux_001_src_data), // .data + .src_channel (cmd_xbar_mux_001_src_channel), // .channel + .src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready + .sink0_valid (cmd_xbar_demux_src1_valid), // .valid + .sink0_channel (cmd_xbar_demux_src1_channel), // .channel + .sink0_data (cmd_xbar_demux_src1_data), // .data + .sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket + .sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready + .sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid + .sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel + .sink1_data (cmd_xbar_demux_001_src1_data), // .data + .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_demux rsp_xbar_demux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_src_ready), // sink.ready + .sink_channel (id_router_src_channel), // .channel + .sink_data (id_router_src_data), // .data + .sink_startofpacket (id_router_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_src_endofpacket), // .endofpacket + .sink_valid (id_router_src_valid), // .valid + .src0_ready (rsp_xbar_demux_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_src0_valid), // .valid + .src0_data (rsp_xbar_demux_src0_data), // .data + .src0_channel (rsp_xbar_demux_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket + .src1_ready (rsp_xbar_demux_src1_ready), // src1.ready + .src1_valid (rsp_xbar_demux_src1_valid), // .valid + .src1_data (rsp_xbar_demux_src1_data), // .data + .src1_channel (rsp_xbar_demux_src1_channel), // .channel + .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_demux rsp_xbar_demux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_001_src_ready), // sink.ready + .sink_channel (id_router_001_src_channel), // .channel + .sink_data (id_router_001_src_data), // .data + .sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket + .sink_valid (id_router_001_src_valid), // .valid + .src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_001_src0_valid), // .valid + .src0_data (rsp_xbar_demux_001_src0_data), // .data + .src0_channel (rsp_xbar_demux_001_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket + .src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready + .src1_valid (rsp_xbar_demux_001_src1_valid), // .valid + .src1_data (rsp_xbar_demux_001_src1_data), // .data + .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel + .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_002 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_002_src_ready), // sink.ready + .sink_channel (id_router_002_src_channel), // .channel + .sink_data (id_router_002_src_data), // .data + .sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket + .sink_valid (id_router_002_src_valid), // .valid + .src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_002_src0_valid), // .valid + .src0_data (rsp_xbar_demux_002_src0_data), // .data + .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_003 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_003_src_ready), // sink.ready + .sink_channel (id_router_003_src_channel), // .channel + .sink_data (id_router_003_src_data), // .data + .sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket + .sink_valid (id_router_003_src_valid), // .valid + .src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_003_src0_valid), // .valid + .src0_data (rsp_xbar_demux_003_src0_data), // .data + .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_004 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_004_src_ready), // sink.ready + .sink_channel (id_router_004_src_channel), // .channel + .sink_data (id_router_004_src_data), // .data + .sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket + .sink_valid (id_router_004_src_valid), // .valid + .src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_004_src0_valid), // .valid + .src0_data (rsp_xbar_demux_004_src0_data), // .data + .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_005 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_005_src_ready), // sink.ready + .sink_channel (id_router_005_src_channel), // .channel + .sink_data (id_router_005_src_data), // .data + .sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket + .sink_valid (id_router_005_src_valid), // .valid + .src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_005_src0_valid), // .valid + .src0_data (rsp_xbar_demux_005_src0_data), // .data + .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_006 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_006_src_ready), // sink.ready + .sink_channel (id_router_006_src_channel), // .channel + .sink_data (id_router_006_src_data), // .data + .sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket + .sink_valid (id_router_006_src_valid), // .valid + .src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_006_src0_valid), // .valid + .src0_data (rsp_xbar_demux_006_src0_data), // .data + .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_007 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_007_src_ready), // sink.ready + .sink_channel (id_router_007_src_channel), // .channel + .sink_data (id_router_007_src_data), // .data + .sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket + .sink_valid (id_router_007_src_valid), // .valid + .src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_007_src0_valid), // .valid + .src0_data (rsp_xbar_demux_007_src0_data), // .data + .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_008 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_008_src_ready), // sink.ready + .sink_channel (id_router_008_src_channel), // .channel + .sink_data (id_router_008_src_data), // .data + .sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket + .sink_valid (id_router_008_src_valid), // .valid + .src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_008_src0_valid), // .valid + .src0_data (rsp_xbar_demux_008_src0_data), // .data + .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_009 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_009_src_ready), // sink.ready + .sink_channel (id_router_009_src_channel), // .channel + .sink_data (id_router_009_src_data), // .data + .sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket + .sink_valid (id_router_009_src_valid), // .valid + .src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_009_src0_valid), // .valid + .src0_data (rsp_xbar_demux_009_src0_data), // .data + .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_010 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_010_src_ready), // sink.ready + .sink_channel (id_router_010_src_channel), // .channel + .sink_data (id_router_010_src_data), // .data + .sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket + .sink_valid (id_router_010_src_valid), // .valid + .src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_010_src0_valid), // .valid + .src0_data (rsp_xbar_demux_010_src0_data), // .data + .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_011 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_011_src_ready), // sink.ready + .sink_channel (id_router_011_src_channel), // .channel + .sink_data (id_router_011_src_data), // .data + .sink_startofpacket (id_router_011_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_011_src_endofpacket), // .endofpacket + .sink_valid (id_router_011_src_valid), // .valid + .src0_ready (rsp_xbar_demux_011_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_011_src0_valid), // .valid + .src0_data (rsp_xbar_demux_011_src0_data), // .data + .src0_channel (rsp_xbar_demux_011_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_012 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_012_src_ready), // sink.ready + .sink_channel (id_router_012_src_channel), // .channel + .sink_data (id_router_012_src_data), // .data + .sink_startofpacket (id_router_012_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_012_src_endofpacket), // .endofpacket + .sink_valid (id_router_012_src_valid), // .valid + .src0_ready (rsp_xbar_demux_012_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_012_src0_valid), // .valid + .src0_data (rsp_xbar_demux_012_src0_data), // .data + .src0_channel (rsp_xbar_demux_012_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_013 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_013_src_ready), // sink.ready + .sink_channel (id_router_013_src_channel), // .channel + .sink_data (id_router_013_src_data), // .data + .sink_startofpacket (id_router_013_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_013_src_endofpacket), // .endofpacket + .sink_valid (id_router_013_src_valid), // .valid + .src0_ready (rsp_xbar_demux_013_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_013_src0_valid), // .valid + .src0_data (rsp_xbar_demux_013_src0_data), // .data + .src0_channel (rsp_xbar_demux_013_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_013_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_014 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_014_src_ready), // sink.ready + .sink_channel (id_router_014_src_channel), // .channel + .sink_data (id_router_014_src_data), // .data + .sink_startofpacket (id_router_014_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_014_src_endofpacket), // .endofpacket + .sink_valid (id_router_014_src_valid), // .valid + .src0_ready (rsp_xbar_demux_014_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_014_src0_valid), // .valid + .src0_data (rsp_xbar_demux_014_src0_data), // .data + .src0_channel (rsp_xbar_demux_014_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_014_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_015 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_015_src_ready), // sink.ready + .sink_channel (id_router_015_src_channel), // .channel + .sink_data (id_router_015_src_data), // .data + .sink_startofpacket (id_router_015_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_015_src_endofpacket), // .endofpacket + .sink_valid (id_router_015_src_valid), // .valid + .src0_ready (rsp_xbar_demux_015_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_015_src0_valid), // .valid + .src0_data (rsp_xbar_demux_015_src0_data), // .data + .src0_channel (rsp_xbar_demux_015_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_015_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_016 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_016_src_ready), // sink.ready + .sink_channel (id_router_016_src_channel), // .channel + .sink_data (id_router_016_src_data), // .data + .sink_startofpacket (id_router_016_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_016_src_endofpacket), // .endofpacket + .sink_valid (id_router_016_src_valid), // .valid + .src0_ready (rsp_xbar_demux_016_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_016_src0_valid), // .valid + .src0_data (rsp_xbar_demux_016_src0_data), // .data + .src0_channel (rsp_xbar_demux_016_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_016_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_017 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_017_src_ready), // sink.ready + .sink_channel (id_router_017_src_channel), // .channel + .sink_data (id_router_017_src_data), // .data + .sink_startofpacket (id_router_017_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_017_src_endofpacket), // .endofpacket + .sink_valid (id_router_017_src_valid), // .valid + .src0_ready (rsp_xbar_demux_017_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_017_src0_valid), // .valid + .src0_data (rsp_xbar_demux_017_src0_data), // .data + .src0_channel (rsp_xbar_demux_017_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_mux rsp_xbar_mux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (rsp_xbar_mux_src_ready), // src.ready + .src_valid (rsp_xbar_mux_src_valid), // .valid + .src_data (rsp_xbar_mux_src_data), // .data + .src_channel (rsp_xbar_mux_src_channel), // .channel + .src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket + .sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready + .sink0_valid (rsp_xbar_demux_src0_valid), // .valid + .sink0_channel (rsp_xbar_demux_src0_channel), // .channel + .sink0_data (rsp_xbar_demux_src0_data), // .data + .sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket + .sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready + .sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid + .sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel + .sink1_data (rsp_xbar_demux_001_src0_data), // .data + .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_mux_001 rsp_xbar_mux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (rsp_xbar_mux_001_src_ready), // src.ready + .src_valid (rsp_xbar_mux_001_src_valid), // .valid + .src_data (rsp_xbar_mux_001_src_data), // .data + .src_channel (rsp_xbar_mux_001_src_channel), // .channel + .src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready + .sink0_valid (rsp_xbar_demux_src1_valid), // .valid + .sink0_channel (rsp_xbar_demux_src1_channel), // .channel + .sink0_data (rsp_xbar_demux_src1_data), // .data + .sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket + .sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready + .sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid + .sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel + .sink1_data (rsp_xbar_demux_001_src1_data), // .data + .sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket + .sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready + .sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid + .sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel + .sink2_data (rsp_xbar_demux_002_src0_data), // .data + .sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket + .sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket + .sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready + .sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid + .sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel + .sink3_data (rsp_xbar_demux_003_src0_data), // .data + .sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket + .sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket + .sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready + .sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid + .sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel + .sink4_data (rsp_xbar_demux_004_src0_data), // .data + .sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket + .sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket + .sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready + .sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid + .sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel + .sink5_data (rsp_xbar_demux_005_src0_data), // .data + .sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket + .sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket + .sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready + .sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid + .sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel + .sink6_data (rsp_xbar_demux_006_src0_data), // .data + .sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket + .sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket + .sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready + .sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid + .sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel + .sink7_data (rsp_xbar_demux_007_src0_data), // .data + .sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket + .sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket + .sink8_ready (rsp_xbar_demux_008_src0_ready), // sink8.ready + .sink8_valid (rsp_xbar_demux_008_src0_valid), // .valid + .sink8_channel (rsp_xbar_demux_008_src0_channel), // .channel + .sink8_data (rsp_xbar_demux_008_src0_data), // .data + .sink8_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket + .sink8_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket + .sink9_ready (rsp_xbar_demux_009_src0_ready), // sink9.ready + .sink9_valid (rsp_xbar_demux_009_src0_valid), // .valid + .sink9_channel (rsp_xbar_demux_009_src0_channel), // .channel + .sink9_data (rsp_xbar_demux_009_src0_data), // .data + .sink9_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket + .sink9_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket + .sink10_ready (rsp_xbar_demux_010_src0_ready), // sink10.ready + .sink10_valid (rsp_xbar_demux_010_src0_valid), // .valid + .sink10_channel (rsp_xbar_demux_010_src0_channel), // .channel + .sink10_data (rsp_xbar_demux_010_src0_data), // .data + .sink10_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket + .sink10_endofpacket (rsp_xbar_demux_010_src0_endofpacket), // .endofpacket + .sink11_ready (rsp_xbar_demux_011_src0_ready), // sink11.ready + .sink11_valid (rsp_xbar_demux_011_src0_valid), // .valid + .sink11_channel (rsp_xbar_demux_011_src0_channel), // .channel + .sink11_data (rsp_xbar_demux_011_src0_data), // .data + .sink11_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket + .sink11_endofpacket (rsp_xbar_demux_011_src0_endofpacket), // .endofpacket + .sink12_ready (rsp_xbar_demux_012_src0_ready), // sink12.ready + .sink12_valid (rsp_xbar_demux_012_src0_valid), // .valid + .sink12_channel (rsp_xbar_demux_012_src0_channel), // .channel + .sink12_data (rsp_xbar_demux_012_src0_data), // .data + .sink12_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket + .sink12_endofpacket (rsp_xbar_demux_012_src0_endofpacket), // .endofpacket + .sink13_ready (rsp_xbar_demux_013_src0_ready), // sink13.ready + .sink13_valid (rsp_xbar_demux_013_src0_valid), // .valid + .sink13_channel (rsp_xbar_demux_013_src0_channel), // .channel + .sink13_data (rsp_xbar_demux_013_src0_data), // .data + .sink13_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket + .sink13_endofpacket (rsp_xbar_demux_013_src0_endofpacket), // .endofpacket + .sink14_ready (rsp_xbar_demux_014_src0_ready), // sink14.ready + .sink14_valid (rsp_xbar_demux_014_src0_valid), // .valid + .sink14_channel (rsp_xbar_demux_014_src0_channel), // .channel + .sink14_data (rsp_xbar_demux_014_src0_data), // .data + .sink14_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket + .sink14_endofpacket (rsp_xbar_demux_014_src0_endofpacket), // .endofpacket + .sink15_ready (rsp_xbar_demux_015_src0_ready), // sink15.ready + .sink15_valid (rsp_xbar_demux_015_src0_valid), // .valid + .sink15_channel (rsp_xbar_demux_015_src0_channel), // .channel + .sink15_data (rsp_xbar_demux_015_src0_data), // .data + .sink15_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket + .sink15_endofpacket (rsp_xbar_demux_015_src0_endofpacket), // .endofpacket + .sink16_ready (rsp_xbar_demux_016_src0_ready), // sink16.ready + .sink16_valid (rsp_xbar_demux_016_src0_valid), // .valid + .sink16_channel (rsp_xbar_demux_016_src0_channel), // .channel + .sink16_data (rsp_xbar_demux_016_src0_data), // .data + .sink16_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket + .sink16_endofpacket (rsp_xbar_demux_016_src0_endofpacket), // .endofpacket + .sink17_ready (rsp_xbar_demux_017_src0_ready), // sink17.ready + .sink17_valid (rsp_xbar_demux_017_src0_valid), // .valid + .sink17_channel (rsp_xbar_demux_017_src0_channel), // .channel + .sink17_data (rsp_xbar_demux_017_src0_data), // .data + .sink17_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket + .sink17_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket + ); + + nios_system_irq_mapper irq_mapper ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq + .sender_irq (nios2_processor_d_irq_irq) // sender.irq + ); + +endmodule diff --git a/db/ip/nios_system/nios_system__report.html b/db/ip/nios_system/nios_system__report.html new file mode 100644 index 0000000..a214052 --- /dev/null +++ b/db/ip/nios_system/nios_system__report.html @@ -0,0 +1,4862 @@ + + + + + datasheet for nios_system + + + + + + + + +

nios_system

+
+
+

+ + + + + +

2017.01.26.11:05:34

Datasheet

Overview

+ + + + + + + + +

clk_0	nios_system

Processor +
   + nios2_processor + Nios II 13.0 +
All Components +
   + nios2_processor + altera_nios2_qsys 13.0 +
   + onchip_memory + altera_avalon_onchip_memory2 13.0.1.99.2 +
   + jtag_uart + altera_avalon_jtag_uart 13.0.1.99.2 +
   + LEDs + altera_avalon_pio 13.0.1.99.2 +
   + LEDRs + altera_avalon_pio 13.0.1.99.2 +
   + switches + altera_avalon_pio 13.0.1.99.2 +
   + push_switches + altera_avalon_pio 13.0.1.99.2 +
   + hex0 + altera_avalon_pio 13.0.1.99.2 +
   + hex1 + altera_avalon_pio 13.0.1.99.2 +
   + hex2 + altera_avalon_pio 13.0.1.99.2 +
   + hex3 + altera_avalon_pio 13.0.1.99.2 +
   + hex4 + altera_avalon_pio 13.0.1.99.2 +
   + hex5 + altera_avalon_pio 13.0.1.99.2 +
   + hex6 + altera_avalon_pio 13.0.1.99.2 +
   + hex7 + altera_avalon_pio 13.0.1.99.2 +
   + lcd_16207_0 + altera_avalon_lcd_16207 13.0.1.99.2 +
   + lcd_on + altera_avalon_pio 13.0.1.99.2 +
   + lcd_blon + altera_avalon_pio 13.0.1.99.2 +

Memory Map

	+ nios2_processor + +
	data_master	instruction_master
+ nios2_processor + +
jtag_debug_module	0x00040800	0x00040800
+ onchip_memory + +
s1	0x00000000	0x00000000
+ jtag_uart + +
avalon_jtag_slave	0x00041100
+ LEDs + +
s1	0x000410f0
+ LEDRs + +
s1	0x000410e0
+ switches + +
s1	0x000410d0
+ push_switches + +
s1	0x000410c0
+ hex0 + +
s1	0x000410b0
+ hex1 + +
s1	0x000410a0
+ hex2 + +
s1	0x00041090
+ hex3 + +
s1	0x00041080
+ hex4 + +
s1	0x00041070
+ hex5 + +
s1	0x00041060
+ hex6 + +
s1	0x00041050
+ hex7 + +
s1	0x00041040
+ lcd_16207_0 + +
control_slave	0x00041030
+ lcd_on + +
s1	0x00041010
+ lcd_blon + +
s1	0x00041020

+ +

clk_0

clock_source v13.0 +
+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + +

clockFrequency	50000000
clockFrequencyKnown	true
inputClockFrequency	0
resetSynchronousEdges	NONE
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

(none)

+ +

nios2_processor

altera_nios2_qsys v13.0 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	nios2_processor
	clk
	clk_reset
	reset_n
			jtag_debug_module_reset	+ onchip_memory +
			reset1
			instruction_master
			s1
			data_master
			s1

			jtag_debug_module_reset	+ jtag_uart +
			reset
			d_irq
			irq
			data_master
			avalon_jtag_slave

			jtag_debug_module_reset	+ LEDs +
			reset
			data_master
			s1

			data_master	+ LEDRs +
			s1
			jtag_debug_module_reset
			reset

			jtag_debug_module_reset	+ switches +
			reset
			data_master
			s1

			data_master	+ push_switches +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex0 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex1 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex2 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex3 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex4 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex5 +
		s1
		jtag_debug_module_reset
		reset

		data_master	+ hex6 +
		s1
		jtag_debug_module_reset
		reset

		data_master	+ hex7 +
		s1
		jtag_debug_module_reset
		reset

		jtag_debug_module_reset	+ lcd_16207_0 +
		reset
		data_master
		control_slave

		data_master	+ lcd_on +
		s1
		jtag_debug_module_reset
		reset

		jtag_debug_module_reset	+ lcd_blon +
		reset
		data_master
		s1

+
+
+ + + + +

Parameters

setting_showUnpublishedSettings	false
setting_showInternalSettings	false
setting_preciseSlaveAccessErrorException	false
setting_preciseIllegalMemAccessException	false
setting_preciseDivisionErrorException	false
setting_performanceCounter	false
setting_illegalMemAccessDetection	false
setting_illegalInstructionsTrap	false
setting_fullWaveformSignals	false
setting_extraExceptionInfo	false
setting_exportPCB	false
setting_debugSimGen	false
setting_clearXBitsLDNonBypass	true
setting_bit31BypassDCache	true
setting_bigEndian	false
setting_export_large_RAMs	false
setting_asic_enabled	false
setting_asic_synopsys_translate_on_off	false
setting_oci_export_jtag_signals	false
setting_bhtIndexPcOnly	false
setting_avalonDebugPortPresent	false
setting_alwaysEncrypt	true
setting_allowFullAddressRange	false
setting_activateTrace	true
setting_activateTestEndChecker	false
setting_activateMonitors	true
setting_activateModelChecker	false
setting_HDLSimCachesCleared	true
setting_HBreakTest	false
muldiv_divider	false
mpu_useLimit	false
mpu_enabled	false
mmu_enabled	false
mmu_autoAssignTlbPtrSz	true
manuallyAssignCpuID	true
debug_triggerArming	true
debug_embeddedPLL	true
debug_debugReqSignals	false
debug_assignJtagInstanceID	false
dcache_omitDataMaster	false
cpuReset	false
is_hardcopy_compatible	false
setting_shadowRegisterSets	0
mpu_numOfInstRegion	8
mpu_numOfDataRegion	8
mmu_TLBMissExcOffset	0
debug_jtagInstanceID	0
resetOffset	0
exceptionOffset	32
cpuID	0
cpuID_stored	0
breakOffset	32
userDefinedSettings
resetSlave	onchip_memory.s1
mmu_TLBMissExcSlave	None
exceptionSlave	onchip_memory.s1
breakSlave	nios2_processor.jtag_debug_module
setting_perfCounterWidth	32
setting_interruptControllerType	Internal
setting_branchPredictionType	Automatic
setting_bhtPtrSz	8
muldiv_multiplierType	EmbeddedMulFast
mpu_minInstRegionSize	12
mpu_minDataRegionSize	12
mmu_uitlbNumEntries	4
mmu_udtlbNumEntries	6
mmu_tlbPtrSz	7
mmu_tlbNumWays	16
mmu_processIDNumBits	8
impl	Tiny
icache_size	4096
icache_tagramBlockType	Automatic
icache_ramBlockType	Automatic
icache_numTCIM	0
icache_burstType	None
dcache_bursts	false
dcache_victim_buf_impl	ram
debug_level	Level1
debug_OCIOnchipTrace	_128
dcache_size	2048
dcache_tagramBlockType	Automatic
dcache_ramBlockType	Automatic
dcache_numTCDM	0
dcache_lineSize	32
setting_exportvectors	false
setting_ecc_present	false
regfile_ramBlockType	Automatic
ocimem_ramBlockType	Automatic
mmu_ramBlockType	Automatic
bht_ramBlockType	Automatic
resetAbsoluteAddr	0
exceptionAbsoluteAddr	32
breakAbsoluteAddr	264224
mmu_TLBMissExcAbsAddr	0
dcache_bursts_derived	false
dcache_size_derived	2048
dcache_lineSize_derived	32
translate_on	"synthesis translate_on"
translate_off	"synthesis translate_off"
instAddrWidth	19
dataAddrWidth	19
tightlyCoupledDataMaster0AddrWidth	1
tightlyCoupledDataMaster1AddrWidth	1
tightlyCoupledDataMaster2AddrWidth	1
tightlyCoupledDataMaster3AddrWidth	1
tightlyCoupledInstructionMaster0AddrWidth	1
tightlyCoupledInstructionMaster1AddrWidth	1
tightlyCoupledInstructionMaster2AddrWidth	1
tightlyCoupledInstructionMaster3AddrWidth	1
instSlaveMapParam	<address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='nios2_processor.jtag_debug_module' start='0x40800' end='0x41000' /></address-map>
dataSlaveMapParam	<address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='nios2_processor.jtag_debug_module' start='0x40800' end='0x41000' /><slave name='lcd_on.s1' start='0x41010' end='0x41020' /><slave name='lcd_blon.s1' start='0x41020' end='0x41030' /><slave name='lcd_16207_0.control_slave' start='0x41030' end='0x41040' /><slave name='hex7.s1' start='0x41040' end='0x41050' /><slave name='hex6.s1' start='0x41050' end='0x41060' /><slave name='hex5.s1' start='0x41060' end='0x41070' /><slave name='hex4.s1' start='0x41070' end='0x41080' /><slave name='hex3.s1' start='0x41080' end='0x41090' /><slave name='hex2.s1' start='0x41090' end='0x410A0' /><slave name='hex1.s1' start='0x410A0' end='0x410B0' /><slave name='hex0.s1' start='0x410B0' end='0x410C0' /><slave name='push_switches.s1' start='0x410C0' end='0x410D0' /><slave name='switches.s1' start='0x410D0' end='0x410E0' /><slave name='LEDRs.s1' start='0x410E0' end='0x410F0' /><slave name='LEDs.s1' start='0x410F0' end='0x41100' /><slave name='jtag_uart.avalon_jtag_slave' start='0x41100' end='0x41108' /></address-map>
clockFrequency	50000000
deviceFamilyName	CYCLONEIVE
internalIrqMaskSystemInfo	32
customInstSlavesSystemInfo	<info/>
deviceFeaturesSystemInfo	ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIG_ENDIAN	0
BREAK_ADDR	0x00040820
CPU_FREQ	50000000u
CPU_ID_SIZE	1
CPU_ID_VALUE	0x00000000
CPU_IMPLEMENTATION	"tiny"
DATA_ADDR_WIDTH	19
DCACHE_LINE_SIZE	0
DCACHE_LINE_SIZE_LOG2	0
DCACHE_SIZE	0
EXCEPTION_ADDR	0x00000020
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT	0
HARDWARE_MULTIPLY_PRESENT	0
HARDWARE_MULX_PRESENT	0
HAS_DEBUG_CORE	1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE	0
ICACHE_LINE_SIZE_LOG2	0
ICACHE_SIZE	0
INST_ADDR_WIDTH	19
RESET_ADDR	0x00000000

+ +

onchip_memory

altera_avalon_onchip_memory2 v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	onchip_memory
	clk1
	clk_reset
	reset1

+ nios2_processor +	jtag_debug_module_reset
	reset1
	instruction_master
	s1
	data_master
	s1

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

allowInSystemMemoryContentEditor	false
blockType	AUTO
dataWidth	32
dualPort	false
initMemContent	true
initializationFileName	onchip_mem.hex
instanceID	NONE
memorySize	204800
readDuringWriteMode	DONT_CARE
simAllowMRAMContentsFile	false
simMemInitOnlyFilename	0
singleClockOperation	false
slave1Latency	1
slave2Latency	1
useNonDefaultInitFile	false
useShallowMemBlocks	false
writable	true
autoInitializationFileName	nios_system_onchip_memory
deviceFamily	CYCLONEIVE
deviceFeatures	ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width	16
derived_gui_ram_block_type	Automatic
derived_is_hardcopy	false
derived_init_file_name	nios_system_onchip_memory.hex
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR	0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE	0
CONTENTS_INFO	""
DUAL_PORT	0
GUI_RAM_BLOCK_TYPE	AUTO
INIT_CONTENTS_FILE	nios_system_onchip_memory
INIT_MEM_CONTENT	1
INSTANCE_ID	NONE
NON_DEFAULT_INIT_FILE_ENABLED	0
RAM_BLOCK_TYPE	AUTO
READ_DURING_WRITE_MODE	DONT_CARE
SINGLE_CLOCK_OP	0
SIZE_MULTIPLE	1
SIZE_VALUE	204800
WRITABLE	1

+ +

jtag_uart

altera_avalon_jtag_uart v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ nios2_processor +	jtag_debug_module_reset	jtag_uart
	reset
	d_irq
	irq
	data_master
	avalon_jtag_slave

+ clk_0 +	clk_reset
	reset
	clk
	clk

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

allowMultipleConnections	false
hubInstanceID	0
readBufferDepth	64
readIRQThreshold	8
simInputCharacterStream
simInteractiveOptions	NO_INTERACTIVE_WINDOWS
useRegistersForReadBuffer	false
useRegistersForWriteBuffer	false
useRelativePathForSimFile	false
writeBufferDepth	64
writeIRQThreshold	8
avalonSpec	2.0
legacySignalAllow	false
enableInteractiveInput	false
enableInteractiveOutput	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + +

READ_DEPTH	64
READ_THRESHOLD	8
WRITE_DEPTH	64
WRITE_THRESHOLD	8

+ +

LEDs

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	LEDs
	clk
	clk_reset
	reset

+ nios2_processor +	jtag_debug_module_reset
	reset
	data_master
	s1

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	8
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	8
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

LEDRs

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	LEDRs
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	18
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	18
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

switches

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	switches
	clk
	clk_reset
	reset

+ nios2_processor +	jtag_debug_module_reset
	reset
	data_master
	s1

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Input
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	18
clockRate	50000000
derived_has_tri	false
derived_has_out	false
derived_has_in	true
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	18
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	1
HAS_OUT	0
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

push_switches

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	push_switches
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Input
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	3
clockRate	50000000
derived_has_tri	false
derived_has_out	false
derived_has_in	true
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	3
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	1
HAS_OUT	0
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex0

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex0
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex1

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex1
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex2

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex2
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex3

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex3
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex4

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex4
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex5

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex5
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex6

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex6
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex7

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex7
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

lcd_16207_0

altera_avalon_lcd_16207 v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	lcd_16207_0
	clk
	clk_reset
	reset

+ nios2_processor +	jtag_debug_module_reset
	reset
	data_master
	control_slave

+
+
+ + + + +

Parameters

+ + + + + + + + + +

deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

(none)

+ +

lcd_on

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	lcd_on
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	1
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	1
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

lcd_blon

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	lcd_blon
	clk
	clk_reset
	reset

+ nios2_processor +	jtag_debug_module_reset
	reset
	data_master
	s1

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	1
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	1
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ + + + + +

generation took 0.00 seconds

rendering took 0.16 seconds

+ + diff --git a/db/ip/nios_system/nios_system__report.xml b/db/ip/nios_system/nios_system__report.xml new file mode 100644 index 0000000..e4e96f0 --- /dev/null +++ b/db/ip/nios_system/nios_system__report.xml @@ -0,0 +1,2521 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 0 starting:nios_system "nios_system" + Transform: PipelineBridgeSwap + 19 modules, 75 connections]]> + Transform: ClockCrossingBridgeSwap + Transform: QsysBetaIPSwap + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + Transform: MMTransform + Transform: TranslatorTransform + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 39 modules, 155 connections]]> + Transform: IDPadTransform + Transform: DomainTransform + Transform merlin_domain_transform not run on matched interfaces nios2_processor.instruction_master and nios2_processor_instruction_master_translator.avalon_anti_master_0 + Transform merlin_domain_transform not run on matched interfaces nios2_processor.data_master and nios2_processor_data_master_translator.avalon_anti_master_0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Transform merlin_domain_transform not run on matched interfaces nios2_processor_jtag_debug_module_translator.avalon_anti_slave_0 and nios2_processor.jtag_debug_module + Transform merlin_domain_transform not run on matched interfaces onchip_memory_s1_translator.avalon_anti_slave_0 and onchip_memory.s1 + Transform merlin_domain_transform not run on matched interfaces LEDs_s1_translator.avalon_anti_slave_0 and LEDs.s1 + Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave + Transform merlin_domain_transform not run on matched interfaces LEDRs_s1_translator.avalon_anti_slave_0 and LEDRs.s1 + Transform merlin_domain_transform not run on matched interfaces switches_s1_translator.avalon_anti_slave_0 and switches.s1 + Transform merlin_domain_transform not run on matched interfaces push_switches_s1_translator.avalon_anti_slave_0 and push_switches.s1 + Transform merlin_domain_transform not run on matched interfaces hex0_s1_translator.avalon_anti_slave_0 and hex0.s1 + Transform merlin_domain_transform not run on matched interfaces hex1_s1_translator.avalon_anti_slave_0 and hex1.s1 + Transform merlin_domain_transform not run on matched interfaces hex2_s1_translator.avalon_anti_slave_0 and hex2.s1 + Transform merlin_domain_transform not run on matched interfaces hex3_s1_translator.avalon_anti_slave_0 and hex3.s1 + Transform merlin_domain_transform not run on matched interfaces hex4_s1_translator.avalon_anti_slave_0 and hex4.s1 + Transform merlin_domain_transform not run on matched interfaces hex5_s1_translator.avalon_anti_slave_0 and hex5.s1 + Transform merlin_domain_transform not run on matched interfaces hex6_s1_translator.avalon_anti_slave_0 and hex6.s1 + Transform merlin_domain_transform not run on matched interfaces hex7_s1_translator.avalon_anti_slave_0 and hex7.s1 + Transform merlin_domain_transform not run on matched interfaces lcd_16207_0_control_slave_translator.avalon_anti_slave_0 and lcd_16207_0.control_slave + Transform merlin_domain_transform not run on matched interfaces lcd_on_s1_translator.avalon_anti_slave_0 and lcd_on.s1 + Transform merlin_domain_transform not run on matched interfaces lcd_blon_s1_translator.avalon_anti_slave_0 and lcd_blon.s1 + 78 modules, 423 connections]]> + Transform: RouterTransform + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 98 modules, 503 connections]]> + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: CombinedWidthTransform + Transform: ResetAdaptation + + + + 99 modules, 390 connections]]> + Transform: NetworkToSwitchTransform + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 138 modules, 470 connections]]> + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: TrafficLimiterUpdateTransform + 138 modules, 470 connections]]> + Transform: InterruptMapperTransform + + + + 139 modules, 473 connections]]> + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + "No matching role found for rst_controller:reset_out:reset_req (reset_req)" + nios_system" reuses altera_nios2_qsys "submodules/nios_system_nios2_processor"]]> + nios_system" reuses altera_avalon_onchip_memory2 "submodules/nios_system_onchip_memory"]]> + nios_system" reuses altera_avalon_jtag_uart "submodules/nios_system_jtag_uart"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_LEDs"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_LEDRs"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_switches"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_push_switches"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_hex0"]]> + nios_system" reuses altera_avalon_lcd_16207 "submodules/nios_system_lcd_16207_0"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_lcd_on"]]> + nios_system" reuses altera_avalon_pio "submodules/nios_system_lcd_on"]]> + nios_system" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + nios_system" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + nios_system" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + nios_system" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + nios_system" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_addr_router"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_addr_router_001"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_merlin_router "submodules/nios_system_id_router_002"]]> + nios_system" reuses altera_reset_controller "submodules/altera_reset_controller"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux_001"]]> + nios_system" reuses altera_merlin_multiplexer "submodules/nios_system_cmd_xbar_mux"]]> + nios_system" reuses altera_merlin_multiplexer "submodules/nios_system_cmd_xbar_mux"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002"]]> + nios_system" reuses altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux"]]> + nios_system" reuses altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux_001"]]> + nios_system" reuses altera_irq_mapper "submodules/nios_system_irq_mapper"]]> + queue size: 121 starting:altera_nios2_qsys "submodules/nios_system_nios2_processor" + Starting RTL generation for module 'nios_system_nios2_processor' + Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] + # 2017.01.26 11:05:40 (*) Starting Nios II generation + # 2017.01.26 11:05:40 (*) Checking for plaintext license. + # 2017.01.26 11:05:41 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus + # 2017.01.26 11:05:41 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2017.01.26 11:05:41 (*) LM_LICENSE_FILE environment variable is empty + # 2017.01.26 11:05:41 (*) Plaintext license not found. + # 2017.01.26 11:05:41 (*) No license required to generate encrypted Nios II/e. + # 2017.01.26 11:05:41 (*) Elaborating CPU configuration settings + # 2017.01.26 11:05:41 (*) Creating all objects for CPU + # 2017.01.26 11:05:42 (*) Generating RTL from CPU objects + # 2017.01.26 11:05:42 (*) Creating plain-text RTL + # 2017.01.26 11:05:44 (*) Done Nios II generation + Done RTL generation for module 'nios_system_nios2_processor' + nios_system" instantiated altera_nios2_qsys "nios2_processor"]]> + queue size: 120 starting:altera_avalon_onchip_memory2 "submodules/nios_system_onchip_memory" + Starting RTL generation for module 'nios_system_onchip_memory' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_onchip_memory' + nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory"]]> + queue size: 119 starting:altera_avalon_jtag_uart "submodules/nios_system_jtag_uart" + Starting RTL generation for module 'nios_system_jtag_uart' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_jtag_uart' + nios_system" instantiated altera_avalon_jtag_uart "jtag_uart"]]> + queue size: 118 starting:altera_avalon_pio "submodules/nios_system_LEDs" + Starting RTL generation for module 'nios_system_LEDs' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_LEDs' + nios_system" instantiated altera_avalon_pio "LEDs"]]> + queue size: 117 starting:altera_avalon_pio "submodules/nios_system_LEDRs" + Starting RTL generation for module 'nios_system_LEDRs' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_LEDRs' + nios_system" instantiated altera_avalon_pio "LEDRs"]]> + queue size: 116 starting:altera_avalon_pio "submodules/nios_system_switches" + Starting RTL generation for module 'nios_system_switches' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_switches' + nios_system" instantiated altera_avalon_pio "switches"]]> + queue size: 115 starting:altera_avalon_pio "submodules/nios_system_push_switches" + Starting RTL generation for module 'nios_system_push_switches' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_push_switches' + nios_system" instantiated altera_avalon_pio "push_switches"]]> + queue size: 114 starting:altera_avalon_pio "submodules/nios_system_hex0" + Starting RTL generation for module 'nios_system_hex0' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_hex0' + nios_system" instantiated altera_avalon_pio "hex0"]]> + queue size: 106 starting:altera_avalon_lcd_16207 "submodules/nios_system_lcd_16207_0" + Starting RTL generation for module 'nios_system_lcd_16207_0' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_lcd_16207_0' + nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0"]]> + queue size: 105 starting:altera_avalon_pio "submodules/nios_system_lcd_on" + Starting RTL generation for module 'nios_system_lcd_on' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_lcd_on' + nios_system" instantiated altera_avalon_pio "lcd_on"]]> + queue size: 103 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator"]]> + queue size: 101 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator"]]> + queue size: 83 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent"]]> + queue size: 81 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent"]]> + queue size: 80 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo"]]> + queue size: 45 starting:altera_merlin_router "submodules/nios_system_addr_router" + nios_system" instantiated altera_merlin_router "addr_router"]]> + queue size: 44 starting:altera_merlin_router "submodules/nios_system_addr_router_001" + nios_system" instantiated altera_merlin_router "addr_router_001"]]> + queue size: 43 starting:altera_merlin_router "submodules/nios_system_id_router" + nios_system" instantiated altera_merlin_router "id_router"]]> + queue size: 41 starting:altera_merlin_router "submodules/nios_system_id_router_002" + nios_system" instantiated altera_merlin_router "id_router_002"]]> + queue size: 25 starting:altera_reset_controller "submodules/altera_reset_controller" + nios_system" instantiated altera_reset_controller "rst_controller"]]> + queue size: 24 starting:altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux" + nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"]]> + queue size: 23 starting:altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux_001" + nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001"]]> + queue size: 22 starting:altera_merlin_multiplexer "submodules/nios_system_cmd_xbar_mux" + nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux"]]> + queue size: 18 starting:altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002" + nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002"]]> + queue size: 2 starting:altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux" + nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux"]]> + C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv]]> + queue size: 1 starting:altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux_001" + nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001"]]> + C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv]]> + queue size: 0 starting:altera_irq_mapper "submodules/nios_system_irq_mapper" + nios_system" instantiated altera_irq_mapper "irq_mapper"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 121 starting:altera_nios2_qsys "submodules/nios_system_nios2_processor" + Starting RTL generation for module 'nios_system_nios2_processor' + Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] + # 2017.01.26 11:05:40 (*) Starting Nios II generation + # 2017.01.26 11:05:40 (*) Checking for plaintext license. + # 2017.01.26 11:05:41 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus + # 2017.01.26 11:05:41 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2017.01.26 11:05:41 (*) LM_LICENSE_FILE environment variable is empty + # 2017.01.26 11:05:41 (*) Plaintext license not found. + # 2017.01.26 11:05:41 (*) No license required to generate encrypted Nios II/e. + # 2017.01.26 11:05:41 (*) Elaborating CPU configuration settings + # 2017.01.26 11:05:41 (*) Creating all objects for CPU + # 2017.01.26 11:05:42 (*) Generating RTL from CPU objects + # 2017.01.26 11:05:42 (*) Creating plain-text RTL + # 2017.01.26 11:05:44 (*) Done Nios II generation + Done RTL generation for module 'nios_system_nios2_processor' + nios_system" instantiated altera_nios2_qsys "nios2_processor"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 120 starting:altera_avalon_onchip_memory2 "submodules/nios_system_onchip_memory" + Starting RTL generation for module 'nios_system_onchip_memory' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_onchip_memory' + nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 119 starting:altera_avalon_jtag_uart "submodules/nios_system_jtag_uart" + Starting RTL generation for module 'nios_system_jtag_uart' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_jtag_uart' + nios_system" instantiated altera_avalon_jtag_uart "jtag_uart"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 118 starting:altera_avalon_pio "submodules/nios_system_LEDs" + Starting RTL generation for module 'nios_system_LEDs' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_LEDs' + nios_system" instantiated altera_avalon_pio "LEDs"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 117 starting:altera_avalon_pio "submodules/nios_system_LEDRs" + Starting RTL generation for module 'nios_system_LEDRs' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_LEDRs' + nios_system" instantiated altera_avalon_pio "LEDRs"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 116 starting:altera_avalon_pio "submodules/nios_system_switches" + Starting RTL generation for module 'nios_system_switches' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_switches' + nios_system" instantiated altera_avalon_pio "switches"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 115 starting:altera_avalon_pio "submodules/nios_system_push_switches" + Starting RTL generation for module 'nios_system_push_switches' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_push_switches' + nios_system" instantiated altera_avalon_pio "push_switches"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 114 starting:altera_avalon_pio "submodules/nios_system_hex0" + Starting RTL generation for module 'nios_system_hex0' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_hex0' + nios_system" instantiated altera_avalon_pio "hex0"]]> + + + + + + + + + + + + + + queue size: 106 starting:altera_avalon_lcd_16207 "submodules/nios_system_lcd_16207_0" + Starting RTL generation for module 'nios_system_lcd_16207_0' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_lcd_16207_0' + nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 105 starting:altera_avalon_pio "submodules/nios_system_lcd_on" + Starting RTL generation for module 'nios_system_lcd_on' + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7192_4423007586961821325.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'nios_system_lcd_on' + nios_system" instantiated altera_avalon_pio "lcd_on"]]> + + + + + + + + + + + + + + + queue size: 103 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator"]]> + + + + + + + + + + + + + + queue size: 101 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator"]]> + + + + + + + + + + + + + + + + + + + queue size: 83 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent"]]> + + + + + + + + + + + + + + + + + + + + + queue size: 81 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent"]]> + + + + + + + + + + + + + + + + queue size: 80 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo"]]> + + + + + + + + + + + + + + + queue size: 45 starting:altera_merlin_router "submodules/nios_system_addr_router" + nios_system" instantiated altera_merlin_router "addr_router"]]> + + + + + + + + + + + + + + + queue size: 44 starting:altera_merlin_router "submodules/nios_system_addr_router_001" + nios_system" instantiated altera_merlin_router "addr_router_001"]]> + + + + + + + + + + + + + + + queue size: 43 starting:altera_merlin_router "submodules/nios_system_id_router" + nios_system" instantiated altera_merlin_router "id_router"]]> + + + + + + + + + + + + + + + queue size: 41 starting:altera_merlin_router "submodules/nios_system_id_router_002" + nios_system" instantiated altera_merlin_router "id_router_002"]]> + + + + + + + + + + + + + + + + + queue size: 25 starting:altera_reset_controller "submodules/altera_reset_controller" + nios_system" instantiated altera_reset_controller "rst_controller"]]> + + + + + + + + + + + + + + + + + + + + + queue size: 24 starting:altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux" + nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"]]> + + + + + + + + + + + + + + + + + + + + + queue size: 23 starting:altera_merlin_demultiplexer "submodules/nios_system_cmd_xbar_demux_001" + nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 22 starting:altera_merlin_multiplexer "submodules/nios_system_cmd_xbar_mux" + nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux"]]> + + + + + + + + + + + + + + + + + + + + + queue size: 18 starting:altera_merlin_demultiplexer "submodules/nios_system_rsp_xbar_demux_002" + nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 2 starting:altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux" + nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux"]]> + C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 1 starting:altera_merlin_multiplexer "submodules/nios_system_rsp_xbar_mux_001" + nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001"]]> + C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv]]> + + + + + + + + + + + + + + + + + + queue size: 0 starting:altera_irq_mapper "submodules/nios_system_irq_mapper" + nios_system" instantiated altera_irq_mapper "irq_mapper"]]> + + + diff --git a/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v b/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v new file mode 100644 index 0000000..94e2787 --- /dev/null +++ b/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v @@ -0,0 +1,877 @@ +// ----------------------------------------------------------- +// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your +// use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any +// output files any of the foregoing (including device programming or +// simulation files), and any associated documentation or information are +// expressly subject to the terms and conditions of the Altera Program +// License Subscription Agreement or other applicable license agreement, +// including, without limitation, that your use is for the sole purpose +// of programming logic devices manufactured by Altera and sold by Altera +// or its authorized distributors. Please refer to the applicable +// agreement for further details. +// +// Description: Single clock Avalon-ST FIFO. +// ----------------------------------------------------------- + +`timescale 1 ns / 1 ns + + +//altera message_off 10036 +module altera_avalon_sc_fifo +#( + // -------------------------------------------------- + // Parameters + // -------------------------------------------------- + parameter SYMBOLS_PER_BEAT = 1, + parameter BITS_PER_SYMBOL = 8, + parameter FIFO_DEPTH = 16, + parameter CHANNEL_WIDTH = 0, + parameter ERROR_WIDTH = 0, + parameter USE_PACKETS = 0, + parameter USE_FILL_LEVEL = 0, + parameter USE_STORE_FORWARD = 0, + parameter USE_ALMOST_FULL_IF = 0, + parameter USE_ALMOST_EMPTY_IF = 0, + + // -------------------------------------------------- + // Empty latency is defined as the number of cycles + // required for a write to deassert the empty flag. + // For example, a latency of 1 means that the empty + // flag is deasserted on the cycle after a write. + // + // Another way to think of it is the latency for a + // write to propagate to the output. + // + // An empty latency of 0 implies lookahead, which is + // only implemented for the register-based FIFO. + // -------------------------------------------------- + parameter EMPTY_LATENCY = 3, + parameter USE_MEMORY_BLOCKS = 1, + + // -------------------------------------------------- + // Internal Parameters + // -------------------------------------------------- + parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, + parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) +) +( + // -------------------------------------------------- + // Ports + // -------------------------------------------------- + input clk, + input reset, + + input [DATA_WIDTH-1: 0] in_data, + input in_valid, + input in_startofpacket, + input in_endofpacket, + input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, + input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, + input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, + output in_ready, + + output [DATA_WIDTH-1 : 0] out_data, + output reg out_valid, + output out_startofpacket, + output out_endofpacket, + output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, + output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, + output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, + input out_ready, + + input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, + input csr_write, + input csr_read, + input [31 : 0] csr_writedata, + output reg [31 : 0] csr_readdata, + + output wire almost_full_data, + output wire almost_empty_data +); + + // -------------------------------------------------- + // Local Parameters + // -------------------------------------------------- + localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); + localparam DEPTH = FIFO_DEPTH; + localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; + localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? + 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; + + // -------------------------------------------------- + // Internal Signals + // -------------------------------------------------- + genvar i; + + reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; + reg [ADDR_WIDTH-1 : 0] wr_ptr; + reg [ADDR_WIDTH-1 : 0] rd_ptr; + reg [DEPTH-1 : 0] mem_used; + + wire [ADDR_WIDTH-1 : 0] next_wr_ptr; + wire [ADDR_WIDTH-1 : 0] next_rd_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; + + wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; + + wire read; + wire write; + + reg empty; + reg next_empty; + reg full; + reg next_full; + + wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; + wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; + wire [PAYLOAD_WIDTH-1 : 0] in_payload; + reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; + reg [PAYLOAD_WIDTH-1 : 0] out_payload; + + reg internal_out_valid; + wire internal_out_ready; + + reg [ADDR_WIDTH : 0] fifo_fill_level; + reg [ADDR_WIDTH : 0] fill_level; + + reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; + reg [23:0] almost_full_threshold; + reg [23:0] almost_empty_threshold; + reg [23:0] cut_through_threshold; + reg [15:0] pkt_cnt; + reg [15:0] pkt_cnt_r; + reg [15:0] pkt_cnt_plusone; + reg [15:0] pkt_cnt_minusone; + reg drop_on_error_en; + reg error_in_pkt; + reg pkt_has_started; + reg sop_has_left_fifo; + reg fifo_too_small_r; + reg pkt_cnt_eq_zero; + reg pkt_cnt_eq_one; + reg pkt_cnt_changed; + + wire wait_for_threshold; + reg pkt_mode; + wire wait_for_pkt; + wire ok_to_forward; + wire in_pkt_eop_arrive; + wire out_pkt_leave; + wire in_pkt_start; + wire in_pkt_error; + wire drop_on_error; + wire fifo_too_small; + wire out_pkt_sop_leave; + wire [31:0] max_fifo_size; + reg fifo_fill_level_lt_cut_through_threshold; + + // -------------------------------------------------- + // Define Payload + // + // Icky part where we decide which signals form the + // payload to the FIFO with generate blocks. + // -------------------------------------------------- + generate + if (EMPTY_WIDTH > 0) begin + assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; + assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; + end + else begin + assign out_empty = in_error; + assign in_packet_signals = {in_startofpacket, in_endofpacket}; + assign {out_startofpacket, out_endofpacket} = out_packet_signals; + end + endgenerate + + generate + if (USE_PACKETS) begin + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; + assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data, in_error}; + assign {out_packet_signals, out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_channel}; + assign {out_packet_signals, out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data}; + assign {out_packet_signals, out_data} = out_payload; + end + end + end + else begin + assign out_packet_signals = 0; + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_error, in_channel}; + assign {out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_data, in_error}; + assign {out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_channel}; + assign {out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = in_data; + assign out_data = out_payload; + end + end + end + endgenerate + + // -------------------------------------------------- + // Memory-based FIFO storage + // + // To allow a ready latency of 0, the read index is + // obtained from the next read pointer and memory + // outputs are unregistered. + // + // If the empty latency is 1, we infer bypass logic + // around the memory so writes propagate to the + // outputs on the next cycle. + // + // Do not change the way this is coded: Quartus needs + // a perfect match to the template, and any attempt to + // refactor the two always blocks into one will break + // memory inference. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + if (EMPTY_LATENCY == 1) begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] = in_payload; + + internal_out_payload = mem[mem_rd_ptr]; + end + + end else begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] <= in_payload; + + internal_out_payload <= mem[mem_rd_ptr]; + end + + end + + assign mem_rd_ptr = next_rd_ptr; + + end else begin + + // -------------------------------------------------- + // Register-based FIFO storage + // + // Uses a shift register as the storage element. Each + // shift register slot has a bit which indicates if + // the slot is occupied (credit to Sam H for the idea). + // The occupancy bits are contiguous and start from the + // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep + // FIFO. + // + // Each slot is enabled during a read or when it + // is unoccupied. New data is always written to every + // going-to-be-empty slot (we keep track of which ones + // are actually useful with the occupancy bits). On a + // read we shift occupied slots. + // + // The exception is the last slot, which always gets + // new data when it is unoccupied. + // -------------------------------------------------- + for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg + always @(posedge clk or posedge reset) begin + if (reset) begin + mem[i] <= 0; + end + else if (read || !mem_used[i]) begin + if (!mem_used[i+1]) + mem[i] <= in_payload; + else + mem[i] <= mem[i+1]; + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + mem[DEPTH-1] <= 0; + end + else begin + if (!mem_used[DEPTH-1]) + mem[DEPTH-1] <= in_payload; + + if (DEPTH == 1) begin + if (write) + mem[DEPTH-1] <= in_payload; + end + end + end + + end + endgenerate + + assign read = internal_out_ready && internal_out_valid && ok_to_forward; + assign write = in_ready && in_valid; + + // -------------------------------------------------- + // Pointer Management + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + assign incremented_wr_ptr = wr_ptr + 1'b1; + assign incremented_rd_ptr = rd_ptr + 1'b1; + assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; + assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; + + always @(posedge clk or posedge reset) begin + if (reset) begin + wr_ptr <= 0; + rd_ptr <= 0; + end + else begin + wr_ptr <= next_wr_ptr; + rd_ptr <= next_rd_ptr; + end + end + + end else begin + + // -------------------------------------------------- + // Shift Register Occupancy Bits + // + // Consider a 4-deep FIFO with 2 entries: 0011 + // On a read and write, do not modify the bits. + // On a write, left-shift the bits to get 0111. + // On a read, right-shift the bits to get 0001. + // + // Also, on a write we set bit0 (the head), while + // clearing the tail on a read. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[0] <= 0; + end + else begin + if (write ^ read) begin + if (read) begin + if (DEPTH > 1) + mem_used[0] <= mem_used[1]; + else + mem_used[0] <= 0; + end + if (write) + mem_used[0] <= 1; + end + end + end + + if (DEPTH > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[DEPTH-1] <= 0; + end + else begin + if (write ^ read) begin + mem_used[DEPTH-1] <= 0; + if (write) + mem_used[DEPTH-1] <= mem_used[DEPTH-2]; + end + end + end + end + + for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic + always @(posedge clk, posedge reset) begin + if (reset) begin + mem_used[i] <= 0; + end + else begin + if (write ^ read) begin + if (read) + mem_used[i] <= mem_used[i+1]; + if (write) + mem_used[i] <= mem_used[i-1]; + end + end + end + end + + end + endgenerate + + + // -------------------------------------------------- + // Memory FIFO Status Management + // + // Generates the full and empty signals from the + // pointers. The FIFO is full when the next write + // pointer will be equal to the read pointer after + // a write. Reading from a FIFO clears full. + // + // The FIFO is empty when the next read pointer will + // be equal to the write pointer after a read. Writing + // to a FIFO clears empty. + // + // A simultaneous read and write must not change any of + // the empty or full flags unless there is a drop on error event. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + always @* begin + next_full = full; + next_empty = empty; + + if (read && !write) begin + next_full = 1'b0; + + if (incremented_rd_ptr == wr_ptr) + next_empty = 1'b1; + end + + if (write && !read) begin + if (!drop_on_error) + next_empty = 1'b0; + else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo + next_empty = 1'b1; + + if (incremented_wr_ptr == rd_ptr && !drop_on_error) + next_full = 1'b1; + end + + if (write && read && drop_on_error) begin + if (sop_ptr == next_rd_ptr) + next_empty = 1'b1; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + empty <= 1; + full <= 0; + end + else begin + empty <= next_empty; + full <= next_full; + end + end + + end else begin + // -------------------------------------------------- + // Register FIFO Status Management + // + // Full when the tail occupancy bit is 1. Empty when + // the head occupancy bit is 0. + // -------------------------------------------------- + always @* begin + full = mem_used[DEPTH-1]; + empty = !mem_used[0]; + + // ------------------------------------------ + // For a single slot FIFO, reading clears the + // full status immediately. + // ------------------------------------------ + if (DEPTH == 1) + full = mem_used[0] && !read; + + internal_out_payload = mem[0]; + + // ------------------------------------------ + // Writes clear empty immediately for lookahead modes. + // Note that we use in_valid instead of write to avoid + // combinational loops (in lookahead mode, qualifying + // with in_ready is meaningless). + // + // In a 1-deep FIFO, a possible combinational loop runs + // from write -> out_valid -> out_ready -> write + // ------------------------------------------ + if (EMPTY_LATENCY == 0) begin + empty = !mem_used[0] && !in_valid; + + if (!mem_used[0] && in_valid) + internal_out_payload = in_payload; + end + end + + end + endgenerate + + // -------------------------------------------------- + // Avalon-ST Signals + // + // The in_ready signal is straightforward. + // + // To match memory latency when empty latency > 1, + // out_valid assertions must be delayed by one clock + // cycle. + // + // Note: out_valid deassertions must not be delayed or + // the FIFO will underflow. + // -------------------------------------------------- + assign in_ready = !full; + assign internal_out_ready = out_ready || !out_valid; + + generate if (EMPTY_LATENCY > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) + internal_out_valid <= 0; + else begin + internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; + + if (read) begin + if (incremented_rd_ptr == wr_ptr) + internal_out_valid <= 1'b0; + end + end + end + end else begin + always @* begin + internal_out_valid = !empty & ok_to_forward; + end + end + endgenerate + + // -------------------------------------------------- + // Single Output Pipeline Stage + // + // This output pipeline stage is enabled if the FIFO's + // empty latency is set to 3 (default). It is disabled + // for all other allowed latencies. + // + // Reason: The memory outputs are unregistered, so we have to + // register the output or fmax will drop if combinatorial + // logic is present on the output datapath. + // + // Q: The Avalon-ST spec says that I have to register my outputs + // But isn't the memory counted as a register? + // A: The path from the address lookup to the memory output is + // slow. Registering the memory outputs is a good idea. + // + // The registers get packed into the memory by the fitter + // which means minimal resources are consumed (the result + // is a altsyncram with registered outputs, available on + // all modern Altera devices). + // + // This output stage acts as an extra slot in the FIFO, + // and complicates the fill level. + // -------------------------------------------------- + generate if (EMPTY_LATENCY == 3) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + out_valid <= 0; + out_payload <= 0; + end + else begin + if (internal_out_ready) begin + out_valid <= internal_out_valid & ok_to_forward; + out_payload <= internal_out_payload; + end + end + end + end + else begin + always @* begin + out_valid = internal_out_valid; + out_payload = internal_out_payload; + end + end + endgenerate + + // -------------------------------------------------- + // Fill Level + // + // The fill level is calculated from the next write + // and read pointers to avoid unnecessary latency. + // + // If the output pipeline is enabled, the fill level + // must account for it, or we'll always be off by one. + // This may, or may not be important depending on the + // application. + // + // For now, we'll always calculate the exact fill level + // at the cost of an extra adder when the output stage + // is enabled. + // -------------------------------------------------- + generate if (USE_FILL_LEVEL) begin + wire [31:0] depth32; + assign depth32 = DEPTH; + always @(posedge clk or posedge reset) begin + if (reset) + fifo_fill_level <= 0; + else if (next_full & !drop_on_error) + fifo_fill_level <= depth32[ADDR_WIDTH:0]; + else begin + fifo_fill_level[ADDR_WIDTH] <= 1'b0; + fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; + end + end + + always @* begin + fill_level = fifo_fill_level; + + if (EMPTY_LATENCY == 3) + fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; + end + end + else begin + initial fill_level = 0; + end + endgenerate + + generate if (USE_ALMOST_FULL_IF) begin + assign almost_full_data = (fill_level >= almost_full_threshold); + end + else + assign almost_full_data = 0; + endgenerate + + generate if (USE_ALMOST_EMPTY_IF) begin + assign almost_empty_data = (fill_level <= almost_empty_threshold); + end + else + assign almost_empty_data = 0; + endgenerate + + // -------------------------------------------------- + // Avalon-MM Status & Control Connection Point + // + // Register map: + // + // | Addr | RW | 31 - 0 | + // | 0 | R | Fill level | + // + // The registering of this connection point means + // that there is a cycle of latency between + // reads/writes and the updating of the fill level. + // -------------------------------------------------- + generate if (USE_STORE_FORWARD) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + cut_through_threshold <= 0; + drop_on_error_en <= 0; + csr_readdata <= 0; + pkt_mode <= 1'b1; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b100) begin + cut_through_threshold <= csr_writedata[23:0]; + pkt_mode <= (csr_writedata[23:0] == 0); + end + if(csr_address == 3'b101) + drop_on_error_en <= csr_writedata[0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + if (csr_address == 4) + csr_readdata <= {8'b0, cut_through_threshold}; + if (csr_address == 5) + csr_readdata <= {31'b0, drop_on_error_en}; + end + end + end + end + else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + csr_readdata <= 0; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + end + end + end + end + else begin + always @(posedge clk or posedge reset) begin + if (reset) begin + csr_readdata <= 0; + end + else if (csr_read) begin + csr_readdata <= 0; + + if (csr_address == 0) + csr_readdata <= fill_level; + end + end + end + endgenerate + + // -------------------------------------------------- + // Store and forward logic + // -------------------------------------------------- + // if the fifo gets full before the entire packet or the + // cut-threshold condition is met then start sending out + // data in order to avoid dead-lock situation + + generate if (USE_STORE_FORWARD) begin + assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; + assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); + assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : + ~wait_for_threshold) | fifo_too_small_r; + assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; + assign in_pkt_start = in_valid & in_ready & in_startofpacket; + assign in_pkt_error = in_valid & in_ready & |in_error; + assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; + assign out_pkt_leave = out_valid & out_ready & out_endofpacket; + assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; + + // count packets coming and going into the fifo + always @(posedge clk or posedge reset) begin + if (reset) begin + pkt_cnt <= 0; + pkt_cnt_r <= 0; + pkt_cnt_plusone <= 1; + pkt_cnt_minusone <= 0; + pkt_cnt_changed <= 0; + pkt_has_started <= 0; + sop_has_left_fifo <= 0; + fifo_too_small_r <= 0; + pkt_cnt_eq_zero <= 1'b1; + pkt_cnt_eq_one <= 1'b0; + fifo_fill_level_lt_cut_through_threshold <= 1'b1; + end + else begin + fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; + fifo_too_small_r <= fifo_too_small; + pkt_cnt_plusone <= pkt_cnt + 1'b1; + pkt_cnt_minusone <= pkt_cnt - 1'b1; + pkt_cnt_r <= pkt_cnt; + pkt_cnt_changed <= 1'b0; + + if( in_pkt_eop_arrive ) + sop_has_left_fifo <= 1'b0; + else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) + sop_has_left_fifo <= 1'b1; + + if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; + pkt_cnt_eq_zero <= 0; + if (pkt_cnt == 0) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; + if (pkt_cnt == 1) + pkt_cnt_eq_zero <= 1'b1; + else + pkt_cnt_eq_zero <= 1'b0; + if (pkt_cnt == 2) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + + if (in_pkt_start) + pkt_has_started <= 1'b1; + else if (in_pkt_eop_arrive) + pkt_has_started <= 1'b0; + end + end + + // drop on error logic + always @(posedge clk or posedge reset) begin + if (reset) begin + sop_ptr <= 0; + error_in_pkt <= 0; + end + else begin + // save the location of the SOP + if ( in_pkt_start ) + sop_ptr <= wr_ptr; + + // remember if error in pkt + // log error only if packet has already started + if (in_pkt_eop_arrive) + error_in_pkt <= 1'b0; + else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) + error_in_pkt <= 1'b1; + end + end + assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & + ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); + + end + else begin + assign ok_to_forward = 1'b1; + assign drop_on_error = 1'b0; + end + endgenerate + + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + integer i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv b/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv new file mode 100644 index 0000000..00dc788 --- /dev/null +++ b/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv @@ -0,0 +1,270 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2010 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ +// $Revision: #3 $ +// $Date: 2010/07/07 $ +// $Author: jyeap $ + +/* ----------------------------------------------------------------------- +Round-robin/fixed arbitration implementation. + +Q: how do you find the least-significant set-bit in an n-bit binary number, X? + +A: M = X & (~X + 1) + +Example: X = 101000100 + 101000100 & + 010111011 + 1 = + + 101000100 & + 010111100 = + ----------- + 000000100 + +The method can be generalized to find the first set-bit +at a bit index no lower than bit-index N, simply by adding +2**N rather than 1. + + +Q: how does this relate to round-robin arbitration? +A: +Let X be the concatenation of all request signals. +Let the number to be added to X (hereafter called the +top_priority) initialize to 1, and be assigned from the +concatenation of the previous saved-grant, left-rotated +by one position, each time arbitration occurs. The +concatenation of grants is then M. + +Problem: consider this case: + +top_priority = 010000 +request = 001001 +~request + top_priority = 000110 +next_grant = 000000 <- no one is granted! + +There was no "set bit at a bit index no lower than bit-index 4", so +the result was 0. + +We need to propagate the carry out from (~request + top_priority) to the LSB, so +that the sum becomes 000111, and next_grant is 000001. This operation could be +called a "circular add". + +A bit of experimentation on the circular add reveals a significant amount of +delay in exiting and re-entering the carry chain - this will vary with device +family. Quartus also reports a combinational loop warning. Finally, +Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But +Modelsim _doesn't_ report a combinational loop!) + +An alternate solution: concatenate the request vector with itself, and OR +corresponding bits from the top and bottom halves to determine next_grant. + +Example: + +top_priority = 010000 +{request, request} = 001001 001001 +{~request, ~request} + top_priority = 110111 000110 +result of & operation = 000001 000000 +next_grant = 000001 + +Notice that if request = 0, the sum operation will overflow, but we can ignore +this; the next_grant result is 0 (no one granted), as you might expect. +In the implementation, the last-granted value must be maintained as +a non-zero value - best probably simply not to update it when no requests +occur. + +----------------------------------------------------------------------- */ + +`timescale 1 ns / 1 ns + +module altera_merlin_arbitrator +#( + parameter NUM_REQUESTERS = 8, + // -------------------------------------- + // Implemented schemes + // "round-robin" + // "fixed-priority" + // "no-arb" + // -------------------------------------- + parameter SCHEME = "round-robin", + parameter PIPELINE = 0 +) +( + input clk, + input reset, + + // -------------------------------------- + // Requests + // -------------------------------------- + input [NUM_REQUESTERS-1:0] request, + + // -------------------------------------- + // Grants + // -------------------------------------- + output [NUM_REQUESTERS-1:0] grant, + + // -------------------------------------- + // Control Signals + // -------------------------------------- + input increment_top_priority, + input save_top_priority +); + + // -------------------------------------- + // Signals + // -------------------------------------- + wire [NUM_REQUESTERS-1:0] top_priority; + reg [NUM_REQUESTERS-1:0] top_priority_reg; + reg [NUM_REQUESTERS-1:0] last_grant; + wire [2*NUM_REQUESTERS-1:0] result; + + // -------------------------------------- + // Scheme Selection + // -------------------------------------- + generate + if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin + assign top_priority = top_priority_reg; + end + else begin + // Fixed arbitration (or single-requester corner case) + assign top_priority = 1'b1; + end + endgenerate + + // -------------------------------------- + // Decision Logic + // -------------------------------------- + altera_merlin_arb_adder + #( + .WIDTH (2 * NUM_REQUESTERS) + ) + adder + ( + .a ({ ~request, ~request }), + .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), + .sum (result) + ); + + + generate if (SCHEME == "no-arb") begin + + // -------------------------------------- + // No arbitration: just wire request directly to grant + // -------------------------------------- + assign grant = request; + + end else begin + // Do the math in double-vector domain + wire [2*NUM_REQUESTERS-1:0] grant_double_vector; + assign grant_double_vector = {request, request} & result; + + // -------------------------------------- + // Extract grant from the top and bottom halves + // of the double vector. + // -------------------------------------- + assign grant = + grant_double_vector[NUM_REQUESTERS - 1 : 0] | + grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; + + end + endgenerate + + // -------------------------------------- + // Left-rotate the last grant vector to create top_priority. + // -------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + top_priority_reg <= 1'b1; + end + else begin + if (PIPELINE) begin + if (increment_top_priority) begin + top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1]} : top_priority_reg; + end + end else begin + if (save_top_priority) begin + top_priority_reg <= grant; + end + if (increment_top_priority) begin + if (|request) + top_priority_reg <= { grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1] }; + else + top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; + end + end + end + end + +endmodule + +// ---------------------------------------------- +// Adder for the standard arbitrator +// ---------------------------------------------- +module altera_merlin_arb_adder +#( + parameter WIDTH = 8 +) +( + input [WIDTH-1:0] a, + input [WIDTH-1:0] b, + + output [WIDTH-1:0] sum +); + + // ---------------------------------------------- + // Benchmarks indicate that for small widths, the full + // adder has higher fmax because synthesis can merge + // it with the mux, allowing partial decisions to be + // made early. + // + // The magic number is 4 requesters, which means an + // 8 bit adder. + // ---------------------------------------------- + genvar i; + generate if (WIDTH <= 8) begin : full_adder + + wire cout[WIDTH-1:0]; + + assign sum[0] = (a[0] ^ b[0]); + assign cout[0] = (a[0] & b[0]); + + for (i = 1; i < WIDTH; i = i+1) begin : arb + + assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; + assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); + + end + + end else begin : carry_chain + + assign sum = a + b; + + end + endgenerate + +endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv b/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv new file mode 100644 index 0000000..9b49c44 --- /dev/null +++ b/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv @@ -0,0 +1,286 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Burst Uncompressor +// +// Compressed read bursts -> uncompressed +// ------------------------------------------ + +`timescale 1 ns / 1 ns + +module altera_merlin_burst_uncompressor +#( + parameter ADDR_W = 16, + parameter BURSTWRAP_W = 3, + parameter BYTE_CNT_W = 4, + parameter PKT_SYMBOLS = 4, + parameter BURST_SIZE_W = 3 +) +( + input clk, + input reset, + + // sink ST signals + input sink_startofpacket, + input sink_endofpacket, + input sink_valid, + output sink_ready, + + // sink ST "data" + input [ADDR_W - 1: 0] sink_addr, + input [BURSTWRAP_W - 1 : 0] sink_burstwrap, + input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, + input sink_is_compressed, + input [BURST_SIZE_W-1 : 0] sink_burstsize, + + // source ST signals + output source_startofpacket, + output source_endofpacket, + output source_valid, + input source_ready, + + // source ST "data" + output [ADDR_W - 1: 0] source_addr, + output [BURSTWRAP_W - 1 : 0] source_burstwrap, + output [BYTE_CNT_W - 1 : 0] source_byte_cnt, + + // Note: in the slave agent, the output should always be uncompressed. In + // other applications, it may be required to leave-compressed or not. How to + // control? Seems like a simple mux - pass-through if no uncompression is + // required. + output source_is_compressed, + output [BURST_SIZE_W-1 : 0] source_burstsize +); + +//---------------------------------------------------- +// AXSIZE decoding +// +// Turns the axsize value into the actual number of bytes +// being transferred. +// --------------------------------------------------- +function reg[63:0] bytes_in_transfer; + input [2:0] axsize; + case (axsize) + 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; + 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; + 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; + 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; + 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; + 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; + 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; + default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + endcase + +endfunction + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + // def: Burst Compression. In a merlin network, a compressed burst is one + // which is transmitted in a single beat. Example: read burst. In + // constrast, an uncompressed burst (example: write burst) is transmitted in + // one beat per writedata item. + // + // For compressed bursts which require response packets, burst + // uncompression is required. Concrete example: a read burst of size 8 + // occupies one response-fifo position. When that fifo position reaches the + // front of the FIFO, the slave starts providing the required 8 readdatavalid + // pulses. The 8 return response beats must be provided in a single packet, + // with incrementing address and decrementing byte_cnt fields. Upon receipt + // of the final readdata item of the burst, the response FIFO item is + // retired. + // Burst uncompression logic provides: + // a) 2-state FSM (idle, busy) + // reset to idle state + // transition to busy state for 2nd and subsequent rdv pulses + // - a single-cycle burst (aka non-burst read) causes no transition to + // busy state. + // b) response startofpacket/endofpacket logic. The response FIFO item + // will have sop asserted, and may have eop asserted. (In the case of + // multiple read bursts transmit in the command fabric in a single packet, + // the eop assertion will come in a later FIFO item.) To support packet + // conservation, and emit a well-formed packet on the response fabric, + // i) response fabric startofpacket is asserted only for the first resp. + // beat; + // ii) response fabric endofpacket is asserted only for the last resp. + // beat. + // c) response address field. The response address field contains an + // incrementing sequence, such that each readdata item is associated with + // its slave-map location. N.b. a) computing the address correctly requires + // knowledge of burstwrap behavior b) there may be no clients of the address + // field, which makes this field a good target for optimization. See + // burst_uncompress_address_counter below. + // d) response byte_cnt field. The response byte_cnt field contains a + // decrementing sequence, such that each beat of the response contains the + // count of bytes to follow. In the case of sub-bursts in a single packet, + // the byte_cnt field may decrement down to num_symbols, then back up to + // some value, multiple times in the packet. + + reg burst_uncompress_busy; + reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; + wire first_packet_beat; + wire last_packet_beat; + + assign first_packet_beat = sink_valid & ~burst_uncompress_busy; + + // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to + // the output. + assign source_byte_cnt = + first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; + assign source_valid = sink_valid; + + // Last packet beat is set throughout receipt of an uncompressed read burst + // from the response FIFO - this forces all the burst uncompression machinery + // idle. + assign last_packet_beat = ~sink_is_compressed | + ( + burst_uncompress_busy ? + (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : + sink_valid & (sink_byte_cnt == num_symbols) + ); + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (source_valid & source_ready & sink_valid) begin + // No matter what the current state, last_packet_beat leads to + // idle. + if (last_packet_beat) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (burst_uncompress_busy) begin + burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? + (burst_uncompress_byte_counter - num_symbols) : + (sink_byte_cnt - num_symbols); + end + else begin // not busy, at least one more beat to go + burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; + // To do: should busy go true for numsymbols-size compressed + // bursts? + burst_uncompress_busy <= '1; + end + end + end + end + end + + wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; + reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; + reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; + + wire [63:0] decoded_burstsize_wire; + wire [ADDR_W-1:0] decoded_burstsize; + + // The input burstwrap value can be used as a mask against address values, + // but with one caveat: the address width may be (probably is) wider than + // the burstwrap width. The spec says: extend the msb of the burstwrap + // value out over the entire address width (but only if the address width + // actually is wider than the burstwrap width; otherwise it's a 0-width or + // negative range and concatenation multiplier). + assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; + generate + if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend + // Sign-extend, just wires: + assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = + {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; + end + endgenerate + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_base <= '0; + end + else if (first_packet_beat & source_ready) begin + burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; + end + end + + assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits + assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed + + wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = + ( + (first_packet_beat ? + sink_addr : + burst_uncompress_address_offset) + decoded_burstsize + ) & + addr_width_burstwrap; + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_offset <= '0; + end + else begin + if (source_ready & source_valid) begin + burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; + // if (first_packet_beat) begin + // burst_uncompress_address_offset <= + // (sink_addr + num_symbols) & addr_width_burstwrap; + // end + // else begin + // burst_uncompress_address_offset <= + // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; + // end + end + end + end + + // On the first packet beat, send the input address out unchanged, + // while values are computed/registered for 2nd and subsequent beats. + assign source_addr = first_packet_beat ? sink_addr : + burst_uncompress_address_base | burst_uncompress_address_offset; + assign source_burstwrap = sink_burstwrap; + assign source_burstsize = sink_burstsize; + + //------------------------------------------------------------------- + // A single (compressed) read burst will have sop/eop in the same beat. + // A sequence of read sub-bursts emitted by a burst adapter in response to a + // single read burst will have sop on the first sub-burst, eop on the last. + // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve + // packet conservation. + assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; + assign source_endofpacket = sink_endofpacket & last_packet_beat; + assign sink_ready = source_valid & source_ready & last_packet_beat; + + // This is correct for the slave agent usage, but won't always be true in the + // width adapter. To do: add an "please uncompress" input, and use it to + // pass-through or modify, and set source_is_compressed accordingly. + assign source_is_compressed = 1'b0; +endmodule + diff --git a/db/ip/nios_system/submodules/altera_merlin_master_agent.sv b/db/ip/nios_system/submodules/altera_merlin_master_agent.sv new file mode 100644 index 0000000..070f26f --- /dev/null +++ b/db/ip/nios_system/submodules/altera_merlin_master_agent.sv @@ -0,0 +1,309 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Agent +// +// Converts Avalon-MM transactions into +// Merlin network packets. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_master_agent +#( + // ------------------- + // Packet Format Parameters + // ------------------- + parameter PKT_QOS_H = 109, + PKT_QOS_L = 106, + PKT_DATA_SIDEBAND_H = 105, + PKT_DATA_SIDEBAND_L = 98, + PKT_ADDR_SIDEBAND_H = 97, + PKT_ADDR_SIDEBAND_L = 93, + PKT_CACHE_H = 92, + PKT_CACHE_L = 89, + PKT_THREAD_ID_H = 88, + PKT_THREAD_ID_L = 87, + PKT_BEGIN_BURST = 81, + PKT_PROTECTION_H = 80, + PKT_PROTECTION_L = 80, + PKT_BURSTWRAP_H = 79, + PKT_BURSTWRAP_L = 77, + PKT_BYTE_CNT_H = 76, + PKT_BYTE_CNT_L = 74, + PKT_ADDR_H = 73, + PKT_ADDR_L = 42, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + PKT_BURST_TYPE_H = 94, + PKT_BURST_TYPE_L = 93, + PKT_TRANS_EXCLUSIVE = 83, + PKT_TRANS_LOCK = 82, + PKT_TRANS_COMPRESSED_READ = 41, + PKT_TRANS_POSTED = 40, + PKT_TRANS_WRITE = 39, + PKT_TRANS_READ = 38, + PKT_DATA_H = 37, + PKT_DATA_L = 6, + PKT_BYTEEN_H = 5, + PKT_BYTEEN_L = 2, + PKT_SRC_ID_H = 1, + PKT_SRC_ID_L = 1, + PKT_DEST_ID_H = 0, + PKT_DEST_ID_L = 0, + PKT_RESPONSE_STATUS_L = 110, + PKT_RESPONSE_STATUS_H = 111, + ST_DATA_W = 112, + ST_CHANNEL_W = 1, + + // ------------------- + // Agent Parameters + // ------------------- + AV_BURSTCOUNT_W = 3, + ID = 1, + SUPPRESS_0_BYTEEN_RSP = 1, + BURSTWRAP_VALUE = 4, + CACHE_VALUE = 0, + SECURE_ACCESS_BIT = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + // ------------------- + // Derived Parameters + // ------------------- + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, + PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 +) +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Avalon-MM Anti-Master + // ------------------- + input [PKT_ADDR_W-1 : 0] av_address, + input av_write, + input av_read, + input [PKT_DATA_W-1 : 0] av_writedata, + output reg [PKT_DATA_W-1 : 0] av_readdata, + output reg av_waitrequest, + output reg av_readdatavalid, + input [PKT_BYTEEN_W-1 : 0] av_byteenable, + input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, + input av_debugaccess, + input av_lock, + output reg [1:0] av_response, + input av_writeresponserequest, + output reg av_writeresponsevalid, + + // ------------------- + // Command Source + // ------------------- + output reg cp_valid, + output reg [ST_DATA_W-1 : 0] cp_data, + output wire cp_startofpacket, + output wire cp_endofpacket, + input cp_ready, + + // ------------------- + // Response Sink + // ------------------- + input rp_valid, + input [ST_DATA_W-1 : 0] rp_data, + input [ST_CHANNEL_W-1 : 0] rp_channel, + input rp_startofpacket, + input rp_endofpacket, + output reg rp_ready +); + // ------------------------------------------------------------ + // Utility Functions + // ------------------------------------------------------------ + function integer clogb2; + input [31:0] value; + begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; + clogb2 = clogb2 - 1; + end + endfunction // clogb2 + + localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); + localparam NUMSYMBOLS = PKT_BYTEEN_W; + localparam BURSTING = (MAX_BURST > NUMSYMBOLS); + localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); + localparam BURST_SIZE = clogb2(NUMSYMBOLS); + + typedef enum bit [1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + OTHER_WRAP = 2'b11 + } MerlinBurstType; + + // -------------------------------------- + // Potential optimization: compare in words to save bits? + // -------------------------------------- + wire is_burst; + assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); + + wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; + wire [31:0] id_int = ID; + wire [2:0] burstsize_sig = BURST_SIZE[2:0]; + wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; + + // -------------------------------------- + // Address alignment + // + // The packet format requires that addresses be aligned to + // the transaction size. + // -------------------------------------- + wire [PKT_ADDR_W-1 : 0] av_address_aligned; + generate + if (NUMSYMBOLS > 1) begin + assign av_address_aligned = + {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; + end + else begin + assign av_address_aligned = av_address; + end + endgenerate + + // -------------------------------------- + // Command & Response Construction + // -------------------------------------- + always @* begin + cp_data = '0; // default assignment; override below as needed. + + cp_data[PKT_PROTECTION_L] = av_debugaccess; + cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // Default Non-secured (AXI) + cp_data[PKT_PROTECTION_L+2] = 1'b0; // Default Data access (AXI) + cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; + cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; + cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; + cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; + cp_data[PKT_TRANS_LOCK ] = av_lock; + cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; + cp_data[PKT_TRANS_READ ] = av_read; + cp_data[PKT_TRANS_WRITE ] = av_write; + // posted and non-posted write avaiable now + cp_data[PKT_TRANS_POSTED ] = av_write & !av_writeresponserequest; + cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; + cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; + cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; + cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; + cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; + cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; + cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE[3:0]; + cp_data[PKT_QOS_H : PKT_QOS_L] = '0; + cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; + cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; + + av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; + if (USE_WRITERESPONSE || USE_READRESPONSE) + av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; + else + av_response = '0; + + end + + // -------------------------------------- + // Command Control + // -------------------------------------- + always @* begin + cp_valid = 0; + + if (av_write || av_read) + cp_valid = 1; + end + + generate if (BURSTING) begin + reg sop_enable; + + always @(posedge clk, posedge reset) begin + if (reset) begin + sop_enable <= 1'b1; + end + else begin + if (cp_valid && cp_ready) begin + sop_enable <= 1'b0; + if (cp_endofpacket) + sop_enable <= 1'b1; + end + end + end + + assign cp_startofpacket = sop_enable; + assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); + + end + else begin + + assign cp_startofpacket = 1'b1; + assign cp_endofpacket = 1'b1; + + end + endgenerate + + // -------------------------------------- + // Backpressure & Readdatavalid + // -------------------------------------- + reg hold_waitrequest; + + always @ (posedge clk, posedge reset) begin + if (reset) + hold_waitrequest <= 1'b1; + else + hold_waitrequest <= 1'b0; + end + + always @* begin + rp_ready = 1; + av_readdatavalid = 0; + av_writeresponsevalid = 0; + av_waitrequest = hold_waitrequest | !cp_ready; + + // -------------------------------------- + // Currently, responses are _always_ read responses because + // this Avalon agent only issues posted writes, which do + // not have responses. -> not true for now + // Now Avalon supports response, so based on type of transaction + // return, assert correct thing + // -------------------------------------- + if (rp_data[PKT_TRANS_WRITE] == 1) + av_writeresponsevalid = rp_valid; + else + av_readdatavalid = rp_valid; + + if (SUPPRESS_0_BYTEEN_RSP) begin + if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) + av_readdatavalid = 0; + end + end + +endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_master_translator.sv b/db/ip/nios_system/submodules/altera_merlin_master_translator.sv new file mode 100644 index 0000000..a43760f --- /dev/null +++ b/db/ip/nios_system/submodules/altera_merlin_master_translator.sv @@ -0,0 +1,554 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Translator +// +// Converts Avalon-MM Master Interfaces into +// Avalon-MM Universal Master Interfaces +// -------------------------------------- + +`timescale 1 ns / 1 ns + + + +module altera_merlin_master_translator #( + parameter + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + + //Optional Port Declarations + + USE_BURSTCOUNT = 1, + USE_BEGINBURSTTRANSFER = 0, + USE_BEGINTRANSFER = 0, + USE_CHIPSELECT = 0, + USE_READ = 1, + USE_READDATAVALID = 1, + USE_WRITE = 1, + USE_WAITREQUEST = 1, + USE_WRITERESPONSE = 0, + USE_READRESPONSE = 0, + + AV_REGISTERINCOMINGSIGNALS = 0, + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_CONSTANT_BURST_BEHAVIOR = 1, + AV_BURSTCOUNT_SYMBOLS = 0, + AV_LINEWRAPBURSTS = 0, + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_CONSTANT_BURST_BEHAVIOR = 0 + )( + //Universal Avalon Master + input wire clk, + input wire reset, + output reg uav_write, + output reg uav_read, + output reg [UAV_ADDRESS_W -1 : 0] uav_address, + output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, + output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, + output wire [AV_DATA_W -1 : 0] uav_writedata, + output wire uav_lock, + output wire uav_debugaccess, + output wire uav_clken, + + input wire [ AV_DATA_W -1 : 0] uav_readdata, + input wire uav_readdatavalid, + input wire uav_waitrequest, + input wire [1:0] uav_response, + output reg uav_writeresponserequest, + input wire uav_writeresponsevalid, + + //Avalon-MM !Master + input reg av_write, + input reg av_read, + input wire [AV_ADDRESS_W -1 : 0] av_address, + input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, + input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, + input wire [AV_DATA_W -1 : 0] av_writedata, + input wire av_begintransfer, + input wire av_beginbursttransfer, + input wire av_lock, + input wire av_chipselect, + input wire av_debugaccess, + input wire av_clken, + + output wire [AV_DATA_W -1 : 0] av_readdata, + output wire av_readdatavalid, + output reg av_waitrequest, + output reg [1:0] av_response, + input wire av_writeresponserequest, + output reg av_writeresponsevalid + + ); + + + localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); + localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); + localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; + + localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; + localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; + + + // -1 for burstcount restriction 2^(n-1) + + localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; + localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; + + localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; + localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; + + localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; + localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; + + function integer flog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + if ( i <= 0 ) flog2 = 0; + else begin + for(flog2 = -1; i > 0; flog2 = flog2 + 1) + i = i >> 1; + end + end + + endfunction // flog2 + + function integer clog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2 = 0; i > 0; clog2 = clog2 + 1) + i = i >> 1; + end + + endfunction + + function integer pow2; + input [31:0] toShift; + begin + pow2=1; + pow2= pow2 << toShift; + end + endfunction // pow2 + + // ------------------------------------------------- + // Assign some constants to appropriately-sized signals to + // avoid synthesis warnings. This also helps some simulators + // with their inferred sensitivity lists. + // ------------------------------------------------- + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); + wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; + + + reg internal_beginbursttransfer; + reg internal_begintransfer; + reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; + reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; + + + + reg uav_read_pre; + reg uav_write_pre; + reg read_accepted; + + //Passthru assignmenst + + assign uav_writedata = av_writedata; + assign av_readdata = uav_readdata; + assign uav_byteenable = av_byteenable; + assign uav_lock = av_lock; + assign av_readdatavalid = uav_readdatavalid; + assign uav_debugaccess = av_debugaccess; + assign uav_clken = av_clken; + + //Response signals + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) + av_response = '0; + else + av_response = uav_response; + if (USE_WRITERESPONSE) begin + uav_writeresponserequest = av_writeresponserequest; + av_writeresponsevalid = uav_writeresponsevalid; + end else begin + uav_writeresponserequest = '0; + av_writeresponsevalid = '0; + end + end + + //address + burstcount assignment + + reg [UAV_ADDRESS_W - 1 : 0] address_register; + reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; + + always @* begin + uav_address=uav_address_pre; + uav_burstcount=uav_burstcount_pre; + + if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin + uav_address=address_register; + uav_burstcount=burstcount_register; + end + end + + reg first_burst_stalled; + reg burst_stalled; + + + wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; + wire [UAV_ADDRESS_W-1:0] combi_addr_reg; + generate + if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin + if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + end + else begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + end + end + else begin + assign combi_burst_addr_reg = + uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + assign combi_addr_reg = + address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + end + endgenerate + + always@(posedge clk, posedge reset) begin + + if(reset) begin + address_register <= '0; + burstcount_register <= '0; + first_burst_stalled <= 1'b0; + burst_stalled <= 1'b0; + end + else begin + address_register <= address_register; + burstcount_register <= burstcount_register; + + if(internal_beginbursttransfer||first_burst_stalled) begin + + if(av_waitrequest) begin + first_burst_stalled <= 1'b1; + address_register <= uav_address_pre; + burstcount_register <= uav_burstcount_pre; + end else begin + first_burst_stalled <= 1'b0; + address_register <= combi_burst_addr_reg; + burstcount_register <= uav_burstcount_pre - symbols_per_word; + end + end + + else if(internal_begintransfer || burst_stalled) begin + if(~av_waitrequest) begin + burst_stalled <= 1'b0; + address_register <= combi_addr_reg; + burstcount_register <= burstcount_register - symbols_per_word; + end else + burst_stalled<=1'b1; + end + end + + end + + //Address + always @* begin + uav_address_pre = '0; + + if(AV_ADDRESS_SYMBOLS) + uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; + else begin + uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; + end + end + + //Burstcount + always@* begin + uav_burstcount_pre = symbols_per_word; // default to a single transfer + + if(USE_BURSTCOUNT) begin + uav_burstcount_pre = '0; + + if(AV_BURSTCOUNT_SYMBOLS) + uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; + else begin + uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; + end + + end + + end + + + //waitrequest translation + + always@(posedge clk, posedge reset) begin + if(reset) + read_accepted <= 1'b0; + else begin + read_accepted <= read_accepted; + + if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives + read_accepted <= 1'b0; + + if(read_accepted == 0) + read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; + end + + end + + reg write_accepted = 0; + generate if (AV_REGISTERINCOMINGSIGNALS) begin + always@(posedge clk, posedge reset) begin + if(reset) + write_accepted <= 1'b0; + else begin + write_accepted <= + ~av_waitrequest ? 1'b0 : + uav_write & ~uav_waitrequest? 1'b1 : + write_accepted; + end + end + end endgenerate + + always@* begin + av_waitrequest = uav_waitrequest; + + if(USE_READDATAVALID == 0 ) begin + av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; + end + + if (AV_REGISTERINCOMINGSIGNALS) begin + av_waitrequest = + uav_read_pre ? ~uav_readdatavalid : + uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : + 1'b1; + end + + if(USE_WAITREQUEST == 0) begin + av_waitrequest = 0; + end + end + + //read/write generation + always@* begin + + uav_write = 1'b0; + uav_write_pre = 1'b0; + uav_read = 1'b0; + uav_read_pre = 1'b0; + + if(!USE_CHIPSELECT) begin + if (USE_READ) begin + uav_read_pre=av_read; + end + + if (USE_WRITE) begin + uav_write_pre=av_write; + end + end + else begin + if(!USE_WRITE && USE_READ) begin + uav_read_pre=av_read; + uav_write_pre=av_chipselect & ~av_read; + end + else if(!USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre = av_chipselect & ~av_write; + end + else if (USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre=av_read; + end + end + + if(USE_READDATAVALID == 0) + uav_read = uav_read_pre & ~read_accepted; + else + uav_read = uav_read_pre; + + if(AV_REGISTERINCOMINGSIGNALS == 0) + uav_write=uav_write_pre; + else + uav_write=uav_write_pre & ~write_accepted; + + + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + if(USE_BEGINTRANSFER) begin + internal_begintransfer = av_begintransfer; + end else begin + internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(internal_begintransfer == 1 && uav_waitrequest) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + wire last_burst_transfer_pre; + wire last_burst_transfer_reg; + wire last_burst_transfer; + + // compare values before the mux to shorten critical path; benchmark before changing + assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); + assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); + assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; + + always@* begin + if(USE_BEGINBURSTTRANSFER) begin + internal_beginbursttransfer = av_beginbursttransfer; + end else begin + internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_beginbursttransfer <= 1'b0; + end + else begin + end_beginbursttransfer <= end_beginbursttransfer; + if( last_burst_transfer && internal_begintransfer || uav_read ) begin + end_beginbursttransfer <= 1'b0; + end + else if(uav_write && internal_begintransfer) begin + end_beginbursttransfer <= 1'b1; + end + end + + end + + // synthesis translate_off + + // ------------------------------------------------ + // check_1 : for waitrequest signal violation + // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls + // Exception : begintransfer / beginbursttransfer + // : previously not in any transaction (idle) + // Note : Not checking clken which is not exactly part of Avalon controls/inputs + // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE + // ------------------------------------------------ + + reg av_waitrequest_r; + reg av_write_r,av_writeresponserequest_r,av_read_r,av_lock_r,av_chipselect_r,av_debugaccess_r; + reg [AV_ADDRESS_W-1:0] av_address_r; + reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; + reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; + reg [AV_DATA_W-1:0] av_writedata_r; + + always @(posedge clk or posedge reset) begin + if (reset) begin + av_waitrequest_r <= '0; + av_write_r <= '0; + av_writeresponserequest_r <= '0; + av_read_r <= '0; + av_lock_r <= '0; + av_chipselect_r <= '0; + av_debugaccess_r <= '0; + av_address_r <= '0; + av_byteenable_r <= '0; + av_burstcount_r <= '0; + av_writedata_r <= '0; + + end + else begin + av_waitrequest_r <= av_waitrequest; + av_write_r <= av_write; + av_writeresponserequest_r <= av_writeresponserequest; + av_read_r <= av_read; + av_lock_r <= av_lock; + av_chipselect_r <= av_chipselect; + av_debugaccess_r <= av_debugaccess; + av_address_r <= av_address; + av_byteenable_r <= av_byteenable; + av_burstcount_r <= av_burstcount; + av_writedata_r <= av_writedata; + + if ( av_waitrequest_r && // When waitrequest is asserted + ( (av_write != av_write_r) || // Checks that : Input controls/data does not change + (av_writeresponserequest != av_writeresponserequest_r) || + (av_read != av_read_r) || + (av_lock != av_lock_r) || + (av_debugaccess != av_debugaccess_r) || + (av_address != av_address_r) || + (av_byteenable != av_byteenable_r) || + (av_burstcount != av_burstcount_r) + ) && + (av_write_r | av_read_r) && // Check only when : previously initiated a write/read + (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) + ) + $display("%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.\nav_address %x --> %x\nav_byteenable %x --> %x\nav_burstcount %x --> %x\nav_writedata %x --> %x\nav_writeresponserequest %x --> %x\nav_write %x --> %x\nav_read %x --> %x\nav_lock %x --> %x\nav_chipselect %x --> %x\nav_debugaccess %x --> %x ", $time(), + av_address_r , av_address, + av_byteenable_r , av_byteenable, + av_burstcount_r , av_burstcount, + av_writedata_r , av_writedata, + av_writeresponserequest_r, av_writeresponserequest, + av_write_r , av_write, + av_read_r , av_read, + av_lock_r , av_lock, + av_chipselect_r, av_chipselect, + av_debugaccess_r, av_debugaccess); + end + + // end check_1 + + end + + // synthesis translate_on + + + endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv b/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv new file mode 100644 index 0000000..ea599eb --- /dev/null +++ b/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv @@ -0,0 +1,588 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2011 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_agent +#( + // Packet parameters + parameter PKT_BEGIN_BURST = 81, + parameter PKT_DATA_H = 31, + parameter PKT_DATA_L = 0, + parameter PKT_SYMBOL_W = 8, + parameter PKT_BYTEEN_H = 71, + parameter PKT_BYTEEN_L = 68, + parameter PKT_ADDR_H = 63, + parameter PKT_ADDR_L = 32, + parameter PKT_TRANS_LOCK = 87, + parameter PKT_TRANS_COMPRESSED_READ = 67, + parameter PKT_TRANS_POSTED = 66, + parameter PKT_TRANS_WRITE = 65, + parameter PKT_TRANS_READ = 64, + parameter PKT_SRC_ID_H = 74, + parameter PKT_SRC_ID_L = 72, + parameter PKT_DEST_ID_H = 77, + parameter PKT_DEST_ID_L = 75, + parameter PKT_BURSTWRAP_H = 85, + parameter PKT_BURSTWRAP_L = 82, + parameter PKT_BYTE_CNT_H = 81, + parameter PKT_BYTE_CNT_L = 78, + parameter PKT_PROTECTION_H = 86, + parameter PKT_PROTECTION_L = 86, + parameter PKT_RESPONSE_STATUS_H = 89, + parameter PKT_RESPONSE_STATUS_L = 88, + parameter PKT_BURST_SIZE_H = 92, + parameter PKT_BURST_SIZE_L = 90, + parameter ST_DATA_W = 93, + parameter ST_CHANNEL_W = 32, + + // Slave parameters + parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + parameter AVS_BURSTCOUNT_W = 4, + parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, + + // Slave agent parameters + parameter PREVENT_FIFO_OVERFLOW = 0, + parameter SUPPRESS_0_BYTEEN_CMD = 1, + parameter USE_READRESPONSE = 0, + parameter USE_WRITERESPONSE = 0, + + // Derived slave parameters + parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + parameter BURST_SIZE_W = 3, + + // Derived FIFO width + parameter FIFO_DATA_W = ST_DATA_W + 1 +) +( + + input clk, + input reset, + + // Universal-Avalon anti-slave + output [ADDR_W-1:0] m0_address, + output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, + output [AVS_BE_W-1:0] m0_byteenable, + output m0_read, + input [AVS_DATA_W-1:0] m0_readdata, + input m0_waitrequest, + output m0_write, + output [AVS_DATA_W-1:0] m0_writedata, + input m0_readdatavalid, + output m0_debugaccess, + output m0_lock, + input [1:0] m0_response, + output m0_writeresponserequest, + input m0_writeresponsevalid, + + // Avalon-ST FIFO interfaces. + // Note: there's no need to include the "data" field here, at least for + // reads, since readdata is filled in from slave info. To keep life + // simple, have a data field, but fill it with 0s. + // Av-st response fifo source interface + output reg [FIFO_DATA_W-1:0] rf_source_data, + output rf_source_valid, + output rf_source_startofpacket, + output rf_source_endofpacket, + input rf_source_ready, + + // Av-st response fifo sink interface + input [FIFO_DATA_W-1:0] rf_sink_data, + input rf_sink_valid, + input rf_sink_startofpacket, + input rf_sink_endofpacket, + output rf_sink_ready, + + // Av-st readdata fifo src interface, data and response + // extra 2 bits for storing RESPONSE STATUS + output [AVS_DATA_W+1:0] rdata_fifo_src_data, + output rdata_fifo_src_valid, + input rdata_fifo_src_ready, + + // Av-st readdata fifo sink interface + input [AVS_DATA_W+1:0] rdata_fifo_sink_data, + input rdata_fifo_sink_valid, + output rdata_fifo_sink_ready, + + // Av-st sink command packet interface + output cp_ready, + input cp_valid, + input [ST_DATA_W-1:0] cp_data, + input [ST_CHANNEL_W-1:0] cp_channel, + input cp_startofpacket, + input cp_endofpacket, + + // Av-st source response packet interface + input rp_ready, + output reg rp_valid, + output reg [ST_DATA_W-1:0] rp_data, + output rp_startofpacket, + output rp_endofpacket +); + + // -------------------------------------------------- + // Ceil(log2()) function log2ceil of 4 = 2 + // -------------------------------------------------- + function integer log2ceil; + input reg[63:0] val; + reg [63:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + // ------------------------------------------------ + // Local Parameters + // ------------------------------------------------ + localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; + localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; + localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; + localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; + localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; + localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; + localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); + + // ------------------------------------------------ + // Signals + // ------------------------------------------------ + wire [DATA_W-1:0] cmd_data; + wire [BE_W-1:0] cmd_byteen; + wire [ADDR_W-1:0] cmd_addr; + wire [MID_W-1:0] cmd_mid; + wire [SID_W-1:0] cmd_sid; + wire cmd_read; + wire cmd_write; + wire cmd_compressed; + wire cmd_posted; + wire [BYTE_CNT_W-1:0] cmd_byte_cnt; + wire [BURSTWRAP_W-1:0] cmd_burstwrap; + wire [BURSTSIZE_W-1:0] cmd_burstsize; + wire cmd_debugaccess; + + wire byteen_asserted; + wire needs_response_synthesis; + wire generate_response; + + // Assign command fields + assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; + assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; + assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; + assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; + assign cmd_posted = cp_data[PKT_TRANS_POSTED]; + assign cmd_write = cp_data[PKT_TRANS_WRITE]; + assign cmd_read = cp_data[PKT_TRANS_READ]; + assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; + assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; + assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; + + // Local "ready_for_command" signal: deasserted when the agent is unable to accept + // another command, e.g. rdv FIFO is full, (local readdata storage is full && + // ~rp_ready), ... + // Say, this could depend on the type of command, for example, even if the + // rdv FIFO is full, a write request can be accepted. For later. + wire ready_for_command; + + wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; + wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; + wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; + wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; + wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + generate + if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow + // --------------------------------------------------- + // Backpressure if the slave says to, or if FIFO overflow may occur. + // + // All commands are backpressured once the FIFO is full + // even if they don't need storage. This breaks a long + // combinatorial path from the master read/write through + // this logic and back to the master via the backpressure + // path. + // + // To avoid a loss of throughput the FIFO will be parameterized + // one slot deeper. The extra slot should never be used in normal + // operation, but should a slave misbehave and accept one more + // read than it should then backpressure will kick in. + // + // An example: assume a slave with MPRT = 2. It can accept a + // command sequence RRWW without backpressuring. If the FIFO is + // only 2 deep, we'd backpressure the writes leading to loss of + // throughput. If the FIFO is 3 deep, we'll only backpressure when + // RRR... which is an illegal condition anyway. + // --------------------------------------------------- + + assign ready_for_command = rf_source_ready; + assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; + + end else begin : no_prevent_fifo_overflow + + // Do not suppress the command or the slave will + // not be able to waitrequest + assign ready_for_command = 1'b1; + // Backpressure only if the slave says to. + assign cp_ready = ~m0_waitrequest | ~byteen_asserted; + + end + endgenerate + + generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd + assign byteen_asserted = |cmd_byteen; + end else begin : no_suppress_0_byteen_cmd + assign byteen_asserted = 1'b1; + end + endgenerate + + // ------------------------------------------------------------------- + // Extract avalon signals from command packet. + // ------------------------------------------------------------------- + // Mask off the lower bits of address. + // The burst adapter before this component will break narrow sized packets + // into sub-bursts of length 1. However, the packet addresses are preserved, + // which means this component may see size-aligned addresses. + // + // Masking ensures that the addresses seen by an Avalon slave are aligned to + // the full data width instead of the size. + // + // Example: + // output from burst adapter (datawidth=4, size=2 bytes): + // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 + // expected output from slave agent: + // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 + generate + if (BITS_TO_MASK > 0) begin : mask_address + + assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; + + end else begin : no_mask_address + + assign m0_address = cmd_addr; + + end + endgenerate + + assign m0_byteenable = cmd_byteen; + assign m0_writedata = cmd_data; + + // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - + // this sort of burst exists only in merlin fabric ST packets. What to do + // if we see such a burst? All beats in that burst need to be transmitted + // to the slave so we have enough space-time for byteenable expression. + // + // There can be multiple bursts in a packet, but only one beat per burst + // in cases. The exception is when we've decided not to insert a + // burst adapter for efficiency reasons, in which case this agent is also + // responsible for driving burstcount to 1 on each beat of an uncompressed + // read burst. + + assign m0_read = ready_for_command & byteen_asserted & + (local_compressed_read | local_read); + + generate + begin : m0_burstcount_zero_pad + // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount + // from a sub-range, or 0-pad, as appropriate. + if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin + wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = + {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; + assign m0_burstcount = (local_read & ~local_compressed_read) ? + {zero_pad, num_symbols} : + {zero_pad, cmd_byte_cnt}; + end + else begin : m0_burstcount_no_pad + assign m0_burstcount = (local_read & ~local_compressed_read) ? + num_symbols[AVS_BURSTCOUNT_W-1:0] : + cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; + end + end + endgenerate + + assign m0_write = ready_for_command & local_write & byteen_asserted; + assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); + assign m0_debugaccess = cmd_debugaccess; + // For now, to support write response + assign m0_writeresponserequest = ready_for_command & local_write & byteen_asserted & !cmd_posted; + //assign m0_writeresponserequest = '0; + + // ------------------------------------------------------------------- + // Indirection layer for response packet values. Some may always wire + // directly from the slave translator; others will no doubt emerge from + // various FIFOs. + // What to put in resp_data when a write occured? Answer: it does not + // matter, because only response status is needed for non-posted writes, + // and the packet already has a field for that. + + // tgngo:Use the rdata_fifo to store write response as well + // So that we wont lost response if master can back-pressured + // as well as it needs for write response merging + assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; + //assign rdata_fifo_src_valid = m0_readdatavalid; + assign rdata_fifo_src_data = {m0_response,m0_readdata}; + + // ------------------------------------------------------------------ + // Generate a token when read commands are suppressed. The token + // is stored in the response FIFO, and will be used to synthesize + // a read response. The same token is used for non-posted write + // response synthesis. + // + // Note: this token is not generated for suppressed uncompressed read cycles; + // the burst uncompression logic at the read side of the response FIFO + // generates the correct number of responses. + // ------------------------------------------------------------------ + // When the slave can return the response, let it does its works. Dont generate sysnthesis response + assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | (nonposted_write_endofpacket && !USE_WRITERESPONSE); + + // Avalon-ST interfaces to external response fifo: + // tgngo:Currently, with "generate response synthesis", only one write command is allowed to write in at eop of non-posted write + // To support response from slave, we need to store each sub-burst of write command into fifo. + // Each sub-burst will return a response and these two command and response are popped out together + // Resposne merging will happen and at end_of_packet of the command - the last sub-burst write + // the slave agent will send out the final merged response + + wire internal_cp_endofburst; + wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning + wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; + assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; + assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); + wire local_nonposted_write = ~cp_data[PKT_TRANS_POSTED] & local_write; + wire nonposted_end_of_subburst = local_nonposted_write & internal_cp_endofburst; + + assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && nonposted_end_of_subburst)) + & ready_for_command & cp_ready; + assign rf_source_startofpacket = cp_startofpacket; + assign rf_source_endofpacket = cp_endofpacket; + always @* begin + // default: assign every command packet field to the response FIFO... + rf_source_data = {1'b0, cp_data}; + + // ... and override select fields as needed. + rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; + rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; + rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; + rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; + //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; + rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; + rf_source_data[PKT_TRANS_POSTED] = cmd_posted; + rf_source_data[PKT_TRANS_WRITE] = cmd_write; + rf_source_data[PKT_TRANS_READ] = cmd_read; + rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; + rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; + rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; + rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; + rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; + rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; + rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; + end + + wire uncompressor_source_valid; + wire [BURSTSIZE_W-1:0] uncompressor_burstsize; + + //assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + // tgngo: last_write_response indicates the last response of the burst (incase need sub-burst) + // at this time, the final response merged will send out, and rp_valid is only asserted + // for one response for whole burst + generate + if (USE_READRESPONSE & USE_WRITERESPONSE) begin + wire last_write_response = rf_sink_data[PKT_TRANS_WRITE] & !rf_sink_data[PKT_TRANS_POSTED] & rf_sink_endofpacket; + always @* begin + if (rf_sink_data[PKT_TRANS_WRITE] == 1) + rp_valid = rdata_fifo_sink_valid & last_write_response; + else + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end else begin + always @* begin + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end + endgenerate + // ------------------------------------------------------------------ + // Response merging + // ------------------------------------------------------------------ + wire [1:0] current_response = rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W]; + reg [1:0] response_merged; + generate + begin: response_merging + if (USE_READRESPONSE & USE_WRITERESPONSE) begin + reg first_write_response; + reg reset_merged_output; + reg [1:0] previous_response_in; + reg [1:0] previous_response; + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + first_write_response <= 1'b1; + end + else begin // Merging work for write response, for read: previous_response_in = current_response + if (rf_sink_valid & rdata_fifo_sink_valid & rf_sink_data[PKT_TRANS_WRITE]) begin + first_write_response <= 1'b0; + if (rf_sink_endofpacket) + first_write_response <= 1'b1; + end + end + end + + always_comb begin + reset_merged_output = first_write_response && rdata_fifo_sink_valid; + previous_response_in = reset_merged_output ? current_response : previous_response; + response_merged = current_response >= previous_response ? current_response: previous_response_in; + end + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + previous_response <= 2'b00; + end + else begin + if (rf_sink_valid & rdata_fifo_sink_valid) begin + previous_response <= response_merged; + end + end + end + end else begin + always @* begin + response_merged = current_response; + end + end + end + endgenerate + + assign generate_response = rf_sink_data[FIFO_DATA_W-1]; + + wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; + // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo + wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; + + wire [BYTE_CNT_W-1:0] burst_byte_cnt; + wire [BURSTWRAP_W-1:0] rp_burstwrap; + wire [ADDR_W-1:0] rp_address; + wire rp_is_compressed; + + // ------------------------------------------------------------------ + // Backpressure the readdata fifo if we're supposed to synthesize a response. + // This may be a read response (for suppressed reads) or a write response + // (for non-posted writes). + // ------------------------------------------------------------------ + assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); + + always @* begin + // By default, return all fields... + rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; + + // ... and override specific fields. + rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; + // Assignments directly from the response fifo. + rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; + rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; + rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; + rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; + + // Burst uncompressor assignments + rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; + rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; + rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; + rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; + + // avalon slaves always respond with "okay" -> not true for now + //rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; + rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; + rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; + end + + // ------------------------------------------------------------------ + // Note: the burst uncompressor may be asked to generate responses for + // write packets; these are treated the same as single-cycle uncompressed + // reads. + // ------------------------------------------------------------------ + altera_merlin_burst_uncompressor #( + .ADDR_W (ADDR_W), + .BURSTWRAP_W (BURSTWRAP_W), + .BYTE_CNT_W (BYTE_CNT_W), + .PKT_SYMBOLS (PKT_SYMBOLS) + ) uncompressor + ( + .clk (clk), + .reset (reset), + .sink_startofpacket (rf_sink_startofpacket_wire), + .sink_endofpacket (rf_sink_endofpacket), + .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), + .sink_ready (rf_sink_ready), + .sink_addr (rf_sink_addr), + .sink_burstwrap (rf_sink_burstwrap), + .sink_byte_cnt (rf_sink_byte_cnt), + .sink_is_compressed (rf_sink_compressed), + .sink_burstsize (rf_sink_burstsize), + + .source_startofpacket (rp_startofpacket), + .source_endofpacket (rp_endofpacket), + .source_valid (uncompressor_source_valid), + .source_ready (rp_ready), + .source_addr (rp_address), + .source_burstwrap (rp_burstwrap), + .source_byte_cnt (burst_byte_cnt), + .source_is_compressed (rp_is_compressed), + .source_burstsize (uncompressor_burstsize) + ); + +//-------------------------------------- +// Assertion: In case slave support response. Yhe slave needs return response in order +// Ex: non-posted write followed by a read: write response must complete before read data +//-------------------------------------- +// synthesis translate_off +ERROR_write_response_and_read_response_cannot_happen_same_time: + assert property ( @(posedge clk) + disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) + ); + +// synthesis translate_on +endmodule + diff --git a/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv b/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv new file mode 100644 index 0000000..bcb2311 --- /dev/null +++ b/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv @@ -0,0 +1,533 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Slave Translator +// +// Translates Universal Avalon MM Slave +// to any Avalon MM Slave +// ------------------------------------- +// +//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one +//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero +//The key feature here is that no same cycle turnaround data is processed through the fabric. + +//import avalon_utilities_pkg::*; + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_translator + #( + parameter + //Widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + UAV_BYTEENABLE_W = 4, + + //Read Latency + AV_READLATENCY = 1, + + //Timing + AV_READ_WAIT_CYCLES = 0, + AV_WRITE_WAIT_CYCLES = 0, + AV_SETUP_WAIT_CYCLES = 0, + AV_DATA_HOLD_CYCLES = 0, + + //Optional Port Declarations + USE_READDATAVALID = 1, + USE_WAITREQUEST = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + //Variable Addressing + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_DATA_W = 32, + + AV_CONSTANT_BURST_BEHAVIOR = 0, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + CHIPSELECT_THROUGH_READLATENCY = 0, + + // Tightly-Coupled Options + USE_UAV_CLKEN = 0, + AV_REQUIRE_UNALIGNED_ADDRESSES = 0 + ) + ( + + // ------------------- + // Clock & Reset + // ------------------- + input wire clk, + input wire reset, + + // ------------------- + // Universal Avalon Slave + // ------------------- + + input wire [UAV_ADDRESS_W - 1 : 0] uav_address, + input wire [UAV_DATA_W - 1 : 0] uav_writedata, + input wire uav_write, + input wire uav_read, + input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, + input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, + input wire uav_lock, + input wire uav_debugaccess, + input wire uav_clken, + + output logic uav_readdatavalid, + output logic uav_waitrequest, + output logic [UAV_DATA_W - 1 : 0] uav_readdata, + output logic [1:0] uav_response, + input wire uav_writeresponserequest, + output logic uav_writeresponsevalid, + + // ------------------- + // Customizable Avalon Master + // ------------------- + output logic [AV_ADDRESS_W - 1 : 0] av_address, + output logic [AV_DATA_W - 1 : 0] av_writedata, + output logic av_write, + output logic av_read, + output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, + output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, + output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, + output logic av_begintransfer, + output wire av_chipselect, + output logic av_beginbursttransfer, + output logic av_lock, + output wire av_clken, + output wire av_debugaccess, + output wire av_outputenable, + + input logic [AV_DATA_W - 1 : 0] av_readdata, + input logic av_readdatavalid, + input logic av_waitrequest, + + input logic [1:0] av_response, + output logic av_writeresponserequest, + input wire av_writeresponsevalid + + ); + + function integer clog2_plusone; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) + i = i >> 1; + end + + endfunction + + function integer max; + //returns the larger of two passed arguments + input [31:0] one; + input [31:0] two; + + if(one > two) + max=one; + else + max=two; + endfunction // int + + localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); + localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); + localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); + localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); + localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; + + localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? + AV_ADDRESS_W : + UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; + + localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? + AV_BURSTCOUNT_W : + UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; + localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; + + + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); + wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; + + // +-------------------------------- + // |Backwards Compatibility Signals + // +-------------------------------- + assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; + assign av_debugaccess = uav_debugaccess; + + // +------------------- + // |Passthru Signals + // +------------------- + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin + uav_response = '0; + end else begin + uav_response = av_response; + end + end + assign av_writeresponserequest = uav_writeresponserequest; + assign uav_writeresponsevalid = av_writeresponsevalid; + + //------------------------- + //Writedata and Byteenable + //------------------------- + + always@* begin + av_byteenable = '0; + av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + always@* begin + av_writedata = '0; + av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; + end + + // +------------------- + // |Calculated Signals + // +------------------- + + logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; + + function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; + input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; + + for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin + if(byteenable[i] == 1) begin + return i; + end + end + + return '0; + + endfunction + + reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; + reg [AV_ADDRESS_W - 1 : 0] address_reg; + + + always@(posedge clk, posedge reset) begin + if(reset) begin + burstcount_reg <= '0; + address_reg <= '0; + end + else begin + burstcount_reg <= burstcount_reg; + address_reg <= address_reg; + + if(av_beginbursttransfer) begin + burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + end + end + end + + + logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; + + always@* begin + if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin + temp_wire = decode_byteenable(uav_byteenable); + + real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; + end + else begin + real_uav_address = uav_address; + end + + av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_address = address_reg; + end + + always@* begin + av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_burstcount = burstcount_reg; + end + + always@* begin + av_lock = uav_lock; + end + + // ------------------- + // Writebyteenable Assignment + // ------------------- + +always@* begin + av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; +end + + // ------------------- + // Waitrequest Assignment + // ------------------- + + reg av_waitrequest_generated; + reg av_waitrequest_generated_read; + reg av_waitrequest_generated_write; + reg waitrequest_reset_override; + + reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; + + always@(posedge reset, posedge clk) begin + + if(reset) begin + wait_latency_counter <= '0; + waitrequest_reset_override <= 1'h1; + end + else begin + waitrequest_reset_override <= 1'h0; + + wait_latency_counter <= '0; + + if( uav_read | uav_write ) + wait_latency_counter <= wait_latency_counter + 1'h1; + + if( ~uav_waitrequest | waitrequest_reset_override ) + wait_latency_counter <= '0; + + end + + end + + + always @* begin + + av_read = uav_read; + av_write = uav_write; + + av_waitrequest_generated = 1'h1; + av_waitrequest_generated_read = 1'h1; + av_waitrequest_generated_write = 1'h1; + + if(LOG2_OF_LATENCY_SUM == 1) + av_waitrequest_generated = 0; + + if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin + av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; + av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; + + av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; + av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; + + if(uav_write) + av_waitrequest_generated = av_waitrequest_generated_write; + else + av_waitrequest_generated = av_waitrequest_generated_read; + + end + + if(USE_WAITREQUEST) begin + uav_waitrequest = av_waitrequest; + end + else begin + uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; + end + + end + + // -------------- + // Readdata Assignment + // -------------- + + reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; + + always@(posedge clk, posedge reset) begin + if(reset) + av_readdata_pre <= 'b0; + else + av_readdata_pre <= av_readdata; + end + + always@* begin + uav_readdata = '0; + + if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin + uav_readdata = av_readdata; + end + else begin + uav_readdata = av_readdata_pre; + end + end + // ------------------- + // Readdatavalid Assigment + // ------------------- + + reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; + reg top_read_latency_shift_reg; + + + + always@* begin + + uav_readdatavalid=top_read_latency_shift_reg; + + if(USE_READDATAVALID) begin + uav_readdatavalid = av_readdatavalid; + end + + end + + always@* begin + + top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; + + if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin + top_read_latency_shift_reg=read_latency_shift_reg; + end + + if (AV_READLATENCY > 1) begin + top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; + end + + end + + always@(posedge reset, posedge clk) begin + + if (reset) begin + read_latency_shift_reg <= '0; + end + else if (av_clken) begin + + read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; + + for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin + read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; + end + + end + + end + + // ------------ + // Chipselect and OutputEnable + // ------------ + + reg av_chipselect_pre; + wire cs_extension; + reg av_outputenable_pre; + + + assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; + assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); + + assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; + + always@(posedge reset, posedge clk) begin + if(reset) + av_outputenable_pre <= 1'b0; + else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) + av_outputenable_pre <= 0; + else + av_outputenable_pre <= cs_extension | uav_read; + end + + always@(posedge reset, posedge clk) begin + if(reset) begin + av_chipselect_pre <= 1'b0; + end + else begin + av_chipselect_pre <= 1'b0; + + if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin + //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. + //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. + if(uav_read) begin + av_chipselect_pre <= 1'b1; + end + else if(cs_extension == 1) begin + av_chipselect_pre <= 1'b1; + end + + end + end + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + reg in_transfer; + + + + always@* begin + av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_beginbursttransfer <= 1'b0; + in_transfer <= 1'b0; + end + else begin + + end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); + + if(uav_write && uav_burstcount == symbols_per_word) + in_transfer <=1'b0; + else if(uav_write) + in_transfer <=1'b1; + + end + + end + +endmodule diff --git a/db/ip/nios_system/submodules/altera_reset_controller.sdc b/db/ip/nios_system/submodules/altera_reset_controller.sdc new file mode 100644 index 0000000..d58dd05 --- /dev/null +++ b/db/ip/nios_system/submodules/altera_reset_controller.sdc @@ -0,0 +1,33 @@ +# (C) 2001-2013 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +# +--------------------------------------------------- +# | Cut the async clear paths +# +--------------------------------------------------- +set aclr_counter 0 +set clrn_counter 0 +set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +foreach_in_collection aclr_pin $aclr_collection { + set aclr_counter [expr $aclr_counter + 1] +} +foreach_in_collection clrn_pin $clrn_collection { + set clrn_counter [expr $clrn_counter + 1] +} +if {$aclr_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +} + +if {$clrn_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +} diff --git a/db/ip/nios_system/submodules/altera_reset_controller.v b/db/ip/nios_system/submodules/altera_reset_controller.v new file mode 100644 index 0000000..7c250c7 --- /dev/null +++ b/db/ip/nios_system/submodules/altera_reset_controller.v @@ -0,0 +1,206 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $ +// $Revision: #2 $ +// $Date: 2013/06/03 $ +// $Author: wkleong $ + +// -------------------------------------- +// Reset controller +// +// Combines all the input resets and synchronizes +// the result to the clk. +// ACDS13.1 - Added reset request as part of reset sequencing +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_reset_controller +#( + parameter NUM_RESET_INPUTS = 6, + parameter OUTPUT_RESET_SYNC_EDGES = "deassert", + parameter SYNC_DEPTH = 2, + parameter RESET_REQUEST_PRESENT = 0 +) +( + // -------------------------------------- + // We support up to 16 reset inputs, for now + // -------------------------------------- + input reset_in0, + input reset_in1, + input reset_in2, + input reset_in3, + input reset_in4, + input reset_in5, + input reset_in6, + input reset_in7, + input reset_in8, + input reset_in9, + input reset_in10, + input reset_in11, + input reset_in12, + input reset_in13, + input reset_in14, + input reset_in15, + + input clk, + output reg reset_out, + output reg reset_req +); + + localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); + + localparam DEPTH = 2; + localparam CLKEN_LAGS_RESET = 0; + localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; + + wire merged_reset; + wire reset_out_pre; + + // Registers and Interconnect + (*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain; + reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain; + reg r_sync_rst_dly; + reg r_sync_rst; + reg r_early_rst; + + // -------------------------------------- + // "Or" all the input resets together + // -------------------------------------- + assign merged_reset = ( + reset_in0 | + reset_in1 | + reset_in2 | + reset_in3 | + reset_in4 | + reset_in5 | + reset_in6 | + reset_in7 | + reset_in8 | + reset_in9 | + reset_in10 | + reset_in11 | + reset_in12 | + reset_in13 | + reset_in14 | + reset_in15 + ); + + // -------------------------------------- + // And if required, synchronize it to the required clock domain, + // with the correct synchronization type + // -------------------------------------- + generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin + + assign reset_out_pre = merged_reset; + + end else begin + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(ASYNC_RESET) + ) + alt_rst_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset), + .reset_out (reset_out_pre) + ); + + end + endgenerate + + generate if (RESET_REQUEST_PRESENT == 0) begin + always @* begin + reset_out = reset_out_pre; + reset_req = 1'b0; + end + end + else begin + + // 3-FF Metastability Synchronizer + initial + begin + altera_reset_synchronizer_int_chain <= 3'b111; + end + + always @(posedge clk) + begin + altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre}; + end + + + // Synchronous reset pipe + initial + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + + always @(posedge clk) + begin + if (altera_reset_synchronizer_int_chain[2] == 1'b1) + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + else + begin + r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; + end + end + + // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition + // matches the early input. + initial + begin + r_sync_rst_dly <= 1'b1; + r_sync_rst <= 1'b1; + r_early_rst <= 1'b1; + end + + always @(posedge clk) + begin + // Delayed reset pipeline register + r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; + + case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) + 3'b000: r_sync_rst <= 1'b0; // Not reset + 3'b001: r_sync_rst <= 1'b0; + 3'b010: r_sync_rst <= 1'b0; + 3'b011: r_sync_rst <= 1'b1; + 3'b100: r_sync_rst <= 1'b1; + 3'b101: r_sync_rst <= 1'b1; + 3'b110: r_sync_rst <= 1'b1; + 3'b111: r_sync_rst <= 1'b1; // In Reset + default: r_sync_rst <= 1'b1; + endcase + + case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) + 2'b00: r_early_rst <= 1'b0; // Not reset + 2'b01: r_early_rst <= 1'b1; // Coming out of reset + 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. + 2'b11: r_early_rst <= 1'b1; // Held in reset + default: r_early_rst <= 1'b1; + endcase + end + + always @* begin + reset_out = r_sync_rst; + reset_req = r_early_rst; + end + + end + endgenerate + +endmodule diff --git a/db/ip/nios_system/submodules/altera_reset_synchronizer.v b/db/ip/nios_system/submodules/altera_reset_synchronizer.v new file mode 100644 index 0000000..14936c3 --- /dev/null +++ b/db/ip/nios_system/submodules/altera_reset_synchronizer.v @@ -0,0 +1,87 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_LEDRs.v b/db/ip/nios_system/submodules/nios_system_LEDRs.v new file mode 100644 index 0000000..d323942 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_LEDRs.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_LEDRs ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 17: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 17: 0] data_out; + wire [ 17: 0] out_port; + wire [ 17: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[17 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_LEDs.v b/db/ip/nios_system/submodules/nios_system_LEDs.v new file mode 100644 index 0000000..9fa4825 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_LEDs.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_LEDs ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 7: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 7: 0] data_out; + wire [ 7: 0] out_port; + wire [ 7: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {8 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[7 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_addr_router.sv b/db/ip/nios_system/submodules/nios_system_addr_router.sv new file mode 100644 index 0000000..3c8760e --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_addr_router.sv @@ -0,0 +1,224 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_addr_router_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 15 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_addr_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h40000 - 64'h0); + localparam PAD1 = log2ceil(64'h41000 - 64'h40800); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h41000; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_addr_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x40000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin + src_channel = 18'b10; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; + end + + // ( 0x40800 .. 0x41000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin + src_channel = 18'b01; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_addr_router_001.sv b/db/ip/nios_system/submodules/nios_system_addr_router_001.sv new file mode 100644 index 0000000..7b8c2d0 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_addr_router_001.sv @@ -0,0 +1,336 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_addr_router_001_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 15 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_addr_router_001 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h40000 - 64'h0); + localparam PAD1 = log2ceil(64'h41000 - 64'h40800); + localparam PAD2 = log2ceil(64'h41020 - 64'h41010); + localparam PAD3 = log2ceil(64'h41030 - 64'h41020); + localparam PAD4 = log2ceil(64'h41040 - 64'h41030); + localparam PAD5 = log2ceil(64'h41050 - 64'h41040); + localparam PAD6 = log2ceil(64'h41060 - 64'h41050); + localparam PAD7 = log2ceil(64'h41070 - 64'h41060); + localparam PAD8 = log2ceil(64'h41080 - 64'h41070); + localparam PAD9 = log2ceil(64'h41090 - 64'h41080); + localparam PAD10 = log2ceil(64'h410a0 - 64'h41090); + localparam PAD11 = log2ceil(64'h410b0 - 64'h410a0); + localparam PAD12 = log2ceil(64'h410c0 - 64'h410b0); + localparam PAD13 = log2ceil(64'h410d0 - 64'h410c0); + localparam PAD14 = log2ceil(64'h410e0 - 64'h410d0); + localparam PAD15 = log2ceil(64'h410f0 - 64'h410e0); + localparam PAD16 = log2ceil(64'h41100 - 64'h410f0); + localparam PAD17 = log2ceil(64'h41108 - 64'h41100); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h41108; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_addr_router_001_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x40000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin + src_channel = 18'b000000000000000010; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; + end + + // ( 0x40800 .. 0x41000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin + src_channel = 18'b000000000000000001; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; + end + + // ( 0x41010 .. 0x41020 ) + if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h41010 ) begin + src_channel = 18'b010000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13; + end + + // ( 0x41020 .. 0x41030 ) + if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h41020 ) begin + src_channel = 18'b100000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12; + end + + // ( 0x41030 .. 0x41040 ) + if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h41030 ) begin + src_channel = 18'b001000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11; + end + + // ( 0x41040 .. 0x41050 ) + if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h41040 ) begin + src_channel = 18'b000100000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; + end + + // ( 0x41050 .. 0x41060 ) + if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h41050 ) begin + src_channel = 18'b000010000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; + end + + // ( 0x41060 .. 0x41070 ) + if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h41060 ) begin + src_channel = 18'b000001000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; + end + + // ( 0x41070 .. 0x41080 ) + if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h41070 ) begin + src_channel = 18'b000000100000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; + end + + // ( 0x41080 .. 0x41090 ) + if ( {address[RG:PAD9],{PAD9{1'b0}}} == 19'h41080 ) begin + src_channel = 18'b000000010000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; + end + + // ( 0x41090 .. 0x410a0 ) + if ( {address[RG:PAD10],{PAD10{1'b0}}} == 19'h41090 ) begin + src_channel = 18'b000000001000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; + end + + // ( 0x410a0 .. 0x410b0 ) + if ( {address[RG:PAD11],{PAD11{1'b0}}} == 19'h410a0 ) begin + src_channel = 18'b000000000100000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; + end + + // ( 0x410b0 .. 0x410c0 ) + if ( {address[RG:PAD12],{PAD12{1'b0}}} == 19'h410b0 ) begin + src_channel = 18'b000000000010000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; + end + + // ( 0x410c0 .. 0x410d0 ) + if ( {address[RG:PAD13],{PAD13{1'b0}}} == 19'h410c0 ) begin + src_channel = 18'b000000000001000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16; + end + + // ( 0x410d0 .. 0x410e0 ) + if ( {address[RG:PAD14],{PAD14{1'b0}}} == 19'h410d0 ) begin + src_channel = 18'b000000000000100000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17; + end + + // ( 0x410e0 .. 0x410f0 ) + if ( {address[RG:PAD15],{PAD15{1'b0}}} == 19'h410e0 ) begin + src_channel = 18'b000000000000010000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; + end + + // ( 0x410f0 .. 0x41100 ) + if ( {address[RG:PAD16],{PAD16{1'b0}}} == 19'h410f0 ) begin + src_channel = 18'b000000000000000100; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x41100 .. 0x41108 ) + if ( {address[RG:PAD17],{PAD17{1'b0}}} == 19'h41100 ) begin + src_channel = 18'b000000000000001000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv new file mode 100644 index 0000000..0aef300 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv @@ -0,0 +1,116 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_demux +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_cmd_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv new file mode 100644 index 0000000..433e8d0 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv @@ -0,0 +1,356 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_demux_001 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 18 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_cmd_xbar_demux_001 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + output reg src2_valid, + output reg [96-1 : 0] src2_data, // ST_DATA_W=96 + output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18 + output reg src2_startofpacket, + output reg src2_endofpacket, + input src2_ready, + + output reg src3_valid, + output reg [96-1 : 0] src3_data, // ST_DATA_W=96 + output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18 + output reg src3_startofpacket, + output reg src3_endofpacket, + input src3_ready, + + output reg src4_valid, + output reg [96-1 : 0] src4_data, // ST_DATA_W=96 + output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18 + output reg src4_startofpacket, + output reg src4_endofpacket, + input src4_ready, + + output reg src5_valid, + output reg [96-1 : 0] src5_data, // ST_DATA_W=96 + output reg [18-1 : 0] src5_channel, // ST_CHANNEL_W=18 + output reg src5_startofpacket, + output reg src5_endofpacket, + input src5_ready, + + output reg src6_valid, + output reg [96-1 : 0] src6_data, // ST_DATA_W=96 + output reg [18-1 : 0] src6_channel, // ST_CHANNEL_W=18 + output reg src6_startofpacket, + output reg src6_endofpacket, + input src6_ready, + + output reg src7_valid, + output reg [96-1 : 0] src7_data, // ST_DATA_W=96 + output reg [18-1 : 0] src7_channel, // ST_CHANNEL_W=18 + output reg src7_startofpacket, + output reg src7_endofpacket, + input src7_ready, + + output reg src8_valid, + output reg [96-1 : 0] src8_data, // ST_DATA_W=96 + output reg [18-1 : 0] src8_channel, // ST_CHANNEL_W=18 + output reg src8_startofpacket, + output reg src8_endofpacket, + input src8_ready, + + output reg src9_valid, + output reg [96-1 : 0] src9_data, // ST_DATA_W=96 + output reg [18-1 : 0] src9_channel, // ST_CHANNEL_W=18 + output reg src9_startofpacket, + output reg src9_endofpacket, + input src9_ready, + + output reg src10_valid, + output reg [96-1 : 0] src10_data, // ST_DATA_W=96 + output reg [18-1 : 0] src10_channel, // ST_CHANNEL_W=18 + output reg src10_startofpacket, + output reg src10_endofpacket, + input src10_ready, + + output reg src11_valid, + output reg [96-1 : 0] src11_data, // ST_DATA_W=96 + output reg [18-1 : 0] src11_channel, // ST_CHANNEL_W=18 + output reg src11_startofpacket, + output reg src11_endofpacket, + input src11_ready, + + output reg src12_valid, + output reg [96-1 : 0] src12_data, // ST_DATA_W=96 + output reg [18-1 : 0] src12_channel, // ST_CHANNEL_W=18 + output reg src12_startofpacket, + output reg src12_endofpacket, + input src12_ready, + + output reg src13_valid, + output reg [96-1 : 0] src13_data, // ST_DATA_W=96 + output reg [18-1 : 0] src13_channel, // ST_CHANNEL_W=18 + output reg src13_startofpacket, + output reg src13_endofpacket, + input src13_ready, + + output reg src14_valid, + output reg [96-1 : 0] src14_data, // ST_DATA_W=96 + output reg [18-1 : 0] src14_channel, // ST_CHANNEL_W=18 + output reg src14_startofpacket, + output reg src14_endofpacket, + input src14_ready, + + output reg src15_valid, + output reg [96-1 : 0] src15_data, // ST_DATA_W=96 + output reg [18-1 : 0] src15_channel, // ST_CHANNEL_W=18 + output reg src15_startofpacket, + output reg src15_endofpacket, + input src15_ready, + + output reg src16_valid, + output reg [96-1 : 0] src16_data, // ST_DATA_W=96 + output reg [18-1 : 0] src16_channel, // ST_CHANNEL_W=18 + output reg src16_startofpacket, + output reg src16_endofpacket, + input src16_ready, + + output reg src17_valid, + output reg [96-1 : 0] src17_data, // ST_DATA_W=96 + output reg [18-1 : 0] src17_channel, // ST_CHANNEL_W=18 + output reg src17_startofpacket, + output reg src17_endofpacket, + input src17_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 18; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + src2_data = sink_data; + src2_startofpacket = sink_startofpacket; + src2_endofpacket = sink_endofpacket; + src2_channel = sink_channel >> NUM_OUTPUTS; + + src2_valid = sink_channel[2] && sink_valid; + + src3_data = sink_data; + src3_startofpacket = sink_startofpacket; + src3_endofpacket = sink_endofpacket; + src3_channel = sink_channel >> NUM_OUTPUTS; + + src3_valid = sink_channel[3] && sink_valid; + + src4_data = sink_data; + src4_startofpacket = sink_startofpacket; + src4_endofpacket = sink_endofpacket; + src4_channel = sink_channel >> NUM_OUTPUTS; + + src4_valid = sink_channel[4] && sink_valid; + + src5_data = sink_data; + src5_startofpacket = sink_startofpacket; + src5_endofpacket = sink_endofpacket; + src5_channel = sink_channel >> NUM_OUTPUTS; + + src5_valid = sink_channel[5] && sink_valid; + + src6_data = sink_data; + src6_startofpacket = sink_startofpacket; + src6_endofpacket = sink_endofpacket; + src6_channel = sink_channel >> NUM_OUTPUTS; + + src6_valid = sink_channel[6] && sink_valid; + + src7_data = sink_data; + src7_startofpacket = sink_startofpacket; + src7_endofpacket = sink_endofpacket; + src7_channel = sink_channel >> NUM_OUTPUTS; + + src7_valid = sink_channel[7] && sink_valid; + + src8_data = sink_data; + src8_startofpacket = sink_startofpacket; + src8_endofpacket = sink_endofpacket; + src8_channel = sink_channel >> NUM_OUTPUTS; + + src8_valid = sink_channel[8] && sink_valid; + + src9_data = sink_data; + src9_startofpacket = sink_startofpacket; + src9_endofpacket = sink_endofpacket; + src9_channel = sink_channel >> NUM_OUTPUTS; + + src9_valid = sink_channel[9] && sink_valid; + + src10_data = sink_data; + src10_startofpacket = sink_startofpacket; + src10_endofpacket = sink_endofpacket; + src10_channel = sink_channel >> NUM_OUTPUTS; + + src10_valid = sink_channel[10] && sink_valid; + + src11_data = sink_data; + src11_startofpacket = sink_startofpacket; + src11_endofpacket = sink_endofpacket; + src11_channel = sink_channel >> NUM_OUTPUTS; + + src11_valid = sink_channel[11] && sink_valid; + + src12_data = sink_data; + src12_startofpacket = sink_startofpacket; + src12_endofpacket = sink_endofpacket; + src12_channel = sink_channel >> NUM_OUTPUTS; + + src12_valid = sink_channel[12] && sink_valid; + + src13_data = sink_data; + src13_startofpacket = sink_startofpacket; + src13_endofpacket = sink_endofpacket; + src13_channel = sink_channel >> NUM_OUTPUTS; + + src13_valid = sink_channel[13] && sink_valid; + + src14_data = sink_data; + src14_startofpacket = sink_startofpacket; + src14_endofpacket = sink_endofpacket; + src14_channel = sink_channel >> NUM_OUTPUTS; + + src14_valid = sink_channel[14] && sink_valid; + + src15_data = sink_data; + src15_startofpacket = sink_startofpacket; + src15_endofpacket = sink_endofpacket; + src15_channel = sink_channel >> NUM_OUTPUTS; + + src15_valid = sink_channel[15] && sink_valid; + + src16_data = sink_data; + src16_startofpacket = sink_startofpacket; + src16_endofpacket = sink_endofpacket; + src16_channel = sink_channel >> NUM_OUTPUTS; + + src16_valid = sink_channel[16] && sink_valid; + + src17_data = sink_data; + src17_startofpacket = sink_startofpacket; + src17_endofpacket = sink_endofpacket; + src17_channel = sink_channel >> NUM_OUTPUTS; + + src17_valid = sink_channel[17] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + assign ready_vector[2] = src2_ready; + assign ready_vector[3] = src3_ready; + assign ready_vector[4] = src4_ready; + assign ready_vector[5] = src5_ready; + assign ready_vector[6] = src6_ready; + assign ready_vector[7] = src7_ready; + assign ready_vector[8] = src8_ready; + assign ready_vector[9] = src9_ready; + assign ready_vector[10] = src10_ready; + assign ready_vector[11] = src11_ready; + assign ready_vector[12] = src12_ready; + assign ready_vector[13] = src13_ready; + assign ready_vector[14] = src14_ready; + assign ready_vector[15] = src15_ready; + assign ready_vector[16] = src16_ready; + assign ready_vector[17] = src17_ready; + + assign sink_ready = |(sink_channel & ready_vector); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv new file mode 100644 index 0000000..76ec5b4 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv @@ -0,0 +1,308 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 1 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_cmd_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 1; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + wire [NUM_INPUTS - 1 : 0] eop; + assign eop[0] = sink0_endofpacket; + assign eop[1] = sink1_endofpacket; + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + end + reg [NUM_INPUTS - 1 : 0] locked = '0; + always @(posedge clk or posedge reset) begin + if (reset) begin + locked <= '0; + end + else begin + locked <= next_grant & lock; + end + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (update_grant) begin + share_count <= next_grant_share; + share_count_zero_flag <= (next_grant_share == '0); + end + else if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // The pipeline delays grant by one cycle, so + // we have to calculate the update_grant signal + // one cycle ahead of time. + // + // Possible optimization: omit the first clause + // "if (!packet_in_progress & ~src_valid) ..." + // cost: one idle cycle at the the beginning of each + // grant cycle. + // benefit: save a small amount of logic. + // ------------------------------------------ + if (!packet_in_progress & !src_valid) + update_grant = 1; + if (last_cycle && share_count_zero_flag) + update_grant = 1; + end + + wire save_grant; + assign save_grant = update_grant; + assign grant = saved_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] prev_request; + always @(posedge clk, posedge reset) begin + if (reset) + prev_request <= '0; + else + prev_request <= request & ~(valid & eop); + end + + assign request = (PIPELINE_ARB == 1) ? valid | locked : + prev_request | valid | locked; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("round-robin"), + .PIPELINE (1) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/db/ip/nios_system/submodules/nios_system_hex0.v b/db/ip/nios_system/submodules/nios_system_hex0.v new file mode 100644 index 0000000..5941fac --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_hex0.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_hex0 ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 6: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 6: 0] data_out; + wire [ 6: 0] out_port; + wire [ 6: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {7 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[6 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_id_router.sv b/db/ip/nios_system/submodules/nios_system_id_router.sv new file mode 100644 index 0000000..90937e8 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_id_router.sv @@ -0,0 +1,221 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 1 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 1 ) begin + src_channel = 18'b01; + end + + if (destid == 0 ) begin + src_channel = 18'b10; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_id_router_002.sv b/db/ip/nios_system/submodules/nios_system_id_router_002.sv new file mode 100644 index 0000000..a80e831 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_id_router_002.sv @@ -0,0 +1,217 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_002_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router_002 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_002_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 18'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_id_router_003.sv b/db/ip/nios_system/submodules/nios_system_id_router_003.sv new file mode 100644 index 0000000..5eb343c --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_id_router_003.sv @@ -0,0 +1,217 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_003_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router_003 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_003_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 18'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_irq_mapper.sv b/db/ip/nios_system/submodules/nios_system_irq_mapper.sv new file mode 100644 index 0000000..cc0a8bb --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_irq_mapper.sv @@ -0,0 +1,59 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Altera IRQ Mapper +// +// Parameters +// NUM_RCVRS : 1 +// SENDER_IRW_WIDTH : 32 +// IRQ_MAP : 0:5 +// +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_irq_mapper +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // IRQ Receivers + // ------------------- + input receiver0_irq, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg [31 : 0] sender_irq +); + + + always @* begin + sender_irq = 0; + + sender_irq[5] = receiver0_irq; + end + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_jtag_uart.v b/db/ip/nios_system/submodules/nios_system_jtag_uart.v new file mode 100644 index 0000000..c76125d --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_jtag_uart.v @@ -0,0 +1,583 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_sim_scfifo_w ( + // inputs: + clk, + fifo_wdata, + fifo_wr, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input [ 7: 0] fifo_wdata; + input fifo_wr; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + always @(posedge clk) + begin + if (fifo_wr) + $write("%c", fifo_wdata); + end + + + assign wfifo_used = {6{1'b0}}; + assign r_dat = {8{1'b0}}; + assign fifo_FF = 1'b0; + assign wfifo_empty = 1'b1; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_scfifo_w ( + // inputs: + clk, + fifo_clear, + fifo_wdata, + fifo_wr, + rd_wfifo, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input fifo_clear; + input [ 7: 0] fifo_wdata; + input fifo_wr; + input rd_wfifo; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo wfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (fifo_wdata), +// .empty (wfifo_empty), +// .full (fifo_FF), +// .q (r_dat), +// .rdreq (rd_wfifo), +// .usedw (wfifo_used), +// .wrreq (fifo_wr) +// ); +// +// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// wfifo.lpm_numwords = 64, +// wfifo.lpm_showahead = "OFF", +// wfifo.lpm_type = "scfifo", +// wfifo.lpm_width = 8, +// wfifo.lpm_widthu = 6, +// wfifo.overflow_checking = "OFF", +// wfifo.underflow_checking = "OFF", +// wfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_sim_scfifo_r ( + // inputs: + clk, + fifo_rd, + rst_n, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_rd; + input rst_n; + + reg [ 31: 0] bytes_left; + wire fifo_EF; + reg fifo_rd_d; + wire [ 7: 0] fifo_rdata; + wire new_rom; + wire [ 31: 0] num_bytes; + wire [ 6: 0] rfifo_entries; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Generate rfifo_entries for simulation + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + bytes_left <= 32'h0; + fifo_rd_d <= 1'b0; + end + else + begin + fifo_rd_d <= fifo_rd; + // decrement on read + if (fifo_rd_d) + bytes_left <= bytes_left - 1'b1; + // catch new contents + if (new_rom) + bytes_left <= num_bytes; + end + end + + + assign fifo_EF = bytes_left == 32'b0; + assign rfifo_full = bytes_left > 7'h40; + assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; + assign rfifo_used = rfifo_entries[5 : 0]; + assign new_rom = 1'b0; + assign num_bytes = 32'b0; + assign fifo_rdata = 8'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_scfifo_r ( + // inputs: + clk, + fifo_clear, + fifo_rd, + rst_n, + t_dat, + wr_rfifo, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_clear; + input fifo_rd; + input rst_n; + input [ 7: 0] t_dat; + input wr_rfifo; + + wire fifo_EF; + wire [ 7: 0] fifo_rdata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo rfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (t_dat), +// .empty (fifo_EF), +// .full (rfifo_full), +// .q (fifo_rdata), +// .rdreq (fifo_rd), +// .usedw (rfifo_used), +// .wrreq (wr_rfifo) +// ); +// +// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// rfifo.lpm_numwords = 64, +// rfifo.lpm_showahead = "OFF", +// rfifo.lpm_type = "scfifo", +// rfifo.lpm_width = 8, +// rfifo.lpm_widthu = 6, +// rfifo.overflow_checking = "OFF", +// rfifo.underflow_checking = "OFF", +// rfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart ( + // inputs: + av_address, + av_chipselect, + av_read_n, + av_write_n, + av_writedata, + clk, + rst_n, + + // outputs: + av_irq, + av_readdata, + av_waitrequest, + dataavailable, + readyfordata + ) + /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; + + output av_irq; + output [ 31: 0] av_readdata; + output av_waitrequest; + output dataavailable; + output readyfordata; + input av_address; + input av_chipselect; + input av_read_n; + input av_write_n; + input [ 31: 0] av_writedata; + input clk; + input rst_n; + + reg ac; + wire activity; + wire av_irq; + wire [ 31: 0] av_readdata; + reg av_waitrequest; + reg dataavailable; + reg fifo_AE; + reg fifo_AF; + wire fifo_EF; + wire fifo_FF; + wire fifo_clear; + wire fifo_rd; + wire [ 7: 0] fifo_rdata; + wire [ 7: 0] fifo_wdata; + reg fifo_wr; + reg ien_AE; + reg ien_AF; + wire ipen_AE; + wire ipen_AF; + reg pause_irq; + wire [ 7: 0] r_dat; + wire r_ena; + reg r_val; + wire rd_wfifo; + reg read_0; + reg readyfordata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + reg rvalid; + reg sim_r_ena; + reg sim_t_dat; + reg sim_t_ena; + reg sim_t_pause; + wire [ 7: 0] t_dat; + reg t_dav; + wire t_ena; + wire t_pause; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + reg woverflow; + wire wr_rfifo; + //avalon_jtag_slave, which is an e_avalon_slave + assign rd_wfifo = r_ena & ~wfifo_empty; + assign wr_rfifo = t_ena & ~rfifo_full; + assign fifo_clear = ~rst_n; + nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_clear (fifo_clear), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .rd_wfifo (rd_wfifo), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_clear (fifo_clear), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n), + .t_dat (t_dat), + .wr_rfifo (wr_rfifo) + ); + + assign ipen_AE = ien_AE & fifo_AE; + assign ipen_AF = ien_AF & (pause_irq | fifo_AF); + assign av_irq = ipen_AE | ipen_AF; + assign activity = t_pause | t_ena; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + pause_irq <= 1'b0; + else // only if fifo is not empty... + if (t_pause & ~fifo_EF) + pause_irq <= 1'b1; + else if (read_0) + pause_irq <= 1'b0; + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + r_val <= 1'b0; + t_dav <= 1'b1; + end + else + begin + r_val <= r_ena & ~wfifo_empty; + t_dav <= ~rfifo_full; + end + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + fifo_AE <= 1'b0; + fifo_AF <= 1'b0; + fifo_wr <= 1'b0; + rvalid <= 1'b0; + read_0 <= 1'b0; + ien_AE <= 1'b0; + ien_AF <= 1'b0; + ac <= 1'b0; + woverflow <= 1'b0; + av_waitrequest <= 1'b1; + end + else + begin + fifo_AE <= {fifo_FF,wfifo_used} <= 8; + fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; + fifo_wr <= 1'b0; + read_0 <= 1'b0; + av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); + if (activity) + ac <= 1'b1; + // write + if (av_chipselect & ~av_write_n & av_waitrequest) + // addr 1 is control; addr 0 is data + if (av_address) + begin + ien_AF <= av_writedata[0]; + ien_AE <= av_writedata[1]; + if (av_writedata[10] & ~activity) + ac <= 1'b0; + end + else + begin + fifo_wr <= ~fifo_FF; + woverflow <= fifo_FF; + end + // read + if (av_chipselect & ~av_read_n & av_waitrequest) + begin + // addr 1 is interrupt; addr 0 is data + if (~av_address) + rvalid <= ~fifo_EF; + read_0 <= ~av_address; + end + end + end + + + assign fifo_wdata = av_writedata[7 : 0]; + assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; + assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + readyfordata <= 0; + else + readyfordata <= ~fifo_FF; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Tie off Atlantic Interface signals not used for simulation + always @(posedge clk) + begin + sim_t_pause <= 1'b0; + sim_t_ena <= 1'b0; + sim_t_dat <= t_dav ? r_dat : {8{r_val}}; + sim_r_ena <= 1'b0; + end + + + assign r_ena = sim_r_ena; + assign t_ena = sim_t_ena; + assign t_dat = sim_t_dat; + assign t_pause = sim_t_pause; + always @(fifo_EF) + begin + dataavailable = ~fifo_EF; + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic +// ( +// .clk (clk), +// .r_dat (r_dat), +// .r_ena (r_ena), +// .r_val (r_val), +// .rst_n (rst_n), +// .t_dat (t_dat), +// .t_dav (t_dav), +// .t_ena (t_ena), +// .t_pause (t_pause) +// ); +// +// defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, +// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, +// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, +// nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; +// +// always @(posedge clk or negedge rst_n) +// begin +// if (rst_n == 0) +// dataavailable <= 0; +// else +// dataavailable <= ~fifo_EF; +// end +// +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_lcd.v b/db/ip/nios_system/submodules/nios_system_lcd.v new file mode 100644 index 0000000..18c2d15 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_lcd.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd ( + // inputs: + address, + begintransfer, + clk, + read, + reset_n, + write, + writedata, + + // outputs: + LCD_E, + LCD_RS, + LCD_RW, + LCD_data, + readdata + ) +; + + output LCD_E; + output LCD_RS; + output LCD_RW; + inout [ 7: 0] LCD_data; + output [ 7: 0] readdata; + input [ 1: 0] address; + input begintransfer; + input clk; + input read; + input reset_n; + input write; + input [ 7: 0] writedata; + + wire LCD_E; + wire LCD_RS; + wire LCD_RW; + wire [ 7: 0] LCD_data; + wire [ 7: 0] readdata; + assign LCD_RW = address[0]; + assign LCD_RS = address[1]; + assign LCD_E = read | write; + assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; + assign readdata = LCD_data; + //control_slave, which is an e_avalon_slave + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v b/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v new file mode 100644 index 0000000..78b6e6e --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_16207_0 ( + // inputs: + address, + begintransfer, + clk, + read, + reset_n, + write, + writedata, + + // outputs: + LCD_E, + LCD_RS, + LCD_RW, + LCD_data, + readdata + ) +; + + output LCD_E; + output LCD_RS; + output LCD_RW; + inout [ 7: 0] LCD_data; + output [ 7: 0] readdata; + input [ 1: 0] address; + input begintransfer; + input clk; + input read; + input reset_n; + input write; + input [ 7: 0] writedata; + + wire LCD_E; + wire LCD_RS; + wire LCD_RW; + wire [ 7: 0] LCD_data; + wire [ 7: 0] readdata; + assign LCD_RW = address[0]; + assign LCD_RS = address[1]; + assign LCD_E = read | write; + assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; + assign readdata = LCD_data; + //control_slave, which is an e_avalon_slave + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_lcd_E.v b/db/ip/nios_system/submodules/nios_system_lcd_E.v new file mode 100644 index 0000000..c5680d0 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_lcd_E.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_E ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_lcd_on.v b/db/ip/nios_system/submodules/nios_system_lcd_on.v new file mode 100644 index 0000000..5b987ea --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_lcd_on.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_on ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc b/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc new file mode 100644 index 0000000..f1186f1 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc @@ -0,0 +1,53 @@ +# Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +# use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any +# output files any of the foregoing (including device programming or +# simulation files), and any associated documentation or information are +# expressly subject to the terms and conditions of the Altera Program +# License Subscription Agreement or other applicable license agreement, +# including, without limitation, that your use is for the sole purpose +# of programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +#************************************************************** +# Timequest JTAG clock definition +# Uncommenting the following lines will define the JTAG +# clock in TimeQuest Timing Analyzer +#************************************************************** + +#create_clock -period 10MHz {altera_reserved_tck} +#set_clock_groups -asynchronous -group {altera_reserved_tck} + +#************************************************************** +# Set TCL Path Variables +#************************************************************** + +set nios_system_nios2_processor nios_system_nios2_processor:* +set nios_system_nios2_processor_oci nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci +set nios_system_nios2_processor_oci_break nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break +set nios_system_nios2_processor_ocimem nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem +set nios_system_nios2_processor_oci_debug nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug +set nios_system_nios2_processor_wrapper nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper +set nios_system_nios2_processor_jtag_tck nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck +set nios_system_nios2_processor_jtag_sysclk nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk +set nios_system_nios2_processor_oci_path [format "%s|%s" $nios_system_nios2_processor $nios_system_nios2_processor_oci] +set nios_system_nios2_processor_oci_break_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_break] +set nios_system_nios2_processor_ocimem_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_ocimem] +set nios_system_nios2_processor_oci_debug_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_debug] +set nios_system_nios2_processor_jtag_tck_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_tck] +set nios_system_nios2_processor_jtag_sysclk_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_sysclk] +set nios_system_nios2_processor_jtag_sr [format "%s|*sr" $nios_system_nios2_processor_jtag_tck_path] + +#************************************************************** +# Set False Paths +#************************************************************** + +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_break_path|break_readreg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|*resetlatch] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[33]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_ready] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[0]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_error] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[34]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_ocimem_path|*MonDReg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] +set_false_path -from *$nios_system_nios2_processor_jtag_sr* -to *$nios_system_nios2_processor_jtag_sysclk_path|*jdo* +set_false_path -from sld_hub:*|irf_reg* -to *$nios_system_nios2_processor_jtag_sysclk_path|ir* +set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios_system_nios2_processor_oci_debug_path|monitor_go diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor.v b/db/ip/nios_system/submodules/nios_system_nios2_processor.v new file mode 100644 index 0000000..c21e473 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor.v @@ -0,0 +1,5672 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_register_bank_a_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_register_bank_b_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_debug ( + // inputs: + clk, + dbrk_break, + debugreq, + hbreak_enabled, + jdo, + jrst_n, + ocireg_ers, + ocireg_mrs, + reset, + st_ready_test_idle, + take_action_ocimem_a, + take_action_ocireg, + xbrk_break, + + // outputs: + debugack, + monitor_error, + monitor_go, + monitor_ready, + oci_hbreak_req, + resetlatch, + resetrequest + ) +; + + output debugack; + output monitor_error; + output monitor_go; + output monitor_ready; + output oci_hbreak_req; + output resetlatch; + output resetrequest; + input clk; + input dbrk_break; + input debugreq; + input hbreak_enabled; + input [ 37: 0] jdo; + input jrst_n; + input ocireg_ers; + input ocireg_mrs; + input reset; + input st_ready_test_idle; + input take_action_ocimem_a; + input take_action_ocireg; + input xbrk_break; + + reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire debugack; + reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire oci_hbreak_req; + wire reset_sync; + reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire unxcomplemented_resetxx0; + assign unxcomplemented_resetxx0 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer + ( + .clk (clk), + .din (reset), + .dout (reset_sync), + .reset_n (unxcomplemented_resetxx0) + ); + + defparam the_altera_std_synchronizer.depth = 2; + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + break_on_reset <= 1'b0; + resetrequest <= 1'b0; + jtag_break <= 1'b0; + end + else if (take_action_ocimem_a) + begin + resetrequest <= jdo[22]; + jtag_break <= jdo[21] ? 1 + : jdo[20] ? 0 + : jtag_break; + + break_on_reset <= jdo[19] ? 1 + : jdo[18] ? 0 + : break_on_reset; + + resetlatch <= jdo[24] ? 0 : resetlatch; + end + else if (reset_sync) + begin + jtag_break <= break_on_reset; + resetlatch <= 1; + end + else if (debugreq & ~debugack & break_on_reset) + jtag_break <= 1'b1; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + monitor_ready <= 1'b0; + monitor_error <= 1'b0; + monitor_go <= 1'b0; + end + else + begin + if (take_action_ocimem_a && jdo[25]) + monitor_ready <= 1'b0; + else if (take_action_ocireg && ocireg_mrs) + monitor_ready <= 1'b1; + if (take_action_ocimem_a && jdo[25]) + monitor_error <= 1'b0; + else if (take_action_ocireg && ocireg_ers) + monitor_error <= 1'b1; + if (take_action_ocimem_a && jdo[23]) + monitor_go <= 1'b1; + else if (st_ready_test_idle) + monitor_go <= 1'b0; + end + end + + + assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq; + assign debugack = ~hbreak_enabled; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_ociram_sp_ram_module ( + // inputs: + address, + byteenable, + clock, + data, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input [ 7: 0] address; + input [ 3: 0] byteenable; + input clock; + input [ 31: 0] data; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clock), + .data_a (data), + .q_a (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 256, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 8; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_ocimem ( + // inputs: + address, + byteenable, + clk, + debugaccess, + jdo, + jrst_n, + read, + take_action_ocimem_a, + take_action_ocimem_b, + take_no_action_ocimem_a, + write, + writedata, + + // outputs: + MonDReg, + ociram_readdata, + waitrequest + ) +; + + output [ 31: 0] MonDReg; + output [ 31: 0] ociram_readdata; + output waitrequest; + input [ 8: 0] address; + input [ 3: 0] byteenable; + input clk; + input debugaccess; + input [ 37: 0] jdo; + input jrst_n; + input read; + input take_action_ocimem_a; + input take_action_ocimem_b; + input take_no_action_ocimem_a; + input write; + input [ 31: 0] writedata; + + reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 8: 0] MonARegAddrInc; + wire MonARegAddrIncAccessingRAM; + reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire avalon_ram_wr; + wire [ 31: 0] cfgrom_readdata; + reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 7: 0] ociram_addr; + wire [ 3: 0] ociram_byteenable; + wire [ 31: 0] ociram_readdata; + wire [ 31: 0] ociram_wr_data; + wire ociram_wr_en; + reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + jtag_rd <= 1'b0; + jtag_rd_d1 <= 1'b0; + jtag_ram_wr <= 1'b0; + jtag_ram_rd <= 1'b0; + jtag_ram_rd_d1 <= 1'b0; + jtag_ram_access <= 1'b0; + MonAReg <= 0; + MonDReg <= 0; + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + else + begin + if (take_no_action_ocimem_a) + begin + MonAReg[10 : 2] <= MonARegAddrInc; + jtag_rd <= 1'b1; + jtag_ram_rd <= MonARegAddrIncAccessingRAM; + jtag_ram_access <= MonARegAddrIncAccessingRAM; + end + else if (take_action_ocimem_a) + begin + MonAReg[10 : 2] <= { jdo[17], + jdo[33 : 26] }; + + jtag_rd <= 1'b1; + jtag_ram_rd <= ~jdo[17]; + jtag_ram_access <= ~jdo[17]; + end + else if (take_action_ocimem_b) + begin + MonAReg[10 : 2] <= MonARegAddrInc; + MonDReg <= jdo[34 : 3]; + jtag_ram_wr <= MonARegAddrIncAccessingRAM; + jtag_ram_access <= MonARegAddrIncAccessingRAM; + end + else + begin + jtag_rd <= 0; + jtag_ram_wr <= 0; + jtag_ram_rd <= 0; + jtag_ram_access <= 0; + if (jtag_rd_d1) + MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata; + end + jtag_rd_d1 <= jtag_rd; + jtag_ram_rd_d1 <= jtag_ram_rd; + if (~waitrequest) + begin + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + else if (write) + waitrequest <= ~address[8] & jtag_ram_access; + else if (read) + begin + avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access); + waitrequest <= ~avalon_ociram_readdata_ready; + end + else + begin + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + end + end + + + assign MonARegAddrInc = MonAReg[10 : 2]+1; + assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8]; + assign avalon_ram_wr = write & ~address[8] & debugaccess; + assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0]; + assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata; + assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable; + assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr; +//nios_system_nios2_processor_ociram_sp_ram, which is an nios_sp_ram +nios_system_nios2_processor_ociram_sp_ram_module nios_system_nios2_processor_ociram_sp_ram + ( + .address (ociram_addr), + .byteenable (ociram_byteenable), + .clock (clk), + .data (ociram_wr_data), + .q (ociram_readdata), + .wren (ociram_wr_en) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.dat"; +`else +defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.mif"; +//synthesis read_comments_as_HDL off + assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : + (MonAReg[4 : 2] == 3'd1)? 32'h00001313 : + (MonAReg[4 : 2] == 3'd2)? 32'h00040000 : + (MonAReg[4 : 2] == 3'd3)? 32'h00000000 : + (MonAReg[4 : 2] == 3'd4)? 32'h20000000 : + (MonAReg[4 : 2] == 3'd5)? 32'h00000000 : + (MonAReg[4 : 2] == 3'd6)? 32'h00000000 : + 32'h00000000; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_avalon_reg ( + // inputs: + address, + clk, + debugaccess, + monitor_error, + monitor_go, + monitor_ready, + reset_n, + write, + writedata, + + // outputs: + oci_ienable, + oci_reg_readdata, + oci_single_step_mode, + ocireg_ers, + ocireg_mrs, + take_action_ocireg + ) +; + + output [ 31: 0] oci_ienable; + output [ 31: 0] oci_reg_readdata; + output oci_single_step_mode; + output ocireg_ers; + output ocireg_mrs; + output take_action_ocireg; + input [ 8: 0] address; + input clk; + input debugaccess; + input monitor_error; + input monitor_go; + input monitor_ready; + input reset_n; + input write; + input [ 31: 0] writedata; + + reg [ 31: 0] oci_ienable; + wire oci_reg_00_addressed; + wire oci_reg_01_addressed; + wire [ 31: 0] oci_reg_readdata; + reg oci_single_step_mode; + wire ocireg_ers; + wire ocireg_mrs; + wire ocireg_sstep; + wire take_action_oci_intr_mask_reg; + wire take_action_ocireg; + wire write_strobe; + assign oci_reg_00_addressed = address == 9'h100; + assign oci_reg_01_addressed = address == 9'h101; + assign write_strobe = write & debugaccess; + assign take_action_ocireg = write_strobe & oci_reg_00_addressed; + assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed; + assign ocireg_ers = writedata[1]; + assign ocireg_mrs = writedata[0]; + assign ocireg_sstep = writedata[3]; + assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go, + monitor_ready, monitor_error} : + oci_reg_01_addressed ? oci_ienable : + 32'b0; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + oci_single_step_mode <= 1'b0; + else if (take_action_ocireg) + oci_single_step_mode <= ocireg_sstep; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + oci_ienable <= 32'b00000000000000000000000000100000; + else if (take_action_oci_intr_mask_reg) + oci_ienable <= writedata | ~(32'b00000000000000000000000000100000); + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_break ( + // inputs: + clk, + dbrk_break, + dbrk_goto0, + dbrk_goto1, + jdo, + jrst_n, + reset_n, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + xbrk_goto0, + xbrk_goto1, + + // outputs: + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + trigbrktype, + trigger_state_0, + trigger_state_1, + xbrk_ctrl0, + xbrk_ctrl1, + xbrk_ctrl2, + xbrk_ctrl3 + ) +; + + output [ 31: 0] break_readreg; + output dbrk_hit0_latch; + output dbrk_hit1_latch; + output dbrk_hit2_latch; + output dbrk_hit3_latch; + output trigbrktype; + output trigger_state_0; + output trigger_state_1; + output [ 7: 0] xbrk_ctrl0; + output [ 7: 0] xbrk_ctrl1; + output [ 7: 0] xbrk_ctrl2; + output [ 7: 0] xbrk_ctrl3; + input clk; + input dbrk_break; + input dbrk_goto0; + input dbrk_goto1; + input [ 37: 0] jdo; + input jrst_n; + input reset_n; + input take_action_break_a; + input take_action_break_b; + input take_action_break_c; + input take_no_action_break_a; + input take_no_action_break_b; + input take_no_action_break_c; + input xbrk_goto0; + input xbrk_goto1; + + wire [ 3: 0] break_a_wpr; + wire [ 1: 0] break_a_wpr_high_bits; + wire [ 1: 0] break_a_wpr_low_bits; + wire [ 1: 0] break_b_rr; + wire [ 1: 0] break_c_rr; + reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire dbrk0_high_value; + wire dbrk0_low_value; + wire dbrk1_high_value; + wire dbrk1_low_value; + wire dbrk2_high_value; + wire dbrk2_low_value; + wire dbrk3_high_value; + wire dbrk3_low_value; + wire dbrk_hit0_latch; + wire dbrk_hit1_latch; + wire dbrk_hit2_latch; + wire dbrk_hit3_latch; + wire take_action_any_break; + reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg trigger_state; + wire trigger_state_0; + wire trigger_state_1; + wire [ 31: 0] xbrk0_value; + wire [ 31: 0] xbrk1_value; + wire [ 31: 0] xbrk2_value; + wire [ 31: 0] xbrk3_value; + reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + assign break_a_wpr = jdo[35 : 32]; + assign break_a_wpr_high_bits = break_a_wpr[3 : 2]; + assign break_a_wpr_low_bits = break_a_wpr[1 : 0]; + assign break_b_rr = jdo[33 : 32]; + assign break_c_rr = jdo[33 : 32]; + assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + xbrk_ctrl0 <= 0; + xbrk_ctrl1 <= 0; + xbrk_ctrl2 <= 0; + xbrk_ctrl3 <= 0; + trigbrktype <= 0; + end + else + begin + if (take_action_any_break) + trigbrktype <= 0; + else if (dbrk_break) + trigbrktype <= 1; + if (take_action_break_b) + begin + if ((break_b_rr == 2'b00) && (0 >= 1)) + begin + xbrk_ctrl0[0] <= jdo[27]; + xbrk_ctrl0[1] <= jdo[28]; + xbrk_ctrl0[2] <= jdo[29]; + xbrk_ctrl0[3] <= jdo[30]; + xbrk_ctrl0[4] <= jdo[21]; + xbrk_ctrl0[5] <= jdo[20]; + xbrk_ctrl0[6] <= jdo[19]; + xbrk_ctrl0[7] <= jdo[18]; + end + if ((break_b_rr == 2'b01) && (0 >= 2)) + begin + xbrk_ctrl1[0] <= jdo[27]; + xbrk_ctrl1[1] <= jdo[28]; + xbrk_ctrl1[2] <= jdo[29]; + xbrk_ctrl1[3] <= jdo[30]; + xbrk_ctrl1[4] <= jdo[21]; + xbrk_ctrl1[5] <= jdo[20]; + xbrk_ctrl1[6] <= jdo[19]; + xbrk_ctrl1[7] <= jdo[18]; + end + if ((break_b_rr == 2'b10) && (0 >= 3)) + begin + xbrk_ctrl2[0] <= jdo[27]; + xbrk_ctrl2[1] <= jdo[28]; + xbrk_ctrl2[2] <= jdo[29]; + xbrk_ctrl2[3] <= jdo[30]; + xbrk_ctrl2[4] <= jdo[21]; + xbrk_ctrl2[5] <= jdo[20]; + xbrk_ctrl2[6] <= jdo[19]; + xbrk_ctrl2[7] <= jdo[18]; + end + if ((break_b_rr == 2'b11) && (0 >= 4)) + begin + xbrk_ctrl3[0] <= jdo[27]; + xbrk_ctrl3[1] <= jdo[28]; + xbrk_ctrl3[2] <= jdo[29]; + xbrk_ctrl3[3] <= jdo[30]; + xbrk_ctrl3[4] <= jdo[21]; + xbrk_ctrl3[5] <= jdo[20]; + xbrk_ctrl3[6] <= jdo[19]; + xbrk_ctrl3[7] <= jdo[18]; + end + end + end + end + + + assign dbrk_hit0_latch = 1'b0; + assign dbrk0_low_value = 0; + assign dbrk0_high_value = 0; + assign dbrk_hit1_latch = 1'b0; + assign dbrk1_low_value = 0; + assign dbrk1_high_value = 0; + assign dbrk_hit2_latch = 1'b0; + assign dbrk2_low_value = 0; + assign dbrk2_high_value = 0; + assign dbrk_hit3_latch = 1'b0; + assign dbrk3_low_value = 0; + assign dbrk3_high_value = 0; + assign xbrk0_value = 32'b0; + assign xbrk1_value = 32'b0; + assign xbrk2_value = 32'b0; + assign xbrk3_value = 32'b0; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + break_readreg <= 32'b0; + else if (take_action_any_break) + break_readreg <= jdo[31 : 0]; + else if (take_no_action_break_a) + case (break_a_wpr_high_bits) + + 2'd0: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= xbrk0_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= xbrk1_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= xbrk2_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= xbrk3_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd0 + + 2'd1: begin + break_readreg <= 32'b0; + end // 2'd1 + + 2'd2: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= dbrk0_low_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= dbrk1_low_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= dbrk2_low_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= dbrk3_low_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd2 + + 2'd3: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= dbrk0_high_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= dbrk1_high_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= dbrk2_high_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= dbrk3_high_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd3 + + endcase // break_a_wpr_high_bits + else if (take_no_action_break_b) + break_readreg <= jdo[31 : 0]; + else if (take_no_action_break_c) + break_readreg <= jdo[31 : 0]; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + trigger_state <= 0; + else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0)) + trigger_state <= 0; + else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1)) + trigger_state <= -1; + end + + + assign trigger_state_0 = ~trigger_state; + assign trigger_state_1 = trigger_state; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_xbrk ( + // inputs: + D_valid, + E_valid, + F_pc, + clk, + reset_n, + trigger_state_0, + trigger_state_1, + xbrk_ctrl0, + xbrk_ctrl1, + xbrk_ctrl2, + xbrk_ctrl3, + + // outputs: + xbrk_break, + xbrk_goto0, + xbrk_goto1, + xbrk_traceoff, + xbrk_traceon, + xbrk_trigout + ) +; + + output xbrk_break; + output xbrk_goto0; + output xbrk_goto1; + output xbrk_traceoff; + output xbrk_traceon; + output xbrk_trigout; + input D_valid; + input E_valid; + input [ 16: 0] F_pc; + input clk; + input reset_n; + input trigger_state_0; + input trigger_state_1; + input [ 7: 0] xbrk_ctrl0; + input [ 7: 0] xbrk_ctrl1; + input [ 7: 0] xbrk_ctrl2; + input [ 7: 0] xbrk_ctrl3; + + wire D_cpu_addr_en; + wire E_cpu_addr_en; + reg E_xbrk_goto0; + reg E_xbrk_goto1; + reg E_xbrk_traceoff; + reg E_xbrk_traceon; + reg E_xbrk_trigout; + wire [ 18: 0] cpu_i_address; + wire xbrk0_armed; + wire xbrk0_break_hit; + wire xbrk0_goto0_hit; + wire xbrk0_goto1_hit; + wire xbrk0_toff_hit; + wire xbrk0_ton_hit; + wire xbrk0_tout_hit; + wire xbrk1_armed; + wire xbrk1_break_hit; + wire xbrk1_goto0_hit; + wire xbrk1_goto1_hit; + wire xbrk1_toff_hit; + wire xbrk1_ton_hit; + wire xbrk1_tout_hit; + wire xbrk2_armed; + wire xbrk2_break_hit; + wire xbrk2_goto0_hit; + wire xbrk2_goto1_hit; + wire xbrk2_toff_hit; + wire xbrk2_ton_hit; + wire xbrk2_tout_hit; + wire xbrk3_armed; + wire xbrk3_break_hit; + wire xbrk3_goto0_hit; + wire xbrk3_goto1_hit; + wire xbrk3_toff_hit; + wire xbrk3_ton_hit; + wire xbrk3_tout_hit; + reg xbrk_break; + wire xbrk_break_hit; + wire xbrk_goto0; + wire xbrk_goto0_hit; + wire xbrk_goto1; + wire xbrk_goto1_hit; + wire xbrk_toff_hit; + wire xbrk_ton_hit; + wire xbrk_tout_hit; + wire xbrk_traceoff; + wire xbrk_traceon; + wire xbrk_trigout; + assign cpu_i_address = {F_pc, 2'b00}; + assign D_cpu_addr_en = D_valid; + assign E_cpu_addr_en = E_valid; + assign xbrk0_break_hit = 0; + assign xbrk0_ton_hit = 0; + assign xbrk0_toff_hit = 0; + assign xbrk0_tout_hit = 0; + assign xbrk0_goto0_hit = 0; + assign xbrk0_goto1_hit = 0; + assign xbrk1_break_hit = 0; + assign xbrk1_ton_hit = 0; + assign xbrk1_toff_hit = 0; + assign xbrk1_tout_hit = 0; + assign xbrk1_goto0_hit = 0; + assign xbrk1_goto1_hit = 0; + assign xbrk2_break_hit = 0; + assign xbrk2_ton_hit = 0; + assign xbrk2_toff_hit = 0; + assign xbrk2_tout_hit = 0; + assign xbrk2_goto0_hit = 0; + assign xbrk2_goto1_hit = 0; + assign xbrk3_break_hit = 0; + assign xbrk3_ton_hit = 0; + assign xbrk3_toff_hit = 0; + assign xbrk3_tout_hit = 0; + assign xbrk3_goto0_hit = 0; + assign xbrk3_goto1_hit = 0; + assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit); + assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit); + assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit); + assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit); + assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit); + assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + xbrk_break <= 0; + else if (E_cpu_addr_en) + xbrk_break <= xbrk_break_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_traceon <= 0; + else if (E_cpu_addr_en) + E_xbrk_traceon <= xbrk_ton_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_traceoff <= 0; + else if (E_cpu_addr_en) + E_xbrk_traceoff <= xbrk_toff_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_trigout <= 0; + else if (E_cpu_addr_en) + E_xbrk_trigout <= xbrk_tout_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_goto0 <= 0; + else if (E_cpu_addr_en) + E_xbrk_goto0 <= xbrk_goto0_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_goto1 <= 0; + else if (E_cpu_addr_en) + E_xbrk_goto1 <= xbrk_goto1_hit; + end + + + assign xbrk_traceon = 1'b0; + assign xbrk_traceoff = 1'b0; + assign xbrk_trigout = 1'b0; + assign xbrk_goto0 = 1'b0; + assign xbrk_goto1 = 1'b0; + assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) || + (xbrk_ctrl0[5] & trigger_state_1); + + assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) || + (xbrk_ctrl1[5] & trigger_state_1); + + assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) || + (xbrk_ctrl2[5] & trigger_state_1); + + assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) || + (xbrk_ctrl3[5] & trigger_state_1); + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_dbrk ( + // inputs: + E_st_data, + av_ld_data_aligned_filtered, + clk, + d_address, + d_read, + d_waitrequest, + d_write, + debugack, + reset_n, + + // outputs: + cpu_d_address, + cpu_d_read, + cpu_d_readdata, + cpu_d_wait, + cpu_d_write, + cpu_d_writedata, + dbrk_break, + dbrk_goto0, + dbrk_goto1, + dbrk_traceme, + dbrk_traceoff, + dbrk_traceon, + dbrk_trigout + ) +; + + output [ 18: 0] cpu_d_address; + output cpu_d_read; + output [ 31: 0] cpu_d_readdata; + output cpu_d_wait; + output cpu_d_write; + output [ 31: 0] cpu_d_writedata; + output dbrk_break; + output dbrk_goto0; + output dbrk_goto1; + output dbrk_traceme; + output dbrk_traceoff; + output dbrk_traceon; + output dbrk_trigout; + input [ 31: 0] E_st_data; + input [ 31: 0] av_ld_data_aligned_filtered; + input clk; + input [ 18: 0] d_address; + input d_read; + input d_waitrequest; + input d_write; + input debugack; + input reset_n; + + wire [ 18: 0] cpu_d_address; + wire cpu_d_read; + wire [ 31: 0] cpu_d_readdata; + wire cpu_d_wait; + wire cpu_d_write; + wire [ 31: 0] cpu_d_writedata; + wire dbrk0_armed; + wire dbrk0_break_pulse; + wire dbrk0_goto0; + wire dbrk0_goto1; + wire dbrk0_traceme; + wire dbrk0_traceoff; + wire dbrk0_traceon; + wire dbrk0_trigout; + wire dbrk1_armed; + wire dbrk1_break_pulse; + wire dbrk1_goto0; + wire dbrk1_goto1; + wire dbrk1_traceme; + wire dbrk1_traceoff; + wire dbrk1_traceon; + wire dbrk1_trigout; + wire dbrk2_armed; + wire dbrk2_break_pulse; + wire dbrk2_goto0; + wire dbrk2_goto1; + wire dbrk2_traceme; + wire dbrk2_traceoff; + wire dbrk2_traceon; + wire dbrk2_trigout; + wire dbrk3_armed; + wire dbrk3_break_pulse; + wire dbrk3_goto0; + wire dbrk3_goto1; + wire dbrk3_traceme; + wire dbrk3_traceoff; + wire dbrk3_traceon; + wire dbrk3_trigout; + reg dbrk_break; + reg dbrk_break_pulse; + wire [ 31: 0] dbrk_data; + reg dbrk_goto0; + reg dbrk_goto1; + reg dbrk_traceme; + reg dbrk_traceoff; + reg dbrk_traceon; + reg dbrk_trigout; + assign cpu_d_address = d_address; + assign cpu_d_readdata = av_ld_data_aligned_filtered; + assign cpu_d_read = d_read; + assign cpu_d_writedata = E_st_data; + assign cpu_d_write = d_write; + assign cpu_d_wait = d_waitrequest; + assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + dbrk_break <= 0; + else + dbrk_break <= dbrk_break ? ~debugack + : dbrk_break_pulse; + + end + + + assign dbrk0_armed = 1'b0; + assign dbrk0_trigout = 1'b0; + assign dbrk0_break_pulse = 1'b0; + assign dbrk0_traceoff = 1'b0; + assign dbrk0_traceon = 1'b0; + assign dbrk0_traceme = 1'b0; + assign dbrk0_goto0 = 1'b0; + assign dbrk0_goto1 = 1'b0; + assign dbrk1_armed = 1'b0; + assign dbrk1_trigout = 1'b0; + assign dbrk1_break_pulse = 1'b0; + assign dbrk1_traceoff = 1'b0; + assign dbrk1_traceon = 1'b0; + assign dbrk1_traceme = 1'b0; + assign dbrk1_goto0 = 1'b0; + assign dbrk1_goto1 = 1'b0; + assign dbrk2_armed = 1'b0; + assign dbrk2_trigout = 1'b0; + assign dbrk2_break_pulse = 1'b0; + assign dbrk2_traceoff = 1'b0; + assign dbrk2_traceon = 1'b0; + assign dbrk2_traceme = 1'b0; + assign dbrk2_goto0 = 1'b0; + assign dbrk2_goto1 = 1'b0; + assign dbrk3_armed = 1'b0; + assign dbrk3_trigout = 1'b0; + assign dbrk3_break_pulse = 1'b0; + assign dbrk3_traceoff = 1'b0; + assign dbrk3_traceon = 1'b0; + assign dbrk3_traceme = 1'b0; + assign dbrk3_goto0 = 1'b0; + assign dbrk3_goto1 = 1'b0; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + dbrk_trigout <= 0; + dbrk_break_pulse <= 0; + dbrk_traceoff <= 0; + dbrk_traceon <= 0; + dbrk_traceme <= 0; + dbrk_goto0 <= 0; + dbrk_goto1 <= 0; + end + else + begin + dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout; + dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse; + dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff; + dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon; + dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme; + dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0; + dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1; + end + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_itrace ( + // inputs: + clk, + dbrk_traceoff, + dbrk_traceon, + jdo, + jrst_n, + take_action_tracectrl, + trc_enb, + xbrk_traceoff, + xbrk_traceon, + xbrk_wrap_traceoff, + + // outputs: + dct_buffer, + dct_count, + itm, + trc_ctrl, + trc_on + ) +; + + output [ 29: 0] dct_buffer; + output [ 3: 0] dct_count; + output [ 35: 0] itm; + output [ 15: 0] trc_ctrl; + output trc_on; + input clk; + input dbrk_traceoff; + input dbrk_traceon; + input [ 15: 0] jdo; + input jrst_n; + input take_action_tracectrl; + input trc_enb; + input xbrk_traceoff; + input xbrk_traceon; + input xbrk_wrap_traceoff; + + wire curr_pid; + reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 1: 0] dct_code; + reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire dct_is_taken; + wire [ 31: 0] excaddr; + wire instr_retired; + wire is_advanced_exception; + wire is_cond_dct; + wire is_dct; + wire is_exception_no_break; + wire is_fast_tlb_miss_exception; + wire is_idct; + reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire not_in_debug_mode; + reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire record_dct_outcome_in_sync; + wire record_itrace; + wire [ 31: 0] retired_pcb; + reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 1: 0] sync_code; + wire [ 6: 0] sync_interval; + wire sync_pending; + reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 6: 0] sync_timer_next; + reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire [ 15: 0] trc_ctrl; + reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire trc_on; + assign is_cond_dct = 1'b0; + assign is_dct = 1'b0; + assign dct_is_taken = 1'b0; + assign is_idct = 1'b0; + assign retired_pcb = 32'b0; + assign not_in_debug_mode = 1'b0; + assign instr_retired = 1'b0; + assign is_advanced_exception = 1'b0; + assign is_exception_no_break = 1'b0; + assign is_fast_tlb_miss_exception = 1'b0; + assign curr_pid = 1'b0; + assign excaddr = 32'b0; + assign sync_code = trc_ctrl[3 : 2]; + assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 }; + assign sync_pending = sync_timer == 0; + assign record_dct_outcome_in_sync = dct_is_taken & sync_pending; + assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1); + assign record_itrace = trc_on & trc_ctrl[4]; + assign dct_code = {is_cond_dct, dct_is_taken}; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + trc_clear <= 0; + else + trc_clear <= ~trc_enb & + take_action_tracectrl & jdo[4]; + + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + itm <= 0; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= 0; + pending_frametype <= 4'b0000; + pending_exctype <= 1'b0; + pending_excaddr <= 0; + prev_pid <= 0; + prev_pid_valid <= 0; + snapped_pid <= 0; + snapped_curr_pid <= 0; + snapped_prev_pid <= 0; + pending_curr_pid <= 0; + pending_prev_pid <= 0; + end + else if (trc_clear || (!0 && !0)) + begin + itm <= 0; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= 0; + pending_frametype <= 4'b0000; + pending_exctype <= 1'b0; + pending_excaddr <= 0; + prev_pid <= 0; + prev_pid_valid <= 0; + snapped_pid <= 0; + snapped_curr_pid <= 0; + snapped_prev_pid <= 0; + pending_curr_pid <= 0; + pending_prev_pid <= 0; + end + else + begin + if (!prev_pid_valid) + begin + prev_pid <= curr_pid; + prev_pid_valid <= 1; + end + if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid) + begin + snapped_pid <= 1; + snapped_curr_pid <= curr_pid; + snapped_prev_pid <= prev_pid; + prev_pid <= curr_pid; + prev_pid_valid <= 1; + end + if (instr_retired | is_advanced_exception) + begin + if (~record_itrace) + pending_frametype <= 4'b1010; + else if (is_exception_no_break) + begin + pending_frametype <= 4'b0010; + pending_excaddr <= excaddr; + if (is_fast_tlb_miss_exception) + pending_exctype <= 1'b1; + else + pending_exctype <= 1'b0; + end + else if (is_idct) + pending_frametype <= 4'b1001; + else if (record_dct_outcome_in_sync) + pending_frametype <= 4'b1000; + else if (!is_dct & snapped_pid) + begin + pending_frametype <= 4'b0011; + pending_curr_pid <= snapped_curr_pid; + pending_prev_pid <= snapped_prev_pid; + snapped_pid <= 0; + end + else + pending_frametype <= 4'b0000; + if ((dct_count != 0) & + (~record_itrace | + is_exception_no_break | + is_idct | + record_dct_outcome_in_sync | + (!is_dct & snapped_pid))) + begin + itm <= {4'b0001, dct_buffer, 2'b00}; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= sync_timer_next; + end + else + begin + if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception) + begin + dct_buffer <= {dct_code, dct_buffer[29 : 2]}; + dct_count <= dct_count + 1; + end + if (record_itrace & (pending_frametype == 4'b0010)) + itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype}; + else if (record_itrace & ( + (pending_frametype == 4'b1000) | + (pending_frametype == 4'b1010) | + (pending_frametype == 4'b1001))) + begin + itm <= {pending_frametype, retired_pcb}; + sync_timer <= sync_interval; + if (0 & + ((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) & + !snapped_pid & prev_pid_valid) + begin + snapped_pid <= 1; + snapped_curr_pid <= curr_pid; + snapped_prev_pid <= prev_pid; + end + end + else if (record_itrace & + 0 & (pending_frametype == 4'b0011)) + itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid}; + else if (record_itrace & is_dct) + begin + if (dct_count == 4'd15) + begin + itm <= {4'b0001, dct_code, dct_buffer}; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= sync_timer_next; + end + else + itm <= 4'b0000; + end + else + itm <= {4'b0000, 32'b0}; + end + end + else + itm <= {4'b0000, 32'b0}; + end + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + trc_ctrl_reg[0] <= 1'b0; + trc_ctrl_reg[1] <= 1'b0; + trc_ctrl_reg[3 : 2] <= 2'b00; + trc_ctrl_reg[4] <= 1'b0; + trc_ctrl_reg[7 : 5] <= 3'b000; + trc_ctrl_reg[8] <= 0; + trc_ctrl_reg[9] <= 1'b0; + trc_ctrl_reg[10] <= 1'b0; + end + else if (take_action_tracectrl) + begin + trc_ctrl_reg[0] <= jdo[5]; + trc_ctrl_reg[1] <= jdo[6]; + trc_ctrl_reg[3 : 2] <= jdo[8 : 7]; + trc_ctrl_reg[4] <= jdo[9]; + trc_ctrl_reg[9] <= jdo[14]; + trc_ctrl_reg[10] <= jdo[2]; + if (0) + trc_ctrl_reg[7 : 5] <= jdo[12 : 10]; + if (0 & 0) + trc_ctrl_reg[8] <= jdo[13]; + end + else if (xbrk_wrap_traceoff) + begin + trc_ctrl_reg[1] <= 0; + trc_ctrl_reg[0] <= 0; + end + else if (dbrk_traceoff | xbrk_traceoff) + trc_ctrl_reg[1] <= 0; + else if (trc_ctrl_reg[0] & + (dbrk_traceon | xbrk_traceon)) + trc_ctrl_reg[1] <= 1; + end + + + assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0; + assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode); + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_td_mode ( + // inputs: + ctrl, + + // outputs: + td_mode + ) +; + + output [ 3: 0] td_mode; + input [ 8: 0] ctrl; + + wire [ 2: 0] ctrl_bits_for_mux; + reg [ 3: 0] td_mode; + assign ctrl_bits_for_mux = ctrl[7 : 5]; + always @(ctrl_bits_for_mux) + begin + case (ctrl_bits_for_mux) + + 3'b000: begin + td_mode = 4'b0000; + end // 3'b000 + + 3'b001: begin + td_mode = 4'b1000; + end // 3'b001 + + 3'b010: begin + td_mode = 4'b0100; + end // 3'b010 + + 3'b011: begin + td_mode = 4'b1100; + end // 3'b011 + + 3'b100: begin + td_mode = 4'b0010; + end // 3'b100 + + 3'b101: begin + td_mode = 4'b1010; + end // 3'b101 + + 3'b110: begin + td_mode = 4'b0101; + end // 3'b110 + + 3'b111: begin + td_mode = 4'b1111; + end // 3'b111 + + endcase // ctrl_bits_for_mux + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_dtrace ( + // inputs: + clk, + cpu_d_address, + cpu_d_read, + cpu_d_readdata, + cpu_d_wait, + cpu_d_write, + cpu_d_writedata, + jrst_n, + trc_ctrl, + + // outputs: + atm, + dtm + ) +; + + output [ 35: 0] atm; + output [ 35: 0] dtm; + input clk; + input [ 18: 0] cpu_d_address; + input cpu_d_read; + input [ 31: 0] cpu_d_readdata; + input cpu_d_wait; + input cpu_d_write; + input [ 31: 0] cpu_d_writedata; + input jrst_n; + input [ 15: 0] trc_ctrl; + + reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 31: 0] cpu_d_address_0_padded; + wire [ 31: 0] cpu_d_readdata_0_padded; + wire [ 31: 0] cpu_d_writedata_0_padded; + reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire record_load_addr; + wire record_load_data; + wire record_store_addr; + wire record_store_data; + wire [ 3: 0] td_mode_trc_ctrl; + assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0; + assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0; + assign cpu_d_address_0_padded = cpu_d_address | 32'b0; + //nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode, which is an e_instance + nios_system_nios2_processor_nios2_oci_td_mode nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode + ( + .ctrl (trc_ctrl[8 : 0]), + .td_mode (td_mode_trc_ctrl) + ); + + assign {record_load_addr, record_store_addr, + record_load_data, record_store_data} = td_mode_trc_ctrl; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + atm <= 0; + dtm <= 0; + end + else if (0) + begin + if (cpu_d_write & ~cpu_d_wait & record_store_addr) + atm <= {4'b0101, cpu_d_address_0_padded}; + else if (cpu_d_read & ~cpu_d_wait & record_load_addr) + atm <= {4'b0100, cpu_d_address_0_padded}; + else + atm <= {4'b0000, cpu_d_address_0_padded}; + if (cpu_d_write & ~cpu_d_wait & record_store_data) + dtm <= {4'b0111, cpu_d_writedata_0_padded}; + else if (cpu_d_read & ~cpu_d_wait & record_load_data) + dtm <= {4'b0110, cpu_d_readdata_0_padded}; + else + dtm <= {4'b0000, cpu_d_readdata_0_padded}; + end + else + begin + atm <= 0; + dtm <= 0; + end + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_compute_tm_count ( + // inputs: + atm_valid, + dtm_valid, + itm_valid, + + // outputs: + compute_tm_count + ) +; + + output [ 1: 0] compute_tm_count; + input atm_valid; + input dtm_valid; + input itm_valid; + + reg [ 1: 0] compute_tm_count; + wire [ 2: 0] switch_for_mux; + assign switch_for_mux = {itm_valid, atm_valid, dtm_valid}; + always @(switch_for_mux) + begin + case (switch_for_mux) + + 3'b000: begin + compute_tm_count = 0; + end // 3'b000 + + 3'b001: begin + compute_tm_count = 1; + end // 3'b001 + + 3'b010: begin + compute_tm_count = 1; + end // 3'b010 + + 3'b011: begin + compute_tm_count = 2; + end // 3'b011 + + 3'b100: begin + compute_tm_count = 1; + end // 3'b100 + + 3'b101: begin + compute_tm_count = 2; + end // 3'b101 + + 3'b110: begin + compute_tm_count = 2; + end // 3'b110 + + 3'b111: begin + compute_tm_count = 3; + end // 3'b111 + + endcase // switch_for_mux + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifowp_inc ( + // inputs: + free2, + free3, + tm_count, + + // outputs: + fifowp_inc + ) +; + + output [ 3: 0] fifowp_inc; + input free2; + input free3; + input [ 1: 0] tm_count; + + reg [ 3: 0] fifowp_inc; + always @(free2 or free3 or tm_count) + begin + if (free3 & (tm_count == 3)) + fifowp_inc = 3; + else if (free2 & (tm_count >= 2)) + fifowp_inc = 2; + else if (tm_count >= 1) + fifowp_inc = 1; + else + fifowp_inc = 0; + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifocount_inc ( + // inputs: + empty, + free2, + free3, + tm_count, + + // outputs: + fifocount_inc + ) +; + + output [ 4: 0] fifocount_inc; + input empty; + input free2; + input free3; + input [ 1: 0] tm_count; + + reg [ 4: 0] fifocount_inc; + always @(empty or free2 or free3 or tm_count) + begin + if (empty) + fifocount_inc = tm_count[1 : 0]; + else if (free3 & (tm_count == 3)) + fifocount_inc = 2; + else if (free2 & (tm_count >= 2)) + fifocount_inc = 1; + else if (tm_count >= 1) + fifocount_inc = 0; + else + fifocount_inc = {5{1'b1}}; + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifo ( + // inputs: + atm, + clk, + dbrk_traceme, + dbrk_traceoff, + dbrk_traceon, + dct_buffer, + dct_count, + dtm, + itm, + jrst_n, + reset_n, + test_ending, + test_has_ended, + trc_on, + + // outputs: + tw + ) +; + + output [ 35: 0] tw; + input [ 35: 0] atm; + input clk; + input dbrk_traceme; + input dbrk_traceoff; + input dbrk_traceon; + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input [ 35: 0] dtm; + input [ 35: 0] itm; + input jrst_n; + input reset_n; + input test_ending; + input test_has_ended; + input trc_on; + + wire atm_valid; + wire [ 1: 0] compute_tm_count_tm_count; + wire dtm_valid; + wire empty; + reg [ 35: 0] fifo_0; + wire fifo_0_enable; + wire [ 35: 0] fifo_0_mux; + reg [ 35: 0] fifo_1; + reg [ 35: 0] fifo_10; + wire fifo_10_enable; + wire [ 35: 0] fifo_10_mux; + reg [ 35: 0] fifo_11; + wire fifo_11_enable; + wire [ 35: 0] fifo_11_mux; + reg [ 35: 0] fifo_12; + wire fifo_12_enable; + wire [ 35: 0] fifo_12_mux; + reg [ 35: 0] fifo_13; + wire fifo_13_enable; + wire [ 35: 0] fifo_13_mux; + reg [ 35: 0] fifo_14; + wire fifo_14_enable; + wire [ 35: 0] fifo_14_mux; + reg [ 35: 0] fifo_15; + wire fifo_15_enable; + wire [ 35: 0] fifo_15_mux; + wire fifo_1_enable; + wire [ 35: 0] fifo_1_mux; + reg [ 35: 0] fifo_2; + wire fifo_2_enable; + wire [ 35: 0] fifo_2_mux; + reg [ 35: 0] fifo_3; + wire fifo_3_enable; + wire [ 35: 0] fifo_3_mux; + reg [ 35: 0] fifo_4; + wire fifo_4_enable; + wire [ 35: 0] fifo_4_mux; + reg [ 35: 0] fifo_5; + wire fifo_5_enable; + wire [ 35: 0] fifo_5_mux; + reg [ 35: 0] fifo_6; + wire fifo_6_enable; + wire [ 35: 0] fifo_6_mux; + reg [ 35: 0] fifo_7; + wire fifo_7_enable; + wire [ 35: 0] fifo_7_mux; + reg [ 35: 0] fifo_8; + wire fifo_8_enable; + wire [ 35: 0] fifo_8_mux; + reg [ 35: 0] fifo_9; + wire fifo_9_enable; + wire [ 35: 0] fifo_9_mux; + wire [ 35: 0] fifo_read_mux; + reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 4: 0] fifocount_inc_fifocount; + wire [ 35: 0] fifohead; + reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 3: 0] fifowp1; + wire [ 3: 0] fifowp2; + wire [ 3: 0] fifowp_inc_fifowp; + wire free2; + wire free3; + wire itm_valid; + reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 35: 0] ovr_pending_atm; + wire [ 35: 0] ovr_pending_dtm; + wire [ 1: 0] tm_count; + wire tm_count_ge1; + wire tm_count_ge2; + wire tm_count_ge3; + wire trc_this; + wire [ 35: 0] tw; + assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme; + assign itm_valid = |itm[35 : 32]; + assign atm_valid = |atm[35 : 32] & trc_this; + assign dtm_valid = |dtm[35 : 32] & trc_this; + assign free2 = ~fifocount[4]; + assign free3 = ~fifocount[4] & ~&fifocount[3 : 0]; + assign empty = ~|fifocount; + assign fifowp1 = fifowp + 1; + assign fifowp2 = fifowp + 2; + //nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count, which is an e_instance + nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count + ( + .atm_valid (atm_valid), + .compute_tm_count (compute_tm_count_tm_count), + .dtm_valid (dtm_valid), + .itm_valid (itm_valid) + ); + + assign tm_count = compute_tm_count_tm_count; + //nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp, which is an e_instance + nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp + ( + .fifowp_inc (fifowp_inc_fifowp), + .free2 (free2), + .free3 (free3), + .tm_count (tm_count) + ); + + //nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount, which is an e_instance + nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount + ( + .empty (empty), + .fifocount_inc (fifocount_inc_fifocount), + .free2 (free2), + .free3 (free3), + .tm_count (tm_count) + ); + + //the_nios_system_nios2_processor_oci_test_bench, which is an e_instance + nios_system_nios2_processor_oci_test_bench the_nios_system_nios2_processor_oci_test_bench + ( + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .test_ending (test_ending), + .test_has_ended (test_has_ended) + ); + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + fiforp <= 0; + fifowp <= 0; + fifocount <= 0; + ovf_pending <= 1; + end + else + begin + fifowp <= fifowp + fifowp_inc_fifowp; + fifocount <= fifocount + fifocount_inc_fifocount; + if (~empty) + fiforp <= fiforp + 1; + if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count))) + ovf_pending <= 1; + else if (atm_valid | dtm_valid) + ovf_pending <= 0; + end + end + + + assign fifohead = fifo_read_mux; + assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm; + assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_0 <= 0; + else if (fifo_0_enable) + fifo_0 <= fifo_0_mux; + end + + + assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm : + (((fifowp == 4'd0) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_1 <= 0; + else if (fifo_1_enable) + fifo_1 <= fifo_1_mux; + end + + + assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm : + (((fifowp == 4'd1) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_2 <= 0; + else if (fifo_2_enable) + fifo_2 <= fifo_2_mux; + end + + + assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm : + (((fifowp == 4'd2) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_3 <= 0; + else if (fifo_3_enable) + fifo_3 <= fifo_3_mux; + end + + + assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm : + (((fifowp == 4'd3) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_4 <= 0; + else if (fifo_4_enable) + fifo_4 <= fifo_4_mux; + end + + + assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm : + (((fifowp == 4'd4) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_5 <= 0; + else if (fifo_5_enable) + fifo_5 <= fifo_5_mux; + end + + + assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm : + (((fifowp == 4'd5) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_6 <= 0; + else if (fifo_6_enable) + fifo_6 <= fifo_6_mux; + end + + + assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm : + (((fifowp == 4'd6) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_7 <= 0; + else if (fifo_7_enable) + fifo_7 <= fifo_7_mux; + end + + + assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm : + (((fifowp == 4'd7) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_8 <= 0; + else if (fifo_8_enable) + fifo_8 <= fifo_8_mux; + end + + + assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm : + (((fifowp == 4'd8) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_9 <= 0; + else if (fifo_9_enable) + fifo_9 <= fifo_9_mux; + end + + + assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm : + (((fifowp == 4'd9) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_10 <= 0; + else if (fifo_10_enable) + fifo_10 <= fifo_10_mux; + end + + + assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm : + (((fifowp == 4'd10) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_11 <= 0; + else if (fifo_11_enable) + fifo_11 <= fifo_11_mux; + end + + + assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm : + (((fifowp == 4'd11) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_12 <= 0; + else if (fifo_12_enable) + fifo_12 <= fifo_12_mux; + end + + + assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm : + (((fifowp == 4'd12) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_13 <= 0; + else if (fifo_13_enable) + fifo_13 <= fifo_13_mux; + end + + + assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm : + (((fifowp == 4'd13) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_14 <= 0; + else if (fifo_14_enable) + fifo_14 <= fifo_14_mux; + end + + + assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm : + (((fifowp == 4'd14) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_15 <= 0; + else if (fifo_15_enable) + fifo_15 <= fifo_15_mux; + end + + + assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm : + (((fifowp == 4'd15) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign tm_count_ge1 = |tm_count; + assign tm_count_ge2 = tm_count[1]; + assign tm_count_ge3 = &tm_count; + assign ovr_pending_atm = {ovf_pending, atm[34 : 0]}; + assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]}; + assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 : + (fiforp == 4'd1)? fifo_1 : + (fiforp == 4'd2)? fifo_2 : + (fiforp == 4'd3)? fifo_3 : + (fiforp == 4'd4)? fifo_4 : + (fiforp == 4'd5)? fifo_5 : + (fiforp == 4'd6)? fifo_6 : + (fiforp == 4'd7)? fifo_7 : + (fiforp == 4'd8)? fifo_8 : + (fiforp == 4'd9)? fifo_9 : + (fiforp == 4'd10)? fifo_10 : + (fiforp == 4'd11)? fifo_11 : + (fiforp == 4'd12)? fifo_12 : + (fiforp == 4'd13)? fifo_13 : + (fiforp == 4'd14)? fifo_14 : + fifo_15; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_pib ( + // inputs: + clk, + clkx2, + jrst_n, + tw, + + // outputs: + tr_clk, + tr_data + ) +; + + output tr_clk; + output [ 17: 0] tr_data; + input clk; + input clkx2; + input jrst_n; + input [ 35: 0] tw; + + wire phase; + wire tr_clk; + reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 17: 0] tr_data; + reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + assign phase = x1^x2; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + x1 <= 0; + else + x1 <= ~x1; + end + + + always @(posedge clkx2 or negedge jrst_n) + begin + if (jrst_n == 0) + begin + x2 <= 0; + tr_clk_reg <= 0; + tr_data_reg <= 0; + end + else + begin + x2 <= x1; + tr_clk_reg <= ~phase; + tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18]; + end + end + + + assign tr_clk = 0 ? tr_clk_reg : 0; + assign tr_data = 0 ? tr_data_reg : 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_im ( + // inputs: + clk, + jdo, + jrst_n, + reset_n, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_tracemem_a, + trc_ctrl, + tw, + + // outputs: + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_enb, + trc_im_addr, + trc_wrap, + xbrk_wrap_traceoff + ) +; + + output tracemem_on; + output [ 35: 0] tracemem_trcdata; + output tracemem_tw; + output trc_enb; + output [ 6: 0] trc_im_addr; + output trc_wrap; + output xbrk_wrap_traceoff; + input clk; + input [ 37: 0] jdo; + input jrst_n; + input reset_n; + input take_action_tracectrl; + input take_action_tracemem_a; + input take_action_tracemem_b; + input take_no_action_tracemem_a; + input [ 15: 0] trc_ctrl; + input [ 35: 0] tw; + + wire tracemem_on; + wire [ 35: 0] tracemem_trcdata; + wire tracemem_tw; + wire trc_enb; + reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 35: 0] trc_im_data; + reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire trc_on_chip; + reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire tw_valid; + wire xbrk_wrap_traceoff; + assign trc_im_data = tw; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + trc_im_addr <= 0; + trc_wrap <= 0; + end + else if (!0) + begin + trc_im_addr <= 0; + trc_wrap <= 0; + end + else if (take_action_tracectrl && + (jdo[4] | jdo[3])) + begin + if (jdo[4]) + trc_im_addr <= 0; + if (jdo[3]) + trc_wrap <= 0; + end + else if (trc_enb & trc_on_chip & tw_valid) + begin + trc_im_addr <= trc_im_addr+1; + if (&trc_im_addr) + trc_wrap <= 1; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + trc_jtag_addr <= 0; + else if (take_action_tracemem_a || + take_no_action_tracemem_a || + take_action_tracemem_b) + trc_jtag_addr <= take_action_tracemem_a ? + jdo[35 : 19] : + trc_jtag_addr + 1; + + end + + + assign trc_enb = trc_ctrl[0]; + assign trc_on_chip = ~trc_ctrl[8]; + assign tw_valid = |trc_im_data[35 : 32]; + assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap; + assign tracemem_tw = trc_wrap; + assign tracemem_on = trc_enb; + assign tracemem_trcdata = 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_performance_monitors +; + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci ( + // inputs: + D_valid, + E_st_data, + E_valid, + F_pc, + address_nxt, + av_ld_data_aligned_filtered, + byteenable_nxt, + clk, + d_address, + d_read, + d_waitrequest, + d_write, + debugaccess_nxt, + hbreak_enabled, + read_nxt, + reset, + reset_n, + test_ending, + test_has_ended, + write_nxt, + writedata_nxt, + + // outputs: + jtag_debug_module_debugaccess_to_roms, + oci_hbreak_req, + oci_ienable, + oci_single_step_mode, + readdata, + resetrequest, + waitrequest + ) +; + + output jtag_debug_module_debugaccess_to_roms; + output oci_hbreak_req; + output [ 31: 0] oci_ienable; + output oci_single_step_mode; + output [ 31: 0] readdata; + output resetrequest; + output waitrequest; + input D_valid; + input [ 31: 0] E_st_data; + input E_valid; + input [ 16: 0] F_pc; + input [ 8: 0] address_nxt; + input [ 31: 0] av_ld_data_aligned_filtered; + input [ 3: 0] byteenable_nxt; + input clk; + input [ 18: 0] d_address; + input d_read; + input d_waitrequest; + input d_write; + input debugaccess_nxt; + input hbreak_enabled; + input read_nxt; + input reset; + input reset_n; + input test_ending; + input test_has_ended; + input write_nxt; + input [ 31: 0] writedata_nxt; + + wire [ 31: 0] MonDReg; + reg [ 8: 0] address; + wire [ 35: 0] atm; + wire [ 31: 0] break_readreg; + reg [ 3: 0] byteenable; + wire clkx2; + wire [ 18: 0] cpu_d_address; + wire cpu_d_read; + wire [ 31: 0] cpu_d_readdata; + wire cpu_d_wait; + wire cpu_d_write; + wire [ 31: 0] cpu_d_writedata; + wire dbrk_break; + wire dbrk_goto0; + wire dbrk_goto1; + wire dbrk_hit0_latch; + wire dbrk_hit1_latch; + wire dbrk_hit2_latch; + wire dbrk_hit3_latch; + wire dbrk_traceme; + wire dbrk_traceoff; + wire dbrk_traceon; + wire dbrk_trigout; + wire [ 29: 0] dct_buffer; + wire [ 3: 0] dct_count; + reg debugaccess; + wire debugack; + wire debugreq; + wire [ 35: 0] dtm; + wire dummy_sink; + wire [ 35: 0] itm; + wire [ 37: 0] jdo; + wire jrst_n; + wire jtag_debug_module_debugaccess_to_roms; + wire monitor_error; + wire monitor_go; + wire monitor_ready; + wire oci_hbreak_req; + wire [ 31: 0] oci_ienable; + wire [ 31: 0] oci_reg_readdata; + wire oci_single_step_mode; + wire [ 31: 0] ociram_readdata; + wire ocireg_ers; + wire ocireg_mrs; + reg read; + reg [ 31: 0] readdata; + wire resetlatch; + wire resetrequest; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_ocireg; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire tr_clk; + wire [ 17: 0] tr_data; + wire tracemem_on; + wire [ 35: 0] tracemem_trcdata; + wire tracemem_tw; + wire [ 15: 0] trc_ctrl; + wire trc_enb; + wire [ 6: 0] trc_im_addr; + wire trc_on; + wire trc_wrap; + wire trigbrktype; + wire trigger_state_0; + wire trigger_state_1; + wire trigout; + wire [ 35: 0] tw; + wire waitrequest; + reg write; + reg [ 31: 0] writedata; + wire xbrk_break; + wire [ 7: 0] xbrk_ctrl0; + wire [ 7: 0] xbrk_ctrl1; + wire [ 7: 0] xbrk_ctrl2; + wire [ 7: 0] xbrk_ctrl3; + wire xbrk_goto0; + wire xbrk_goto1; + wire xbrk_traceoff; + wire xbrk_traceon; + wire xbrk_trigout; + wire xbrk_wrap_traceoff; + nios_system_nios2_processor_nios2_oci_debug the_nios_system_nios2_processor_nios2_oci_debug + ( + .clk (clk), + .dbrk_break (dbrk_break), + .debugack (debugack), + .debugreq (debugreq), + .hbreak_enabled (hbreak_enabled), + .jdo (jdo), + .jrst_n (jrst_n), + .monitor_error (monitor_error), + .monitor_go (monitor_go), + .monitor_ready (monitor_ready), + .oci_hbreak_req (oci_hbreak_req), + .ocireg_ers (ocireg_ers), + .ocireg_mrs (ocireg_mrs), + .reset (reset), + .resetlatch (resetlatch), + .resetrequest (resetrequest), + .st_ready_test_idle (st_ready_test_idle), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocireg (take_action_ocireg), + .xbrk_break (xbrk_break) + ); + + nios_system_nios2_processor_nios2_ocimem the_nios_system_nios2_processor_nios2_ocimem + ( + .MonDReg (MonDReg), + .address (address), + .byteenable (byteenable), + .clk (clk), + .debugaccess (debugaccess), + .jdo (jdo), + .jrst_n (jrst_n), + .ociram_readdata (ociram_readdata), + .read (read), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .waitrequest (waitrequest), + .write (write), + .writedata (writedata) + ); + + nios_system_nios2_processor_nios2_avalon_reg the_nios_system_nios2_processor_nios2_avalon_reg + ( + .address (address), + .clk (clk), + .debugaccess (debugaccess), + .monitor_error (monitor_error), + .monitor_go (monitor_go), + .monitor_ready (monitor_ready), + .oci_ienable (oci_ienable), + .oci_reg_readdata (oci_reg_readdata), + .oci_single_step_mode (oci_single_step_mode), + .ocireg_ers (ocireg_ers), + .ocireg_mrs (ocireg_mrs), + .reset_n (reset_n), + .take_action_ocireg (take_action_ocireg), + .write (write), + .writedata (writedata) + ); + + nios_system_nios2_processor_nios2_oci_break the_nios_system_nios2_processor_nios2_oci_break + ( + .break_readreg (break_readreg), + .clk (clk), + .dbrk_break (dbrk_break), + .dbrk_goto0 (dbrk_goto0), + .dbrk_goto1 (dbrk_goto1), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .jdo (jdo), + .jrst_n (jrst_n), + .reset_n (reset_n), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .trigbrktype (trigbrktype), + .trigger_state_0 (trigger_state_0), + .trigger_state_1 (trigger_state_1), + .xbrk_ctrl0 (xbrk_ctrl0), + .xbrk_ctrl1 (xbrk_ctrl1), + .xbrk_ctrl2 (xbrk_ctrl2), + .xbrk_ctrl3 (xbrk_ctrl3), + .xbrk_goto0 (xbrk_goto0), + .xbrk_goto1 (xbrk_goto1) + ); + + nios_system_nios2_processor_nios2_oci_xbrk the_nios_system_nios2_processor_nios2_oci_xbrk + ( + .D_valid (D_valid), + .E_valid (E_valid), + .F_pc (F_pc), + .clk (clk), + .reset_n (reset_n), + .trigger_state_0 (trigger_state_0), + .trigger_state_1 (trigger_state_1), + .xbrk_break (xbrk_break), + .xbrk_ctrl0 (xbrk_ctrl0), + .xbrk_ctrl1 (xbrk_ctrl1), + .xbrk_ctrl2 (xbrk_ctrl2), + .xbrk_ctrl3 (xbrk_ctrl3), + .xbrk_goto0 (xbrk_goto0), + .xbrk_goto1 (xbrk_goto1), + .xbrk_traceoff (xbrk_traceoff), + .xbrk_traceon (xbrk_traceon), + .xbrk_trigout (xbrk_trigout) + ); + + nios_system_nios2_processor_nios2_oci_dbrk the_nios_system_nios2_processor_nios2_oci_dbrk + ( + .E_st_data (E_st_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .clk (clk), + .cpu_d_address (cpu_d_address), + .cpu_d_read (cpu_d_read), + .cpu_d_readdata (cpu_d_readdata), + .cpu_d_wait (cpu_d_wait), + .cpu_d_write (cpu_d_write), + .cpu_d_writedata (cpu_d_writedata), + .d_address (d_address), + .d_read (d_read), + .d_waitrequest (d_waitrequest), + .d_write (d_write), + .dbrk_break (dbrk_break), + .dbrk_goto0 (dbrk_goto0), + .dbrk_goto1 (dbrk_goto1), + .dbrk_traceme (dbrk_traceme), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dbrk_trigout (dbrk_trigout), + .debugack (debugack), + .reset_n (reset_n) + ); + + nios_system_nios2_processor_nios2_oci_itrace the_nios_system_nios2_processor_nios2_oci_itrace + ( + .clk (clk), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .itm (itm), + .jdo (jdo), + .jrst_n (jrst_n), + .take_action_tracectrl (take_action_tracectrl), + .trc_ctrl (trc_ctrl), + .trc_enb (trc_enb), + .trc_on (trc_on), + .xbrk_traceoff (xbrk_traceoff), + .xbrk_traceon (xbrk_traceon), + .xbrk_wrap_traceoff (xbrk_wrap_traceoff) + ); + + nios_system_nios2_processor_nios2_oci_dtrace the_nios_system_nios2_processor_nios2_oci_dtrace + ( + .atm (atm), + .clk (clk), + .cpu_d_address (cpu_d_address), + .cpu_d_read (cpu_d_read), + .cpu_d_readdata (cpu_d_readdata), + .cpu_d_wait (cpu_d_wait), + .cpu_d_write (cpu_d_write), + .cpu_d_writedata (cpu_d_writedata), + .dtm (dtm), + .jrst_n (jrst_n), + .trc_ctrl (trc_ctrl) + ); + + nios_system_nios2_processor_nios2_oci_fifo the_nios_system_nios2_processor_nios2_oci_fifo + ( + .atm (atm), + .clk (clk), + .dbrk_traceme (dbrk_traceme), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .dtm (dtm), + .itm (itm), + .jrst_n (jrst_n), + .reset_n (reset_n), + .test_ending (test_ending), + .test_has_ended (test_has_ended), + .trc_on (trc_on), + .tw (tw) + ); + + nios_system_nios2_processor_nios2_oci_pib the_nios_system_nios2_processor_nios2_oci_pib + ( + .clk (clk), + .clkx2 (clkx2), + .jrst_n (jrst_n), + .tr_clk (tr_clk), + .tr_data (tr_data), + .tw (tw) + ); + + nios_system_nios2_processor_nios2_oci_im the_nios_system_nios2_processor_nios2_oci_im + ( + .clk (clk), + .jdo (jdo), + .jrst_n (jrst_n), + .reset_n (reset_n), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_ctrl (trc_ctrl), + .trc_enb (trc_enb), + .trc_im_addr (trc_im_addr), + .trc_wrap (trc_wrap), + .tw (tw), + .xbrk_wrap_traceoff (xbrk_wrap_traceoff) + ); + + assign trigout = dbrk_trigout | xbrk_trigout; + assign jtag_debug_module_debugaccess_to_roms = debugack; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + address <= 0; + else + address <= address_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + byteenable <= 0; + else + byteenable <= byteenable_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + writedata <= 0; + else + writedata <= writedata_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + debugaccess <= 0; + else + debugaccess <= debugaccess_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + read <= 0; + else + read <= read ? waitrequest : read_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + write <= 0; + else + write <= write ? waitrequest : write_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + readdata <= 0; + else + readdata <= address[8] ? oci_reg_readdata : ociram_readdata; + end + + + nios_system_nios2_processor_jtag_debug_module_wrapper the_nios_system_nios2_processor_jtag_debug_module_wrapper + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .clk (clk), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .jdo (jdo), + .jrst_n (jrst_n), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .st_ready_test_idle (st_ready_test_idle), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1) + ); + + //dummy sink, which is an e_mux + assign dummy_sink = tr_clk | + tr_data | + trigout | + debugack; + + assign debugreq = 0; + assign clkx2 = 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor ( + // inputs: + clk, + d_irq, + d_readdata, + d_waitrequest, + i_readdata, + i_waitrequest, + jtag_debug_module_address, + jtag_debug_module_byteenable, + jtag_debug_module_debugaccess, + jtag_debug_module_read, + jtag_debug_module_write, + jtag_debug_module_writedata, + reset_n, + + // outputs: + d_address, + d_byteenable, + d_read, + d_write, + d_writedata, + i_address, + i_read, + jtag_debug_module_debugaccess_to_roms, + jtag_debug_module_readdata, + jtag_debug_module_resetrequest, + jtag_debug_module_waitrequest, + no_ci_readra + ) +; + + output [ 18: 0] d_address; + output [ 3: 0] d_byteenable; + output d_read; + output d_write; + output [ 31: 0] d_writedata; + output [ 18: 0] i_address; + output i_read; + output jtag_debug_module_debugaccess_to_roms; + output [ 31: 0] jtag_debug_module_readdata; + output jtag_debug_module_resetrequest; + output jtag_debug_module_waitrequest; + output no_ci_readra; + input clk; + input [ 31: 0] d_irq; + input [ 31: 0] d_readdata; + input d_waitrequest; + input [ 31: 0] i_readdata; + input i_waitrequest; + input [ 8: 0] jtag_debug_module_address; + input [ 3: 0] jtag_debug_module_byteenable; + input jtag_debug_module_debugaccess; + input jtag_debug_module_read; + input jtag_debug_module_write; + input [ 31: 0] jtag_debug_module_writedata; + input reset_n; + + wire [ 1: 0] D_compare_op; + wire D_ctrl_alu_force_xor; + wire D_ctrl_alu_signed_comparison; + wire D_ctrl_alu_subtract; + wire D_ctrl_b_is_dst; + wire D_ctrl_br; + wire D_ctrl_br_cmp; + wire D_ctrl_br_uncond; + wire D_ctrl_break; + wire D_ctrl_crst; + wire D_ctrl_custom; + wire D_ctrl_custom_multi; + wire D_ctrl_exception; + wire D_ctrl_force_src2_zero; + wire D_ctrl_hi_imm16; + wire D_ctrl_ignore_dst; + wire D_ctrl_implicit_dst_eretaddr; + wire D_ctrl_implicit_dst_retaddr; + wire D_ctrl_jmp_direct; + wire D_ctrl_jmp_indirect; + wire D_ctrl_ld; + wire D_ctrl_ld_io; + wire D_ctrl_ld_non_io; + wire D_ctrl_ld_signed; + wire D_ctrl_logic; + wire D_ctrl_rdctl_inst; + wire D_ctrl_retaddr; + wire D_ctrl_rot_right; + wire D_ctrl_shift_logical; + wire D_ctrl_shift_right_arith; + wire D_ctrl_shift_rot; + wire D_ctrl_shift_rot_right; + wire D_ctrl_src2_choose_imm; + wire D_ctrl_st; + wire D_ctrl_uncond_cti_non_br; + wire D_ctrl_unsigned_lo_imm16; + wire D_ctrl_wrctl_inst; + wire [ 4: 0] D_dst_regnum; + wire [ 55: 0] D_inst; + reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 4: 0] D_iw_a; + wire [ 4: 0] D_iw_b; + wire [ 4: 0] D_iw_c; + wire [ 2: 0] D_iw_control_regnum; + wire [ 7: 0] D_iw_custom_n; + wire D_iw_custom_readra; + wire D_iw_custom_readrb; + wire D_iw_custom_writerc; + wire [ 15: 0] D_iw_imm16; + wire [ 25: 0] D_iw_imm26; + wire [ 4: 0] D_iw_imm5; + wire [ 1: 0] D_iw_memsz; + wire [ 5: 0] D_iw_op; + wire [ 5: 0] D_iw_opx; + wire [ 4: 0] D_iw_shift_imm5; + wire [ 4: 0] D_iw_trap_break_imm5; + wire [ 16: 0] D_jmp_direct_target_waddr; + wire [ 1: 0] D_logic_op; + wire [ 1: 0] D_logic_op_raw; + wire D_mem16; + wire D_mem32; + wire D_mem8; + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + reg D_valid; + wire [ 55: 0] D_vinst; + wire D_wr_dst_reg; + wire [ 31: 0] E_alu_result; + reg E_alu_sub; + wire [ 32: 0] E_arith_result; + wire [ 31: 0] E_arith_src1; + wire [ 31: 0] E_arith_src2; + wire E_ci_multi_stall; + wire [ 31: 0] E_ci_result; + wire E_cmp_result; + wire [ 31: 0] E_control_rd_data; + wire E_eq; + reg E_invert_arith_src_msb; + wire E_ld_stall; + wire [ 31: 0] E_logic_result; + wire E_logic_result_is_0; + wire E_lt; + wire [ 18: 0] E_mem_baddr; + wire [ 3: 0] E_mem_byte_en; + reg E_new_inst; + reg [ 4: 0] E_shift_rot_cnt; + wire [ 4: 0] E_shift_rot_cnt_nxt; + wire E_shift_rot_done; + wire E_shift_rot_fill_bit; + reg [ 31: 0] E_shift_rot_result; + wire [ 31: 0] E_shift_rot_result_nxt; + wire E_shift_rot_stall; + reg [ 31: 0] E_src1; + reg [ 31: 0] E_src2; + wire [ 31: 0] E_st_data; + wire E_st_stall; + wire E_stall; + reg E_valid; + wire [ 55: 0] E_vinst; + wire E_wrctl_bstatus; + wire E_wrctl_estatus; + wire E_wrctl_ienable; + wire E_wrctl_status; + wire [ 31: 0] F_av_iw; + wire [ 4: 0] F_av_iw_a; + wire [ 4: 0] F_av_iw_b; + wire [ 4: 0] F_av_iw_c; + wire [ 2: 0] F_av_iw_control_regnum; + wire [ 7: 0] F_av_iw_custom_n; + wire F_av_iw_custom_readra; + wire F_av_iw_custom_readrb; + wire F_av_iw_custom_writerc; + wire [ 15: 0] F_av_iw_imm16; + wire [ 25: 0] F_av_iw_imm26; + wire [ 4: 0] F_av_iw_imm5; + wire [ 1: 0] F_av_iw_memsz; + wire [ 5: 0] F_av_iw_op; + wire [ 5: 0] F_av_iw_opx; + wire [ 4: 0] F_av_iw_shift_imm5; + wire [ 4: 0] F_av_iw_trap_break_imm5; + wire F_av_mem16; + wire F_av_mem32; + wire F_av_mem8; + wire [ 55: 0] F_inst; + wire [ 31: 0] F_iw; + wire [ 4: 0] F_iw_a; + wire [ 4: 0] F_iw_b; + wire [ 4: 0] F_iw_c; + wire [ 2: 0] F_iw_control_regnum; + wire [ 7: 0] F_iw_custom_n; + wire F_iw_custom_readra; + wire F_iw_custom_readrb; + wire F_iw_custom_writerc; + wire [ 15: 0] F_iw_imm16; + wire [ 25: 0] F_iw_imm26; + wire [ 4: 0] F_iw_imm5; + wire [ 1: 0] F_iw_memsz; + wire [ 5: 0] F_iw_op; + wire [ 5: 0] F_iw_opx; + wire [ 4: 0] F_iw_shift_imm5; + wire [ 4: 0] F_iw_trap_break_imm5; + wire F_mem16; + wire F_mem32; + wire F_mem8; + wire F_op_add; + wire F_op_addi; + wire F_op_and; + wire F_op_andhi; + wire F_op_andi; + wire F_op_beq; + wire F_op_bge; + wire F_op_bgeu; + wire F_op_blt; + wire F_op_bltu; + wire F_op_bne; + wire F_op_br; + wire F_op_break; + wire F_op_bret; + wire F_op_call; + wire F_op_callr; + wire F_op_cmpeq; + wire F_op_cmpeqi; + wire F_op_cmpge; + wire F_op_cmpgei; + wire F_op_cmpgeu; + wire F_op_cmpgeui; + wire F_op_cmplt; + wire F_op_cmplti; + wire F_op_cmpltu; + wire F_op_cmpltui; + wire F_op_cmpne; + wire F_op_cmpnei; + wire F_op_crst; + wire F_op_custom; + wire F_op_div; + wire F_op_divu; + wire F_op_eret; + wire F_op_flushd; + wire F_op_flushda; + wire F_op_flushi; + wire F_op_flushp; + wire F_op_hbreak; + wire F_op_initd; + wire F_op_initda; + wire F_op_initi; + wire F_op_intr; + wire F_op_jmp; + wire F_op_jmpi; + wire F_op_ldb; + wire F_op_ldbio; + wire F_op_ldbu; + wire F_op_ldbuio; + wire F_op_ldh; + wire F_op_ldhio; + wire F_op_ldhu; + wire F_op_ldhuio; + wire F_op_ldl; + wire F_op_ldw; + wire F_op_ldwio; + wire F_op_mul; + wire F_op_muli; + wire F_op_mulxss; + wire F_op_mulxsu; + wire F_op_mulxuu; + wire F_op_nextpc; + wire F_op_nor; + wire F_op_opx; + wire F_op_or; + wire F_op_orhi; + wire F_op_ori; + wire F_op_rdctl; + wire F_op_rdprs; + wire F_op_ret; + wire F_op_rol; + wire F_op_roli; + wire F_op_ror; + wire F_op_rsv02; + wire F_op_rsv09; + wire F_op_rsv10; + wire F_op_rsv17; + wire F_op_rsv18; + wire F_op_rsv25; + wire F_op_rsv26; + wire F_op_rsv33; + wire F_op_rsv34; + wire F_op_rsv41; + wire F_op_rsv42; + wire F_op_rsv49; + wire F_op_rsv57; + wire F_op_rsv61; + wire F_op_rsv62; + wire F_op_rsv63; + wire F_op_rsvx00; + wire F_op_rsvx10; + wire F_op_rsvx15; + wire F_op_rsvx17; + wire F_op_rsvx21; + wire F_op_rsvx25; + wire F_op_rsvx33; + wire F_op_rsvx34; + wire F_op_rsvx35; + wire F_op_rsvx42; + wire F_op_rsvx43; + wire F_op_rsvx44; + wire F_op_rsvx47; + wire F_op_rsvx50; + wire F_op_rsvx51; + wire F_op_rsvx55; + wire F_op_rsvx56; + wire F_op_rsvx60; + wire F_op_rsvx63; + wire F_op_sll; + wire F_op_slli; + wire F_op_sra; + wire F_op_srai; + wire F_op_srl; + wire F_op_srli; + wire F_op_stb; + wire F_op_stbio; + wire F_op_stc; + wire F_op_sth; + wire F_op_sthio; + wire F_op_stw; + wire F_op_stwio; + wire F_op_sub; + wire F_op_sync; + wire F_op_trap; + wire F_op_wrctl; + wire F_op_wrprs; + wire F_op_xor; + wire F_op_xorhi; + wire F_op_xori; + reg [ 16: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire F_pc_en; + wire [ 16: 0] F_pc_no_crst_nxt; + wire [ 16: 0] F_pc_nxt; + wire [ 16: 0] F_pc_plus_one; + wire [ 1: 0] F_pc_sel_nxt; + wire [ 18: 0] F_pcb; + wire [ 18: 0] F_pcb_nxt; + wire [ 18: 0] F_pcb_plus_four; + wire F_valid; + wire [ 55: 0] F_vinst; + reg [ 1: 0] R_compare_op; + reg R_ctrl_alu_force_xor; + wire R_ctrl_alu_force_xor_nxt; + reg R_ctrl_alu_signed_comparison; + wire R_ctrl_alu_signed_comparison_nxt; + reg R_ctrl_alu_subtract; + wire R_ctrl_alu_subtract_nxt; + reg R_ctrl_b_is_dst; + wire R_ctrl_b_is_dst_nxt; + reg R_ctrl_br; + reg R_ctrl_br_cmp; + wire R_ctrl_br_cmp_nxt; + wire R_ctrl_br_nxt; + reg R_ctrl_br_uncond; + wire R_ctrl_br_uncond_nxt; + reg R_ctrl_break; + wire R_ctrl_break_nxt; + reg R_ctrl_crst; + wire R_ctrl_crst_nxt; + reg R_ctrl_custom; + reg R_ctrl_custom_multi; + wire R_ctrl_custom_multi_nxt; + wire R_ctrl_custom_nxt; + reg R_ctrl_exception; + wire R_ctrl_exception_nxt; + reg R_ctrl_force_src2_zero; + wire R_ctrl_force_src2_zero_nxt; + reg R_ctrl_hi_imm16; + wire R_ctrl_hi_imm16_nxt; + reg R_ctrl_ignore_dst; + wire R_ctrl_ignore_dst_nxt; + reg R_ctrl_implicit_dst_eretaddr; + wire R_ctrl_implicit_dst_eretaddr_nxt; + reg R_ctrl_implicit_dst_retaddr; + wire R_ctrl_implicit_dst_retaddr_nxt; + reg R_ctrl_jmp_direct; + wire R_ctrl_jmp_direct_nxt; + reg R_ctrl_jmp_indirect; + wire R_ctrl_jmp_indirect_nxt; + reg R_ctrl_ld; + reg R_ctrl_ld_io; + wire R_ctrl_ld_io_nxt; + reg R_ctrl_ld_non_io; + wire R_ctrl_ld_non_io_nxt; + wire R_ctrl_ld_nxt; + reg R_ctrl_ld_signed; + wire R_ctrl_ld_signed_nxt; + reg R_ctrl_logic; + wire R_ctrl_logic_nxt; + reg R_ctrl_rdctl_inst; + wire R_ctrl_rdctl_inst_nxt; + reg R_ctrl_retaddr; + wire R_ctrl_retaddr_nxt; + reg R_ctrl_rot_right; + wire R_ctrl_rot_right_nxt; + reg R_ctrl_shift_logical; + wire R_ctrl_shift_logical_nxt; + reg R_ctrl_shift_right_arith; + wire R_ctrl_shift_right_arith_nxt; + reg R_ctrl_shift_rot; + wire R_ctrl_shift_rot_nxt; + reg R_ctrl_shift_rot_right; + wire R_ctrl_shift_rot_right_nxt; + reg R_ctrl_src2_choose_imm; + wire R_ctrl_src2_choose_imm_nxt; + reg R_ctrl_st; + wire R_ctrl_st_nxt; + reg R_ctrl_uncond_cti_non_br; + wire R_ctrl_uncond_cti_non_br_nxt; + reg R_ctrl_unsigned_lo_imm16; + wire R_ctrl_unsigned_lo_imm16_nxt; + reg R_ctrl_wrctl_inst; + wire R_ctrl_wrctl_inst_nxt; + reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire R_en; + reg [ 1: 0] R_logic_op; + wire [ 31: 0] R_rf_a; + wire [ 31: 0] R_rf_b; + wire [ 31: 0] R_src1; + wire [ 31: 0] R_src2; + wire [ 15: 0] R_src2_hi; + wire [ 15: 0] R_src2_lo; + reg R_src2_use_imm; + wire [ 7: 0] R_stb_data; + wire [ 15: 0] R_sth_data; + reg R_valid; + wire [ 55: 0] R_vinst; + reg R_wr_dst_reg; + reg [ 31: 0] W_alu_result; + wire W_br_taken; + reg W_bstatus_reg; + wire W_bstatus_reg_inst_nxt; + wire W_bstatus_reg_nxt; + reg W_cmp_result; + reg [ 31: 0] W_control_rd_data; + reg W_estatus_reg; + wire W_estatus_reg_inst_nxt; + wire W_estatus_reg_nxt; + reg [ 31: 0] W_ienable_reg; + wire [ 31: 0] W_ienable_reg_nxt; + reg [ 31: 0] W_ipending_reg; + wire [ 31: 0] W_ipending_reg_nxt; + wire [ 18: 0] W_mem_baddr; + wire [ 31: 0] W_rf_wr_data; + wire W_rf_wren; + wire W_status_reg; + reg W_status_reg_pie; + wire W_status_reg_pie_inst_nxt; + wire W_status_reg_pie_nxt; + reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 55: 0] W_vinst; + wire [ 31: 0] W_wr_data; + wire [ 31: 0] W_wr_data_non_zero; + wire av_fill_bit; + reg [ 1: 0] av_ld_align_cycle; + wire [ 1: 0] av_ld_align_cycle_nxt; + wire av_ld_align_one_more_cycle; + reg av_ld_aligning_data; + wire av_ld_aligning_data_nxt; + reg [ 7: 0] av_ld_byte0_data; + wire [ 7: 0] av_ld_byte0_data_nxt; + reg [ 7: 0] av_ld_byte1_data; + wire av_ld_byte1_data_en; + wire [ 7: 0] av_ld_byte1_data_nxt; + reg [ 7: 0] av_ld_byte2_data; + wire [ 7: 0] av_ld_byte2_data_nxt; + reg [ 7: 0] av_ld_byte3_data; + wire [ 7: 0] av_ld_byte3_data_nxt; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire [ 31: 0] av_ld_data_aligned_unfiltered; + wire av_ld_done; + wire av_ld_extend; + wire av_ld_getting_data; + wire av_ld_rshift8; + reg av_ld_waiting_for_data; + wire av_ld_waiting_for_data_nxt; + wire av_sign_bit; + wire [ 18: 0] d_address; + reg [ 3: 0] d_byteenable; + reg d_read; + wire d_read_nxt; + wire d_write; + wire d_write_nxt; + reg [ 31: 0] d_writedata; + reg hbreak_enabled; + reg hbreak_pending; + wire hbreak_pending_nxt; + wire hbreak_req; + wire [ 18: 0] i_address; + reg i_read; + wire i_read_nxt; + wire [ 31: 0] iactive; + wire intr_req; + wire jtag_debug_module_clk; + wire jtag_debug_module_debugaccess_to_roms; + wire [ 31: 0] jtag_debug_module_readdata; + wire jtag_debug_module_reset; + wire jtag_debug_module_resetrequest; + wire jtag_debug_module_waitrequest; + wire no_ci_readra; + wire oci_hbreak_req; + wire [ 31: 0] oci_ienable; + wire oci_single_step_mode; + wire oci_tb_hbreak_req; + wire test_ending; + wire test_has_ended; + reg wait_for_one_post_bret_inst; + //the_nios_system_nios2_processor_test_bench, which is an e_instance + nios_system_nios2_processor_test_bench the_nios_system_nios2_processor_test_bench + ( + .D_iw (D_iw), + .D_iw_op (D_iw_op), + .D_iw_opx (D_iw_opx), + .D_valid (D_valid), + .E_valid (E_valid), + .F_pcb (F_pcb), + .F_valid (F_valid), + .R_ctrl_ld (R_ctrl_ld), + .R_ctrl_ld_non_io (R_ctrl_ld_non_io), + .R_dst_regnum (R_dst_regnum), + .R_wr_dst_reg (R_wr_dst_reg), + .W_valid (W_valid), + .W_vinst (W_vinst), + .W_wr_data (W_wr_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), + .clk (clk), + .d_address (d_address), + .d_byteenable (d_byteenable), + .d_read (d_read), + .d_write (d_write), + .d_write_nxt (d_write_nxt), + .i_address (i_address), + .i_read (i_read), + .i_readdata (i_readdata), + .i_waitrequest (i_waitrequest), + .reset_n (reset_n), + .test_has_ended (test_has_ended) + ); + + assign F_av_iw_a = F_av_iw[31 : 27]; + assign F_av_iw_b = F_av_iw[26 : 22]; + assign F_av_iw_c = F_av_iw[21 : 17]; + assign F_av_iw_custom_n = F_av_iw[13 : 6]; + assign F_av_iw_custom_readra = F_av_iw[16]; + assign F_av_iw_custom_readrb = F_av_iw[15]; + assign F_av_iw_custom_writerc = F_av_iw[14]; + assign F_av_iw_opx = F_av_iw[16 : 11]; + assign F_av_iw_op = F_av_iw[5 : 0]; + assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm16 = F_av_iw[21 : 6]; + assign F_av_iw_imm26 = F_av_iw[31 : 6]; + assign F_av_iw_memsz = F_av_iw[4 : 3]; + assign F_av_iw_control_regnum = F_av_iw[8 : 6]; + assign F_av_mem8 = F_av_iw_memsz == 2'b00; + assign F_av_mem16 = F_av_iw_memsz == 2'b01; + assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; + assign F_iw_a = F_iw[31 : 27]; + assign F_iw_b = F_iw[26 : 22]; + assign F_iw_c = F_iw[21 : 17]; + assign F_iw_custom_n = F_iw[13 : 6]; + assign F_iw_custom_readra = F_iw[16]; + assign F_iw_custom_readrb = F_iw[15]; + assign F_iw_custom_writerc = F_iw[14]; + assign F_iw_opx = F_iw[16 : 11]; + assign F_iw_op = F_iw[5 : 0]; + assign F_iw_shift_imm5 = F_iw[10 : 6]; + assign F_iw_trap_break_imm5 = F_iw[10 : 6]; + assign F_iw_imm5 = F_iw[10 : 6]; + assign F_iw_imm16 = F_iw[21 : 6]; + assign F_iw_imm26 = F_iw[31 : 6]; + assign F_iw_memsz = F_iw[4 : 3]; + assign F_iw_control_regnum = F_iw[8 : 6]; + assign F_mem8 = F_iw_memsz == 2'b00; + assign F_mem16 = F_iw_memsz == 2'b01; + assign F_mem32 = F_iw_memsz[1] == 1'b1; + assign D_iw_a = D_iw[31 : 27]; + assign D_iw_b = D_iw[26 : 22]; + assign D_iw_c = D_iw[21 : 17]; + assign D_iw_custom_n = D_iw[13 : 6]; + assign D_iw_custom_readra = D_iw[16]; + assign D_iw_custom_readrb = D_iw[15]; + assign D_iw_custom_writerc = D_iw[14]; + assign D_iw_opx = D_iw[16 : 11]; + assign D_iw_op = D_iw[5 : 0]; + assign D_iw_shift_imm5 = D_iw[10 : 6]; + assign D_iw_trap_break_imm5 = D_iw[10 : 6]; + assign D_iw_imm5 = D_iw[10 : 6]; + assign D_iw_imm16 = D_iw[21 : 6]; + assign D_iw_imm26 = D_iw[31 : 6]; + assign D_iw_memsz = D_iw[4 : 3]; + assign D_iw_control_regnum = D_iw[8 : 6]; + assign D_mem8 = D_iw_memsz == 2'b00; + assign D_mem16 = D_iw_memsz == 2'b01; + assign D_mem32 = D_iw_memsz[1] == 1'b1; + assign F_op_call = F_iw_op == 0; + assign F_op_jmpi = F_iw_op == 1; + assign F_op_ldbu = F_iw_op == 3; + assign F_op_addi = F_iw_op == 4; + assign F_op_stb = F_iw_op == 5; + assign F_op_br = F_iw_op == 6; + assign F_op_ldb = F_iw_op == 7; + assign F_op_cmpgei = F_iw_op == 8; + assign F_op_ldhu = F_iw_op == 11; + assign F_op_andi = F_iw_op == 12; + assign F_op_sth = F_iw_op == 13; + assign F_op_bge = F_iw_op == 14; + assign F_op_ldh = F_iw_op == 15; + assign F_op_cmplti = F_iw_op == 16; + assign F_op_initda = F_iw_op == 19; + assign F_op_ori = F_iw_op == 20; + assign F_op_stw = F_iw_op == 21; + assign F_op_blt = F_iw_op == 22; + assign F_op_ldw = F_iw_op == 23; + assign F_op_cmpnei = F_iw_op == 24; + assign F_op_flushda = F_iw_op == 27; + assign F_op_xori = F_iw_op == 28; + assign F_op_stc = F_iw_op == 29; + assign F_op_bne = F_iw_op == 30; + assign F_op_ldl = F_iw_op == 31; + assign F_op_cmpeqi = F_iw_op == 32; + assign F_op_ldbuio = F_iw_op == 35; + assign F_op_muli = F_iw_op == 36; + assign F_op_stbio = F_iw_op == 37; + assign F_op_beq = F_iw_op == 38; + assign F_op_ldbio = F_iw_op == 39; + assign F_op_cmpgeui = F_iw_op == 40; + assign F_op_ldhuio = F_iw_op == 43; + assign F_op_andhi = F_iw_op == 44; + assign F_op_sthio = F_iw_op == 45; + assign F_op_bgeu = F_iw_op == 46; + assign F_op_ldhio = F_iw_op == 47; + assign F_op_cmpltui = F_iw_op == 48; + assign F_op_initd = F_iw_op == 51; + assign F_op_orhi = F_iw_op == 52; + assign F_op_stwio = F_iw_op == 53; + assign F_op_bltu = F_iw_op == 54; + assign F_op_ldwio = F_iw_op == 55; + assign F_op_rdprs = F_iw_op == 56; + assign F_op_flushd = F_iw_op == 59; + assign F_op_xorhi = F_iw_op == 60; + assign F_op_rsv02 = F_iw_op == 2; + assign F_op_rsv09 = F_iw_op == 9; + assign F_op_rsv10 = F_iw_op == 10; + assign F_op_rsv17 = F_iw_op == 17; + assign F_op_rsv18 = F_iw_op == 18; + assign F_op_rsv25 = F_iw_op == 25; + assign F_op_rsv26 = F_iw_op == 26; + assign F_op_rsv33 = F_iw_op == 33; + assign F_op_rsv34 = F_iw_op == 34; + assign F_op_rsv41 = F_iw_op == 41; + assign F_op_rsv42 = F_iw_op == 42; + assign F_op_rsv49 = F_iw_op == 49; + assign F_op_rsv57 = F_iw_op == 57; + assign F_op_rsv61 = F_iw_op == 61; + assign F_op_rsv62 = F_iw_op == 62; + assign F_op_rsv63 = F_iw_op == 63; + assign F_op_eret = F_op_opx & (F_iw_opx == 1); + assign F_op_roli = F_op_opx & (F_iw_opx == 2); + assign F_op_rol = F_op_opx & (F_iw_opx == 3); + assign F_op_flushp = F_op_opx & (F_iw_opx == 4); + assign F_op_ret = F_op_opx & (F_iw_opx == 5); + assign F_op_nor = F_op_opx & (F_iw_opx == 6); + assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); + assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); + assign F_op_bret = F_op_opx & (F_iw_opx == 9); + assign F_op_ror = F_op_opx & (F_iw_opx == 11); + assign F_op_flushi = F_op_opx & (F_iw_opx == 12); + assign F_op_jmp = F_op_opx & (F_iw_opx == 13); + assign F_op_and = F_op_opx & (F_iw_opx == 14); + assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); + assign F_op_slli = F_op_opx & (F_iw_opx == 18); + assign F_op_sll = F_op_opx & (F_iw_opx == 19); + assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); + assign F_op_or = F_op_opx & (F_iw_opx == 22); + assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); + assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); + assign F_op_srli = F_op_opx & (F_iw_opx == 26); + assign F_op_srl = F_op_opx & (F_iw_opx == 27); + assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); + assign F_op_callr = F_op_opx & (F_iw_opx == 29); + assign F_op_xor = F_op_opx & (F_iw_opx == 30); + assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); + assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); + assign F_op_divu = F_op_opx & (F_iw_opx == 36); + assign F_op_div = F_op_opx & (F_iw_opx == 37); + assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); + assign F_op_mul = F_op_opx & (F_iw_opx == 39); + assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); + assign F_op_initi = F_op_opx & (F_iw_opx == 41); + assign F_op_trap = F_op_opx & (F_iw_opx == 45); + assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); + assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); + assign F_op_add = F_op_opx & (F_iw_opx == 49); + assign F_op_break = F_op_opx & (F_iw_opx == 52); + assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); + assign F_op_sync = F_op_opx & (F_iw_opx == 54); + assign F_op_sub = F_op_opx & (F_iw_opx == 57); + assign F_op_srai = F_op_opx & (F_iw_opx == 58); + assign F_op_sra = F_op_opx & (F_iw_opx == 59); + assign F_op_intr = F_op_opx & (F_iw_opx == 61); + assign F_op_crst = F_op_opx & (F_iw_opx == 62); + assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); + assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); + assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); + assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); + assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); + assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); + assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); + assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); + assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); + assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); + assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); + assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); + assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); + assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); + assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); + assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); + assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); + assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); + assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); + assign F_op_opx = F_iw_op == 58; + assign F_op_custom = F_iw_op == 50; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + assign R_en = 1'b1; + assign E_ci_result = 0; + //custom_instruction_master, which is an e_custom_instruction_master + assign no_ci_readra = 1'b0; + assign E_ci_multi_stall = 1'b0; + assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000100000; + assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : + R_ctrl_break ? 2'b01 : + (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : + 2'b11; + + assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : + (F_pc_sel_nxt == 2'b01)? 66056 : + (F_pc_sel_nxt == 2'b10)? E_arith_result[18 : 2] : + F_pc_plus_one; + + assign F_pc_nxt = F_pc_no_crst_nxt; + assign F_pcb_nxt = {F_pc_nxt, 2'b00}; + assign F_pc_en = W_valid; + assign F_pc_plus_one = F_pc + 1; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + F_pc <= 0; + else if (F_pc_en) + F_pc <= F_pc_nxt; + end + + + assign F_pcb = {F_pc, 2'b00}; + assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; + assign F_valid = i_read & ~i_waitrequest; + assign i_read_nxt = W_valid | (i_read & i_waitrequest); + assign i_address = {F_pc, 2'b00}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + i_read <= 1'b1; + else + i_read <= i_read_nxt; + end + + + assign oci_tb_hbreak_req = oci_hbreak_req; + assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid); + assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled + : hbreak_req; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + wait_for_one_post_bret_inst <= 1'b0; + else + wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + hbreak_pending <= 1'b0; + else + hbreak_pending <= hbreak_pending_nxt; + end + + + assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); + assign F_av_iw = i_readdata; + assign F_iw = hbreak_req ? 4040762 : + 1'b0 ? 127034 : + intr_req ? 3926074 : + F_av_iw; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_iw <= 0; + else if (F_valid) + D_iw <= F_iw; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_valid <= 0; + else + D_valid <= F_valid; + end + + + assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : + D_ctrl_implicit_dst_eretaddr ? 5'd29 : + D_ctrl_b_is_dst ? D_iw_b : + D_iw_c; + + assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; + assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; + assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_jmp_direct_target_waddr = D_iw[31 : 6]; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_valid <= 0; + else + R_valid <= D_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_wr_dst_reg <= 0; + else + R_wr_dst_reg <= D_wr_dst_reg; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_dst_regnum <= 0; + else + R_dst_regnum <= D_dst_regnum; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_logic_op <= 0; + else + R_logic_op <= D_logic_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_compare_op <= 0; + else + R_compare_op <= D_compare_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_src2_use_imm <= 0; + else + R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); + end + + + assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; + assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; +//nios_system_nios2_processor_register_bank_a, which is an nios_sdp_ram +nios_system_nios2_processor_register_bank_a_module nios_system_nios2_processor_register_bank_a + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_a), + .rdaddress (D_iw_a), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.dat"; +`else +defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.mif"; +//synthesis read_comments_as_HDL off +//nios_system_nios2_processor_register_bank_b, which is an nios_sdp_ram +nios_system_nios2_processor_register_bank_b_module nios_system_nios2_processor_register_bank_b + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_b), + .rdaddress (D_iw_b), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.dat"; +`else +defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.mif"; +//synthesis read_comments_as_HDL off + assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : + ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : + R_rf_a; + + assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : + (R_src2_use_imm)? D_iw_imm16 : + R_rf_b[15 : 0]; + + assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : + (R_ctrl_hi_imm16)? D_iw_imm16 : + (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : + R_rf_b[31 : 16]; + + assign R_src2 = {R_src2_hi, R_src2_lo}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_valid <= 0; + else + E_valid <= R_valid | E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_new_inst <= 0; + else + E_new_inst <= R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src1 <= 0; + else + E_src1 <= R_src1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src2 <= 0; + else + E_src2 <= R_src2; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_invert_arith_src_msb <= 0; + else + E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_alu_sub <= 0; + else + E_alu_sub <= D_ctrl_alu_subtract & R_valid; + end + + + assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; + assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, + E_src1[30 : 0]}; + + assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, + E_src2[30 : 0]}; + + assign E_arith_result = E_alu_sub ? + E_arith_src1 - E_arith_src2 : + E_arith_src1 + E_arith_src2; + + assign E_mem_baddr = E_arith_result[18 : 0]; + assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : + (R_logic_op == 2'b01)? (E_src1 & E_src2) : + (R_logic_op == 2'b10)? (E_src1 | E_src2) : + (E_src1 ^ E_src2); + + assign E_logic_result_is_0 = E_logic_result == 0; + assign E_eq = E_logic_result_is_0; + assign E_lt = E_arith_result[32]; + assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : + (R_compare_op == 2'b01)? ~E_lt : + (R_compare_op == 2'b10)? E_lt : + ~E_eq; + + assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; + assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; + assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; + assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : + (R_ctrl_rot_right ? E_shift_rot_result[0] : + E_shift_rot_result[31]); + + assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : + (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : + {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_result <= 0; + else + E_shift_rot_result <= E_shift_rot_result_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_cnt <= 0; + else + E_shift_rot_cnt <= E_shift_rot_cnt_nxt; + end + + + assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : + (D_iw_control_regnum == 3'd1)? W_estatus_reg : + (D_iw_control_regnum == 3'd2)? W_bstatus_reg : + (D_iw_control_regnum == 3'd3)? W_ienable_reg : + (D_iw_control_regnum == 3'd4)? W_ipending_reg : + 0; + + assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : + (R_ctrl_shift_rot)? E_shift_rot_result : + (R_ctrl_logic)? E_logic_result : + (R_ctrl_custom)? E_ci_result : + E_arith_result; + + assign R_stb_data = R_rf_b[7 : 0]; + assign R_sth_data = R_rf_b[15 : 0]; + assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : + (D_mem16)? {R_sth_data, R_sth_data} : + R_rf_b; + + assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : + 4'b1111; + + assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); + assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); + assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); + assign E_st_stall = d_write_nxt; + assign d_address = W_mem_baddr; + assign av_ld_getting_data = d_read & ~d_waitrequest; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_read <= 0; + else + d_read <= d_read_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_writedata <= 0; + else + d_writedata <= E_st_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_byteenable <= 0; + else + d_byteenable <= E_mem_byte_en; + end + + + assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); + assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); + assign av_ld_aligning_data_nxt = av_ld_aligning_data ? + ~av_ld_align_one_more_cycle : + (~D_mem32 & av_ld_getting_data); + + assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? + ~av_ld_getting_data : + (R_ctrl_ld & E_new_inst); + + assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); + assign av_ld_rshift8 = av_ld_aligning_data & + (av_ld_align_cycle < (W_mem_baddr[1 : 0])); + + assign av_ld_extend = av_ld_aligning_data; + assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : + av_ld_extend ? av_ld_byte0_data : + d_readdata[7 : 0]; + + assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[15 : 8]; + + assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[23 : 16]; + + assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[31 : 24]; + + assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); + assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, + av_ld_byte1_data, av_ld_byte0_data}; + + assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; + assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_align_cycle <= 0; + else + av_ld_align_cycle <= av_ld_align_cycle_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_waiting_for_data <= 0; + else + av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_aligning_data <= 0; + else + av_ld_aligning_data <= av_ld_aligning_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte0_data <= 0; + else + av_ld_byte0_data <= av_ld_byte0_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte1_data <= 0; + else if (av_ld_byte1_data_en) + av_ld_byte1_data <= av_ld_byte1_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte2_data <= 0; + else + av_ld_byte2_data <= av_ld_byte2_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte3_data <= 0; + else + av_ld_byte3_data <= av_ld_byte3_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_valid <= 0; + else + W_valid <= E_valid & ~E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_control_rd_data <= 0; + else + W_control_rd_data <= E_control_rd_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_cmp_result <= 0; + else + W_cmp_result <= E_cmp_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_alu_result <= 0; + else + W_alu_result <= E_alu_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_status_reg_pie <= 0; + else + W_status_reg_pie <= W_status_reg_pie_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_estatus_reg <= 0; + else + W_estatus_reg <= W_estatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_bstatus_reg <= 0; + else + W_bstatus_reg <= W_bstatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ienable_reg <= 0; + else + W_ienable_reg <= W_ienable_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ipending_reg <= 0; + else + W_ipending_reg <= W_ipending_reg_nxt; + end + + + assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : + R_ctrl_rdctl_inst ? W_control_rd_data : + W_alu_result[31 : 0]; + + assign W_wr_data = W_wr_data_non_zero; + assign W_br_taken = R_ctrl_br & W_cmp_result; + assign W_mem_baddr = W_alu_result[18 : 0]; + assign W_status_reg = W_status_reg_pie; + assign E_wrctl_status = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd0); + + assign E_wrctl_estatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd1); + + assign E_wrctl_bstatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd2); + + assign E_wrctl_ienable = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd3); + + assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : + (D_op_eret) ? W_estatus_reg : + (D_op_bret) ? W_bstatus_reg : + (E_wrctl_status) ? E_src1[0] : + W_status_reg_pie; + + assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; + assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : + (R_ctrl_exception) ? W_status_reg : + (E_wrctl_estatus) ? E_src1[0] : + W_estatus_reg; + + assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; + assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : + (E_wrctl_bstatus) ? E_src1[0] : + W_bstatus_reg; + + assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; + assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? + E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000100000; + + assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000100000; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + hbreak_enabled <= 1'b1; + else if (E_valid) + hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled; + end + + + nios_system_nios2_processor_nios2_oci the_nios_system_nios2_processor_nios2_oci + ( + .D_valid (D_valid), + .E_st_data (E_st_data), + .E_valid (E_valid), + .F_pc (F_pc), + .address_nxt (jtag_debug_module_address), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .byteenable_nxt (jtag_debug_module_byteenable), + .clk (jtag_debug_module_clk), + .d_address (d_address), + .d_read (d_read), + .d_waitrequest (d_waitrequest), + .d_write (d_write), + .debugaccess_nxt (jtag_debug_module_debugaccess), + .hbreak_enabled (hbreak_enabled), + .jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms), + .oci_hbreak_req (oci_hbreak_req), + .oci_ienable (oci_ienable), + .oci_single_step_mode (oci_single_step_mode), + .read_nxt (jtag_debug_module_read), + .readdata (jtag_debug_module_readdata), + .reset (jtag_debug_module_reset), + .reset_n (reset_n), + .resetrequest (jtag_debug_module_resetrequest), + .test_ending (test_ending), + .test_has_ended (test_has_ended), + .waitrequest (jtag_debug_module_waitrequest), + .write_nxt (jtag_debug_module_write), + .writedata_nxt (jtag_debug_module_writedata) + ); + + //jtag_debug_module, which is an e_avalon_slave + assign jtag_debug_module_clk = clk; + assign jtag_debug_module_reset = ~reset_n; + assign D_ctrl_custom = 1'b0; + assign R_ctrl_custom_nxt = D_ctrl_custom; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom <= 0; + else if (R_en) + R_ctrl_custom <= R_ctrl_custom_nxt; + end + + + assign D_ctrl_custom_multi = 1'b0; + assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom_multi <= 0; + else if (R_en) + R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; + end + + + assign D_ctrl_jmp_indirect = D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_indirect <= 0; + else if (R_en) + R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; + end + + + assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; + assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_direct <= 0; + else if (R_en) + R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; + end + + + assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; + assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_retaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; + end + + + assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; + assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_eretaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; + end + + + assign D_ctrl_exception = D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60; + + assign R_ctrl_exception_nxt = D_ctrl_exception; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_exception <= 0; + else if (R_en) + R_ctrl_exception <= R_ctrl_exception_nxt; + end + + + assign D_ctrl_break = D_op_break|D_op_hbreak; + assign R_ctrl_break_nxt = D_ctrl_break; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_break <= 0; + else if (R_en) + R_ctrl_break <= R_ctrl_break_nxt; + end + + + assign D_ctrl_crst = D_op_crst|D_op_rsvx63; + assign R_ctrl_crst_nxt = D_ctrl_crst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_crst <= 0; + else if (R_en) + R_ctrl_crst <= R_ctrl_crst_nxt; + end + + + assign D_ctrl_uncond_cti_non_br = D_op_call| + D_op_jmpi| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_uncond_cti_non_br <= 0; + else if (R_en) + R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; + end + + + assign D_ctrl_retaddr = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak; + + assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_retaddr <= 0; + else if (R_en) + R_ctrl_retaddr <= R_ctrl_retaddr_nxt; + end + + + assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; + assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_logical <= 0; + else if (R_en) + R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; + end + + + assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; + assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_right_arith <= 0; + else if (R_en) + R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; + end + + + assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; + assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rot_right <= 0; + else if (R_en) + R_ctrl_rot_right <= R_ctrl_rot_right_nxt; + end + + + assign D_ctrl_shift_rot_right = D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot_right <= 0; + else if (R_en) + R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; + end + + + assign D_ctrl_shift_rot = D_op_slli| + D_op_rsvx50| + D_op_sll| + D_op_rsvx51| + D_op_roli| + D_op_rsvx34| + D_op_rol| + D_op_rsvx35| + D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot <= 0; + else if (R_en) + R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; + end + + + assign D_ctrl_logic = D_op_and| + D_op_or| + D_op_xor| + D_op_nor| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori; + + assign R_ctrl_logic_nxt = D_ctrl_logic; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_logic <= 0; + else if (R_en) + R_ctrl_logic <= R_ctrl_logic_nxt; + end + + + assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; + assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_hi_imm16 <= 0; + else if (R_en) + R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; + end + + + assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| + D_op_cmpltui| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_unsigned_lo_imm16 <= 0; + else if (R_en) + R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; + end + + + assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; + assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_uncond <= 0; + else if (R_en) + R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; + end + + + assign D_ctrl_br = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62; + + assign R_ctrl_br_nxt = D_ctrl_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br <= 0; + else if (R_en) + R_ctrl_br <= R_ctrl_br_nxt; + end + + + assign D_ctrl_alu_subtract = D_op_sub| + D_op_rsvx25| + D_op_cmplti| + D_op_cmpltui| + D_op_cmplt| + D_op_cmpltu| + D_op_blt| + D_op_bltu| + D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpge| + D_op_cmpgeu| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42; + + assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_subtract <= 0; + else if (R_en) + R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; + end + + + assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; + assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_signed_comparison <= 0; + else if (R_en) + R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; + end + + + assign D_ctrl_br_cmp = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_rsvx00| + D_op_cmpge| + D_op_cmplt| + D_op_cmpne| + D_op_cmpgeu| + D_op_cmpltu| + D_op_cmpeq| + D_op_rsvx56; + + assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_cmp <= 0; + else if (R_en) + R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; + end + + + assign D_ctrl_ld_signed = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63; + + assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_signed <= 0; + else if (R_en) + R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; + end + + + assign D_ctrl_ld = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio; + + assign R_ctrl_ld_nxt = D_ctrl_ld; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld <= 0; + else if (R_en) + R_ctrl_ld <= R_ctrl_ld_nxt; + end + + + assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; + assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_non_io <= 0; + else if (R_en) + R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; + end + + + assign D_ctrl_st = D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61; + + assign R_ctrl_st_nxt = D_ctrl_st; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_st <= 0; + else if (R_en) + R_ctrl_st <= R_ctrl_st_nxt; + end + + + assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; + assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_io <= 0; + else if (R_en) + R_ctrl_ld_io <= R_ctrl_ld_io_nxt; + end + + + assign D_ctrl_b_is_dst = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda; + + assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_b_is_dst <= 0; + else if (R_en) + R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; + end + + + assign D_ctrl_ignore_dst = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57; + + assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ignore_dst <= 0; + else if (R_en) + R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; + end + + + assign D_ctrl_src2_choose_imm = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_src2_choose_imm <= 0; + else if (R_en) + R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; + end + + + assign D_ctrl_wrctl_inst = D_op_wrctl; + assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_wrctl_inst <= 0; + else if (R_en) + R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; + end + + + assign D_ctrl_rdctl_inst = D_op_rdctl; + assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rdctl_inst <= 0; + else if (R_en) + R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; + end + + + assign D_ctrl_force_src2_zero = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_jmpi; + + assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_force_src2_zero <= 0; + else if (R_en) + R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; + end + + + assign D_ctrl_alu_force_xor = D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpeqi| + D_op_cmpge| + D_op_cmpgeu| + D_op_cmpeq| + D_op_cmpnei| + D_op_cmpne| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42| + D_op_beq| + D_op_rsv34| + D_op_bne| + D_op_rsv62| + D_op_br| + D_op_rsv02; + + assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_force_xor <= 0; + else if (R_en) + R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; + end + + + //data_master, which is an e_avalon_master + //instruction_master, which is an e_avalon_master + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign F_inst = (F_op_call)? 56'h20202063616c6c : + (F_op_jmpi)? 56'h2020206a6d7069 : + (F_op_ldbu)? 56'h2020206c646275 : + (F_op_addi)? 56'h20202061646469 : + (F_op_stb)? 56'h20202020737462 : + (F_op_br)? 56'h20202020206272 : + (F_op_ldb)? 56'h202020206c6462 : + (F_op_cmpgei)? 56'h20636d70676569 : + (F_op_ldhu)? 56'h2020206c646875 : + (F_op_andi)? 56'h202020616e6469 : + (F_op_sth)? 56'h20202020737468 : + (F_op_bge)? 56'h20202020626765 : + (F_op_ldh)? 56'h202020206c6468 : + (F_op_cmplti)? 56'h20636d706c7469 : + (F_op_initda)? 56'h20696e69746461 : + (F_op_ori)? 56'h202020206f7269 : + (F_op_stw)? 56'h20202020737477 : + (F_op_blt)? 56'h20202020626c74 : + (F_op_ldw)? 56'h202020206c6477 : + (F_op_cmpnei)? 56'h20636d706e6569 : + (F_op_flushda)? 56'h666c7573686461 : + (F_op_xori)? 56'h202020786f7269 : + (F_op_bne)? 56'h20202020626e65 : + (F_op_cmpeqi)? 56'h20636d70657169 : + (F_op_ldbuio)? 56'h206c646275696f : + (F_op_muli)? 56'h2020206d756c69 : + (F_op_stbio)? 56'h2020737462696f : + (F_op_beq)? 56'h20202020626571 : + (F_op_ldbio)? 56'h20206c6462696f : + (F_op_cmpgeui)? 56'h636d7067657569 : + (F_op_ldhuio)? 56'h206c646875696f : + (F_op_andhi)? 56'h2020616e646869 : + (F_op_sthio)? 56'h2020737468696f : + (F_op_bgeu)? 56'h20202062676575 : + (F_op_ldhio)? 56'h20206c6468696f : + (F_op_cmpltui)? 56'h636d706c747569 : + (F_op_initd)? 56'h2020696e697464 : + (F_op_orhi)? 56'h2020206f726869 : + (F_op_stwio)? 56'h2020737477696f : + (F_op_bltu)? 56'h202020626c7475 : + (F_op_ldwio)? 56'h20206c6477696f : + (F_op_flushd)? 56'h20666c75736864 : + (F_op_xorhi)? 56'h2020786f726869 : + (F_op_eret)? 56'h20202065726574 : + (F_op_roli)? 56'h202020726f6c69 : + (F_op_rol)? 56'h20202020726f6c : + (F_op_flushp)? 56'h20666c75736870 : + (F_op_ret)? 56'h20202020726574 : + (F_op_nor)? 56'h202020206e6f72 : + (F_op_mulxuu)? 56'h206d756c787575 : + (F_op_cmpge)? 56'h2020636d706765 : + (F_op_bret)? 56'h20202062726574 : + (F_op_ror)? 56'h20202020726f72 : + (F_op_flushi)? 56'h20666c75736869 : + (F_op_jmp)? 56'h202020206a6d70 : + (F_op_and)? 56'h20202020616e64 : + (F_op_cmplt)? 56'h2020636d706c74 : + (F_op_slli)? 56'h202020736c6c69 : + (F_op_sll)? 56'h20202020736c6c : + (F_op_or)? 56'h20202020206f72 : + (F_op_mulxsu)? 56'h206d756c787375 : + (F_op_cmpne)? 56'h2020636d706e65 : + (F_op_srli)? 56'h20202073726c69 : + (F_op_srl)? 56'h2020202073726c : + (F_op_nextpc)? 56'h206e6578747063 : + (F_op_callr)? 56'h202063616c6c72 : + (F_op_xor)? 56'h20202020786f72 : + (F_op_mulxss)? 56'h206d756c787373 : + (F_op_cmpeq)? 56'h2020636d706571 : + (F_op_divu)? 56'h20202064697675 : + (F_op_div)? 56'h20202020646976 : + (F_op_rdctl)? 56'h2020726463746c : + (F_op_mul)? 56'h202020206d756c : + (F_op_cmpgeu)? 56'h20636d70676575 : + (F_op_initi)? 56'h2020696e697469 : + (F_op_trap)? 56'h20202074726170 : + (F_op_wrctl)? 56'h2020777263746c : + (F_op_cmpltu)? 56'h20636d706c7475 : + (F_op_add)? 56'h20202020616464 : + (F_op_break)? 56'h2020627265616b : + (F_op_hbreak)? 56'h2068627265616b : + (F_op_sync)? 56'h20202073796e63 : + (F_op_sub)? 56'h20202020737562 : + (F_op_srai)? 56'h20202073726169 : + (F_op_sra)? 56'h20202020737261 : + (F_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign D_inst = (D_op_call)? 56'h20202063616c6c : + (D_op_jmpi)? 56'h2020206a6d7069 : + (D_op_ldbu)? 56'h2020206c646275 : + (D_op_addi)? 56'h20202061646469 : + (D_op_stb)? 56'h20202020737462 : + (D_op_br)? 56'h20202020206272 : + (D_op_ldb)? 56'h202020206c6462 : + (D_op_cmpgei)? 56'h20636d70676569 : + (D_op_ldhu)? 56'h2020206c646875 : + (D_op_andi)? 56'h202020616e6469 : + (D_op_sth)? 56'h20202020737468 : + (D_op_bge)? 56'h20202020626765 : + (D_op_ldh)? 56'h202020206c6468 : + (D_op_cmplti)? 56'h20636d706c7469 : + (D_op_initda)? 56'h20696e69746461 : + (D_op_ori)? 56'h202020206f7269 : + (D_op_stw)? 56'h20202020737477 : + (D_op_blt)? 56'h20202020626c74 : + (D_op_ldw)? 56'h202020206c6477 : + (D_op_cmpnei)? 56'h20636d706e6569 : + (D_op_flushda)? 56'h666c7573686461 : + (D_op_xori)? 56'h202020786f7269 : + (D_op_bne)? 56'h20202020626e65 : + (D_op_cmpeqi)? 56'h20636d70657169 : + (D_op_ldbuio)? 56'h206c646275696f : + (D_op_muli)? 56'h2020206d756c69 : + (D_op_stbio)? 56'h2020737462696f : + (D_op_beq)? 56'h20202020626571 : + (D_op_ldbio)? 56'h20206c6462696f : + (D_op_cmpgeui)? 56'h636d7067657569 : + (D_op_ldhuio)? 56'h206c646875696f : + (D_op_andhi)? 56'h2020616e646869 : + (D_op_sthio)? 56'h2020737468696f : + (D_op_bgeu)? 56'h20202062676575 : + (D_op_ldhio)? 56'h20206c6468696f : + (D_op_cmpltui)? 56'h636d706c747569 : + (D_op_initd)? 56'h2020696e697464 : + (D_op_orhi)? 56'h2020206f726869 : + (D_op_stwio)? 56'h2020737477696f : + (D_op_bltu)? 56'h202020626c7475 : + (D_op_ldwio)? 56'h20206c6477696f : + (D_op_flushd)? 56'h20666c75736864 : + (D_op_xorhi)? 56'h2020786f726869 : + (D_op_eret)? 56'h20202065726574 : + (D_op_roli)? 56'h202020726f6c69 : + (D_op_rol)? 56'h20202020726f6c : + (D_op_flushp)? 56'h20666c75736870 : + (D_op_ret)? 56'h20202020726574 : + (D_op_nor)? 56'h202020206e6f72 : + (D_op_mulxuu)? 56'h206d756c787575 : + (D_op_cmpge)? 56'h2020636d706765 : + (D_op_bret)? 56'h20202062726574 : + (D_op_ror)? 56'h20202020726f72 : + (D_op_flushi)? 56'h20666c75736869 : + (D_op_jmp)? 56'h202020206a6d70 : + (D_op_and)? 56'h20202020616e64 : + (D_op_cmplt)? 56'h2020636d706c74 : + (D_op_slli)? 56'h202020736c6c69 : + (D_op_sll)? 56'h20202020736c6c : + (D_op_or)? 56'h20202020206f72 : + (D_op_mulxsu)? 56'h206d756c787375 : + (D_op_cmpne)? 56'h2020636d706e65 : + (D_op_srli)? 56'h20202073726c69 : + (D_op_srl)? 56'h2020202073726c : + (D_op_nextpc)? 56'h206e6578747063 : + (D_op_callr)? 56'h202063616c6c72 : + (D_op_xor)? 56'h20202020786f72 : + (D_op_mulxss)? 56'h206d756c787373 : + (D_op_cmpeq)? 56'h2020636d706571 : + (D_op_divu)? 56'h20202064697675 : + (D_op_div)? 56'h20202020646976 : + (D_op_rdctl)? 56'h2020726463746c : + (D_op_mul)? 56'h202020206d756c : + (D_op_cmpgeu)? 56'h20636d70676575 : + (D_op_initi)? 56'h2020696e697469 : + (D_op_trap)? 56'h20202074726170 : + (D_op_wrctl)? 56'h2020777263746c : + (D_op_cmpltu)? 56'h20636d706c7475 : + (D_op_add)? 56'h20202020616464 : + (D_op_break)? 56'h2020627265616b : + (D_op_hbreak)? 56'h2068627265616b : + (D_op_sync)? 56'h20202073796e63 : + (D_op_sub)? 56'h20202020737562 : + (D_op_srai)? 56'h20202073726169 : + (D_op_sra)? 56'h20202020737261 : + (D_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; + assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; + assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; + assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; + assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v new file mode 100644 index 0000000..cd39a05 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v @@ -0,0 +1,181 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_sysclk ( + // inputs: + clk, + ir_in, + sr, + vs_udr, + vs_uir, + + // outputs: + jdo, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input clk; + input [ 1: 0] ir_in; + input [ 37: 0] sr; + input vs_udr; + input vs_uir; + + reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + wire sync_udr; + wire sync_uir; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire unxunused_resetxx3; + wire unxunused_resetxx4; + reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + assign unxunused_resetxx3 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer3 + ( + .clk (clk), + .din (vs_udr), + .dout (sync_udr), + .reset_n (unxunused_resetxx3) + ); + + defparam the_altera_std_synchronizer3.depth = 2; + + assign unxunused_resetxx4 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer4 + ( + .clk (clk), + .din (vs_uir), + .dout (sync_uir), + .reset_n (unxunused_resetxx4) + ); + + defparam the_altera_std_synchronizer4.depth = 2; + + always @(posedge clk) + begin + sync2_udr <= sync_udr; + update_jdo_strobe <= sync_udr & ~sync2_udr; + enable_action_strobe <= update_jdo_strobe; + sync2_uir <= sync_uir; + jxuir <= sync_uir & ~sync2_uir; + end + + + assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && jdo[34]; + + assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && ~jdo[34]; + + assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && + jdo[35]; + + assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + jdo[36]; + + assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + ~jdo[36]; + + assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && + jdo[37]; + + assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + jdo[37]; + + assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + ~jdo[37]; + + assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + jdo[37]; + + assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + ~jdo[37]; + + assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + jdo[37]; + + assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + ~jdo[37]; + + assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && + jdo[15]; + + always @(posedge clk) + begin + if (jxuir) + ir <= ir_in; + if (update_jdo_strobe) + jdo <= sr; + end + + + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v new file mode 100644 index 0000000..e208645 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v @@ -0,0 +1,239 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_tck ( + // inputs: + MonDReg, + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + ir_in, + jtag_state_rti, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tck, + tdi, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + vs_cdr, + vs_sdr, + vs_uir, + + // outputs: + ir_out, + jrst_n, + sr, + st_ready_test_idle, + tdo + ) +; + + output [ 1: 0] ir_out; + output jrst_n; + output [ 37: 0] sr; + output st_ready_test_idle; + output tdo; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input [ 1: 0] ir_in; + input jtag_state_rti; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tck; + input tdi; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + input vs_cdr; + input vs_sdr; + input vs_uir; + + reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire debugack_sync; + reg [ 1: 0] ir_out; + wire jrst_n; + wire monitor_ready_sync; + reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire st_ready_test_idle; + wire tdo; + wire unxcomplemented_resetxx1; + wire unxcomplemented_resetxx2; + always @(posedge tck) + begin + if (vs_cdr) + case (ir_in) + + 2'b00: begin + sr[35] <= debugack_sync; + sr[34] <= monitor_error; + sr[33] <= resetlatch; + sr[32 : 1] <= MonDReg; + sr[0] <= monitor_ready_sync; + end // 2'b00 + + 2'b01: begin + sr[35 : 0] <= tracemem_trcdata; + sr[37] <= tracemem_tw; + sr[36] <= tracemem_on; + end // 2'b01 + + 2'b10: begin + sr[37] <= trigger_state_1; + sr[36] <= dbrk_hit3_latch; + sr[35] <= dbrk_hit2_latch; + sr[34] <= dbrk_hit1_latch; + sr[33] <= dbrk_hit0_latch; + sr[32 : 1] <= break_readreg; + sr[0] <= trigbrktype; + end // 2'b10 + + 2'b11: begin + sr[15 : 12] <= 1'b0; + sr[11 : 2] <= trc_im_addr; + sr[1] <= trc_wrap; + sr[0] <= trc_on; + end // 2'b11 + + endcase // ir_in + if (vs_sdr) + case (DRsize) + + 3'b000: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // 3'b000 + + 3'b001: begin + sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; + end // 3'b001 + + 3'b010: begin + sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; + end // 3'b010 + + 3'b011: begin + sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; + end // 3'b011 + + 3'b100: begin + sr <= {tdi, sr[37], tdi, sr[35 : 1]}; + end // 3'b100 + + 3'b101: begin + sr <= {tdi, sr[37 : 1]}; + end // 3'b101 + + default: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // default + + endcase // DRsize + if (vs_uir) + case (ir_in) + + 2'b00: begin + DRsize <= 3'b100; + end // 2'b00 + + 2'b01: begin + DRsize <= 3'b101; + end // 2'b01 + + 2'b10: begin + DRsize <= 3'b101; + end // 2'b10 + + 2'b11: begin + DRsize <= 3'b010; + end // 2'b11 + + endcase // ir_in + end + + + assign tdo = sr[0]; + assign st_ready_test_idle = jtag_state_rti; + assign unxcomplemented_resetxx1 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer1 + ( + .clk (tck), + .din (debugack), + .dout (debugack_sync), + .reset_n (unxcomplemented_resetxx1) + ); + + defparam the_altera_std_synchronizer1.depth = 2; + + assign unxcomplemented_resetxx2 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer2 + ( + .clk (tck), + .din (monitor_ready), + .dout (monitor_ready_sync), + .reset_n (unxcomplemented_resetxx2) + ); + + defparam the_altera_std_synchronizer2.depth = 2; + + always @(posedge tck or negedge jrst_n) + begin + if (jrst_n == 0) + ir_out <= 2'b0; + else + ir_out <= {debugack_sync, monitor_ready_sync}; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign jrst_n = reset_n; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// assign jrst_n = 1; +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v new file mode 100644 index 0000000..059d4ab --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v @@ -0,0 +1,233 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_wrapper ( + // inputs: + MonDReg, + break_readreg, + clk, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + + // outputs: + jdo, + jrst_n, + st_ready_test_idle, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output jrst_n; + output st_ready_test_idle; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input clk; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + + wire [ 37: 0] jdo; + wire jrst_n; + wire [ 37: 0] sr; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire vji_cdr; + wire [ 1: 0] vji_ir_in; + wire [ 1: 0] vji_ir_out; + wire vji_rti; + wire vji_sdr; + wire vji_tck; + wire vji_tdi; + wire vji_tdo; + wire vji_udr; + wire vji_uir; + //Change the sld_virtual_jtag_basic's defparams to + //switch between a regular Nios II or an internally embedded Nios II. + //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. + //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. + nios_system_nios2_processor_jtag_debug_module_tck the_nios_system_nios2_processor_jtag_debug_module_tck + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .ir_in (vji_ir_in), + .ir_out (vji_ir_out), + .jrst_n (jrst_n), + .jtag_state_rti (vji_rti), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .sr (sr), + .st_ready_test_idle (st_ready_test_idle), + .tck (vji_tck), + .tdi (vji_tdi), + .tdo (vji_tdo), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1), + .vs_cdr (vji_cdr), + .vs_sdr (vji_sdr), + .vs_uir (vji_uir) + ); + + nios_system_nios2_processor_jtag_debug_module_sysclk the_nios_system_nios2_processor_jtag_debug_module_sysclk + ( + .clk (clk), + .ir_in (vji_ir_in), + .jdo (jdo), + .sr (sr), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .vs_udr (vji_udr), + .vs_uir (vji_uir) + ); + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign vji_tck = 1'b0; + assign vji_tdi = 1'b0; + assign vji_sdr = 1'b0; + assign vji_cdr = 1'b0; + assign vji_rti = 1'b0; + assign vji_uir = 1'b0; + assign vji_udr = 1'b0; + assign vji_ir_in = 2'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// sld_virtual_jtag_basic nios_system_nios2_processor_jtag_debug_module_phy +// ( +// .ir_in (vji_ir_in), +// .ir_out (vji_ir_out), +// .jtag_state_rti (vji_rti), +// .tck (vji_tck), +// .tdi (vji_tdi), +// .tdo (vji_tdo), +// .virtual_state_cdr (vji_cdr), +// .virtual_state_sdr (vji_sdr), +// .virtual_state_udr (vji_udr), +// .virtual_state_uir (vji_uir) +// ); +// +// defparam nios_system_nios2_processor_jtag_debug_module_phy.sld_auto_instance_index = "YES", +// nios_system_nios2_processor_jtag_debug_module_phy.sld_instance_index = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_ir_width = 2, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_mfg_id = 70, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_action = "", +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_n_scan = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_total_length = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_type_id = 34, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_version = 3; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v new file mode 100644 index 0000000..17ed4d4 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v @@ -0,0 +1,37 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_oci_test_bench ( + // inputs: + dct_buffer, + dct_count, + test_ending, + test_has_ended + ) +; + + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input test_ending; + input test_has_ended; + + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif new file mode 100644 index 0000000..44481aa --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif @@ -0,0 +1,267 @@ +-- Contents are randomly generated during RTL generation. +WIDTH=32; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : 88997af9; +01 : abaae595; +02 : 32fd14d1; +03 : b66193c4; +04 : c6a6aa09; +05 : 0b43de5b; +06 : d1d93028; +07 : bcd08e2a; +08 : 1c8bae85; +09 : b11dad63; +0a : 864ddf62; +0b : 68301486; +0c : 51a3d8d0; +0d : 7af7d39e; +0e : 4761b503; +0f : 2a976e14; +10 : 98141041; +11 : 4c1f6471; +12 : 41dc0a35; +13 : 7d484ae3; +14 : 2a1329f3; +15 : 44ecf499; +16 : dccdd125; +17 : 240142e9; +18 : 3b7e4b05; +19 : bb92e762; +1a : 4594a3c5; +1b : ea0d940f; +1c : 66525d7c; +1d : 0f552242; +1e : 452bd52d; +1f : d1f4ed11; +20 : 5d590422; +21 : c8016b5f; +22 : 9ab94f07; +23 : 16bac9b4; +24 : fe569ae3; +25 : c6e1e6e7; +26 : 2ff19932; +27 : feb058ad; +28 : 1dcce651; +29 : e18b9bfb; +2a : e2f4fc64; +2b : 05d34847; +2c : 077a8143; +2d : 2ce4207f; +2e : 3f3e5113; +2f : c24d2803; +30 : e289b503; +31 : d16bcd4e; +32 : 57a841cf; +33 : 1194f754; +34 : 5c925a31; +35 : 40fd6946; +36 : e397e5d7; +37 : eada7553; +38 : eba8ec01; +39 : f5b39d0b; +3a : 88af39a3; +3b : 5b7f243e; +3c : 4f2bb4ba; +3d : 9451a234; +3e : 10fd984d; +3f : ad4ef4f7; +40 : 7fe97f8b; +41 : 08ea614d; +42 : 9f2c5cf4; +43 : 3f90b7a2; +44 : 8c2bc774; +45 : 45dd63a5; +46 : 3204329c; +47 : 9909be0d; +48 : be65c97b; +49 : 78f3d4a4; +4a : 3ee8b71c; +4b : 9e9a0de4; +4c : 56db426b; +4d : e6869d81; +4e : 20ab0652; +4f : 05d247ed; +50 : 1edccf12; +51 : 1e483b5a; +52 : 8e48ef1e; +53 : f19aefbf; +54 : 98335d23; +55 : 954ac923; +56 : 4679ced6; +57 : ae18d9b8; +58 : be57db48; +59 : 2af933e3; +5a : 3f04e244; +5b : 5d11c958; +5c : 65bda8cb; +5d : c53fe664; +5e : 797ceac8; +5f : aaa406e5; +60 : f785e24e; +61 : 95510077; +62 : 5b6f55a3; +63 : 2a3c749a; +64 : a92e6ae6; +65 : b2117fb0; +66 : 262a254e; +67 : b8c4da74; +68 : f69070ee; +69 : 9e7f80b8; +6a : 834528b4; +6b : 4aaf6d98; +6c : 96023372; +6d : d11663ed; +6e : 33a3c007; +6f : 0e7f06ee; +70 : 34385787; +71 : 2edfd7b0; +72 : 00d60e4b; +73 : 49535c30; +74 : e83f5c14; +75 : 5e0c4c59; +76 : 1d7b944a; +77 : 6ae69731; +78 : bf8414e4; +79 : 7451c212; +7a : 74ede6d2; +7b : 080eafa5; +7c : f21052d8; +7d : cc0819fb; +7e : 8993e5b6; +7f : e20f2df6; +80 : 0f267a65; +81 : 7a8e8407; +82 : e7be656d; +83 : 01ba4ca3; +84 : 7f998e44; +85 : 29d83420; +86 : 149f9a73; +87 : 643ae51e; +88 : 125714d3; +89 : 6e49dc21; +8a : 0b227946; +8b : 360a837d; +8c : b2187074; +8d : 17b0bdbd; +8e : 938fc73d; +8f : e73f501e; +90 : 70b5b87e; +91 : 2a2aed8a; +92 : f96cc881; +93 : 021b49e1; +94 : 8691600d; +95 : b45e1d12; +96 : 64d9644e; +97 : 486cbaf9; +98 : 386acf20; +99 : 0d1384d4; +9a : 62455f77; +9b : 866fde20; +9c : 006fecec; +9d : 94e84514; +9e : 7babc333; +9f : afaa8445; +a0 : b1175e3a; +a1 : e08de629; +a2 : 7f12a52d; +a3 : 0e322909; +a4 : 18784dc6; +a5 : b23bcc20; +a6 : 266c9e34; +a7 : c857eaf3; +a8 : 2ae3b164; +a9 : 038acf2a; +aa : c1abc60d; +ab : 8af787bd; +ac : 043723a9; +ad : c37c952d; +ae : 693a361f; +af : da4b8e99; +b0 : fb8fdb10; +b1 : 4d6365f2; +b2 : 712358e9; +b3 : 85dae0fa; +b4 : 7e82a418; +b5 : d3493768; +b6 : 739c65ec; +b7 : 73b66b19; +b8 : 22142816; +b9 : ff498322; +ba : 3266495e; +bb : e26e8214; +bc : c8c47131; +bd : 660793d8; +be : 689f8d69; +bf : faae340b; +c0 : 37518ba7; +c1 : f2865fe5; +c2 : 1bb44f3d; +c3 : 3bce44c5; +c4 : aff2d188; +c5 : 985442da; +c6 : 85bb58bd; +c7 : 0c53135d; +c8 : 495f80bc; +c9 : 853c95dc; +ca : dde937f1; +cb : 418f9452; +cc : 7669641c; +cd : 0e752434; +ce : b0fe17a7; +cf : d1be9b88; +d0 : cfbfeb76; +d1 : 80b48a11; +d2 : 9327c69e; +d3 : beca5a88; +d4 : e71d428f; +d5 : b318d275; +d6 : 56fea35e; +d7 : 140cd6bd; +d8 : b8c937ce; +d9 : 540eea36; +da : ee58fc7f; +db : 5615c389; +dc : 46692ad0; +dd : 5c713e51; +de : 6ba95f60; +df : 0e166732; +e0 : ac0e49f5; +e1 : c9a5ea76; +e2 : 05b04d86; +e3 : b29ac712; +e4 : 4e344493; +e5 : d45ede48; +e6 : 3da7e426; +e7 : 4d6a8937; +e8 : 99b59bd4; +e9 : 1f8a5751; +ea : 8b07e64e; +eb : b4dcd496; +ec : 42f84fe6; +ed : f1d5952f; +ee : a2e5a42d; +ef : 15b1af16; +f0 : 168012bc; +f1 : 2e276612; +f2 : 89913eaa; +f3 : c607a1a2; +f4 : fd8b544d; +f5 : aec31a53; +f6 : 25f958ad; +f7 : 365903ec; +f8 : 14761865; +f9 : 568cc23b; +fa : b0386305; +fb : fb9ebd8a; +fc : a25911d4; +fd : 806e3fbb; +fe : 9df35264; +ff : d62b3814; + +END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif new file mode 100644 index 0000000..7969f10 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif @@ -0,0 +1,42 @@ +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif new file mode 100644 index 0000000..7969f10 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif @@ -0,0 +1,42 @@ +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v new file mode 100644 index 0000000..49e9050 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v @@ -0,0 +1,667 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_test_bench ( + // inputs: + D_iw, + D_iw_op, + D_iw_opx, + D_valid, + E_valid, + F_pcb, + F_valid, + R_ctrl_ld, + R_ctrl_ld_non_io, + R_dst_regnum, + R_wr_dst_reg, + W_valid, + W_vinst, + W_wr_data, + av_ld_data_aligned_unfiltered, + clk, + d_address, + d_byteenable, + d_read, + d_write_nxt, + i_address, + i_read, + i_readdata, + i_waitrequest, + reset_n, + + // outputs: + av_ld_data_aligned_filtered, + d_write, + test_has_ended + ) +; + + output [ 31: 0] av_ld_data_aligned_filtered; + output d_write; + output test_has_ended; + input [ 31: 0] D_iw; + input [ 5: 0] D_iw_op; + input [ 5: 0] D_iw_opx; + input D_valid; + input E_valid; + input [ 18: 0] F_pcb; + input F_valid; + input R_ctrl_ld; + input R_ctrl_ld_non_io; + input [ 4: 0] R_dst_regnum; + input R_wr_dst_reg; + input W_valid; + input [ 55: 0] W_vinst; + input [ 31: 0] W_wr_data; + input [ 31: 0] av_ld_data_aligned_unfiltered; + input clk; + input [ 18: 0] d_address; + input [ 3: 0] d_byteenable; + input d_read; + input d_write_nxt; + input [ 18: 0] i_address; + input i_read; + input [ 31: 0] i_readdata; + input i_waitrequest; + input reset_n; + + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire av_ld_data_aligned_unfiltered_0_is_x; + wire av_ld_data_aligned_unfiltered_10_is_x; + wire av_ld_data_aligned_unfiltered_11_is_x; + wire av_ld_data_aligned_unfiltered_12_is_x; + wire av_ld_data_aligned_unfiltered_13_is_x; + wire av_ld_data_aligned_unfiltered_14_is_x; + wire av_ld_data_aligned_unfiltered_15_is_x; + wire av_ld_data_aligned_unfiltered_16_is_x; + wire av_ld_data_aligned_unfiltered_17_is_x; + wire av_ld_data_aligned_unfiltered_18_is_x; + wire av_ld_data_aligned_unfiltered_19_is_x; + wire av_ld_data_aligned_unfiltered_1_is_x; + wire av_ld_data_aligned_unfiltered_20_is_x; + wire av_ld_data_aligned_unfiltered_21_is_x; + wire av_ld_data_aligned_unfiltered_22_is_x; + wire av_ld_data_aligned_unfiltered_23_is_x; + wire av_ld_data_aligned_unfiltered_24_is_x; + wire av_ld_data_aligned_unfiltered_25_is_x; + wire av_ld_data_aligned_unfiltered_26_is_x; + wire av_ld_data_aligned_unfiltered_27_is_x; + wire av_ld_data_aligned_unfiltered_28_is_x; + wire av_ld_data_aligned_unfiltered_29_is_x; + wire av_ld_data_aligned_unfiltered_2_is_x; + wire av_ld_data_aligned_unfiltered_30_is_x; + wire av_ld_data_aligned_unfiltered_31_is_x; + wire av_ld_data_aligned_unfiltered_3_is_x; + wire av_ld_data_aligned_unfiltered_4_is_x; + wire av_ld_data_aligned_unfiltered_5_is_x; + wire av_ld_data_aligned_unfiltered_6_is_x; + wire av_ld_data_aligned_unfiltered_7_is_x; + wire av_ld_data_aligned_unfiltered_8_is_x; + wire av_ld_data_aligned_unfiltered_9_is_x; + reg d_write; + wire test_has_ended; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_write <= 0; + else + d_write <= d_write_nxt; + end + + + assign test_has_ended = 1'b0; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //Clearing 'X' data bits + assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; + + assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; + assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; + assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; + assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; + assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; + assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; + assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; + assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; + assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; + assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; + assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; + assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; + assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; + assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; + assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; + assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; + assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; + assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; + assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; + assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; + assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; + assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; + assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; + assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; + assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; + assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; + assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; + assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; + assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; + assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; + assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; + assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; + assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; + assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; + assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; + assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; + assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; + assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; + assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; + assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; + assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; + assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; + assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; + assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; + assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; + assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; + assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; + assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; + assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; + assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; + assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; + assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; + assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; + assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; + assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; + assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; + assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; + assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; + assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; + assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; + assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; + assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; + assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; + always @(posedge clk) + begin + if (reset_n) + if (^(F_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/F_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(D_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/D_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(E_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/E_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(W_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid) + if (^(R_wr_dst_reg) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_wr_dst_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(R_dst_regnum) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_dst_regnum is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_write) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_write is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write) + if (^(d_byteenable) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_byteenable is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write | d_read) + if (^(d_address) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_read) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(i_read) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read) + if (^(i_address) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read & ~i_waitrequest) + if (^(i_readdata) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_readdata is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_ctrl_ld) + if (^(av_ld_data_aligned_unfiltered) === 1'bx) + begin + $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); + end + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// +// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_onchip_memory.hex b/db/ip/nios_system/submodules/nios_system_onchip_memory.hex new file mode 100644 index 0000000..e265501 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_onchip_memory.hex @@ -0,0 +1,51201 @@ +:0400000000000000FC +:0400010000000000FB +:0400020000000000FA +:0400030000000000F9 +:0400040000000000F8 +:0400050000000000F7 +:0400060000000000F6 +:0400070000000000F5 +:0400080000000000F4 +:0400090000000000F3 +:04000A0000000000F2 +:04000B0000000000F1 +:04000C0000000000F0 +:04000D0000000000EF +:04000E0000000000EE +:04000F0000000000ED +:0400100000000000EC +:0400110000000000EB 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a/db/ip/nios_system/submodules/nios_system_onchip_memory.v b/db/ip/nios_system/submodules/nios_system_onchip_memory.v new file mode 100644 index 0000000..9b07e72 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_onchip_memory.v @@ -0,0 +1,85 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_onchip_memory ( + // inputs: + address, + byteenable, + chipselect, + clk, + clken, + reset, + reset_req, + write, + writedata, + + // outputs: + readdata + ) +; + + parameter INIT_FILE = "nios_system_onchip_memory.hex"; + + + output [ 31: 0] readdata; + input [ 15: 0] address; + input [ 3: 0] byteenable; + input chipselect; + input clk; + input clken; + input reset; + input reset_req; + input write; + input [ 31: 0] writedata; + + wire clocken0; + wire [ 31: 0] readdata; + wire wren; + assign wren = chipselect & write; + assign clocken0 = clken & ~reset_req; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clk), + .clocken0 (clocken0), + .data_a (writedata), + .q_a (readdata), + .wren_a (wren) + ); + + defparam the_altsyncram.byte_size = 8, + the_altsyncram.init_file = INIT_FILE, + the_altsyncram.lpm_type = "altsyncram", + the_altsyncram.maximum_depth = 51200, + the_altsyncram.numwords_a = 51200, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 16; + + //s1, which is an e_avalon_slave + //s2, which is an e_avalon_slave + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_pio_0.v b/db/ip/nios_system/submodules/nios_system_pio_0.v new file mode 100644 index 0000000..9cd2e61 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_pio_0.v @@ -0,0 +1,58 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_pio_0 ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 17: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 17: 0] data_in; + wire [ 17: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_push_switches.v b/db/ip/nios_system/submodules/nios_system_push_switches.v new file mode 100644 index 0000000..0d16e4b --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_push_switches.v @@ -0,0 +1,58 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_push_switches ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 2: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 2: 0] data_in; + wire [ 2: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {3 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv new file mode 100644 index 0000000..44c4d45 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv @@ -0,0 +1,116 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv new file mode 100644 index 0000000..52411df --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv @@ -0,0 +1,101 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux_002 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux_002 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv new file mode 100644 index 0000000..755ac9e --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv @@ -0,0 +1,101 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux_003 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux_003 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv new file mode 100644 index 0000000..6f30bfb --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv @@ -0,0 +1,331 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_rsp_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv new file mode 100644 index 0000000..ce9f7a1 --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv @@ -0,0 +1,651 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_mux_001 +// NUM_INPUTS: 18 +// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_rsp_xbar_mux_001 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + input sink2_valid, + input [96-1 : 0] sink2_data, + input [18-1: 0] sink2_channel, + input sink2_startofpacket, + input sink2_endofpacket, + output sink2_ready, + + input sink3_valid, + input [96-1 : 0] sink3_data, + input [18-1: 0] sink3_channel, + input sink3_startofpacket, + input sink3_endofpacket, + output sink3_ready, + + input sink4_valid, + input [96-1 : 0] sink4_data, + input [18-1: 0] sink4_channel, + input sink4_startofpacket, + input sink4_endofpacket, + output sink4_ready, + + input sink5_valid, + input [96-1 : 0] sink5_data, + input [18-1: 0] sink5_channel, + input sink5_startofpacket, + input sink5_endofpacket, + output sink5_ready, + + input sink6_valid, + input [96-1 : 0] sink6_data, + input [18-1: 0] sink6_channel, + input sink6_startofpacket, + input sink6_endofpacket, + output sink6_ready, + + input sink7_valid, + input [96-1 : 0] sink7_data, + input [18-1: 0] sink7_channel, + input sink7_startofpacket, + input sink7_endofpacket, + output sink7_ready, + + input sink8_valid, + input [96-1 : 0] sink8_data, + input [18-1: 0] sink8_channel, + input sink8_startofpacket, + input sink8_endofpacket, + output sink8_ready, + + input sink9_valid, + input [96-1 : 0] sink9_data, + input [18-1: 0] sink9_channel, + input sink9_startofpacket, + input sink9_endofpacket, + output sink9_ready, + + input sink10_valid, + input [96-1 : 0] sink10_data, + input [18-1: 0] sink10_channel, + input sink10_startofpacket, + input sink10_endofpacket, + output sink10_ready, + + input sink11_valid, + input [96-1 : 0] sink11_data, + input [18-1: 0] sink11_channel, + input sink11_startofpacket, + input sink11_endofpacket, + output sink11_ready, + + input sink12_valid, + input [96-1 : 0] sink12_data, + input [18-1: 0] sink12_channel, + input sink12_startofpacket, + input sink12_endofpacket, + output sink12_ready, + + input sink13_valid, + input [96-1 : 0] sink13_data, + input [18-1: 0] sink13_channel, + input sink13_startofpacket, + input sink13_endofpacket, + output sink13_ready, + + input sink14_valid, + input [96-1 : 0] sink14_data, + input [18-1: 0] sink14_channel, + input sink14_startofpacket, + input sink14_endofpacket, + output sink14_ready, + + input sink15_valid, + input [96-1 : 0] sink15_data, + input [18-1: 0] sink15_channel, + input sink15_startofpacket, + input sink15_endofpacket, + output sink15_ready, + + input sink16_valid, + input [96-1 : 0] sink16_data, + input [18-1: 0] sink16_channel, + input sink16_startofpacket, + input sink16_endofpacket, + output sink16_ready, + + input sink17_valid, + input [96-1 : 0] sink17_data, + input [18-1: 0] sink17_channel, + input sink17_startofpacket, + input sink17_endofpacket, + output sink17_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 18; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + wire [PAYLOAD_W - 1 : 0] sink2_payload; + wire [PAYLOAD_W - 1 : 0] sink3_payload; + wire [PAYLOAD_W - 1 : 0] sink4_payload; + wire [PAYLOAD_W - 1 : 0] sink5_payload; + wire [PAYLOAD_W - 1 : 0] sink6_payload; + wire [PAYLOAD_W - 1 : 0] sink7_payload; + wire [PAYLOAD_W - 1 : 0] sink8_payload; + wire [PAYLOAD_W - 1 : 0] sink9_payload; + wire [PAYLOAD_W - 1 : 0] sink10_payload; + wire [PAYLOAD_W - 1 : 0] sink11_payload; + wire [PAYLOAD_W - 1 : 0] sink12_payload; + wire [PAYLOAD_W - 1 : 0] sink13_payload; + wire [PAYLOAD_W - 1 : 0] sink14_payload; + wire [PAYLOAD_W - 1 : 0] sink15_payload; + wire [PAYLOAD_W - 1 : 0] sink16_payload; + wire [PAYLOAD_W - 1 : 0] sink17_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + assign valid[2] = sink2_valid; + assign valid[3] = sink3_valid; + assign valid[4] = sink4_valid; + assign valid[5] = sink5_valid; + assign valid[6] = sink6_valid; + assign valid[7] = sink7_valid; + assign valid[8] = sink8_valid; + assign valid[9] = sink9_valid; + assign valid[10] = sink10_valid; + assign valid[11] = sink11_valid; + assign valid[12] = sink12_valid; + assign valid[13] = sink13_valid; + assign valid[14] = sink14_valid; + assign valid[15] = sink15_valid; + assign valid[16] = sink16_valid; + assign valid[17] = sink17_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + lock[2] = sink2_data[59]; + lock[3] = sink3_data[59]; + lock[4] = sink4_data[59]; + lock[5] = sink5_data[59]; + lock[6] = sink6_data[59]; + lock[7] = sink7_data[59]; + lock[8] = sink8_data[59]; + lock[9] = sink9_data[59]; + lock[10] = sink10_data[59]; + lock[11] = sink11_data[59]; + lock[12] = sink12_data[59]; + lock[13] = sink13_data[59]; + lock[14] = sink14_data[59]; + lock[15] = sink15_data[59]; + lock[16] = sink16_data[59]; + lock[17] = sink17_data[59]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + // 2 | 1 | 0 + // 3 | 1 | 0 + // 4 | 1 | 0 + // 5 | 1 | 0 + // 6 | 1 | 0 + // 7 | 1 | 0 + // 8 | 1 | 0 + // 9 | 1 | 0 + // 10 | 1 | 0 + // 11 | 1 | 0 + // 12 | 1 | 0 + // 13 | 1 | 0 + // 14 | 1 | 0 + // 15 | 1 | 0 + // 16 | 1 | 0 + // 17 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} } | + share_2 & { SHARE_COUNTER_W {next_grant[2]} } | + share_3 & { SHARE_COUNTER_W {next_grant[3]} } | + share_4 & { SHARE_COUNTER_W {next_grant[4]} } | + share_5 & { SHARE_COUNTER_W {next_grant[5]} } | + share_6 & { SHARE_COUNTER_W {next_grant[6]} } | + share_7 & { SHARE_COUNTER_W {next_grant[7]} } | + share_8 & { SHARE_COUNTER_W {next_grant[8]} } | + share_9 & { SHARE_COUNTER_W {next_grant[9]} } | + share_10 & { SHARE_COUNTER_W {next_grant[10]} } | + share_11 & { SHARE_COUNTER_W {next_grant[11]} } | + share_12 & { SHARE_COUNTER_W {next_grant[12]} } | + share_13 & { SHARE_COUNTER_W {next_grant[13]} } | + share_14 & { SHARE_COUNTER_W {next_grant[14]} } | + share_15 & { SHARE_COUNTER_W {next_grant[15]} } | + share_16 & { SHARE_COUNTER_W {next_grant[16]} } | + share_17 & { SHARE_COUNTER_W {next_grant[17]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + wire final_packet_2 = 1'b1; + + wire final_packet_3 = 1'b1; + + wire final_packet_4 = 1'b1; + + wire final_packet_5 = 1'b1; + + wire final_packet_6 = 1'b1; + + wire final_packet_7 = 1'b1; + + wire final_packet_8 = 1'b1; + + wire final_packet_9 = 1'b1; + + wire final_packet_10 = 1'b1; + + wire final_packet_11 = 1'b1; + + wire final_packet_12 = 1'b1; + + wire final_packet_13 = 1'b1; + + wire final_packet_14 = 1'b1; + + wire final_packet_15 = 1'b1; + + wire final_packet_16 = 1'b1; + + wire final_packet_17 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_17, + final_packet_16, + final_packet_15, + final_packet_14, + final_packet_13, + final_packet_12, + final_packet_11, + final_packet_10, + final_packet_9, + final_packet_8, + final_packet_7, + final_packet_6, + final_packet_5, + final_packet_4, + final_packet_3, + final_packet_2, + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + assign sink2_ready = src_ready && grant[2]; + assign sink3_ready = src_ready && grant[3]; + assign sink4_ready = src_ready && grant[4]; + assign sink5_ready = src_ready && grant[5]; + assign sink6_ready = src_ready && grant[6]; + assign sink7_ready = src_ready && grant[7]; + assign sink8_ready = src_ready && grant[8]; + assign sink9_ready = src_ready && grant[9]; + assign sink10_ready = src_ready && grant[10]; + assign sink11_ready = src_ready && grant[11]; + assign sink12_ready = src_ready && grant[12]; + assign sink13_ready = src_ready && grant[13]; + assign sink14_ready = src_ready && grant[14]; + assign sink15_ready = src_ready && grant[15]; + assign sink16_ready = src_ready && grant[16]; + assign sink17_ready = src_ready && grant[17]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} } | + sink2_payload & {PAYLOAD_W {grant[2]} } | + sink3_payload & {PAYLOAD_W {grant[3]} } | + sink4_payload & {PAYLOAD_W {grant[4]} } | + sink5_payload & {PAYLOAD_W {grant[5]} } | + sink6_payload & {PAYLOAD_W {grant[6]} } | + sink7_payload & {PAYLOAD_W {grant[7]} } | + sink8_payload & {PAYLOAD_W {grant[8]} } | + sink9_payload & {PAYLOAD_W {grant[9]} } | + sink10_payload & {PAYLOAD_W {grant[10]} } | + sink11_payload & {PAYLOAD_W {grant[11]} } | + sink12_payload & {PAYLOAD_W {grant[12]} } | + sink13_payload & {PAYLOAD_W {grant[13]} } | + sink14_payload & {PAYLOAD_W {grant[14]} } | + sink15_payload & {PAYLOAD_W {grant[15]} } | + sink16_payload & {PAYLOAD_W {grant[16]} } | + sink17_payload & {PAYLOAD_W {grant[17]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + assign sink2_payload = {sink2_channel,sink2_data, + sink2_startofpacket,sink2_endofpacket}; + assign sink3_payload = {sink3_channel,sink3_data, + sink3_startofpacket,sink3_endofpacket}; + assign sink4_payload = {sink4_channel,sink4_data, + sink4_startofpacket,sink4_endofpacket}; + assign sink5_payload = {sink5_channel,sink5_data, + sink5_startofpacket,sink5_endofpacket}; + assign sink6_payload = {sink6_channel,sink6_data, + sink6_startofpacket,sink6_endofpacket}; + assign sink7_payload = {sink7_channel,sink7_data, + sink7_startofpacket,sink7_endofpacket}; + assign sink8_payload = {sink8_channel,sink8_data, + sink8_startofpacket,sink8_endofpacket}; + assign sink9_payload = {sink9_channel,sink9_data, + sink9_startofpacket,sink9_endofpacket}; + assign sink10_payload = {sink10_channel,sink10_data, + sink10_startofpacket,sink10_endofpacket}; + assign sink11_payload = {sink11_channel,sink11_data, + sink11_startofpacket,sink11_endofpacket}; + assign sink12_payload = {sink12_channel,sink12_data, + sink12_startofpacket,sink12_endofpacket}; + assign sink13_payload = {sink13_channel,sink13_data, + sink13_startofpacket,sink13_endofpacket}; + assign sink14_payload = {sink14_channel,sink14_data, + sink14_startofpacket,sink14_endofpacket}; + assign sink15_payload = {sink15_channel,sink15_data, + sink15_startofpacket,sink15_endofpacket}; + assign sink16_payload = {sink16_channel,sink16_data, + sink16_startofpacket,sink16_endofpacket}; + assign sink17_payload = {sink17_channel,sink17_data, + sink17_startofpacket,sink17_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/db/ip/nios_system/submodules/nios_system_switches.v b/db/ip/nios_system/submodules/nios_system_switches.v new file mode 100644 index 0000000..29545ab --- /dev/null +++ b/db/ip/nios_system/submodules/nios_system_switches.v @@ -0,0 +1,58 @@ +//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_switches ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 17: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 17: 0] data_in; + wire [ 17: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/db/lights.db_info b/db/lights.db_info new file mode 100644 index 0000000..7418b82 --- /dev/null +++ b/db/lights.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Sat Jan 28 15:11:38 2017 diff --git a/db/lights.ipinfo b/db/lights.ipinfo new file mode 100644 index 0000000..fa2304d --- /dev/null +++ b/db/lights.ipinfo Binary files differ diff --git a/db/lights.sld_design_entry.sci b/db/lights.sld_design_entry.sci new file mode 100644 index 0000000..1d6d60f --- /dev/null +++ b/db/lights.sld_design_entry.sci Binary files differ diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat new file mode 100644 index 0000000..c4ac3b4 --- /dev/null +++ b/db/logic_util_heursitic.dat Binary files differ diff --git a/db/mux_nob.tdf b/db/mux_nob.tdf new file mode 100644 index 0000000..f31664f --- /dev/null +++ b/db/mux_nob.tdf @@ -0,0 +1,295 @@ +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=7 LPM_WIDTH=32 LPM_WIDTHS=3 data result sel +--VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 160 +SUBDESIGN mux_nob +( + data[223..0] : input; + result[31..0] : output; + sel[2..0] : input; +) +VARIABLE + result_node[31..0] : WIRE; + sel_ffs_wire[2..0] : WIRE; + sel_node[2..0] : WIRE; + w_data1945w[7..0] : WIRE; + w_data1967w[3..0] : WIRE; + w_data1968w[3..0] : WIRE; + w_data2016w[7..0] : WIRE; + w_data2038w[3..0] : WIRE; + w_data2039w[3..0] : WIRE; + w_data2085w[7..0] : WIRE; + w_data2107w[3..0] : WIRE; + w_data2108w[3..0] : WIRE; + w_data2154w[7..0] : WIRE; + w_data2176w[3..0] : WIRE; + w_data2177w[3..0] : WIRE; + w_data2223w[7..0] : WIRE; + w_data2245w[3..0] : WIRE; + w_data2246w[3..0] : WIRE; + w_data2292w[7..0] : WIRE; + w_data2314w[3..0] : WIRE; + w_data2315w[3..0] : WIRE; + w_data2361w[7..0] : WIRE; + w_data2383w[3..0] : WIRE; + w_data2384w[3..0] : WIRE; + w_data2430w[7..0] : WIRE; + w_data2452w[3..0] : WIRE; + w_data2453w[3..0] : WIRE; + w_data2499w[7..0] : WIRE; + w_data2521w[3..0] : WIRE; + w_data2522w[3..0] : WIRE; + w_data2568w[7..0] : WIRE; + w_data2590w[3..0] : WIRE; + w_data2591w[3..0] : WIRE; + w_data2637w[7..0] : WIRE; + w_data2659w[3..0] : WIRE; + w_data2660w[3..0] : WIRE; + w_data2706w[7..0] : WIRE; + w_data2728w[3..0] : WIRE; + w_data2729w[3..0] : WIRE; + w_data2775w[7..0] : WIRE; + w_data2797w[3..0] : WIRE; + w_data2798w[3..0] : WIRE; + w_data2844w[7..0] : WIRE; + w_data2866w[3..0] : WIRE; + w_data2867w[3..0] : WIRE; + w_data2913w[7..0] : WIRE; + w_data2935w[3..0] : WIRE; + w_data2936w[3..0] : WIRE; + w_data2982w[7..0] : WIRE; + w_data3004w[3..0] : WIRE; + w_data3005w[3..0] : WIRE; + w_data3051w[7..0] : WIRE; + w_data3073w[3..0] : WIRE; + w_data3074w[3..0] : WIRE; + w_data3120w[7..0] : WIRE; + w_data3142w[3..0] : WIRE; + w_data3143w[3..0] : WIRE; + w_data3189w[7..0] : WIRE; + w_data3211w[3..0] : WIRE; + w_data3212w[3..0] : WIRE; + w_data3258w[7..0] : WIRE; + w_data3280w[3..0] : WIRE; + w_data3281w[3..0] : WIRE; + w_data3327w[7..0] : WIRE; + w_data3349w[3..0] : WIRE; + w_data3350w[3..0] : WIRE; + w_data3396w[7..0] : WIRE; + w_data3418w[3..0] : WIRE; + w_data3419w[3..0] : WIRE; + w_data3465w[7..0] : WIRE; + w_data3487w[3..0] : WIRE; + w_data3488w[3..0] : WIRE; + w_data3534w[7..0] : WIRE; + w_data3556w[3..0] : WIRE; + w_data3557w[3..0] : WIRE; + w_data3603w[7..0] : WIRE; + w_data3625w[3..0] : WIRE; + w_data3626w[3..0] : WIRE; + w_data3672w[7..0] : WIRE; + w_data3694w[3..0] : WIRE; + w_data3695w[3..0] : WIRE; + w_data3741w[7..0] : WIRE; + w_data3763w[3..0] : WIRE; + w_data3764w[3..0] : WIRE; + w_data3810w[7..0] : WIRE; + w_data3832w[3..0] : WIRE; + w_data3833w[3..0] : WIRE; + w_data3879w[7..0] : WIRE; + w_data3901w[3..0] : WIRE; + w_data3902w[3..0] : WIRE; + w_data3948w[7..0] : WIRE; + w_data3970w[3..0] : WIRE; + w_data3971w[3..0] : WIRE; + w_data4017w[7..0] : WIRE; + w_data4039w[3..0] : WIRE; + w_data4040w[3..0] : WIRE; + w_data4086w[7..0] : WIRE; + w_data4108w[3..0] : WIRE; + w_data4109w[3..0] : WIRE; + w_sel1969w[1..0] : WIRE; + w_sel2040w[1..0] : WIRE; + w_sel2109w[1..0] : WIRE; + w_sel2178w[1..0] : WIRE; + w_sel2247w[1..0] : WIRE; + w_sel2316w[1..0] : WIRE; + w_sel2385w[1..0] : WIRE; + w_sel2454w[1..0] : WIRE; + w_sel2523w[1..0] : WIRE; + w_sel2592w[1..0] : WIRE; + w_sel2661w[1..0] : WIRE; + w_sel2730w[1..0] : WIRE; + w_sel2799w[1..0] : WIRE; + w_sel2868w[1..0] : WIRE; + w_sel2937w[1..0] : WIRE; + w_sel3006w[1..0] : WIRE; + w_sel3075w[1..0] : WIRE; + w_sel3144w[1..0] : WIRE; + w_sel3213w[1..0] : WIRE; + w_sel3282w[1..0] : WIRE; + w_sel3351w[1..0] : WIRE; + w_sel3420w[1..0] : WIRE; + w_sel3489w[1..0] : WIRE; + w_sel3558w[1..0] : WIRE; + w_sel3627w[1..0] : WIRE; + w_sel3696w[1..0] : WIRE; + w_sel3765w[1..0] : WIRE; + w_sel3834w[1..0] : WIRE; + w_sel3903w[1..0] : WIRE; + w_sel3972w[1..0] : WIRE; + w_sel4041w[1..0] : WIRE; + w_sel4110w[1..0] : WIRE; + +BEGIN + result[] = result_node[]; + result_node[] = ( ((sel_node[2..2] & (((w_data4109w[1..1] & w_sel4110w[0..0]) & (! (((w_data4109w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4109w[2..2]))))) # ((((w_data4109w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4109w[2..2]))) & (w_data4109w[3..3] # (! w_sel4110w[0..0]))))) # ((! sel_node[2..2]) & (((w_data4108w[1..1] & w_sel4110w[0..0]) & (! (((w_data4108w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4108w[2..2]))))) # ((((w_data4108w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4108w[2..2]))) & (w_data4108w[3..3] # (! w_sel4110w[0..0])))))), ((sel_node[2..2] & (((w_data4040w[1..1] & w_sel4041w[0..0]) & (! (((w_data4040w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4040w[2..2]))))) # ((((w_data4040w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4040w[2..2]))) & (w_data4040w[3..3] # (! w_sel4041w[0..0]))))) # ((! sel_node[2..2]) & (((w_data4039w[1..1] & w_sel4041w[0..0]) & (! (((w_data4039w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4039w[2..2]))))) # ((((w_data4039w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4039w[2..2]))) & (w_data4039w[3..3] # (! w_sel4041w[0..0])))))), ((sel_node[2..2] & (((w_data3971w[1..1] & w_sel3972w[0..0]) & (! (((w_data3971w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3971w[2..2]))))) # ((((w_data3971w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3971w[2..2]))) & (w_data3971w[3..3] # (! w_sel3972w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3970w[1..1] & w_sel3972w[0..0]) & (! (((w_data3970w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3970w[2..2]))))) # ((((w_data3970w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3970w[2..2]))) & (w_data3970w[3..3] # (! w_sel3972w[0..0])))))), ((sel_node[2..2] & (((w_data3902w[1..1] & w_sel3903w[0..0]) & (! (((w_data3902w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3902w[2..2]))))) # ((((w_data3902w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3902w[2..2]))) & (w_data3902w[3..3] # (! w_sel3903w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3901w[1..1] & w_sel3903w[0..0]) & (! (((w_data3901w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3901w[2..2]))))) # ((((w_data3901w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3901w[2..2]))) & (w_data3901w[3..3] # (! w_sel3903w[0..0])))))), ((sel_node[2..2] & (((w_data3833w[1..1] & w_sel3834w[0..0]) & (! (((w_data3833w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3833w[2..2]))))) # ((((w_data3833w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3833w[2..2]))) & (w_data3833w[3..3] # (! w_sel3834w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3832w[1..1] & w_sel3834w[0..0]) & (! (((w_data3832w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3832w[2..2]))))) # ((((w_data3832w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3832w[2..2]))) & (w_data3832w[3..3] # (! w_sel3834w[0..0])))))), ((sel_node[2..2] & (((w_data3764w[1..1] & w_sel3765w[0..0]) & (! (((w_data3764w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3764w[2..2]))))) # ((((w_data3764w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3764w[2..2]))) & (w_data3764w[3..3] # (! w_sel3765w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3763w[1..1] & w_sel3765w[0..0]) & (! (((w_data3763w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3763w[2..2]))))) # ((((w_data3763w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3763w[2..2]))) & (w_data3763w[3..3] # (! w_sel3765w[0..0])))))), ((sel_node[2..2] & (((w_data3695w[1..1] & w_sel3696w[0..0]) & (! (((w_data3695w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3695w[2..2]))))) # ((((w_data3695w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3695w[2..2]))) & (w_data3695w[3..3] # (! w_sel3696w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3694w[1..1] & w_sel3696w[0..0]) & (! (((w_data3694w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3694w[2..2]))))) # ((((w_data3694w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3694w[2..2]))) & (w_data3694w[3..3] # (! w_sel3696w[0..0])))))), ((sel_node[2..2] & (((w_data3626w[1..1] & w_sel3627w[0..0]) & (! (((w_data3626w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3626w[2..2]))))) # ((((w_data3626w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3626w[2..2]))) & (w_data3626w[3..3] # (! w_sel3627w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3625w[1..1] & w_sel3627w[0..0]) & (! (((w_data3625w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3625w[2..2]))))) # ((((w_data3625w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3625w[2..2]))) & (w_data3625w[3..3] # (! w_sel3627w[0..0])))))), ((sel_node[2..2] & (((w_data3557w[1..1] & w_sel3558w[0..0]) & (! (((w_data3557w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3557w[2..2]))))) # ((((w_data3557w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3557w[2..2]))) & (w_data3557w[3..3] # (! w_sel3558w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3556w[1..1] & w_sel3558w[0..0]) & (! (((w_data3556w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3556w[2..2]))))) # ((((w_data3556w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3556w[2..2]))) & (w_data3556w[3..3] # (! w_sel3558w[0..0])))))), ((sel_node[2..2] & (((w_data3488w[1..1] & w_sel3489w[0..0]) & (! (((w_data3488w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3488w[2..2]))))) # ((((w_data3488w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3488w[2..2]))) & (w_data3488w[3..3] # (! w_sel3489w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3487w[1..1] & w_sel3489w[0..0]) & (! (((w_data3487w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3487w[2..2]))))) # ((((w_data3487w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3487w[2..2]))) & (w_data3487w[3..3] # (! w_sel3489w[0..0])))))), ((sel_node[2..2] & (((w_data3419w[1..1] & w_sel3420w[0..0]) & (! (((w_data3419w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3419w[2..2]))))) # ((((w_data3419w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3419w[2..2]))) & (w_data3419w[3..3] # (! w_sel3420w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3418w[1..1] & w_sel3420w[0..0]) & (! (((w_data3418w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3418w[2..2]))))) # ((((w_data3418w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3418w[2..2]))) & (w_data3418w[3..3] # (! w_sel3420w[0..0])))))), ((sel_node[2..2] & (((w_data3350w[1..1] & w_sel3351w[0..0]) & (! (((w_data3350w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3350w[2..2]))))) # ((((w_data3350w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3350w[2..2]))) & (w_data3350w[3..3] # (! w_sel3351w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3349w[1..1] & w_sel3351w[0..0]) & (! (((w_data3349w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3349w[2..2]))))) # ((((w_data3349w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3349w[2..2]))) & (w_data3349w[3..3] # (! w_sel3351w[0..0])))))), ((sel_node[2..2] & (((w_data3281w[1..1] & w_sel3282w[0..0]) & (! (((w_data3281w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3281w[2..2]))))) # ((((w_data3281w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3281w[2..2]))) & (w_data3281w[3..3] # (! w_sel3282w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3280w[1..1] & w_sel3282w[0..0]) & (! (((w_data3280w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3280w[2..2]))))) # ((((w_data3280w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3280w[2..2]))) & (w_data3280w[3..3] # (! w_sel3282w[0..0])))))), ((sel_node[2..2] & (((w_data3212w[1..1] & w_sel3213w[0..0]) & (! (((w_data3212w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3212w[2..2]))))) # ((((w_data3212w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3212w[2..2]))) & (w_data3212w[3..3] # (! w_sel3213w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3211w[1..1] & w_sel3213w[0..0]) & (! (((w_data3211w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3211w[2..2]))))) # ((((w_data3211w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3211w[2..2]))) & (w_data3211w[3..3] # (! w_sel3213w[0..0])))))), ((sel_node[2..2] & (((w_data3143w[1..1] & w_sel3144w[0..0]) & (! (((w_data3143w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3143w[2..2]))))) # ((((w_data3143w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3143w[2..2]))) & (w_data3143w[3..3] # (! w_sel3144w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3142w[1..1] & w_sel3144w[0..0]) & (! (((w_data3142w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3142w[2..2]))))) # ((((w_data3142w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3142w[2..2]))) & (w_data3142w[3..3] # (! w_sel3144w[0..0])))))), ((sel_node[2..2] & (((w_data3074w[1..1] & w_sel3075w[0..0]) & (! (((w_data3074w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3074w[2..2]))))) # ((((w_data3074w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3074w[2..2]))) & (w_data3074w[3..3] # (! w_sel3075w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3073w[1..1] & w_sel3075w[0..0]) & (! (((w_data3073w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3073w[2..2]))))) # ((((w_data3073w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3073w[2..2]))) & (w_data3073w[3..3] # (! w_sel3075w[0..0])))))), ((sel_node[2..2] & (((w_data3005w[1..1] & w_sel3006w[0..0]) & (! (((w_data3005w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3005w[2..2]))))) # ((((w_data3005w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3005w[2..2]))) & (w_data3005w[3..3] # (! w_sel3006w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3004w[1..1] & w_sel3006w[0..0]) & (! (((w_data3004w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3004w[2..2]))))) # ((((w_data3004w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3004w[2..2]))) & (w_data3004w[3..3] # (! w_sel3006w[0..0])))))), ((sel_node[2..2] & (((w_data2936w[1..1] & w_sel2937w[0..0]) & (! (((w_data2936w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2936w[2..2]))))) # ((((w_data2936w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2936w[2..2]))) & (w_data2936w[3..3] # (! w_sel2937w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2935w[1..1] & w_sel2937w[0..0]) & (! (((w_data2935w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2935w[2..2]))))) # ((((w_data2935w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2935w[2..2]))) & (w_data2935w[3..3] # (! w_sel2937w[0..0])))))), ((sel_node[2..2] & (((w_data2867w[1..1] & w_sel2868w[0..0]) & (! (((w_data2867w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2867w[2..2]))))) # ((((w_data2867w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2867w[2..2]))) & (w_data2867w[3..3] # (! w_sel2868w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2866w[1..1] & w_sel2868w[0..0]) & (! (((w_data2866w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2866w[2..2]))))) # ((((w_data2866w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2866w[2..2]))) & (w_data2866w[3..3] # (! w_sel2868w[0..0])))))), ((sel_node[2..2] & (((w_data2798w[1..1] & w_sel2799w[0..0]) & (! (((w_data2798w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2798w[2..2]))))) # ((((w_data2798w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2798w[2..2]))) & (w_data2798w[3..3] # (! w_sel2799w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2797w[1..1] & w_sel2799w[0..0]) & (! (((w_data2797w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2797w[2..2]))))) # ((((w_data2797w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2797w[2..2]))) & (w_data2797w[3..3] # (! w_sel2799w[0..0])))))), ((sel_node[2..2] & (((w_data2729w[1..1] & w_sel2730w[0..0]) & (! (((w_data2729w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2729w[2..2]))))) # ((((w_data2729w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2729w[2..2]))) & (w_data2729w[3..3] # (! w_sel2730w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2728w[1..1] & w_sel2730w[0..0]) & (! (((w_data2728w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2728w[2..2]))))) # ((((w_data2728w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2728w[2..2]))) & (w_data2728w[3..3] # (! w_sel2730w[0..0])))))), ((sel_node[2..2] & (((w_data2660w[1..1] & w_sel2661w[0..0]) & (! (((w_data2660w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2660w[2..2]))))) # ((((w_data2660w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2660w[2..2]))) & (w_data2660w[3..3] # (! w_sel2661w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2659w[1..1] & w_sel2661w[0..0]) & (! (((w_data2659w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2659w[2..2]))))) # ((((w_data2659w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2659w[2..2]))) & (w_data2659w[3..3] # (! w_sel2661w[0..0])))))), ((sel_node[2..2] & (((w_data2591w[1..1] & w_sel2592w[0..0]) & (! (((w_data2591w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2591w[2..2]))))) # ((((w_data2591w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2591w[2..2]))) & (w_data2591w[3..3] # (! w_sel2592w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2590w[1..1] & w_sel2592w[0..0]) & (! (((w_data2590w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2590w[2..2]))))) # ((((w_data2590w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2590w[2..2]))) & (w_data2590w[3..3] # (! w_sel2592w[0..0])))))), ((sel_node[2..2] & (((w_data2522w[1..1] & w_sel2523w[0..0]) & (! (((w_data2522w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2522w[2..2]))))) # ((((w_data2522w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2522w[2..2]))) & (w_data2522w[3..3] # (! w_sel2523w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2521w[1..1] & w_sel2523w[0..0]) & (! (((w_data2521w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2521w[2..2]))))) # ((((w_data2521w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2521w[2..2]))) & (w_data2521w[3..3] # (! w_sel2523w[0..0])))))), ((sel_node[2..2] & (((w_data2453w[1..1] & w_sel2454w[0..0]) & (! (((w_data2453w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2453w[2..2]))))) # ((((w_data2453w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2453w[2..2]))) & (w_data2453w[3..3] # (! w_sel2454w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2452w[1..1] & w_sel2454w[0..0]) & (! (((w_data2452w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2452w[2..2]))))) # ((((w_data2452w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2452w[2..2]))) & (w_data2452w[3..3] # (! w_sel2454w[0..0])))))), ((sel_node[2..2] & (((w_data2384w[1..1] & w_sel2385w[0..0]) & (! (((w_data2384w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2384w[2..2]))))) # ((((w_data2384w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2384w[2..2]))) & (w_data2384w[3..3] # (! w_sel2385w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2383w[1..1] & w_sel2385w[0..0]) & (! (((w_data2383w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2383w[2..2]))))) # ((((w_data2383w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2383w[2..2]))) & (w_data2383w[3..3] # (! w_sel2385w[0..0])))))), ((sel_node[2..2] & (((w_data2315w[1..1] & w_sel2316w[0..0]) & (! (((w_data2315w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2315w[2..2]))))) # ((((w_data2315w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2315w[2..2]))) & (w_data2315w[3..3] # (! w_sel2316w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2314w[1..1] & w_sel2316w[0..0]) & (! (((w_data2314w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2314w[2..2]))))) # ((((w_data2314w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2314w[2..2]))) & (w_data2314w[3..3] # (! w_sel2316w[0..0])))))), ((sel_node[2..2] & (((w_data2246w[1..1] & w_sel2247w[0..0]) & (! (((w_data2246w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2246w[2..2]))))) # ((((w_data2246w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2246w[2..2]))) & (w_data2246w[3..3] # (! w_sel2247w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2245w[1..1] & w_sel2247w[0..0]) & (! (((w_data2245w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2245w[2..2]))))) # ((((w_data2245w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2245w[2..2]))) & (w_data2245w[3..3] # (! w_sel2247w[0..0])))))), ((sel_node[2..2] & (((w_data2177w[1..1] & w_sel2178w[0..0]) & (! (((w_data2177w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2177w[2..2]))))) # ((((w_data2177w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2177w[2..2]))) & (w_data2177w[3..3] # (! w_sel2178w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2176w[1..1] & w_sel2178w[0..0]) & (! (((w_data2176w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2176w[2..2]))))) # ((((w_data2176w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2176w[2..2]))) & (w_data2176w[3..3] # (! w_sel2178w[0..0])))))), ((sel_node[2..2] & (((w_data2108w[1..1] & w_sel2109w[0..0]) & (! (((w_data2108w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2108w[2..2]))))) # ((((w_data2108w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2108w[2..2]))) & (w_data2108w[3..3] # (! w_sel2109w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2107w[1..1] & w_sel2109w[0..0]) & (! (((w_data2107w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2107w[2..2]))))) # ((((w_data2107w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2107w[2..2]))) & (w_data2107w[3..3] # (! w_sel2109w[0..0])))))), ((sel_node[2..2] & (((w_data2039w[1..1] & w_sel2040w[0..0]) & (! (((w_data2039w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2039w[2..2]))))) # ((((w_data2039w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2039w[2..2]))) & (w_data2039w[3..3] # (! w_sel2040w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2038w[1..1] & w_sel2040w[0..0]) & (! (((w_data2038w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2038w[2..2]))))) # ((((w_data2038w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2038w[2..2]))) & (w_data2038w[3..3] # (! w_sel2040w[0..0])))))), ((sel_node[2..2] & (((w_data1968w[1..1] & w_sel1969w[0..0]) & (! (((w_data1968w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1968w[2..2]))))) # ((((w_data1968w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1968w[2..2]))) & (w_data1968w[3..3] # (! w_sel1969w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1967w[1..1] & w_sel1969w[0..0]) & (! (((w_data1967w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1967w[2..2]))))) # ((((w_data1967w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1967w[2..2]))) & (w_data1967w[3..3] # (! w_sel1969w[0..0]))))))); + sel_ffs_wire[] = ( sel[2..0]); + sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]); + w_data1945w[] = ( B"0", data[192..192], data[160..160], data[128..128], data[96..96], data[64..64], data[32..32], data[0..0]); + w_data1967w[3..0] = w_data1945w[3..0]; + w_data1968w[3..0] = w_data1945w[7..4]; + w_data2016w[] = ( B"0", data[193..193], data[161..161], data[129..129], data[97..97], data[65..65], data[33..33], data[1..1]); + w_data2038w[3..0] = w_data2016w[3..0]; + w_data2039w[3..0] = w_data2016w[7..4]; + w_data2085w[] = ( B"0", data[194..194], data[162..162], data[130..130], data[98..98], data[66..66], data[34..34], data[2..2]); + w_data2107w[3..0] = w_data2085w[3..0]; + w_data2108w[3..0] = w_data2085w[7..4]; + w_data2154w[] = ( B"0", data[195..195], data[163..163], data[131..131], data[99..99], data[67..67], data[35..35], data[3..3]); + w_data2176w[3..0] = w_data2154w[3..0]; + w_data2177w[3..0] = w_data2154w[7..4]; + w_data2223w[] = ( B"0", data[196..196], data[164..164], data[132..132], data[100..100], data[68..68], data[36..36], data[4..4]); + w_data2245w[3..0] = w_data2223w[3..0]; + w_data2246w[3..0] = w_data2223w[7..4]; + w_data2292w[] = ( B"0", data[197..197], data[165..165], data[133..133], data[101..101], data[69..69], data[37..37], data[5..5]); + w_data2314w[3..0] = w_data2292w[3..0]; + w_data2315w[3..0] = w_data2292w[7..4]; + w_data2361w[] = ( B"0", data[198..198], data[166..166], data[134..134], data[102..102], data[70..70], data[38..38], data[6..6]); + w_data2383w[3..0] = w_data2361w[3..0]; + w_data2384w[3..0] = w_data2361w[7..4]; + w_data2430w[] = ( B"0", data[199..199], data[167..167], data[135..135], data[103..103], data[71..71], data[39..39], data[7..7]); + w_data2452w[3..0] = w_data2430w[3..0]; + w_data2453w[3..0] = w_data2430w[7..4]; + w_data2499w[] = ( B"0", data[200..200], data[168..168], data[136..136], data[104..104], data[72..72], data[40..40], data[8..8]); + w_data2521w[3..0] = w_data2499w[3..0]; + w_data2522w[3..0] = w_data2499w[7..4]; + w_data2568w[] = ( B"0", data[201..201], data[169..169], data[137..137], data[105..105], data[73..73], data[41..41], data[9..9]); + w_data2590w[3..0] = w_data2568w[3..0]; + w_data2591w[3..0] = w_data2568w[7..4]; + w_data2637w[] = ( B"0", data[202..202], data[170..170], data[138..138], data[106..106], data[74..74], data[42..42], data[10..10]); + w_data2659w[3..0] = w_data2637w[3..0]; + w_data2660w[3..0] = w_data2637w[7..4]; + w_data2706w[] = ( B"0", data[203..203], data[171..171], data[139..139], data[107..107], data[75..75], data[43..43], data[11..11]); + w_data2728w[3..0] = w_data2706w[3..0]; + w_data2729w[3..0] = w_data2706w[7..4]; + w_data2775w[] = ( B"0", data[204..204], data[172..172], data[140..140], data[108..108], data[76..76], data[44..44], data[12..12]); + w_data2797w[3..0] = w_data2775w[3..0]; + w_data2798w[3..0] = w_data2775w[7..4]; + w_data2844w[] = ( B"0", data[205..205], data[173..173], data[141..141], data[109..109], data[77..77], data[45..45], data[13..13]); + w_data2866w[3..0] = w_data2844w[3..0]; + w_data2867w[3..0] = w_data2844w[7..4]; + w_data2913w[] = ( B"0", data[206..206], data[174..174], data[142..142], data[110..110], data[78..78], data[46..46], data[14..14]); + w_data2935w[3..0] = w_data2913w[3..0]; + w_data2936w[3..0] = w_data2913w[7..4]; + w_data2982w[] = ( B"0", data[207..207], data[175..175], data[143..143], data[111..111], data[79..79], data[47..47], data[15..15]); + w_data3004w[3..0] = w_data2982w[3..0]; + w_data3005w[3..0] = w_data2982w[7..4]; + w_data3051w[] = ( B"0", data[208..208], data[176..176], data[144..144], data[112..112], data[80..80], data[48..48], data[16..16]); + w_data3073w[3..0] = w_data3051w[3..0]; + w_data3074w[3..0] = w_data3051w[7..4]; + w_data3120w[] = ( B"0", data[209..209], data[177..177], data[145..145], data[113..113], data[81..81], data[49..49], data[17..17]); + w_data3142w[3..0] = w_data3120w[3..0]; + w_data3143w[3..0] = w_data3120w[7..4]; + w_data3189w[] = ( B"0", data[210..210], data[178..178], data[146..146], data[114..114], data[82..82], data[50..50], data[18..18]); + w_data3211w[3..0] = w_data3189w[3..0]; + w_data3212w[3..0] = w_data3189w[7..4]; + w_data3258w[] = ( B"0", data[211..211], data[179..179], data[147..147], data[115..115], data[83..83], data[51..51], data[19..19]); + w_data3280w[3..0] = w_data3258w[3..0]; + w_data3281w[3..0] = w_data3258w[7..4]; + w_data3327w[] = ( B"0", data[212..212], data[180..180], data[148..148], data[116..116], data[84..84], data[52..52], data[20..20]); + w_data3349w[3..0] = w_data3327w[3..0]; + w_data3350w[3..0] = w_data3327w[7..4]; + w_data3396w[] = ( B"0", data[213..213], data[181..181], data[149..149], data[117..117], data[85..85], data[53..53], data[21..21]); + w_data3418w[3..0] = w_data3396w[3..0]; + w_data3419w[3..0] = w_data3396w[7..4]; + w_data3465w[] = ( B"0", data[214..214], data[182..182], data[150..150], data[118..118], data[86..86], data[54..54], data[22..22]); + w_data3487w[3..0] = w_data3465w[3..0]; + w_data3488w[3..0] = w_data3465w[7..4]; + w_data3534w[] = ( B"0", data[215..215], data[183..183], data[151..151], data[119..119], data[87..87], data[55..55], data[23..23]); + w_data3556w[3..0] = w_data3534w[3..0]; + w_data3557w[3..0] = w_data3534w[7..4]; + w_data3603w[] = ( B"0", data[216..216], data[184..184], data[152..152], data[120..120], data[88..88], data[56..56], data[24..24]); + w_data3625w[3..0] = w_data3603w[3..0]; + w_data3626w[3..0] = w_data3603w[7..4]; + w_data3672w[] = ( B"0", data[217..217], data[185..185], data[153..153], data[121..121], data[89..89], data[57..57], data[25..25]); + w_data3694w[3..0] = w_data3672w[3..0]; + w_data3695w[3..0] = w_data3672w[7..4]; + w_data3741w[] = ( B"0", data[218..218], data[186..186], data[154..154], data[122..122], data[90..90], data[58..58], data[26..26]); + w_data3763w[3..0] = w_data3741w[3..0]; + w_data3764w[3..0] = w_data3741w[7..4]; + w_data3810w[] = ( B"0", data[219..219], data[187..187], data[155..155], data[123..123], data[91..91], data[59..59], data[27..27]); + w_data3832w[3..0] = w_data3810w[3..0]; + w_data3833w[3..0] = w_data3810w[7..4]; + w_data3879w[] = ( B"0", data[220..220], data[188..188], data[156..156], data[124..124], data[92..92], data[60..60], data[28..28]); + w_data3901w[3..0] = w_data3879w[3..0]; + w_data3902w[3..0] = w_data3879w[7..4]; + w_data3948w[] = ( B"0", data[221..221], data[189..189], data[157..157], data[125..125], data[93..93], data[61..61], data[29..29]); + w_data3970w[3..0] = w_data3948w[3..0]; + w_data3971w[3..0] = w_data3948w[7..4]; + w_data4017w[] = ( B"0", data[222..222], data[190..190], data[158..158], data[126..126], data[94..94], data[62..62], data[30..30]); + w_data4039w[3..0] = w_data4017w[3..0]; + w_data4040w[3..0] = w_data4017w[7..4]; + w_data4086w[] = ( B"0", data[223..223], data[191..191], data[159..159], data[127..127], data[95..95], data[63..63], data[31..31]); + w_data4108w[3..0] = w_data4086w[3..0]; + w_data4109w[3..0] = w_data4086w[7..4]; + w_sel1969w[1..0] = sel_node[1..0]; + w_sel2040w[1..0] = sel_node[1..0]; + w_sel2109w[1..0] = sel_node[1..0]; + w_sel2178w[1..0] = sel_node[1..0]; + w_sel2247w[1..0] = sel_node[1..0]; + w_sel2316w[1..0] = sel_node[1..0]; + w_sel2385w[1..0] = sel_node[1..0]; + w_sel2454w[1..0] = sel_node[1..0]; + w_sel2523w[1..0] = sel_node[1..0]; + w_sel2592w[1..0] = sel_node[1..0]; + w_sel2661w[1..0] = sel_node[1..0]; + w_sel2730w[1..0] = sel_node[1..0]; + w_sel2799w[1..0] = sel_node[1..0]; + w_sel2868w[1..0] = sel_node[1..0]; + w_sel2937w[1..0] = sel_node[1..0]; + w_sel3006w[1..0] = sel_node[1..0]; + w_sel3075w[1..0] = sel_node[1..0]; + w_sel3144w[1..0] = sel_node[1..0]; + w_sel3213w[1..0] = sel_node[1..0]; + w_sel3282w[1..0] = sel_node[1..0]; + w_sel3351w[1..0] = sel_node[1..0]; + w_sel3420w[1..0] = sel_node[1..0]; + w_sel3489w[1..0] = sel_node[1..0]; + w_sel3558w[1..0] = sel_node[1..0]; + w_sel3627w[1..0] = sel_node[1..0]; + w_sel3696w[1..0] = sel_node[1..0]; + w_sel3765w[1..0] = sel_node[1..0]; + w_sel3834w[1..0] = sel_node[1..0]; + w_sel3903w[1..0] = sel_node[1..0]; + w_sel3972w[1..0] = sel_node[1..0]; + w_sel4041w[1..0] = sel_node[1..0]; + w_sel4110w[1..0] = sel_node[1..0]; +END; +--VALID FILE diff --git a/db/prev_cmp_lights.qmsg b/db/prev_cmp_lights.qmsg new file mode 100644 index 0000000..b612175 --- /dev/null +++ b/db/prev_cmp_lights.qmsg @@ -0,0 +1,9 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1485396318570 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "MIF/HEX Update Quartus II 64-Bit " "Running Quartus II 64-Bit MIF/HEX Update" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1485396318570 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 26 11:05:18 2017 " "Processing started: Thu Jan 26 11:05:18 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1485396318570 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1485396318570 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb lights -c lights --update_mif " "Command: quartus_cdb lights -c lights --update_mif" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1485396318570 ""} +{ "Warning" "WQATM_MIF_NOT_FOUND" "nios_system_nios2_processor_rf_ram_a.mif " "Can't find Memory Initialization File nios_system_nios2_processor_rf_ram_a.mif -- skipped updates for this file" { } { } 0 39023 "Can't find Memory Initialization File %1!s! -- skipped updates for this file" 0 0 "Quartus II" 0 -1 1485396319617 ""} +{ "Warning" "WQATM_MIF_NOT_FOUND" "nios_system_nios2_processor_rf_ram_b.mif " "Can't find Memory Initialization File nios_system_nios2_processor_rf_ram_b.mif -- skipped updates for this file" { } { } 0 39023 "Can't find Memory Initialization File %1!s! -- skipped updates for this file" 0 0 "Quartus II" 0 -1 1485396319617 ""} +{ "Warning" "WQATM_MIF_NOT_FOUND" "nios_system_nios2_processor_ociram_default_contents.mif " "Can't find Memory Initialization File nios_system_nios2_processor_ociram_default_contents.mif -- skipped updates for this file" { } { } 0 39023 "Can't find Memory Initialization File %1!s! -- skipped updates for this file" 0 0 "Quartus II" 0 -1 1485396319617 ""} +{ "Warning" "WMIO_MIO_HEX_DATA_WRAPPING_HEAD" "nios_system_onchip_memory.hex 6400 10 " "Width of data items in \"nios_system_onchip_memory.hex\" is greater than the memory width. Wrapping data items to subsequent addresses. Found 6400 warnings, reporting 10" { { "Warning" "WMIO_MIO_DATA_WRAPPING" "2 nios_system_onchip_memory.hex " "Data at line (2) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 2 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "3 nios_system_onchip_memory.hex " "Data at line (3) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 3 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "4 nios_system_onchip_memory.hex " "Data at line (4) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 4 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "5 nios_system_onchip_memory.hex " "Data at line (5) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 5 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "6 nios_system_onchip_memory.hex " "Data at line (6) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 6 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "7 nios_system_onchip_memory.hex " "Data at line (7) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 7 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "8 nios_system_onchip_memory.hex " "Data at line (8) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 8 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "9 nios_system_onchip_memory.hex " "Data at line (9) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 9 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "10 nios_system_onchip_memory.hex " "Data at line (10) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 10 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "11 nios_system_onchip_memory.hex " "Data at line (11) of memory initialization file \"nios_system_onchip_memory.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." { } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 11 -1 0 } } } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Quartus II" 0 -1 1485396319977 ""} } { { "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 1 -1 0 } } } 0 113015 "Width of data items in \"%1!s!\" is greater than the memory width. Wrapping data items to subsequent addresses. Found %2!u! warnings, reporting %3!u!" 0 0 "Quartus II" 0 -1 1485396319977 ""} +{ "Info" "IQATM_MIFS_PROCESSED" "" "Processed the following Memory Initialization File(s)" { { "Info" "IQATM_PROCESSED_MIF_CONTENT" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex " "Processed Memory Initialization File C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" { } { { "nios_system_onchip_memory.hex" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/software/DE2_115_ASM3_release/mem_init/nios_system_onchip_memory.hex" 0 0 0 } } } 0 39025 "Processed Memory Initialization File %1!s!" 0 0 "Quartus II" 0 -1 1485396323180 ""} } { } 0 39024 "Processed the following Memory Initialization File(s)" 0 0 "Quartus II" 0 -1 1485396323180 ""} +{ "Info" "IQEXE_ERROR_COUNT" "MIF/HEX Update 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit MIF/HEX Update was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "551 " "Peak virtual memory: 551 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1485396323321 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 26 11:05:23 2017 " "Processing ended: Thu Jan 26 11:05:23 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1485396323321 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1485396323321 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1485396323321 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1485396323321 ""} diff --git a/db/scfifo_jr21.tdf b/db/scfifo_jr21.tdf new file mode 100644 index 0000000..3e1d114 --- /dev/null +++ b/db/scfifo_jr21.tdf @@ -0,0 +1,53 @@ +--scfifo DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTHU=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" +--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION a_dpfifo_q131 (aclr, clock, data[7..0], rreq, sclr, wreq) +RETURNS ( empty, full, q[7..0], usedw[5..0]); + +--synthesis_resources = lut 18 M9K 1 reg 20 +SUBDESIGN scfifo_jr21 +( + aclr : input; + clock : input; + data[7..0] : input; + empty : output; + full : output; + q[7..0] : output; + rdreq : input; + usedw[5..0] : output; + wrreq : input; +) +VARIABLE + dpfifo : a_dpfifo_q131; + sclr : NODE; + +BEGIN + dpfifo.aclr = aclr; + dpfifo.clock = clock; + dpfifo.data[] = data[]; + dpfifo.rreq = rdreq; + dpfifo.sclr = sclr; + dpfifo.wreq = wrreq; + empty = dpfifo.empty; + full = dpfifo.full; + q[] = dpfifo.q[]; + sclr = GND; + usedw[] = dpfifo.usedw[]; +END; +--VALID FILE diff --git a/lights.qpf b/lights.qpf new file mode 100644 index 0000000..b0e80dc --- /dev/null +++ b/lights.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:50:27 October 13, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "15:50:27 October 13, 2016" + +# Revisions + +PROJECT_REVISION = "lights" diff --git a/lights.qsf b/lights.qsf new file mode 100644 index 0000000..9a39622 --- /dev/null +++ b/lights.qsf @@ -0,0 +1,1109 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:50:27 October 13, 2016 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# lights_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY lights +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:50:27 OCTOBER 13, 2016" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_location_assignment PIN_E1 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 +set_location_assignment PIN_Y2 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_location_assignment PIN_T4 -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_location_assignment PIN_V6 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK +set_location_assignment PIN_A21 -to ENET0_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 +set_location_assignment PIN_C20 -to ENET0_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO +set_location_assignment PIN_C19 -to ENET0_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK +set_location_assignment PIN_D24 -to ENET1_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 +set_location_assignment PIN_D23 -to ENET1_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO +set_location_assignment PIN_D22 -to ENET1_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER +set_location_assignment PIN_A14 -to ENETCLK_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 +set_location_assignment PIN_D9 -to EX_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] +set_location_assignment PIN_E10 -to EX_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] +set_location_assignment PIN_F14 -to EX_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] +set_location_assignment PIN_H14 -to EX_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] +set_location_assignment PIN_H13 -to EX_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] +set_location_assignment PIN_J14 -to EX_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] +set_location_assignment PIN_J10 -to EX_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] +set_location_assignment PIN_AG7 -to FL_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] +set_location_assignment PIN_AG8 -to FL_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N +set_location_assignment PIN_AG26 -to GPIO[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_AH23 -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_location_assignment PIN_AH26 -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_location_assignment PIN_AF20 -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_location_assignment PIN_AG23 -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_location_assignment PIN_AE20 -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_location_assignment PIN_AF26 -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_location_assignment PIN_AH22 -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_location_assignment PIN_AE24 -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_location_assignment PIN_AG22 -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_location_assignment PIN_AE25 -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_location_assignment PIN_AH25 -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_location_assignment PIN_AD25 -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_location_assignment PIN_AG25 -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_location_assignment PIN_AD22 -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_location_assignment PIN_AF22 -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_location_assignment PIN_AF21 -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_location_assignment PIN_AE22 -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_location_assignment PIN_AC22 -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_location_assignment PIN_AF25 -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_location_assignment PIN_AE21 -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_location_assignment PIN_AF24 -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_location_assignment PIN_AF15 -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_location_assignment PIN_AD19 -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_location_assignment PIN_AF16 -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_location_assignment PIN_AC19 -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_location_assignment PIN_AE15 -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_location_assignment PIN_AD15 -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_location_assignment PIN_AE16 -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_location_assignment PIN_AD21 -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_location_assignment PIN_Y16 -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_location_assignment PIN_AC21 -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_location_assignment PIN_Y17 -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_location_assignment PIN_AB21 -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_location_assignment PIN_AC15 -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_location_assignment PIN_AB22 -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_location_assignment PIN_H22 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] +set_location_assignment PIN_J22 -to HEX0[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] +set_location_assignment PIN_L25 -to HEX0[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] +set_location_assignment PIN_L26 -to HEX0[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] +set_location_assignment PIN_E17 -to HEX0[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] +set_location_assignment PIN_F22 -to HEX0[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] +set_location_assignment PIN_G18 -to HEX0[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] +set_location_assignment PIN_U24 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] +set_location_assignment PIN_U23 -to HEX1[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] +set_location_assignment PIN_W25 -to HEX1[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] +set_location_assignment PIN_W22 -to HEX1[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] +set_location_assignment PIN_W21 -to HEX1[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] +set_location_assignment PIN_Y22 -to HEX1[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] +set_location_assignment PIN_M24 -to HEX1[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] +set_location_assignment PIN_W28 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] +set_location_assignment PIN_W27 -to HEX2[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] +set_location_assignment PIN_Y26 -to HEX2[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] +set_location_assignment PIN_W26 -to HEX2[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] +set_location_assignment PIN_Y25 -to HEX2[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] +set_location_assignment PIN_AA26 -to HEX2[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] +set_location_assignment PIN_AA25 -to HEX2[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] +set_location_assignment PIN_Y19 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_location_assignment PIN_AF23 -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_location_assignment PIN_AD24 -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_location_assignment PIN_AA21 -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_location_assignment PIN_AB20 -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_location_assignment PIN_U21 -to HEX3[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] +set_location_assignment PIN_V21 -to HEX3[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] +set_location_assignment PIN_AE18 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_location_assignment PIN_AF19 -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_location_assignment PIN_AE19 -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_location_assignment PIN_AH21 -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_location_assignment PIN_AG21 -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_location_assignment PIN_AA19 -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_location_assignment PIN_AB19 -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_location_assignment PIN_AH18 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_location_assignment PIN_AF18 -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_location_assignment PIN_AG19 -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_location_assignment PIN_AH19 -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_location_assignment PIN_AB18 -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_location_assignment PIN_AC18 -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_location_assignment PIN_AD18 -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_location_assignment PIN_AC17 -to HEX6[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] +set_location_assignment PIN_AA15 -to HEX6[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] +set_location_assignment PIN_AB15 -to HEX6[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] +set_location_assignment PIN_AB17 -to HEX6[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] +set_location_assignment PIN_AA16 -to HEX6[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] +set_location_assignment PIN_AB16 -to HEX6[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] +set_location_assignment PIN_AA17 -to HEX6[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] +set_location_assignment PIN_AA14 -to HEX7[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] +set_location_assignment PIN_AG18 -to HEX7[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] +set_location_assignment PIN_AF17 -to HEX7[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] +set_location_assignment PIN_AH17 -to HEX7[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] +set_location_assignment PIN_AG17 -to HEX7[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] +set_location_assignment PIN_AE17 -to HEX7[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] +set_location_assignment PIN_AD17 -to HEX7[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0 +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] +set_location_assignment PIN_B7 -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT +set_location_assignment PIN_Y15 -to IRDA_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD +set_location_assignment PIN_R24 -to KEY[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] +set_location_assignment PIN_N21 -to KEY[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] +set_location_assignment PIN_M21 -to KEY[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] +set_location_assignment PIN_M23 -to KEY[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] +set_location_assignment PIN_L6 -to LCD_BLON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] +set_location_assignment PIN_L4 -to LCD_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN +set_location_assignment PIN_L5 -to LCD_ON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON +set_location_assignment PIN_M2 -to LCD_RS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS +set_location_assignment PIN_M1 -to LCD_RW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW +set_location_assignment PIN_F17 -to LEDG[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] +set_location_assignment PIN_G21 -to LEDG[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] +set_location_assignment PIN_G22 -to LEDG[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] +set_location_assignment PIN_G20 -to LEDG[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] +set_location_assignment PIN_H21 -to LEDG[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] +set_location_assignment PIN_E24 -to LEDG[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] +set_location_assignment PIN_E25 -to LEDG[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] +set_location_assignment PIN_E22 -to LEDG[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] +set_location_assignment PIN_E21 -to LEDG[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] +set_location_assignment PIN_H15 -to LEDR[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] +set_location_assignment PIN_G16 -to LEDR[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] +set_location_assignment PIN_G15 -to LEDR[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] +set_location_assignment PIN_F15 -to LEDR[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] +set_location_assignment PIN_H17 -to LEDR[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] +set_location_assignment PIN_J16 -to LEDR[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] +set_location_assignment PIN_H16 -to LEDR[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] +set_location_assignment PIN_J15 -to LEDR[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] +set_location_assignment PIN_G17 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] +set_location_assignment PIN_J17 -to LEDR[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] +set_location_assignment PIN_H19 -to LEDR[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] +set_location_assignment PIN_J19 -to LEDR[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] +set_location_assignment PIN_E18 -to LEDR[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] +set_location_assignment PIN_F18 -to LEDR[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] +set_location_assignment PIN_F21 -to LEDR[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] +set_location_assignment PIN_E19 -to LEDR[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] +set_location_assignment PIN_F19 -to LEDR[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] +set_location_assignment PIN_G19 -to LEDR[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N +set_location_assignment PIN_D4 -to OTG_DACK_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1] +set_location_assignment PIN_C4 -to OTG_DACK_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] +set_location_assignment PIN_B4 -to OTG_DREQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0] +set_location_assignment PIN_C6 -to OTG_FSPEED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED +set_location_assignment PIN_D5 -to OTG_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1] +set_location_assignment PIN_A6 -to OTG_INT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0] +set_location_assignment PIN_B6 -to OTG_LSPEED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED +set_location_assignment PIN_B3 -to OTG_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N +set_location_assignment PIN_C5 -to OTG_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N +set_location_assignment PIN_G6 -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_location_assignment PIN_G5 -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_location_assignment PIN_H5 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_location_assignment PIN_F5 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 +set_location_assignment PIN_AE13 -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] +set_location_assignment PIN_AF14 -to SD_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N +set_location_assignment PIN_Y23 -to SW[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] +set_location_assignment PIN_Y24 -to SW[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] +set_location_assignment PIN_AA22 -to SW[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] +set_location_assignment PIN_AA23 -to SW[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] +set_location_assignment PIN_AA24 -to SW[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] +set_location_assignment PIN_AB23 -to SW[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] +set_location_assignment PIN_AB24 -to SW[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] +set_location_assignment PIN_AC24 -to SW[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] +set_location_assignment PIN_AB25 -to SW[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] +set_location_assignment PIN_AC25 -to SW[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] +set_location_assignment PIN_AB26 -to SW[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] +set_location_assignment PIN_AD26 -to SW[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] +set_location_assignment PIN_AC26 -to SW[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] +set_location_assignment PIN_AB27 -to SW[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] +set_location_assignment PIN_AD27 -to SW[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] +set_location_assignment PIN_AC27 -to SW[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] +set_location_assignment PIN_AC28 -to SW[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] +set_location_assignment PIN_AB28 -to SW[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] +set_location_assignment PIN_B14 -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_location_assignment PIN_F7 -to TD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_location_assignment PIN_E8 -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_location_assignment PIN_E5 -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_location_assignment PIN_G7 -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_location_assignment PIN_E4 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS +set_location_assignment PIN_G14 -to UART_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS +set_location_assignment PIN_G12 -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_location_assignment PIN_G9 -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_location_assignment PIN_D12 -to VGA_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] +set_location_assignment PIN_D11 -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_location_assignment PIN_C12 -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_location_assignment PIN_A11 -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_location_assignment PIN_B11 -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_location_assignment PIN_C11 -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_location_assignment PIN_A10 -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_location_assignment PIN_B10 -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_location_assignment PIN_A12 -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_location_assignment PIN_C9 -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_location_assignment PIN_F10 -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_location_assignment PIN_B8 -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_location_assignment PIN_C8 -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_location_assignment PIN_H12 -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_location_assignment PIN_F8 -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_location_assignment PIN_G11 -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_location_assignment PIN_G8 -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_location_assignment PIN_G13 -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_location_assignment PIN_H10 -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_location_assignment PIN_H8 -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_location_assignment PIN_J12 -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_location_assignment PIN_G10 -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_location_assignment PIN_F12 -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_location_assignment PIN_D10 -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_location_assignment PIN_E11 -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_location_assignment PIN_E12 -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_location_assignment PIN_C13 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 +set_global_assignment -name QIP_FILE software/DE2_115_ASM3_release/mem_init/meminit.qip +set_global_assignment -name QSYS_FILE nios_system.qsys +set_global_assignment -name SOURCE_FILE nios_system.cmp +set_global_assignment -name VHDL_FILE lights.vhd +set_global_assignment -name VERILOG_FILE nios_system/synthesis/nios_system.v +set_global_assignment -name CDF_FILE output_files/lights.cdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/lights.qws b/lights.qws new file mode 100644 index 0000000..3311bba --- /dev/null +++ b/lights.qws Binary files differ diff --git a/lights.vhd b/lights.vhd new file mode 100644 index 0000000..83a1bb7 --- /dev/null +++ b/lights.vhd @@ -0,0 +1,76 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity lights is port ( + CLOCK_50 : in std_logic; + KEY : in std_logic_vector(3 downto 0); + SW : in std_logic_vector(17 downto 0); + LEDG : out std_logic_vector(7 downto 0); + LEDR : out std_logic_vector(17 downto 0); + HEX0 : out std_logic_vector(6 downto 0); + HEX1 : out std_logic_vector(6 downto 0); + HEX2 : out std_logic_vector(6 downto 0); + HEX3 : out std_logic_vector(6 downto 0); + HEX4 : out std_logic_vector(6 downto 0); + HEX5 : out std_logic_vector(6 downto 0); + HEX6 : out std_logic_vector(6 downto 0); + HEX7 : out std_logic_vector(6 downto 0); + LCD_RS : out std_logic; + LCD_RW : out std_logic; + LCD_data : out std_logic_vector(7 downto 0); + LCD_EN : out std_logic; + LCD_ON : out std_logic; + LCD_BLON : out std_logic +); +end lights; + +architecture lights_rtl of lights is + component nios_system + port ( + signal clk_clk : in std_logic; + signal reset_reset_n : in std_logic; + signal switches_export : in std_logic_vector(17 downto 0); + signal push_switches_export : in std_logic_vector(2 downto 0); + signal leds_export : out std_logic_vector(7 downto 0); + signal ledrs_export : out std_logic_vector(17 downto 0); + signal hex0_export : out std_logic_vector(6 downto 0); + signal hex1_export : out std_logic_vector(6 downto 0); + signal hex2_export : out std_logic_vector(6 downto 0); + signal hex3_export : out std_logic_vector(6 downto 0); + signal hex4_export : out std_logic_vector(6 downto 0); + signal hex5_export : out std_logic_vector(6 downto 0); + signal hex6_export : out std_logic_vector(6 downto 0); + signal hex7_export : out std_logic_vector(6 downto 0); + signal lcd_16207_0_RS : out std_logic; + signal lcd_16207_0_RW : out std_logic; + signal lcd_16207_0_data : out std_logic_vector(7 downto 0); + signal lcd_16207_0_E : out std_logic; + signal lcd_on_export : out std_logic; + signal lcd_blon_export : out std_logic + ); + end component; +begin + NiosII : nios_system + port map ( + clk_clk => CLOCK_50, + reset_reset_n => KEY(0), + switches_export => SW(17 downto 0), + push_switches_export => KEY(3 downto 1), + leds_export => LEDG(7 downto 0), + ledrs_export => LEDR(17 downto 0), + hex0_export => HEX0(6 downto 0), + hex1_export => HEX1(6 downto 0), + hex2_export => HEX2(6 downto 0), + hex3_export => HEX3(6 downto 0), + hex4_export => HEX4(6 downto 0), + hex5_export => HEX5(6 downto 0), + hex6_export => HEX6(6 downto 0), + hex7_export => HEX7(6 downto 0), + lcd_16207_0_RS => LCD_RS, + lcd_16207_0_RW => LCD_RW, + lcd_16207_0_data => LCD_DATA, + lcd_16207_0_E => LCD_EN, + lcd_on_export => LCD_ON, + lcd_blon_export => LCD_BLON + ); +end lights_rtl; \ No newline at end of file diff --git a/nios_system.bsf b/nios_system.bsf new file mode 100644 index 0000000..dac37b1 --- /dev/null +++ b/nios_system.bsf @@ -0,0 +1,248 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 384 792) + (text "nios_system" (rect 155 -1 206 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 776 20 788)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 160 72)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 160 152)(line_width 1)) + ) + (port + (pt 0 232) + (input) + (text "switches_export[17..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) + (text "switches_export[17..0]" (rect 4 221 136 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 160 232)(line_width 3)) + ) + (port + (pt 0 272) + (input) + (text "push_switches_export[2..0]" (rect 0 0 108 12)(font "Arial" (font_size 8))) + (text "push_switches_export[2..0]" (rect 4 261 160 272)(font "Arial" (font_size 8))) + (line (pt 0 272)(pt 160 272)(line_width 3)) + ) + (port + (pt 0 112) + (output) + (text "leds_export[7..0]" (rect 0 0 66 12)(font "Arial" (font_size 8))) + (text "leds_export[7..0]" (rect 4 101 106 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 160 112)(line_width 3)) + ) + (port + (pt 0 192) + (output) + (text "ledrs_export[17..0]" (rect 0 0 73 12)(font "Arial" (font_size 8))) + (text "ledrs_export[17..0]" (rect 4 181 118 192)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 160 192)(line_width 3)) + ) + (port + (pt 0 312) + (output) + (text "hex0_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "hex0_export[6..0]" (rect 4 301 106 312)(font "Arial" (font_size 8))) + (line (pt 0 312)(pt 160 312)(line_width 3)) + ) + (port + (pt 0 352) + (output) + (text "hex1_export[6..0]" (rect 0 0 68 12)(font "Arial" (font_size 8))) + (text "hex1_export[6..0]" (rect 4 341 106 352)(font "Arial" (font_size 8))) + (line (pt 0 352)(pt 160 352)(line_width 3)) + ) + (port + (pt 0 392) + (output) + (text "hex2_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "hex2_export[6..0]" (rect 4 381 106 392)(font "Arial" (font_size 8))) + (line (pt 0 392)(pt 160 392)(line_width 3)) + ) + (port + (pt 0 432) + (output) + (text "hex3_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "hex3_export[6..0]" (rect 4 421 106 432)(font "Arial" (font_size 8))) + (line (pt 0 432)(pt 160 432)(line_width 3)) + ) + (port + (pt 0 472) + (output) + (text "hex4_export[6..0]" (rect 0 0 70 12)(font "Arial" (font_size 8))) + (text "hex4_export[6..0]" (rect 4 461 106 472)(font "Arial" (font_size 8))) + (line (pt 0 472)(pt 160 472)(line_width 3)) + ) + (port + (pt 0 512) + (output) + (text "hex5_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "hex5_export[6..0]" (rect 4 501 106 512)(font "Arial" (font_size 8))) + (line (pt 0 512)(pt 160 512)(line_width 3)) + ) + (port + (pt 0 552) + (output) + (text "hex6_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "hex6_export[6..0]" (rect 4 541 106 552)(font "Arial" (font_size 8))) + (line (pt 0 552)(pt 160 552)(line_width 3)) + ) + (port + (pt 0 592) + (output) + (text "hex7_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "hex7_export[6..0]" (rect 4 581 106 592)(font "Arial" (font_size 8))) + (line (pt 0 592)(pt 160 592)(line_width 3)) + ) + (port + (pt 0 632) + (output) + (text "lcd_16207_0_RS" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "lcd_16207_0_RS" (rect 4 621 88 632)(font "Arial" (font_size 8))) + (line (pt 0 632)(pt 160 632)(line_width 1)) + ) + (port + (pt 0 648) + (output) + (text "lcd_16207_0_RW" (rect 0 0 74 12)(font "Arial" (font_size 8))) + (text "lcd_16207_0_RW" (rect 4 637 88 648)(font "Arial" (font_size 8))) + (line (pt 0 648)(pt 160 648)(line_width 1)) + ) + (port + (pt 0 680) + (output) + (text "lcd_16207_0_E" (rect 0 0 62 12)(font "Arial" (font_size 8))) + (text "lcd_16207_0_E" (rect 4 669 82 680)(font "Arial" (font_size 8))) + (line (pt 0 680)(pt 160 680)(line_width 1)) + ) + (port + (pt 0 720) + (output) + (text "lcd_on_export" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "lcd_on_export" (rect 4 709 82 720)(font "Arial" (font_size 8))) + (line (pt 0 720)(pt 160 720)(line_width 1)) + ) + (port + (pt 0 760) + (output) + (text "lcd_blon_export" (rect 0 0 62 12)(font "Arial" (font_size 8))) + (text "lcd_blon_export" (rect 4 749 94 760)(font "Arial" (font_size 8))) + (line (pt 0 760)(pt 160 760)(line_width 1)) + ) + (port + (pt 0 664) + (bidir) + (text "lcd_16207_0_data[7..0]" (rect 0 0 92 12)(font "Arial" (font_size 8))) + (text "lcd_16207_0_data[7..0]" (rect 4 653 136 664)(font "Arial" (font_size 8))) + (line (pt 0 664)(pt 160 664)(line_width 3)) + ) + (drawing + (text "clk" (rect 145 43 308 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0))) + (text "leds" (rect 137 83 298 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 107 366 224)(font "Arial" (color 0 0 0))) + (text "reset" (rect 131 123 292 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 165 147 372 304)(font "Arial" (color 0 0 0))) + (text "ledrs" (rect 132 163 294 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 187 366 384)(font "Arial" (color 0 0 0))) + (text "switches" (rect 110 203 268 419)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 227 366 464)(font "Arial" (color 0 0 0))) + (text "push_switches" (rect 74 243 226 499)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 267 366 544)(font "Arial" (color 0 0 0))) + (text "hex0" (rect 134 283 292 579)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 307 366 624)(font "Arial" (color 0 0 0))) + (text "hex1" (rect 136 323 296 659)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 347 366 704)(font "Arial" (color 0 0 0))) + (text "hex2" (rect 134 363 292 739)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 387 366 784)(font "Arial" (color 0 0 0))) + (text "hex3" (rect 134 403 292 819)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 427 366 864)(font "Arial" (color 0 0 0))) + (text "hex4" (rect 134 443 292 899)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 467 366 944)(font "Arial" (color 0 0 0))) + (text "hex5" (rect 134 483 292 979)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 507 366 1024)(font "Arial" (color 0 0 0))) + (text "hex6" (rect 134 523 292 1059)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 547 366 1104)(font "Arial" (color 0 0 0))) + (text "hex7" (rect 134 563 292 1139)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 587 366 1184)(font "Arial" (color 0 0 0))) + (text "lcd_16207_0" (rect 89 603 244 1219)(font "Arial" (color 128 0 0)(font_size 9))) + (text "RS" (rect 165 627 342 1264)(font "Arial" (color 0 0 0))) + (text "RW" (rect 165 643 342 1296)(font "Arial" (color 0 0 0))) + (text "data" (rect 165 659 354 1328)(font "Arial" (color 0 0 0))) + (text "E" (rect 165 675 336 1360)(font "Arial" (color 0 0 0))) + (text "lcd_on" (rect 123 691 282 1395)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 715 366 1440)(font "Arial" (color 0 0 0))) + (text "lcd_blon" (rect 113 731 274 1475)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 755 366 1520)(font "Arial" (color 0 0 0))) + (text " nios_system " (rect 326 776 730 1562)(font "Arial" )) + (line (pt 161 52)(pt 161 76)(line_width 1)) + (line (pt 162 52)(pt 162 76)(line_width 1)) + (line (pt 161 92)(pt 161 116)(line_width 1)) + (line (pt 162 92)(pt 162 116)(line_width 1)) + (line (pt 161 132)(pt 161 156)(line_width 1)) + (line (pt 162 132)(pt 162 156)(line_width 1)) + (line (pt 161 172)(pt 161 196)(line_width 1)) + (line (pt 162 172)(pt 162 196)(line_width 1)) + (line (pt 161 212)(pt 161 236)(line_width 1)) + (line (pt 162 212)(pt 162 236)(line_width 1)) + (line (pt 161 252)(pt 161 276)(line_width 1)) + (line (pt 162 252)(pt 162 276)(line_width 1)) + (line (pt 161 292)(pt 161 316)(line_width 1)) + (line (pt 162 292)(pt 162 316)(line_width 1)) + (line (pt 161 332)(pt 161 356)(line_width 1)) + (line (pt 162 332)(pt 162 356)(line_width 1)) + (line (pt 161 372)(pt 161 396)(line_width 1)) + (line (pt 162 372)(pt 162 396)(line_width 1)) + (line (pt 161 412)(pt 161 436)(line_width 1)) + (line (pt 162 412)(pt 162 436)(line_width 1)) + (line (pt 161 452)(pt 161 476)(line_width 1)) + (line (pt 162 452)(pt 162 476)(line_width 1)) + (line (pt 161 492)(pt 161 516)(line_width 1)) + (line (pt 162 492)(pt 162 516)(line_width 1)) + (line (pt 161 532)(pt 161 556)(line_width 1)) + (line (pt 162 532)(pt 162 556)(line_width 1)) + (line (pt 161 572)(pt 161 596)(line_width 1)) + (line (pt 162 572)(pt 162 596)(line_width 1)) + (line (pt 161 612)(pt 161 684)(line_width 1)) + (line (pt 162 612)(pt 162 684)(line_width 1)) + (line (pt 161 700)(pt 161 724)(line_width 1)) + (line (pt 162 700)(pt 162 724)(line_width 1)) + (line (pt 161 740)(pt 161 764)(line_width 1)) + (line (pt 162 740)(pt 162 764)(line_width 1)) + (line (pt 160 32)(pt 224 32)(line_width 1)) + (line (pt 224 32)(pt 224 776)(line_width 1)) + (line (pt 160 776)(pt 224 776)(line_width 1)) + (line (pt 160 32)(pt 160 776)(line_width 1)) + (line (pt 0 0)(pt 384 0)(line_width 1)) + (line (pt 384 0)(pt 384 792)(line_width 1)) + (line (pt 0 792)(pt 384 792)(line_width 1)) + (line (pt 0 0)(pt 0 792)(line_width 1)) + ) +) diff --git a/nios_system.cmp b/nios_system.cmp new file mode 100644 index 0000000..97030ef --- /dev/null +++ b/nios_system.cmp @@ -0,0 +1,25 @@ + component nios_system is + port ( + clk_clk : in std_logic := 'X'; -- clk + leds_export : out std_logic_vector(7 downto 0); -- export + reset_reset_n : in std_logic := 'X'; -- reset_n + ledrs_export : out std_logic_vector(17 downto 0); -- export + switches_export : in std_logic_vector(17 downto 0) := (others => 'X'); -- export + push_switches_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export + hex0_export : out std_logic_vector(6 downto 0); -- export + hex1_export : out std_logic_vector(6 downto 0); -- export + hex2_export : out std_logic_vector(6 downto 0); -- export + hex3_export : out std_logic_vector(6 downto 0); -- export + hex4_export : out std_logic_vector(6 downto 0); -- export + hex5_export : out std_logic_vector(6 downto 0); -- export + hex6_export : out std_logic_vector(6 downto 0); -- export + hex7_export : out std_logic_vector(6 downto 0); -- export + lcd_16207_0_RS : out std_logic; -- RS + lcd_16207_0_RW : out std_logic; -- RW + lcd_16207_0_data : inout std_logic_vector(7 downto 0) := (others => 'X'); -- data + lcd_16207_0_E : out std_logic; -- E + lcd_on_export : out std_logic; -- export + lcd_blon_export : out std_logic -- export + ); + end component nios_system; + diff --git a/nios_system.html b/nios_system.html new file mode 100644 index 0000000..8959bd4 --- /dev/null +++ b/nios_system.html @@ -0,0 +1,4862 @@ + + + + + datasheet for nios_system + + + + + + + + +

nios_system

+
+
+

+ + + + + +

2016.12.22.10:06:15

Datasheet

Overview

+ + + + + + + + +

clk_0	nios_system

Memory Map

	+ nios2_processor + +
	data_master	instruction_master
+ nios2_processor + +
jtag_debug_module	0x00040800	0x00040800
+ onchip_memory + +
s1	0x00000000	0x00000000
+ jtag_uart + +
avalon_jtag_slave	0x00041100
+ LEDs + +
s1	0x000410f0
+ LEDRs + +
s1	0x000410e0
+ switches + +
s1	0x000410d0
+ push_switches + +
s1	0x000410c0
+ hex0 + +
s1	0x000410b0
+ hex1 + +
s1	0x000410a0
+ hex2 + +
s1	0x00041090
+ hex3 + +
s1	0x00041080
+ hex4 + +
s1	0x00041070
+ hex5 + +
s1	0x00041060
+ hex6 + +
s1	0x00041050
+ hex7 + +
s1	0x00041040
+ lcd_16207_0 + +
control_slave	0x00041030
+ lcd_on + +
s1	0x00041010
+ lcd_blon + +
s1	0x00041020

+ +

clk_0

clock_source v13.0 +
+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + +

clockFrequency	50000000
clockFrequencyKnown	true
inputClockFrequency	0
resetSynchronousEdges	NONE
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

(none)

+ +

nios2_processor

altera_nios2_qsys v13.0 +
+

+ clk_0 +	clk	nios2_processor
	clk
	clk_reset
	reset_n
			jtag_debug_module_reset	+ onchip_memory +
			reset1
			instruction_master
			s1
			data_master
			s1

			jtag_debug_module_reset	+ jtag_uart +
			reset
			d_irq
			irq
			data_master
			avalon_jtag_slave

			jtag_debug_module_reset	+ LEDs +
			reset
			data_master
			s1

			data_master	+ LEDRs +
			s1
			jtag_debug_module_reset
			reset

			jtag_debug_module_reset	+ switches +
			reset
			data_master
			s1

			data_master	+ push_switches +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex0 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex1 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex2 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex3 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex4 +
			s1
			jtag_debug_module_reset
			reset

			data_master	+ hex5 +
		s1
		jtag_debug_module_reset
		reset

		data_master	+ hex6 +
		s1
		jtag_debug_module_reset
		reset

		data_master	+ hex7 +
		s1
		jtag_debug_module_reset
		reset

		jtag_debug_module_reset	+ lcd_16207_0 +
		reset
		data_master
		control_slave

		data_master	+ lcd_on +
		s1
		jtag_debug_module_reset
		reset

		jtag_debug_module_reset	+ lcd_blon +
		reset
		data_master
		s1

+
+
+ + + + +

Parameters

setting_showUnpublishedSettings	false
setting_showInternalSettings	false
setting_preciseSlaveAccessErrorException	false
setting_preciseIllegalMemAccessException	false
setting_preciseDivisionErrorException	false
setting_performanceCounter	false
setting_illegalMemAccessDetection	false
setting_illegalInstructionsTrap	false
setting_fullWaveformSignals	false
setting_extraExceptionInfo	false
setting_exportPCB	false
setting_debugSimGen	false
setting_clearXBitsLDNonBypass	true
setting_bit31BypassDCache	true
setting_bigEndian	false
setting_export_large_RAMs	false
setting_asic_enabled	false
setting_asic_synopsys_translate_on_off	false
setting_oci_export_jtag_signals	false
setting_bhtIndexPcOnly	false
setting_avalonDebugPortPresent	false
setting_alwaysEncrypt	true
setting_allowFullAddressRange	false
setting_activateTrace	true
setting_activateTestEndChecker	false
setting_activateMonitors	true
setting_activateModelChecker	false
setting_HDLSimCachesCleared	true
setting_HBreakTest	false
muldiv_divider	false
mpu_useLimit	false
mpu_enabled	false
mmu_enabled	false
mmu_autoAssignTlbPtrSz	true
manuallyAssignCpuID	true
debug_triggerArming	true
debug_embeddedPLL	true
debug_debugReqSignals	false
debug_assignJtagInstanceID	false
dcache_omitDataMaster	false
cpuReset	false
is_hardcopy_compatible	false
setting_shadowRegisterSets	0
mpu_numOfInstRegion	8
mpu_numOfDataRegion	8
mmu_TLBMissExcOffset	0
debug_jtagInstanceID	0
resetOffset	0
exceptionOffset	32
cpuID	0
cpuID_stored	0
breakOffset	32
userDefinedSettings
resetSlave	onchip_memory.s1
mmu_TLBMissExcSlave	None
exceptionSlave	onchip_memory.s1
breakSlave	nios2_processor.jtag_debug_module
setting_perfCounterWidth	32
setting_interruptControllerType	Internal
setting_branchPredictionType	Automatic
setting_bhtPtrSz	8
muldiv_multiplierType	EmbeddedMulFast
mpu_minInstRegionSize	12
mpu_minDataRegionSize	12
mmu_uitlbNumEntries	4
mmu_udtlbNumEntries	6
mmu_tlbPtrSz	7
mmu_tlbNumWays	16
mmu_processIDNumBits	8
impl	Tiny
icache_size	4096
icache_tagramBlockType	Automatic
icache_ramBlockType	Automatic
icache_numTCIM	0
icache_burstType	None
dcache_bursts	false
dcache_victim_buf_impl	ram
debug_level	Level1
debug_OCIOnchipTrace	_128
dcache_size	2048
dcache_tagramBlockType	Automatic
dcache_ramBlockType	Automatic
dcache_numTCDM	0
dcache_lineSize	32
setting_exportvectors	false
setting_ecc_present	false
regfile_ramBlockType	Automatic
ocimem_ramBlockType	Automatic
mmu_ramBlockType	Automatic
bht_ramBlockType	Automatic
resetAbsoluteAddr	0
exceptionAbsoluteAddr	32
breakAbsoluteAddr	264224
mmu_TLBMissExcAbsAddr	0
dcache_bursts_derived	false
dcache_size_derived	2048
dcache_lineSize_derived	32
translate_on	"synthesis translate_on"
translate_off	"synthesis translate_off"
instAddrWidth	19
dataAddrWidth	19
tightlyCoupledDataMaster0AddrWidth	1
tightlyCoupledDataMaster1AddrWidth	1
tightlyCoupledDataMaster2AddrWidth	1
tightlyCoupledDataMaster3AddrWidth	1
tightlyCoupledInstructionMaster0AddrWidth	1
tightlyCoupledInstructionMaster1AddrWidth	1
tightlyCoupledInstructionMaster2AddrWidth	1
tightlyCoupledInstructionMaster3AddrWidth	1
instSlaveMapParam	<address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='nios2_processor.jtag_debug_module' start='0x40800' end='0x41000' /></address-map>
dataSlaveMapParam	<address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='nios2_processor.jtag_debug_module' start='0x40800' end='0x41000' /><slave name='lcd_on.s1' start='0x41010' end='0x41020' /><slave name='lcd_blon.s1' start='0x41020' end='0x41030' /><slave name='lcd_16207_0.control_slave' start='0x41030' end='0x41040' /><slave name='hex7.s1' start='0x41040' end='0x41050' /><slave name='hex6.s1' start='0x41050' end='0x41060' /><slave name='hex5.s1' start='0x41060' end='0x41070' /><slave name='hex4.s1' start='0x41070' end='0x41080' /><slave name='hex3.s1' start='0x41080' end='0x41090' /><slave name='hex2.s1' start='0x41090' end='0x410A0' /><slave name='hex1.s1' start='0x410A0' end='0x410B0' /><slave name='hex0.s1' start='0x410B0' end='0x410C0' /><slave name='push_switches.s1' start='0x410C0' end='0x410D0' /><slave name='switches.s1' start='0x410D0' end='0x410E0' /><slave name='LEDRs.s1' start='0x410E0' end='0x410F0' /><slave name='LEDs.s1' start='0x410F0' end='0x41100' /><slave name='jtag_uart.avalon_jtag_slave' start='0x41100' end='0x41108' /></address-map>
clockFrequency	50000000
deviceFamilyName	CYCLONEIVE
internalIrqMaskSystemInfo	32
customInstSlavesSystemInfo	<info/>
deviceFeaturesSystemInfo	ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIG_ENDIAN	0
BREAK_ADDR	0x00040820
CPU_FREQ	50000000u
CPU_ID_SIZE	1
CPU_ID_VALUE	0x00000000
CPU_IMPLEMENTATION	"tiny"
DATA_ADDR_WIDTH	19
DCACHE_LINE_SIZE	0
DCACHE_LINE_SIZE_LOG2	0
DCACHE_SIZE	0
EXCEPTION_ADDR	0x00000020
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT	0
HARDWARE_MULTIPLY_PRESENT	0
HARDWARE_MULX_PRESENT	0
HAS_DEBUG_CORE	1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE	0
ICACHE_LINE_SIZE_LOG2	0
ICACHE_SIZE	0
INST_ADDR_WIDTH	19
RESET_ADDR	0x00000000

+ +

onchip_memory

altera_avalon_onchip_memory2 v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	onchip_memory
	clk1
	clk_reset
	reset1

+ nios2_processor +	jtag_debug_module_reset
	reset1
	instruction_master
	s1
	data_master
	s1

+
+
+ + + + +

Parameters

allowInSystemMemoryContentEditor	false
blockType	AUTO
dataWidth	32
dualPort	false
initMemContent	true
initializationFileName	onchip_mem.hex
instanceID	NONE
memorySize	204800
readDuringWriteMode	DONT_CARE
simAllowMRAMContentsFile	false
simMemInitOnlyFilename	0
singleClockOperation	false
slave1Latency	1
slave2Latency	1
useNonDefaultInitFile	false
useShallowMemBlocks	false
writable	true
autoInitializationFileName	nios_system_onchip_memory
deviceFamily	CYCLONEIVE
deviceFeatures	ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width	16
derived_gui_ram_block_type	Automatic
derived_is_hardcopy	false
derived_init_file_name	nios_system_onchip_memory.hex
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR	0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE	0
CONTENTS_INFO	""
DUAL_PORT	0
GUI_RAM_BLOCK_TYPE	AUTO
INIT_CONTENTS_FILE	nios_system_onchip_memory
INIT_MEM_CONTENT	1
INSTANCE_ID	NONE
NON_DEFAULT_INIT_FILE_ENABLED	0
RAM_BLOCK_TYPE	AUTO
READ_DURING_WRITE_MODE	DONT_CARE
SINGLE_CLOCK_OP	0
SIZE_MULTIPLE	1
SIZE_VALUE	204800
WRITABLE	1

+ +

jtag_uart

altera_avalon_jtag_uart v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ nios2_processor +	jtag_debug_module_reset	jtag_uart
	reset
	d_irq
	irq
	data_master
	avalon_jtag_slave

+ clk_0 +	clk_reset
	reset
	clk
	clk

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

allowMultipleConnections	false
hubInstanceID	0
readBufferDepth	64
readIRQThreshold	8
simInputCharacterStream
simInteractiveOptions	NO_INTERACTIVE_WINDOWS
useRegistersForReadBuffer	false
useRegistersForWriteBuffer	false
useRelativePathForSimFile	false
writeBufferDepth	64
writeIRQThreshold	8
avalonSpec	2.0
legacySignalAllow	false
enableInteractiveInput	false
enableInteractiveOutput	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + +

READ_DEPTH	64
READ_THRESHOLD	8
WRITE_DEPTH	64
WRITE_THRESHOLD	8

+ +

LEDs

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	LEDs
	clk
	clk_reset
	reset

+ nios2_processor +	jtag_debug_module_reset
	reset
	data_master
	s1

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	8
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	8
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

LEDRs

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	LEDRs
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	18
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	18
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

switches

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	switches
	clk
	clk_reset
	reset

+ nios2_processor +	jtag_debug_module_reset
	reset
	data_master
	s1

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Input
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	18
clockRate	50000000
derived_has_tri	false
derived_has_out	false
derived_has_in	true
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	18
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	1
HAS_OUT	0
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

push_switches

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	push_switches
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Input
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	3
clockRate	50000000
derived_has_tri	false
derived_has_out	false
derived_has_in	true
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	3
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	1
HAS_OUT	0
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex0

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex0
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex1

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex1
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex2

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex2
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex3

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex3
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex4

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex4
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex5

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex5
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex6

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex6
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

hex7

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	hex7
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	7
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	7
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

lcd_16207_0

altera_avalon_lcd_16207 v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	lcd_16207_0
	clk
	clk_reset
	reset

+ nios2_processor +	jtag_debug_module_reset
	reset
	data_master
	control_slave

+
+
+ + + + +

Parameters

+ + + + + + + + + +

deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

(none)

+ +

lcd_on

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	lcd_on
	clk
	clk_reset
	reset

+ nios2_processor +	data_master
	s1
	jtag_debug_module_reset
	reset

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	1
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	1
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ +

lcd_blon

altera_avalon_pio v13.0.1.99.2 +
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ clk_0 +	clk	lcd_blon
	clk
	clk_reset
	reset

+ nios2_processor +	jtag_debug_module_reset
	reset
	data_master
	s1

+
+
+ + + + +

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

bitClearingEdgeCapReg	false
bitModifyingOutReg	false
captureEdge	false
direction	Output
edgeType	RISING
generateIRQ	false
irqType	LEVEL
resetValue	0
simDoTestBenchWiring	false
simDrivenValue	0
width	1
clockRate	50000000
derived_has_tri	false
derived_has_out	true
derived_has_in	false
derived_do_test_bench_wiring	false
derived_capture	false
derived_edge_type	NONE
derived_irq_type	NONE
derived_has_irq	false
deviceFamily	UNKNOWN
generateLegacySim	false

+ + + + +

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BIT_CLEARING_EDGE_REGISTER	0
BIT_MODIFYING_OUTPUT_REGISTER	0
CAPTURE	0
DATA_WIDTH	1
DO_TEST_BENCH_WIRING	0
DRIVEN_SIM_VALUE	0
EDGE_TYPE	NONE
FREQ	50000000
HAS_IN	0
HAS_OUT	1
HAS_TRI	0
IRQ_TYPE	NONE
RESET_VALUE	0

+ + + + + +

generation took 0.00 seconds

rendering took 0.17 seconds

+ + diff --git a/nios_system.qsys b/nios_system.qsys new file mode 100644 index 0000000..da73ace --- /dev/null +++ b/nios_system.qsys @@ -0,0 +1,1274 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + nios2_processor.jtag_debug_module + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + ]]> + + + + + ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_onchip_memory + + ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + NO_INTERACTIVE_WINDOWS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/nios_system.sopcinfo b/nios_system.sopcinfo new file mode 100644 index 0000000..e460637 --- /dev/null +++ b/nios_system.sopcinfo @@ -0,0 +1,18218 @@ + + + + + + + java.lang.Integer + 1485396334 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + + + java.lang.String + EP4CE115F29C7 + false + true + false + true + + + java.lang.Long + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.String + Cyclone IV E + false + true + false + true + + + boolean + false + false + true + true + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + nios2_processor + clk + nios2_processor.clk + + + false + onchip_memory + clk1 + onchip_memory.clk1 + + + false + jtag_uart + clk + jtag_uart.clk + + + false + LEDs + clk + LEDs.clk + + + false + LEDRs + clk + LEDRs.clk + + + false + switches + clk + switches.clk + + + false + push_switches + clk + push_switches.clk + + + false + hex0 + clk + hex0.clk + + + false + hex1 + clk + hex1.clk + + + false + hex2 + clk + hex2.clk + + + false + hex3 + clk + hex3.clk + + + false + hex4 + clk + hex4.clk + + + false + hex5 + clk + hex5.clk + + + false + hex6 + clk + hex6.clk + + + false + hex7 + clk + hex7.clk + + + false + lcd_16207_0 + clk + lcd_16207_0.clk + + + false + lcd_on + clk + lcd_on.clk + + + false + lcd_blon + clk + lcd_blon.clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + debug.hostConnection + type jtag id 70:34|110:135 + + + embeddedsw.CMacro.BIG_ENDIAN + 0 + + + embeddedsw.CMacro.BREAK_ADDR + 0x00040820 + + + embeddedsw.CMacro.CPU_FREQ + 50000000u + + + embeddedsw.CMacro.CPU_ID_SIZE + 1 + + + embeddedsw.CMacro.CPU_ID_VALUE + 0x00000000 + + + embeddedsw.CMacro.CPU_IMPLEMENTATION + "tiny" + + + embeddedsw.CMacro.DATA_ADDR_WIDTH + 19 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE + 0 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 + 0 + + + embeddedsw.CMacro.DCACHE_SIZE + 0 + + + embeddedsw.CMacro.EXCEPTION_ADDR + 0x00000020 + + + embeddedsw.CMacro.FLUSHDA_SUPPORTED + + + + embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT + 0 + + + embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT + 0 + + + embeddedsw.CMacro.HARDWARE_MULX_PRESENT + 0 + + + embeddedsw.CMacro.HAS_DEBUG_CORE + 1 + + + embeddedsw.CMacro.HAS_DEBUG_STUB + + + + embeddedsw.CMacro.HAS_JMPI_INSTRUCTION + + + + embeddedsw.CMacro.ICACHE_LINE_SIZE + 0 + + + embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 + 0 + + + embeddedsw.CMacro.ICACHE_SIZE + 0 + + + embeddedsw.CMacro.INST_ADDR_WIDTH + 19 + + + embeddedsw.CMacro.RESET_ADDR + 0x00000000 + + + embeddedsw.configuration.HDLSimCachesCleared + 1 + + + embeddedsw.configuration.breakOffset + 32 + + + embeddedsw.configuration.breakSlave + nios2_processor.jtag_debug_module + + + embeddedsw.configuration.cpuArchitecture + Nios II + + + embeddedsw.configuration.exceptionOffset + 32 + + + embeddedsw.configuration.exceptionSlave + onchip_memory.s1 + + + embeddedsw.configuration.resetOffset + 0 + + + embeddedsw.configuration.resetSlave + onchip_memory.s1 + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + 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+ 8 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 32 + false + false + true + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + onchip_memory.s1 + false + true + true + true + + + java.lang.String + None + false + false + true + true + + + java.lang.String + onchip_memory.s1 + false + true + true + true + + + java.lang.String + nios2_processor.jtag_debug_module + false + false + true + true + + + int + 32 + false + true + false + true + + + java.lang.String + Internal + false + false + true + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 8 + false + true + false + true + + + java.lang.String + EmbeddedMulFast + false + false + true + true + + + int + 12 + false + false + true + true + + + int + 12 + false + false + true + true + + + int + 4 + false + false + true + true + + + int + 6 + false + false + true + true + + + int + 7 + false + false + true + true + + + int + 16 + false + false + true + true + + + int + 8 + false + false + true + true + + + java.lang.String + Tiny + false + true + true + true + + + int + 4096 + false + false + true + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + None + false + false + true + true + + + java.lang.String + false + false + false + true + true + + + java.lang.String + ram + false + false + true + true + + + java.lang.String + Level1 + false + true + true + true + + + java.lang.String + _128 + false + false + true + true + + + int + 2048 + false + false + true + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 32 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + true + true + true + true + + + int + 32 + true + true + true + true + + + int + 264224 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + false + true + true + false + true + + + int + 2048 + true + true + false + true + + + int + 32 + true + true + false + true + + + java.lang.String + "synthesis translate_on" + true + true + false + true + + + java.lang.String + "synthesis translate_off" + true + true + false + true + + + int + 19 + false + true + false + true + + + int + 19 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + ]]> + false + true + false + true + + + java.lang.String + ]]> + false + true + false + true + + + long + 50000000 + false + true + false + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + + + long + 32 + false + true + false + true + + + java.lang.String + ]]> + false + true + false + true + + + java.lang.String + ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + debug.providesServices + master + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + d_address + Output + 19 + address + + + d_byteenable + Output + 4 + byteenable + + + d_read + Output + 1 + read + + + d_readdata + Input + 32 + readdata + + + d_waitrequest + Input + 1 + waitrequest + + + d_write + Output + 1 + write + + + d_writedata + Output + 32 + writedata + + + jtag_debug_module_debugaccess_to_roms + Output + 1 + debugaccess + + + false + nios2_processor + jtag_debug_module + nios2_processor.jtag_debug_module + 264192 + 2048 + + + false + onchip_memory + s1 + onchip_memory.s1 + 0 + 204800 + + + false + LEDs + s1 + LEDs.s1 + 266480 + 16 + + + false + jtag_uart + avalon_jtag_slave + jtag_uart.avalon_jtag_slave + 266496 + 8 + + + false + LEDRs + s1 + LEDRs.s1 + 266464 + 16 + + + false + switches + s1 + switches.s1 + 266448 + 16 + + + false + push_switches + s1 + push_switches.s1 + 266432 + 16 + + + false + hex0 + s1 + hex0.s1 + 266416 + 16 + + + false + hex1 + s1 + hex1.s1 + 266400 + 16 + + + false + hex2 + s1 + hex2.s1 + 266384 + 16 + + + false + hex3 + s1 + hex3.s1 + 266368 + 16 + + + false + hex4 + s1 + hex4.s1 + 266352 + 16 + + + false + hex5 + s1 + hex5.s1 + 266336 + 16 + + + false + hex6 + s1 + hex6.s1 + 266320 + 16 + + + false + hex7 + s1 + hex7.s1 + 266304 + 16 + + + false + lcd_16207_0 + control_slave + lcd_16207_0.control_slave + 266288 + 16 + + + false + lcd_on + s1 + lcd_on.s1 + 266256 + 16 + + + false + lcd_blon + s1 + lcd_blon.s1 + 266272 + 16 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + i_address + Output + 19 + address + + + i_read + Output + 1 + read + + + i_readdata + Input + 32 + readdata + + + i_waitrequest + Input + 1 + waitrequest + + + false + nios2_processor + jtag_debug_module + nios2_processor.jtag_debug_module + 264192 + 2048 + + + false + onchip_memory + s1 + onchip_memory.s1 + 0 + 204800 + + + + + + com.altera.entityinterfaces.IConnectionPoint + nios2_processor.data_master + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset_n + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + d_irq + Input + 32 + irq + + + false + jtag_uart + irq + jtag_uart.irq + 5 + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + none + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + jtag_debug_module_resetrequest + Output + 1 + reset + + + + + + embeddedsw.configuration.hideDevice + 1 + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + qsys.ui.connect + instruction_master,data_master + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 2048 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + jtag_debug_module_address + Input + 9 + address + + + jtag_debug_module_byteenable + Input + 4 + byteenable + + + jtag_debug_module_debugaccess + Input + 1 + debugaccess + + + jtag_debug_module_read + Input + 1 + read + + + jtag_debug_module_readdata + Output + 32 + readdata + + + jtag_debug_module_waitrequest + Output + 1 + waitrequest + + + jtag_debug_module_write + Input + 1 + write + + + jtag_debug_module_writedata + Input + 32 + writedata + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + no_ci_readra + Output + 1 + readra + + + + + + + embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR + 0 + + + embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE + 0 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.CMacro.DUAL_PORT + 0 + + + embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE + AUTO + + + embeddedsw.CMacro.INIT_CONTENTS_FILE + nios_system_onchip_memory + + + embeddedsw.CMacro.INIT_MEM_CONTENT + 1 + + + embeddedsw.CMacro.INSTANCE_ID + NONE + + + embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED + 0 + + + embeddedsw.CMacro.RAM_BLOCK_TYPE + AUTO + + + embeddedsw.CMacro.READ_DURING_WRITE_MODE + DONT_CARE + + + embeddedsw.CMacro.SINGLE_CLOCK_OP + 0 + + + embeddedsw.CMacro.SIZE_MULTIPLE + 1 + + + embeddedsw.CMacro.SIZE_VALUE + 204800 + + + embeddedsw.CMacro.WRITABLE + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.MEM_INIT_FILENAME + nios_system_onchip_memory + + + postgeneration.simulation.init_file.param_name + INIT_FILE + + + postgeneration.simulation.init_file.type + MEM_INIT + + + boolean + false + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + int + 32 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + onchip_mem.hex + false + false + true + true + + + java.lang.String + NONE + false + false + true + true + + + long + 204800 + false + true + true + true + + + java.lang.String + DONT_CARE + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + false + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + nios_system_onchip_memory + false + true + false + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + + + java.lang.String + ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + + + int + 16 + true + true + false + true + + + java.lang.String + Automatic + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + nios_system_onchip_memory.hex + true + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 204800 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk1 + false + true + true + true + + + java.lang.String + reset1 + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 204800 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 16 + address + + + clken + Input + 1 + clken + + + chipselect + Input + 1 + chipselect + + + write + Input + 1 + write + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + byteenable + Input + 4 + byteenable + + + + + + java.lang.String + clk1 + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + reset_req + Input + 1 + reset_req + + + + + + + embeddedsw.CMacro.READ_DEPTH + 64 + + + embeddedsw.CMacro.READ_THRESHOLD + 8 + + + embeddedsw.CMacro.WRITE_DEPTH + 64 + + + embeddedsw.CMacro.WRITE_THRESHOLD + 8 + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + + false + false + false + true + + + java.lang.String + NO_INTERACTIVE_WINDOWS + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + 2.0 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + rst_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 2 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + av_chipselect + Input + 1 + chipselect + + + av_address + Input + 1 + address + + + av_read_n + Input + 1 + read_n + + + av_readdata + Output + 32 + readdata + + + av_write_n + Input + 1 + write_n + + + av_writedata + Input + 32 + writedata + + + av_waitrequest + Output + 1 + waitrequest + + + + + + com.altera.entityinterfaces.IConnectionPoint + jtag_uart.avalon_jtag_slave + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + av_irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 8 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 8 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 8 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 18 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 18 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 18 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 18 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 1 + + + embeddedsw.CMacro.HAS_OUT + 0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + Input + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + long + 0 + false + false + true + true + + + int + 18 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + in_port + Input + 18 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 3 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 1 + + + embeddedsw.CMacro.HAS_OUT + 0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + Input + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + long + 0 + false + false + true + true + + + int + 3 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + in_port + Input + 3 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 250 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 250 + false + true + false + true + + + int + 250 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 250 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Nanoseconds + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 250 + false + true + false + true + + + int + 250 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + begintransfer + Input + 1 + begintransfer + + + read + Input + 1 + read + + + write + Input + 1 + write + + + readdata + Output + 8 + readdata + + + writedata + Input + 8 + writedata + + + address + Input + 2 + address + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + LCD_RS + Output + 1 + export + + + LCD_RW + Output + 1 + export + + + LCD_data + Bidir + 8 + export + + + LCD_E + Output + 1 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 1 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 1 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 1 + export + + + + + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 1 + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0 + + + embeddedsw.CMacro.EDGE_TYPE + NONE + + + embeddedsw.CMacro.FREQ + 50000000 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.IRQ_TYPE + NONE + + + embeddedsw.CMacro.RESET_VALUE + 0 + + + embeddedsw.dts.compatible + altr,pio-1.0 + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + Output + false + true + true + true + + + java.lang.String + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 1 + false + true + true + true + + + long + 50000000 + false + true + false + true + + + boolean + false + true + true + false + true + + + boolean + true + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + java.lang.String + NONE + true + true + false + true + + + boolean + false + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 1 + export + + + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00040800 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + instruction_master + nios2_processor + jtag_debug_module + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00040800 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + nios2_processor + jtag_debug_module + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + nios2_processor + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + onchip_memory + clk1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + nios2_processor + reset_n + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + onchip_memory + reset1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + nios2_processor + reset_n + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + onchip_memory + reset1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + instruction_master + onchip_memory + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x0000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + onchip_memory + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + jtag_uart + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + jtag_uart + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + jtag_uart + clk + + + + int + 5 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + d_irq + jtag_uart + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + LEDs + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + LEDs + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + LEDs + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x000410f0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + LEDs + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041100 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + jtag_uart + avalon_jtag_slave + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + LEDRs + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + LEDRs + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x000410e0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + LEDRs + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + LEDRs + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + switches + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + switches + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + switches + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x000410d0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + switches + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + push_switches + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + push_switches + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x000410c0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + push_switches + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + push_switches + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + hex0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + hex0 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x000410b0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + hex0 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + hex0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + hex1 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + hex1 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x000410a0 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + hex1 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + hex1 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + hex2 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + hex2 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041090 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + hex2 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + hex2 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + hex3 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + hex3 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041080 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + hex3 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + hex3 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + hex4 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + hex4 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041070 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + hex4 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + hex4 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + hex5 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + hex5 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041060 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + hex5 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + hex5 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + hex6 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + hex6 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041050 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + hex6 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + hex6 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + hex7 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + hex7 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041040 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + hex7 + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + hex7 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + lcd_16207_0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + lcd_16207_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + lcd_16207_0 + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041030 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + lcd_16207_0 + control_slave + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + lcd_on + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + lcd_blon + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + lcd_on + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + lcd_blon + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041010 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + lcd_on + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + lcd_on + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + jtag_debug_module_reset + lcd_blon + reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00041020 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios2_processor + data_master + lcd_blon + s1 + + + 1 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 13.0 + + + 15 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 13.0 + + + 1 + altera_avalon_onchip_memory2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + On-Chip Memory (RAM or ROM) + 13.0.1.99.2 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.0 + + + 1 + altera_nios2_qsys + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Nios II Processor + 13.0 + + + 1 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 13.0 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.0 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 13.0 + + + 14 + altera_avalon_pio + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + PIO (Parallel I/O) + 13.0.1.99.2 + + + 1 + altera_avalon_jtag_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG UART + 13.0.1.99.2 + + + 18 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 13.0 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 13.0 + + + 2 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 13.0 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 13.0 + + + 20 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 13.0 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 13.0 + + + 18 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 13.0 + + + 36 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 13.0 + + + 1 + nios_custom_instruction_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Master + 13.0 + + + 18 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 13.0 + + + 1 + altera_avalon_lcd_16207 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Altera Avalon LCD 16207 + 13.0.1.99.2 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 13.0 + + + 18 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.0 + + 13.0sp1 232 + + diff --git a/nios_system/synthesis/nios_system.qip b/nios_system/synthesis/nios_system.qip new file mode 100644 index 0000000..76e2e7b --- /dev/null +++ b/nios_system/synthesis/nios_system.qip @@ -0,0 +1,133 @@ +set_global_assignment -entity "nios_system" -library "nios_system" -name IP_TOOL_NAME "Qsys" +set_global_assignment -entity "nios_system" -library "nios_system" -name IP_TOOL_VERSION "13.0sp1" +set_global_assignment -entity "nios_system" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -library "nios_system" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../nios_system.sopcinfo"] +set_instance_assignment -entity "nios_system" -library "nios_system" -name SLD_INFO "QSYS_NAME nios_system HAS_SOPCINFO 1 GENERATION_ID 1482368774" +set_global_assignment -library "nios_system" -name MISC_FILE [file join $::quartus(qip_path) "../../nios_system.cmp"] +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "nios_system" -name MISC_FILE [file join $::quartus(qip_path) "../../nios_system.qsys"] + +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "nios_system.v"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_irq_mapper.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_arbitrator.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_rsp_xbar_mux_001.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_rsp_xbar_mux.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_rsp_xbar_demux_002.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_cmd_xbar_mux.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_cmd_xbar_demux_001.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_cmd_xbar_demux.sv"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"] +set_global_assignment -library "nios_system" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_id_router_002.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_id_router.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_addr_router_001.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_addr_router.sv"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_sc_fifo.v"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_agent.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_uncompressor.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_agent.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"] +set_global_assignment -library "nios_system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_lcd_on.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_lcd_16207_0.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_hex0.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_push_switches.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_switches.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_LEDRs.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_LEDs.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_jtag_uart.v"] +set_global_assignment -library "nios_system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios_system_onchip_memory.hex"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_onchip_memory.v"] +set_global_assignment -library "nios_system" -name SDC_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor.sdc"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_jtag_debug_module_tck.v"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v"] +set_global_assignment -library "nios_system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_ociram_default_contents.mif"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_oci_test_bench.v"] +set_global_assignment -library "nios_system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_rf_ram_a.mif"] +set_global_assignment -library "nios_system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_rf_ram_b.mif"] +set_global_assignment -library "nios_system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios_system_nios2_processor_test_bench.v"] + +set_global_assignment -entity "nios_system_irq_mapper" -library "nios_system" -name IP_TOOL_NAME "altera_irq_mapper" +set_global_assignment -entity "nios_system_irq_mapper" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_irq_mapper" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_rsp_xbar_mux_001" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "nios_system_rsp_xbar_mux_001" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_rsp_xbar_mux_001" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_rsp_xbar_mux" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "nios_system_rsp_xbar_mux" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_rsp_xbar_mux" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_rsp_xbar_demux_002" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "nios_system_rsp_xbar_demux_002" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_rsp_xbar_demux_002" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_cmd_xbar_mux" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "nios_system_cmd_xbar_mux" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_cmd_xbar_mux" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_cmd_xbar_demux_001" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "nios_system_cmd_xbar_demux_001" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_cmd_xbar_demux_001" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_cmd_xbar_demux" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "nios_system_cmd_xbar_demux" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_cmd_xbar_demux" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_reset_controller" -library "nios_system" -name IP_TOOL_NAME "altera_reset_controller" +set_global_assignment -entity "altera_reset_controller" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "altera_reset_controller" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_id_router_002" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "nios_system_id_router_002" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_id_router_002" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_id_router" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "nios_system_id_router" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_id_router" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_addr_router_001" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "nios_system_addr_router_001" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_addr_router_001" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_addr_router" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "nios_system_addr_router" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_addr_router" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_sc_fifo" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_merlin_slave_agent" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_slave_agent" +set_global_assignment -entity "altera_merlin_slave_agent" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "altera_merlin_slave_agent" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_merlin_master_agent" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_master_agent" +set_global_assignment -entity "altera_merlin_master_agent" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "altera_merlin_master_agent" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_merlin_slave_translator" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_slave_translator" +set_global_assignment -entity "altera_merlin_slave_translator" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "altera_merlin_slave_translator" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "altera_merlin_master_translator" -library "nios_system" -name IP_TOOL_NAME "altera_merlin_master_translator" +set_global_assignment -entity "altera_merlin_master_translator" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "altera_merlin_master_translator" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_lcd_on" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "nios_system_lcd_on" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_lcd_on" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_lcd_16207_0" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_lcd_16207" +set_global_assignment -entity "nios_system_lcd_16207_0" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_lcd_16207_0" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_hex0" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "nios_system_hex0" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_hex0" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_push_switches" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "nios_system_push_switches" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_push_switches" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_switches" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "nios_system_switches" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_switches" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_LEDRs" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "nios_system_LEDRs" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_LEDRs" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_LEDs" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "nios_system_LEDs" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_LEDs" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_jtag_uart" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_jtag_uart" +set_global_assignment -entity "nios_system_jtag_uart" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_jtag_uart" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_onchip_memory" -library "nios_system" -name IP_TOOL_NAME "altera_avalon_onchip_memory2" +set_global_assignment -entity "nios_system_onchip_memory" -library "nios_system" -name IP_TOOL_VERSION "13.0.1.99.2" +set_global_assignment -entity "nios_system_onchip_memory" -library "nios_system" -name IP_TOOL_ENV "Qsys" +set_global_assignment -entity "nios_system_nios2_processor" -library "nios_system" -name IP_TOOL_NAME "altera_nios2_qsys" +set_global_assignment -entity "nios_system_nios2_processor" -library "nios_system" -name IP_TOOL_VERSION "13.0" +set_global_assignment -entity "nios_system_nios2_processor" -library "nios_system" -name IP_TOOL_ENV "Qsys" diff --git a/nios_system/synthesis/nios_system.v b/nios_system/synthesis/nios_system.v new file mode 100644 index 0000000..4626fed --- /dev/null +++ b/nios_system/synthesis/nios_system.v @@ -0,0 +1,5964 @@ +// nios_system.v + +// Generated using ACDS version 13.0sp1 232 at 2016.12.22.10:06:19 + +`timescale 1 ps / 1 ps +module nios_system ( + input wire clk_clk, // clk.clk + output wire [7:0] leds_export, // leds.export + input wire reset_reset_n, // reset.reset_n + output wire [17:0] ledrs_export, // ledrs.export + input wire [17:0] switches_export, // switches.export + input wire [2:0] push_switches_export, // push_switches.export + output wire [6:0] hex0_export, // hex0.export + output wire [6:0] hex1_export, // hex1.export + output wire [6:0] hex2_export, // hex2.export + output wire [6:0] hex3_export, // hex3.export + output wire [6:0] hex4_export, // hex4.export + output wire [6:0] hex5_export, // hex5.export + output wire [6:0] hex6_export, // hex6.export + output wire [6:0] hex7_export, // hex7.export + output wire lcd_16207_0_RS, // lcd_16207_0.RS + output wire lcd_16207_0_RW, // .RW + inout wire [7:0] lcd_16207_0_data, // .data + output wire lcd_16207_0_E, // .E + output wire lcd_on_export, // lcd_on.export + output wire lcd_blon_export // lcd_blon.export + ); + + wire nios2_processor_instruction_master_waitrequest; // nios2_processor_instruction_master_translator:av_waitrequest -> nios2_processor:i_waitrequest + wire [18:0] nios2_processor_instruction_master_address; // nios2_processor:i_address -> nios2_processor_instruction_master_translator:av_address + wire nios2_processor_instruction_master_read; // nios2_processor:i_read -> nios2_processor_instruction_master_translator:av_read + wire [31:0] nios2_processor_instruction_master_readdata; // nios2_processor_instruction_master_translator:av_readdata -> nios2_processor:i_readdata + wire nios2_processor_data_master_waitrequest; // nios2_processor_data_master_translator:av_waitrequest -> nios2_processor:d_waitrequest + wire [31:0] nios2_processor_data_master_writedata; // nios2_processor:d_writedata -> nios2_processor_data_master_translator:av_writedata + wire [18:0] nios2_processor_data_master_address; // nios2_processor:d_address -> nios2_processor_data_master_translator:av_address + wire nios2_processor_data_master_write; // nios2_processor:d_write -> nios2_processor_data_master_translator:av_write + wire nios2_processor_data_master_read; // nios2_processor:d_read -> nios2_processor_data_master_translator:av_read + wire [31:0] nios2_processor_data_master_readdata; // nios2_processor_data_master_translator:av_readdata -> nios2_processor:d_readdata + wire nios2_processor_data_master_debugaccess; // nios2_processor:jtag_debug_module_debugaccess_to_roms -> nios2_processor_data_master_translator:av_debugaccess + wire [3:0] nios2_processor_data_master_byteenable; // nios2_processor:d_byteenable -> nios2_processor_data_master_translator:av_byteenable + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_processor:jtag_debug_module_waitrequest -> nios2_processor_jtag_debug_module_translator:av_waitrequest + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_processor_jtag_debug_module_translator:av_writedata -> nios2_processor:jtag_debug_module_writedata + wire [8:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_processor_jtag_debug_module_translator:av_address -> nios2_processor:jtag_debug_module_address + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_processor_jtag_debug_module_translator:av_write -> nios2_processor:jtag_debug_module_write + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_processor_jtag_debug_module_translator:av_read -> nios2_processor:jtag_debug_module_read + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_processor:jtag_debug_module_readdata -> nios2_processor_jtag_debug_module_translator:av_readdata + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_processor_jtag_debug_module_translator:av_debugaccess -> nios2_processor:jtag_debug_module_debugaccess + wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_processor_jtag_debug_module_translator:av_byteenable -> nios2_processor:jtag_debug_module_byteenable + wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_s1_translator:av_writedata -> onchip_memory:writedata + wire [15:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // onchip_memory_s1_translator:av_address -> onchip_memory:address + wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_s1_translator:av_chipselect -> onchip_memory:chipselect + wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_s1_translator:av_clken -> onchip_memory:clken + wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // onchip_memory_s1_translator:av_write -> onchip_memory:write + wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory:readdata -> onchip_memory_s1_translator:av_readdata + wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_s1_translator:av_byteenable -> onchip_memory:byteenable + wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata + wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address + wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect + wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n + wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata + wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata + wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_writedata; // LEDRs_s1_translator:av_writedata -> LEDRs:writedata + wire [1:0] ledrs_s1_translator_avalon_anti_slave_0_address; // LEDRs_s1_translator:av_address -> LEDRs:address + wire ledrs_s1_translator_avalon_anti_slave_0_chipselect; // LEDRs_s1_translator:av_chipselect -> LEDRs:chipselect + wire ledrs_s1_translator_avalon_anti_slave_0_write; // LEDRs_s1_translator:av_write -> LEDRs:write_n + wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_readdata; // LEDRs:readdata -> LEDRs_s1_translator:av_readdata + wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address + wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata + wire [1:0] push_switches_s1_translator_avalon_anti_slave_0_address; // push_switches_s1_translator:av_address -> push_switches:address + wire [31:0] push_switches_s1_translator_avalon_anti_slave_0_readdata; // push_switches:readdata -> push_switches_s1_translator:av_readdata + wire [31:0] hex0_s1_translator_avalon_anti_slave_0_writedata; // hex0_s1_translator:av_writedata -> hex0:writedata + wire [1:0] hex0_s1_translator_avalon_anti_slave_0_address; // hex0_s1_translator:av_address -> hex0:address + wire hex0_s1_translator_avalon_anti_slave_0_chipselect; // hex0_s1_translator:av_chipselect -> hex0:chipselect + wire hex0_s1_translator_avalon_anti_slave_0_write; // hex0_s1_translator:av_write -> hex0:write_n + wire [31:0] hex0_s1_translator_avalon_anti_slave_0_readdata; // hex0:readdata -> hex0_s1_translator:av_readdata + wire [31:0] hex1_s1_translator_avalon_anti_slave_0_writedata; // hex1_s1_translator:av_writedata -> hex1:writedata + wire [1:0] hex1_s1_translator_avalon_anti_slave_0_address; // hex1_s1_translator:av_address -> hex1:address + wire hex1_s1_translator_avalon_anti_slave_0_chipselect; // hex1_s1_translator:av_chipselect -> hex1:chipselect + wire hex1_s1_translator_avalon_anti_slave_0_write; // hex1_s1_translator:av_write -> hex1:write_n + wire [31:0] hex1_s1_translator_avalon_anti_slave_0_readdata; // hex1:readdata -> hex1_s1_translator:av_readdata + wire [31:0] hex2_s1_translator_avalon_anti_slave_0_writedata; // hex2_s1_translator:av_writedata -> hex2:writedata + wire [1:0] hex2_s1_translator_avalon_anti_slave_0_address; // hex2_s1_translator:av_address -> hex2:address + wire hex2_s1_translator_avalon_anti_slave_0_chipselect; // hex2_s1_translator:av_chipselect -> hex2:chipselect + wire hex2_s1_translator_avalon_anti_slave_0_write; // hex2_s1_translator:av_write -> hex2:write_n + wire [31:0] hex2_s1_translator_avalon_anti_slave_0_readdata; // hex2:readdata -> hex2_s1_translator:av_readdata + wire [31:0] hex3_s1_translator_avalon_anti_slave_0_writedata; // hex3_s1_translator:av_writedata -> hex3:writedata + wire [1:0] hex3_s1_translator_avalon_anti_slave_0_address; // hex3_s1_translator:av_address -> hex3:address + wire hex3_s1_translator_avalon_anti_slave_0_chipselect; // hex3_s1_translator:av_chipselect -> hex3:chipselect + wire hex3_s1_translator_avalon_anti_slave_0_write; // hex3_s1_translator:av_write -> hex3:write_n + wire [31:0] hex3_s1_translator_avalon_anti_slave_0_readdata; // hex3:readdata -> hex3_s1_translator:av_readdata + wire [31:0] hex4_s1_translator_avalon_anti_slave_0_writedata; // hex4_s1_translator:av_writedata -> hex4:writedata + wire [1:0] hex4_s1_translator_avalon_anti_slave_0_address; // hex4_s1_translator:av_address -> hex4:address + wire hex4_s1_translator_avalon_anti_slave_0_chipselect; // hex4_s1_translator:av_chipselect -> hex4:chipselect + wire hex4_s1_translator_avalon_anti_slave_0_write; // hex4_s1_translator:av_write -> hex4:write_n + wire [31:0] hex4_s1_translator_avalon_anti_slave_0_readdata; // hex4:readdata -> hex4_s1_translator:av_readdata + wire [31:0] hex5_s1_translator_avalon_anti_slave_0_writedata; // hex5_s1_translator:av_writedata -> hex5:writedata + wire [1:0] hex5_s1_translator_avalon_anti_slave_0_address; // hex5_s1_translator:av_address -> hex5:address + wire hex5_s1_translator_avalon_anti_slave_0_chipselect; // hex5_s1_translator:av_chipselect -> hex5:chipselect + wire hex5_s1_translator_avalon_anti_slave_0_write; // hex5_s1_translator:av_write -> hex5:write_n + wire [31:0] hex5_s1_translator_avalon_anti_slave_0_readdata; // hex5:readdata -> hex5_s1_translator:av_readdata + wire [31:0] hex6_s1_translator_avalon_anti_slave_0_writedata; // hex6_s1_translator:av_writedata -> hex6:writedata + wire [1:0] hex6_s1_translator_avalon_anti_slave_0_address; // hex6_s1_translator:av_address -> hex6:address + wire hex6_s1_translator_avalon_anti_slave_0_chipselect; // hex6_s1_translator:av_chipselect -> hex6:chipselect + wire hex6_s1_translator_avalon_anti_slave_0_write; // hex6_s1_translator:av_write -> hex6:write_n + wire [31:0] hex6_s1_translator_avalon_anti_slave_0_readdata; // hex6:readdata -> hex6_s1_translator:av_readdata + wire [31:0] hex7_s1_translator_avalon_anti_slave_0_writedata; // hex7_s1_translator:av_writedata -> hex7:writedata + wire [1:0] hex7_s1_translator_avalon_anti_slave_0_address; // hex7_s1_translator:av_address -> hex7:address + wire hex7_s1_translator_avalon_anti_slave_0_chipselect; // hex7_s1_translator:av_chipselect -> hex7:chipselect + wire hex7_s1_translator_avalon_anti_slave_0_write; // hex7_s1_translator:av_write -> hex7:write_n + wire [31:0] hex7_s1_translator_avalon_anti_slave_0_readdata; // hex7:readdata -> hex7_s1_translator:av_readdata + wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata; // lcd_16207_0_control_slave_translator:av_writedata -> lcd_16207_0:writedata + wire [1:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address; // lcd_16207_0_control_slave_translator:av_address -> lcd_16207_0:address + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write; // lcd_16207_0_control_slave_translator:av_write -> lcd_16207_0:write + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read; // lcd_16207_0_control_slave_translator:av_read -> lcd_16207_0:read + wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata; // lcd_16207_0:readdata -> lcd_16207_0_control_slave_translator:av_readdata + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer; // lcd_16207_0_control_slave_translator:av_begintransfer -> lcd_16207_0:begintransfer + wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_writedata; // lcd_on_s1_translator:av_writedata -> lcd_on:writedata + wire [1:0] lcd_on_s1_translator_avalon_anti_slave_0_address; // lcd_on_s1_translator:av_address -> lcd_on:address + wire lcd_on_s1_translator_avalon_anti_slave_0_chipselect; // lcd_on_s1_translator:av_chipselect -> lcd_on:chipselect + wire lcd_on_s1_translator_avalon_anti_slave_0_write; // lcd_on_s1_translator:av_write -> lcd_on:write_n + wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_readdata; // lcd_on:readdata -> lcd_on_s1_translator:av_readdata + wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_writedata; // lcd_blon_s1_translator:av_writedata -> lcd_blon:writedata + wire [1:0] lcd_blon_s1_translator_avalon_anti_slave_0_address; // lcd_blon_s1_translator:av_address -> lcd_blon:address + wire lcd_blon_s1_translator_avalon_anti_slave_0_chipselect; // lcd_blon_s1_translator:av_chipselect -> lcd_blon:chipselect + wire lcd_blon_s1_translator_avalon_anti_slave_0_write; // lcd_blon_s1_translator:av_write -> lcd_blon:write_n + wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_readdata; // lcd_blon:readdata -> lcd_blon_s1_translator:av_readdata + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_instruction_master_translator:uav_waitrequest + wire [2:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_instruction_master_translator:uav_burstcount -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_processor_instruction_master_translator:uav_writedata -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_writedata + wire [18:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_address; // nios2_processor_instruction_master_translator:uav_address -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_address + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_lock; // nios2_processor_instruction_master_translator:uav_lock -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_lock + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_write; // nios2_processor_instruction_master_translator:uav_write -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_write + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_read; // nios2_processor_instruction_master_translator:uav_read -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_instruction_master_translator:uav_readdata + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_instruction_master_translator:uav_debugaccess -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_instruction_master_translator:uav_byteenable -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_instruction_master_translator:uav_readdatavalid + wire nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_data_master_translator:uav_waitrequest + wire [2:0] nios2_processor_data_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_data_master_translator:uav_burstcount -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_writedata; // nios2_processor_data_master_translator:uav_writedata -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_writedata + wire [18:0] nios2_processor_data_master_translator_avalon_universal_master_0_address; // nios2_processor_data_master_translator:uav_address -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_address + wire nios2_processor_data_master_translator_avalon_universal_master_0_lock; // nios2_processor_data_master_translator:uav_lock -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_lock + wire nios2_processor_data_master_translator_avalon_universal_master_0_write; // nios2_processor_data_master_translator:uav_write -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_write + wire nios2_processor_data_master_translator_avalon_universal_master_0_read; // nios2_processor_data_master_translator:uav_read -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_readdata; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_data_master_translator:uav_readdata + wire nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_data_master_translator:uav_debugaccess -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] nios2_processor_data_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_data_master_translator:uav_byteenable -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_byteenable + wire nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_data_master_translator:uav_readdatavalid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_processor_jtag_debug_module_translator:uav_waitrequest -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_processor_jtag_debug_module_translator:uav_burstcount + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_processor_jtag_debug_module_translator:uav_writedata + wire [18:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_processor_jtag_debug_module_translator:uav_address + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_processor_jtag_debug_module_translator:uav_write + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_processor_jtag_debug_module_translator:uav_lock + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_processor_jtag_debug_module_translator:uav_read + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_processor_jtag_debug_module_translator:uav_readdata -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_processor_jtag_debug_module_translator:uav_readdatavalid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_processor_jtag_debug_module_translator:uav_debugaccess + wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_processor_jtag_debug_module_translator:uav_byteenable + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount + wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata + wire [18:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_s1_translator:uav_address + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_s1_translator:uav_write + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_s1_translator:uav_lock + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_s1_translator:uav_read + wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess + wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount + wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata + wire [18:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read + wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess + wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata + wire [18:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess + wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDRs_s1_translator:uav_waitrequest -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDRs_s1_translator:uav_burstcount + wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDRs_s1_translator:uav_writedata + wire [18:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDRs_s1_translator:uav_address + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDRs_s1_translator:uav_write + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDRs_s1_translator:uav_lock + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDRs_s1_translator:uav_read + wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDRs_s1_translator:uav_readdata -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDRs_s1_translator:uav_readdatavalid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDRs_s1_translator:uav_debugaccess + wire [3:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDRs_s1_translator:uav_byteenable + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount + wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata + wire [18:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read + wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess + wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // push_switches_s1_translator:uav_waitrequest -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> push_switches_s1_translator:uav_burstcount + wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> push_switches_s1_translator:uav_writedata + wire [18:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> push_switches_s1_translator:uav_address + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> push_switches_s1_translator:uav_write + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> push_switches_s1_translator:uav_lock + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> push_switches_s1_translator:uav_read + wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // push_switches_s1_translator:uav_readdata -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // push_switches_s1_translator:uav_readdatavalid -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> push_switches_s1_translator:uav_debugaccess + wire [3:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> push_switches_s1_translator:uav_byteenable + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount + wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex0_s1_translator:uav_writedata + wire [18:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex0_s1_translator:uav_address + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex0_s1_translator:uav_write + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex0_s1_translator:uav_lock + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex0_s1_translator:uav_read + wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess + wire [3:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount + wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex1_s1_translator:uav_writedata + wire [18:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex1_s1_translator:uav_address + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex1_s1_translator:uav_write + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex1_s1_translator:uav_lock + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex1_s1_translator:uav_read + wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess + wire [3:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount + wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex2_s1_translator:uav_writedata + wire [18:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex2_s1_translator:uav_address + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex2_s1_translator:uav_write + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex2_s1_translator:uav_lock + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex2_s1_translator:uav_read + wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess + wire [3:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount + wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex3_s1_translator:uav_writedata + wire [18:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex3_s1_translator:uav_address + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex3_s1_translator:uav_write + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex3_s1_translator:uav_lock + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex3_s1_translator:uav_read + wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess + wire [3:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount + wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex4_s1_translator:uav_writedata + wire [18:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex4_s1_translator:uav_address + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex4_s1_translator:uav_write + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex4_s1_translator:uav_lock + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex4_s1_translator:uav_read + wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess + wire [3:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount + wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex5_s1_translator:uav_writedata + wire [18:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex5_s1_translator:uav_address + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex5_s1_translator:uav_write + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex5_s1_translator:uav_lock + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex5_s1_translator:uav_read + wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess + wire [3:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex6_s1_translator:uav_waitrequest -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex6_s1_translator:uav_burstcount + wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex6_s1_translator:uav_writedata + wire [18:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex6_s1_translator:uav_address + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex6_s1_translator:uav_write + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex6_s1_translator:uav_lock + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex6_s1_translator:uav_read + wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex6_s1_translator:uav_readdata -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex6_s1_translator:uav_readdatavalid -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex6_s1_translator:uav_debugaccess + wire [3:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex6_s1_translator:uav_byteenable + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex7_s1_translator:uav_waitrequest -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex7_s1_translator:uav_burstcount + wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex7_s1_translator:uav_writedata + wire [18:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex7_s1_translator:uav_address + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex7_s1_translator:uav_write + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex7_s1_translator:uav_lock + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex7_s1_translator:uav_read + wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex7_s1_translator:uav_readdata -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex7_s1_translator:uav_readdatavalid -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex7_s1_translator:uav_debugaccess + wire [3:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex7_s1_translator:uav_byteenable + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_16207_0_control_slave_translator:uav_waitrequest -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_16207_0_control_slave_translator:uav_burstcount + wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_16207_0_control_slave_translator:uav_writedata + wire [18:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> lcd_16207_0_control_slave_translator:uav_address + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> lcd_16207_0_control_slave_translator:uav_write + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_16207_0_control_slave_translator:uav_lock + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> lcd_16207_0_control_slave_translator:uav_read + wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_16207_0_control_slave_translator:uav_readdata -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_16207_0_control_slave_translator:uav_readdatavalid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_16207_0_control_slave_translator:uav_debugaccess + wire [3:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_16207_0_control_slave_translator:uav_byteenable + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_on_s1_translator:uav_waitrequest -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_on_s1_translator:uav_burstcount + wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_on_s1_translator:uav_writedata + wire [18:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_on_s1_translator:uav_address + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_on_s1_translator:uav_write + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_on_s1_translator:uav_lock + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_on_s1_translator:uav_read + wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_on_s1_translator:uav_readdata -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_on_s1_translator:uav_readdatavalid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_on_s1_translator:uav_debugaccess + wire [3:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_on_s1_translator:uav_byteenable + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_blon_s1_translator:uav_waitrequest -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_blon_s1_translator:uav_burstcount + wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_blon_s1_translator:uav_writedata + wire [18:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_blon_s1_translator:uav_address + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_blon_s1_translator:uav_write + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_blon_s1_translator:uav_lock + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_blon_s1_translator:uav_read + wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_blon_s1_translator:uav_readdata -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_blon_s1_translator:uav_readdatavalid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_blon_s1_translator:uav_debugaccess + wire [3:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_blon_s1_translator:uav_byteenable + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket + wire [95:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_ready + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket + wire [95:0] nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket + wire [95:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket + wire [95:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket + wire [95:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket + wire [95:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket + wire [95:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket + wire [95:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket + wire [95:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket + wire [95:0] hex0_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket + wire [95:0] hex1_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket + wire [95:0] hex2_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket + wire [95:0] hex3_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket + wire [95:0] hex4_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket + wire [95:0] hex5_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket + wire [95:0] hex6_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket + wire [95:0] hex7_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket + wire [95:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket + wire [95:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket + wire [95:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_017:sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDRs:reset_n, LEDRs_s1_translator:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, hex0:reset_n, hex0_s1_translator:reset, hex0_s1_translator_avalon_universal_slave_0_agent:reset, hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex1:reset_n, hex1_s1_translator:reset, hex1_s1_translator_avalon_universal_slave_0_agent:reset, hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex2:reset_n, hex2_s1_translator:reset, hex2_s1_translator_avalon_universal_slave_0_agent:reset, hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex3:reset_n, hex3_s1_translator:reset, hex3_s1_translator_avalon_universal_slave_0_agent:reset, hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex4:reset_n, hex4_s1_translator:reset, hex4_s1_translator_avalon_universal_slave_0_agent:reset, hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex5:reset_n, hex5_s1_translator:reset, hex5_s1_translator_avalon_universal_slave_0_agent:reset, hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex6:reset_n, hex6_s1_translator:reset, hex6_s1_translator_avalon_universal_slave_0_agent:reset, hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex7:reset_n, hex7_s1_translator:reset, hex7_s1_translator_avalon_universal_slave_0_agent:reset, hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, irq_mapper:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_16207_0:reset_n, lcd_16207_0_control_slave_translator:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_blon:reset_n, lcd_blon_s1_translator:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_on:reset_n, lcd_on_s1_translator:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_processor:reset_n, nios2_processor_data_master_translator:reset, nios2_processor_data_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_instruction_master_translator:reset, nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_jtag_debug_module_translator:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory:reset, onchip_memory_s1_translator:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, push_switches:reset_n, push_switches_s1_translator:reset, push_switches_s1_translator_avalon_universal_slave_0_agent:reset, push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset] + wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory:reset_req + wire nios2_processor_jtag_debug_module_reset_reset; // nios2_processor:jtag_debug_module_resetrequest -> rst_controller:reset_in1 + wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket + wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid + wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket + wire [95:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data + wire [17:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel + wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready + wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket + wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid + wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket + wire [95:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data + wire [17:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel + wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready + wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket + wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid + wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket + wire [95:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data + wire [17:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel + wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready + wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket + wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid + wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket + wire [95:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data + wire [17:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel + wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready + wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src13_endofpacket; // cmd_xbar_demux_001:src13_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src13_valid; // cmd_xbar_demux_001:src13_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src13_startofpacket; // cmd_xbar_demux_001:src13_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src13_data; // cmd_xbar_demux_001:src13_data -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src13_channel; // cmd_xbar_demux_001:src13_channel -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src14_endofpacket; // cmd_xbar_demux_001:src14_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src14_valid; // cmd_xbar_demux_001:src14_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src14_startofpacket; // cmd_xbar_demux_001:src14_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src14_data; // cmd_xbar_demux_001:src14_data -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src14_channel; // cmd_xbar_demux_001:src14_channel -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src15_endofpacket; // cmd_xbar_demux_001:src15_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src15_valid; // cmd_xbar_demux_001:src15_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src15_startofpacket; // cmd_xbar_demux_001:src15_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src15_data; // cmd_xbar_demux_001:src15_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src15_channel; // cmd_xbar_demux_001:src15_channel -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src16_endofpacket; // cmd_xbar_demux_001:src16_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src16_valid; // cmd_xbar_demux_001:src16_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src16_startofpacket; // cmd_xbar_demux_001:src16_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src16_data; // cmd_xbar_demux_001:src16_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src16_channel; // cmd_xbar_demux_001:src16_channel -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src17_endofpacket; // cmd_xbar_demux_001:src17_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src17_valid; // cmd_xbar_demux_001:src17_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src17_startofpacket; // cmd_xbar_demux_001:src17_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src17_data; // cmd_xbar_demux_001:src17_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src17_channel; // cmd_xbar_demux_001:src17_channel -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket + wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid + wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket + wire [95:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data + wire [17:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel + wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready + wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket + wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid + wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket + wire [95:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data + wire [17:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel + wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready + wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket + wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid + wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket + wire [95:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data + wire [17:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel + wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready + wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket + wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid + wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket + wire [95:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data + wire [17:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel + wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready + wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket + wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid + wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket + wire [95:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data + wire [17:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel + wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready + wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket + wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid + wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket + wire [95:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data + wire [17:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel + wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready + wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket + wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid + wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket + wire [95:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data + wire [17:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel + wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready + wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket + wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid + wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket + wire [95:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data + wire [17:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel + wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready + wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket + wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid + wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket + wire [95:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data + wire [17:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel + wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready + wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket + wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid + wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket + wire [95:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data + wire [17:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel + wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready + wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket + wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid + wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket + wire [95:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data + wire [17:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel + wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready + wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket + wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid + wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket + wire [95:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data + wire [17:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel + wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready + wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket + wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid + wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket + wire [95:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data + wire [17:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel + wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready + wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket + wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid + wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket + wire [95:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data + wire [17:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel + wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready + wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket + wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid + wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket + wire [95:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data + wire [17:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel + wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready + wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_001:sink13_endofpacket + wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_001:sink13_valid + wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_001:sink13_startofpacket + wire [95:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_001:sink13_data + wire [17:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_001:sink13_channel + wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_001:sink13_ready -> rsp_xbar_demux_013:src0_ready + wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_001:sink14_endofpacket + wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_001:sink14_valid + wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_001:sink14_startofpacket + wire [95:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_001:sink14_data + wire [17:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_001:sink14_channel + wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_001:sink14_ready -> rsp_xbar_demux_014:src0_ready + wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_001:sink15_endofpacket + wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_001:sink15_valid + wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_001:sink15_startofpacket + wire [95:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_001:sink15_data + wire [17:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_001:sink15_channel + wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_001:sink15_ready -> rsp_xbar_demux_015:src0_ready + wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_001:sink16_endofpacket + wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_001:sink16_valid + wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_001:sink16_startofpacket + wire [95:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_001:sink16_data + wire [17:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_001:sink16_channel + wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_001:sink16_ready -> rsp_xbar_demux_016:src0_ready + wire rsp_xbar_demux_017_src0_endofpacket; // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_001:sink17_endofpacket + wire rsp_xbar_demux_017_src0_valid; // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_001:sink17_valid + wire rsp_xbar_demux_017_src0_startofpacket; // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_001:sink17_startofpacket + wire [95:0] rsp_xbar_demux_017_src0_data; // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_001:sink17_data + wire [17:0] rsp_xbar_demux_017_src0_channel; // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_001:sink17_channel + wire rsp_xbar_demux_017_src0_ready; // rsp_xbar_mux_001:sink17_ready -> rsp_xbar_demux_017:src0_ready + wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket + wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid + wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket + wire [95:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data + wire [17:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel + wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready + wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_valid + wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [95:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_data + wire [17:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_channel + wire rsp_xbar_mux_src_ready; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready + wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket + wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid + wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket + wire [95:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data + wire [17:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel + wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready + wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_valid + wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [95:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_data + wire [17:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_channel + wire rsp_xbar_mux_001_src_ready; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready + wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready + wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket + wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid + wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket + wire [95:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data + wire [17:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel + wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready + wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_001_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready + wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket + wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid + wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket + wire [95:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data + wire [17:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel + wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready + wire cmd_xbar_demux_001_src2_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready + wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket + wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid + wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket + wire [95:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data + wire [17:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel + wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready + wire cmd_xbar_demux_001_src3_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready + wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket + wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid + wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket + wire [95:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data + wire [17:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel + wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready + wire cmd_xbar_demux_001_src4_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready + wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket + wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid + wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket + wire [95:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data + wire [17:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel + wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready + wire cmd_xbar_demux_001_src5_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready + wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket + wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid + wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket + wire [95:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data + wire [17:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel + wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready + wire cmd_xbar_demux_001_src6_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready + wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket + wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid + wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket + wire [95:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data + wire [17:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel + wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready + wire cmd_xbar_demux_001_src7_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready + wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket + wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid + wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket + wire [95:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data + wire [17:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel + wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready + wire cmd_xbar_demux_001_src8_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready + wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket + wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid + wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket + wire [95:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data + wire [17:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel + wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready + wire cmd_xbar_demux_001_src9_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready + wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket + wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid + wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket + wire [95:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data + wire [17:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel + wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready + wire cmd_xbar_demux_001_src10_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready + wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket + wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid + wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket + wire [95:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data + wire [17:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel + wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready + wire cmd_xbar_demux_001_src11_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready + wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket + wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid + wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket + wire [95:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data + wire [17:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel + wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready + wire cmd_xbar_demux_001_src12_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready + wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket + wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid + wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket + wire [95:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data + wire [17:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel + wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready + wire cmd_xbar_demux_001_src13_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src13_ready + wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket + wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid + wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket + wire [95:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data + wire [17:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel + wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready + wire cmd_xbar_demux_001_src14_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src14_ready + wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket + wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid + wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket + wire [95:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data + wire [17:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel + wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready + wire cmd_xbar_demux_001_src15_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src15_ready + wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket + wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid + wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket + wire [95:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data + wire [17:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel + wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready + wire cmd_xbar_demux_001_src16_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src16_ready + wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket + wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid + wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket + wire [95:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data + wire [17:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel + wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready + wire cmd_xbar_demux_001_src17_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src17_ready + wire id_router_017_src_endofpacket; // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket + wire id_router_017_src_valid; // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid + wire id_router_017_src_startofpacket; // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket + wire [95:0] id_router_017_src_data; // id_router_017:src_data -> rsp_xbar_demux_017:sink_data + wire [17:0] id_router_017_src_channel; // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel + wire id_router_017_src_ready; // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready + wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq + wire [31:0] nios2_processor_d_irq_irq; // irq_mapper:sender_irq -> nios2_processor:d_irq + + nios_system_nios2_processor nios2_processor ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n + .d_address (nios2_processor_data_master_address), // data_master.address + .d_byteenable (nios2_processor_data_master_byteenable), // .byteenable + .d_read (nios2_processor_data_master_read), // .read + .d_readdata (nios2_processor_data_master_readdata), // .readdata + .d_waitrequest (nios2_processor_data_master_waitrequest), // .waitrequest + .d_write (nios2_processor_data_master_write), // .write + .d_writedata (nios2_processor_data_master_writedata), // .writedata + .jtag_debug_module_debugaccess_to_roms (nios2_processor_data_master_debugaccess), // .debugaccess + .i_address (nios2_processor_instruction_master_address), // instruction_master.address + .i_read (nios2_processor_instruction_master_read), // .read + .i_readdata (nios2_processor_instruction_master_readdata), // .readdata + .i_waitrequest (nios2_processor_instruction_master_waitrequest), // .waitrequest + .d_irq (nios2_processor_d_irq_irq), // d_irq.irq + .jtag_debug_module_resetrequest (nios2_processor_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset + .jtag_debug_module_address (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address + .jtag_debug_module_byteenable (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable + .jtag_debug_module_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess + .jtag_debug_module_read (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read + .jtag_debug_module_readdata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata + .jtag_debug_module_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .jtag_debug_module_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write + .jtag_debug_module_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata + .no_ci_readra () // custom_instruction_master.readra + ); + + nios_system_onchip_memory onchip_memory ( + .clk (clk_clk), // clk1.clk + .address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // s1.address + .clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken + .chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write + .readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable + .reset (rst_controller_reset_out_reset), // reset1.reset + .reset_req (rst_controller_reset_out_reset_req) // .reset_req + ); + + nios_system_jtag_uart jtag_uart ( + .clk (clk_clk), // clk.clk + .rst_n (~rst_controller_reset_out_reset), // reset.reset_n + .av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect + .av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address + .av_read_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n + .av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write_n (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n + .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_irq (irq_mapper_receiver0_irq) // irq.irq + ); + + nios_system_LEDs leds ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (leds_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~leds_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (leds_export) // external_connection.export + ); + + nios_system_LEDRs ledrs ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (ledrs_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~ledrs_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (ledrs_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (ledrs_export) // external_connection.export + ); + + nios_system_switches switches ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (switches_s1_translator_avalon_anti_slave_0_address), // s1.address + .readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .in_port (switches_export) // external_connection.export + ); + + nios_system_push_switches push_switches ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (push_switches_s1_translator_avalon_anti_slave_0_address), // s1.address + .readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .in_port (push_switches_export) // external_connection.export + ); + + nios_system_hex0 hex0 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex0_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex0_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex0_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex0_export) // external_connection.export + ); + + nios_system_hex0 hex1 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex1_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex1_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex1_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex1_export) // external_connection.export + ); + + nios_system_hex0 hex2 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex2_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex2_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex2_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex2_export) // external_connection.export + ); + + nios_system_hex0 hex3 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex3_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex3_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex3_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex3_export) // external_connection.export + ); + + nios_system_hex0 hex4 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex4_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex4_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex4_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex4_export) // external_connection.export + ); + + nios_system_hex0 hex5 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex5_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex5_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex5_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex5_export) // external_connection.export + ); + + nios_system_hex0 hex6 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex6_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex6_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex6_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex6_export) // external_connection.export + ); + + nios_system_hex0 hex7 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (hex7_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~hex7_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (hex7_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (hex7_export) // external_connection.export + ); + + nios_system_lcd_16207_0 lcd_16207_0 ( + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .clk (clk_clk), // clk.clk + .begintransfer (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer), // control_slave.begintransfer + .read (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read), // .read + .write (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write), // .write + .readdata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .writedata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .address (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address), // .address + .LCD_RS (lcd_16207_0_RS), // external.export + .LCD_RW (lcd_16207_0_RW), // .export + .LCD_data (lcd_16207_0_data), // .export + .LCD_E (lcd_16207_0_E) // .export + ); + + nios_system_lcd_on lcd_on ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (lcd_on_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~lcd_on_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (lcd_on_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (lcd_on_export) // external_connection.export + ); + + nios_system_lcd_on lcd_blon ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (lcd_blon_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~lcd_blon_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (lcd_blon_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (lcd_blon_export) // external_connection.export + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (19), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (0), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (1), + .AV_REGISTERINCOMINGSIGNALS (0) + ) nios2_processor_instruction_master_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (nios2_processor_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (nios2_processor_instruction_master_translator_avalon_universal_master_0_read), // .read + .uav_write (nios2_processor_instruction_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (nios2_processor_instruction_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (nios2_processor_instruction_master_address), // avalon_anti_master_0.address + .av_waitrequest (nios2_processor_instruction_master_waitrequest), // .waitrequest + .av_read (nios2_processor_instruction_master_read), // .read + .av_readdata (nios2_processor_instruction_master_readdata), // .readdata + .av_burstcount (1'b1), // (terminated) + .av_byteenable (4'b1111), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_readdatavalid (), // (terminated) + .av_write (1'b0), // (terminated) + .av_writedata (32'b00000000000000000000000000000000), // (terminated) + .av_lock (1'b0), // (terminated) + .av_debugaccess (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponserequest (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponserequest (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (19), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (1) + ) nios2_processor_data_master_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (nios2_processor_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (nios2_processor_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (nios2_processor_data_master_translator_avalon_universal_master_0_read), // .read + .uav_write (nios2_processor_data_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (nios2_processor_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (nios2_processor_data_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (nios2_processor_data_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (nios2_processor_data_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (nios2_processor_data_master_address), // avalon_anti_master_0.address + .av_waitrequest (nios2_processor_data_master_waitrequest), // .waitrequest + .av_byteenable (nios2_processor_data_master_byteenable), // .byteenable + .av_read (nios2_processor_data_master_read), // .read + .av_readdata (nios2_processor_data_master_readdata), // .readdata + .av_write (nios2_processor_data_master_write), // .write + .av_writedata (nios2_processor_data_master_writedata), // .writedata + .av_debugaccess (nios2_processor_data_master_debugaccess), // .debugaccess + .av_burstcount (1'b1), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_readdatavalid (), // (terminated) + .av_lock (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponserequest (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponserequest (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (9), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) nios2_processor_jtag_debug_module_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write + .av_read (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read + .av_readdata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata + .av_byteenable (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable + .av_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (16), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) onchip_memory_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable + .av_chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) leds_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (leds_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (leds_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (1), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) jtag_uart_avalon_jtag_slave_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write + .av_read (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read + .av_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_chipselect (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) ledrs_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (ledrs_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (ledrs_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (ledrs_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) switches_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write (), // (terminated) + .av_read (), // (terminated) + .av_writedata (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) push_switches_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (push_switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write (), // (terminated) + .av_read (), // (terminated) + .av_writedata (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex0_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex0_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex0_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex1_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex1_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex1_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex2_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex2_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex2_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex2_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex2_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex2_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex2_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex3_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex3_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex3_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex3_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex3_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex3_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex3_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex4_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex4_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex4_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex4_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex4_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex4_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex4_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex5_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex5_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex5_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex5_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex5_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex5_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex5_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex6_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex6_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex6_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex6_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex6_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex6_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex6_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) hex7_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (hex7_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (hex7_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (hex7_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (hex7_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (hex7_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (hex7_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (8), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (13), + .AV_WRITE_WAIT_CYCLES (13), + .AV_SETUP_WAIT_CYCLES (13), + .AV_DATA_HOLD_CYCLES (13) + ) lcd_16207_0_control_slave_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write), // .write + .av_read (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read), // .read + .av_readdata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_begintransfer (lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer), // .begintransfer + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) lcd_on_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (lcd_on_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (lcd_on_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (lcd_on_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) lcd_blon_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (lcd_blon_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (lcd_blon_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (lcd_blon_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponserequest (1'b0), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponserequest (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_BEGIN_BURST (74), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .PKT_BURST_TYPE_H (71), + .PKT_BURST_TYPE_L (70), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_TRANS_EXCLUSIVE (60), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_THREAD_ID_H (86), + .PKT_THREAD_ID_L (86), + .PKT_CACHE_H (93), + .PKT_CACHE_L (90), + .PKT_DATA_SIDEBAND_H (73), + .PKT_DATA_SIDEBAND_L (73), + .PKT_QOS_H (75), + .PKT_QOS_L (75), + .PKT_ADDR_SIDEBAND_H (72), + .PKT_ADDR_SIDEBAND_L (72), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .ST_DATA_W (96), + .ST_CHANNEL_W (18), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (1), + .BURSTWRAP_VALUE (3), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .av_address (nios2_processor_instruction_master_translator_avalon_universal_master_0_address), // av.address + .av_write (nios2_processor_instruction_master_translator_avalon_universal_master_0_write), // .write + .av_read (nios2_processor_instruction_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (nios2_processor_instruction_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid + .cp_data (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .cp_startofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .cp_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready + .rp_valid (rsp_xbar_mux_src_valid), // rp.valid + .rp_data (rsp_xbar_mux_src_data), // .data + .rp_channel (rsp_xbar_mux_src_channel), // .channel + .rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket + .rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket + .rp_ready (rsp_xbar_mux_src_ready), // .ready + .av_response (), // (terminated) + .av_writeresponserequest (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_BEGIN_BURST (74), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .PKT_BURST_TYPE_H (71), + .PKT_BURST_TYPE_L (70), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_TRANS_EXCLUSIVE (60), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_THREAD_ID_H (86), + .PKT_THREAD_ID_L (86), + .PKT_CACHE_H (93), + .PKT_CACHE_L (90), + .PKT_DATA_SIDEBAND_H (73), + .PKT_DATA_SIDEBAND_L (73), + .PKT_QOS_H (75), + .PKT_QOS_L (75), + .PKT_ADDR_SIDEBAND_H (72), + .PKT_ADDR_SIDEBAND_L (72), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .ST_DATA_W (96), + .ST_CHANNEL_W (18), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (0), + .BURSTWRAP_VALUE (7), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) nios2_processor_data_master_translator_avalon_universal_master_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .av_address (nios2_processor_data_master_translator_avalon_universal_master_0_address), // av.address + .av_write (nios2_processor_data_master_translator_avalon_universal_master_0_write), // .write + .av_read (nios2_processor_data_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (nios2_processor_data_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (nios2_processor_data_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (nios2_processor_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (nios2_processor_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (nios2_processor_data_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid + .cp_data (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .cp_startofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .cp_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready + .rp_valid (rsp_xbar_mux_001_src_valid), // rp.valid + .rp_data (rsp_xbar_mux_001_src_data), // .data + .rp_channel (rsp_xbar_mux_001_src_channel), // .channel + .rp_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket + .rp_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket + .rp_ready (rsp_xbar_mux_001_src_ready), // .ready + .av_response (), // (terminated) + .av_writeresponserequest (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_mux_src_ready), // cp.ready + .cp_valid (cmd_xbar_mux_src_valid), // .valid + .cp_data (cmd_xbar_mux_src_data), // .data + .cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_mux_src_channel), // .channel + .rf_sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) onchip_memory_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready + .cp_valid (cmd_xbar_mux_001_src_valid), // .valid + .cp_data (cmd_xbar_mux_001_src_data), // .data + .cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_mux_001_src_channel), // .channel + .rf_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) leds_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src2_valid), // .valid + .cp_data (cmd_xbar_demux_001_src2_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src2_channel), // .channel + .rf_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src3_valid), // .valid + .cp_data (cmd_xbar_demux_001_src3_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src3_channel), // .channel + .rf_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) ledrs_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src4_valid), // .valid + .cp_data (cmd_xbar_demux_001_src4_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src4_channel), // .channel + .rf_sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) switches_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src5_valid), // .valid + .cp_data (cmd_xbar_demux_001_src5_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src5_channel), // .channel + .rf_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) push_switches_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src6_valid), // .valid + .cp_data (cmd_xbar_demux_001_src6_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src6_channel), // .channel + .rf_sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex0_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src7_valid), // .valid + .cp_data (cmd_xbar_demux_001_src7_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src7_channel), // .channel + .rf_sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex1_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src8_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src8_valid), // .valid + .cp_data (cmd_xbar_demux_001_src8_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src8_channel), // .channel + .rf_sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex2_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex2_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex2_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex2_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex2_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src9_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src9_valid), // .valid + .cp_data (cmd_xbar_demux_001_src9_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src9_channel), // .channel + .rf_sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex3_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex3_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex3_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex3_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex3_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src10_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src10_valid), // .valid + .cp_data (cmd_xbar_demux_001_src10_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src10_channel), // .channel + .rf_sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex4_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex4_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex4_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex4_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex4_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src11_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src11_valid), // .valid + .cp_data (cmd_xbar_demux_001_src11_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src11_channel), // .channel + .rf_sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex5_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex5_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex5_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex5_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex5_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src12_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src12_valid), // .valid + .cp_data (cmd_xbar_demux_001_src12_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src12_channel), // .channel + .rf_sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex6_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex6_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex6_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex6_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex6_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src13_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src13_valid), // .valid + .cp_data (cmd_xbar_demux_001_src13_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src13_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src13_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src13_channel), // .channel + .rf_sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) hex7_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (hex7_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (hex7_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (hex7_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (hex7_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src14_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src14_valid), // .valid + .cp_data (cmd_xbar_demux_001_src14_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src14_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src14_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src14_channel), // .channel + .rf_sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src15_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src15_valid), // .valid + .cp_data (cmd_xbar_demux_001_src15_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src15_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src15_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src15_channel), // .channel + .rf_sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) lcd_on_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src16_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src16_valid), // .valid + .cp_data (cmd_xbar_demux_001_src16_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src16_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src16_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src16_channel), // .channel + .rf_sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) + ) lcd_blon_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src17_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src17_valid), // .valid + .cp_data (cmd_xbar_demux_001_src17_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src17_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src17_channel), // .channel + .rf_sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .m0_response (2'b00), // (terminated) + .m0_writeresponserequest (), // (terminated) + .m0_writeresponsevalid (1'b0) // (terminated) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + nios_system_addr_router addr_router ( + .sink_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready + .sink_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid + .sink_data (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .sink_startofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (addr_router_src_ready), // src.ready + .src_valid (addr_router_src_valid), // .valid + .src_data (addr_router_src_data), // .data + .src_channel (addr_router_src_channel), // .channel + .src_startofpacket (addr_router_src_startofpacket), // .startofpacket + .src_endofpacket (addr_router_src_endofpacket) // .endofpacket + ); + + nios_system_addr_router_001 addr_router_001 ( + .sink_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready + .sink_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid + .sink_data (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .sink_startofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (addr_router_001_src_ready), // src.ready + .src_valid (addr_router_001_src_valid), // .valid + .src_data (addr_router_001_src_data), // .data + .src_channel (addr_router_001_src_channel), // .channel + .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket + .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket + ); + + nios_system_id_router id_router ( + .sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_src_ready), // src.ready + .src_valid (id_router_src_valid), // .valid + .src_data (id_router_src_data), // .data + .src_channel (id_router_src_channel), // .channel + .src_startofpacket (id_router_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_src_endofpacket) // .endofpacket + ); + + nios_system_id_router id_router_001 ( + .sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_001_src_ready), // src.ready + .src_valid (id_router_001_src_valid), // .valid + .src_data (id_router_001_src_data), // .data + .src_channel (id_router_001_src_channel), // .channel + .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_002 ( + .sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_002_src_ready), // src.ready + .src_valid (id_router_002_src_valid), // .valid + .src_data (id_router_002_src_data), // .data + .src_channel (id_router_002_src_channel), // .channel + .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_003 ( + .sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_003_src_ready), // src.ready + .src_valid (id_router_003_src_valid), // .valid + .src_data (id_router_003_src_data), // .data + .src_channel (id_router_003_src_channel), // .channel + .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_004 ( + .sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_004_src_ready), // src.ready + .src_valid (id_router_004_src_valid), // .valid + .src_data (id_router_004_src_data), // .data + .src_channel (id_router_004_src_channel), // .channel + .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_005 ( + .sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_005_src_ready), // src.ready + .src_valid (id_router_005_src_valid), // .valid + .src_data (id_router_005_src_data), // .data + .src_channel (id_router_005_src_channel), // .channel + .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_006 ( + .sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_006_src_ready), // src.ready + .src_valid (id_router_006_src_valid), // .valid + .src_data (id_router_006_src_data), // .data + .src_channel (id_router_006_src_channel), // .channel + .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_007 ( + .sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_007_src_ready), // src.ready + .src_valid (id_router_007_src_valid), // .valid + .src_data (id_router_007_src_data), // .data + .src_channel (id_router_007_src_channel), // .channel + .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_008 ( + .sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_008_src_ready), // src.ready + .src_valid (id_router_008_src_valid), // .valid + .src_data (id_router_008_src_data), // .data + .src_channel (id_router_008_src_channel), // .channel + .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_009 ( + .sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex2_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_009_src_ready), // src.ready + .src_valid (id_router_009_src_valid), // .valid + .src_data (id_router_009_src_data), // .data + .src_channel (id_router_009_src_channel), // .channel + .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_010 ( + .sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex3_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_010_src_ready), // src.ready + .src_valid (id_router_010_src_valid), // .valid + .src_data (id_router_010_src_data), // .data + .src_channel (id_router_010_src_channel), // .channel + .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_011 ( + .sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex4_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_011_src_ready), // src.ready + .src_valid (id_router_011_src_valid), // .valid + .src_data (id_router_011_src_data), // .data + .src_channel (id_router_011_src_channel), // .channel + .src_startofpacket (id_router_011_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_011_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_012 ( + .sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex5_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_012_src_ready), // src.ready + .src_valid (id_router_012_src_valid), // .valid + .src_data (id_router_012_src_data), // .data + .src_channel (id_router_012_src_channel), // .channel + .src_startofpacket (id_router_012_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_012_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_013 ( + .sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex6_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_013_src_ready), // src.ready + .src_valid (id_router_013_src_valid), // .valid + .src_data (id_router_013_src_data), // .data + .src_channel (id_router_013_src_channel), // .channel + .src_startofpacket (id_router_013_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_013_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_014 ( + .sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (hex7_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_014_src_ready), // src.ready + .src_valid (id_router_014_src_valid), // .valid + .src_data (id_router_014_src_data), // .data + .src_channel (id_router_014_src_channel), // .channel + .src_startofpacket (id_router_014_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_014_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_015 ( + .sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_015_src_ready), // src.ready + .src_valid (id_router_015_src_valid), // .valid + .src_data (id_router_015_src_data), // .data + .src_channel (id_router_015_src_channel), // .channel + .src_startofpacket (id_router_015_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_015_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_016 ( + .sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_016_src_ready), // src.ready + .src_valid (id_router_016_src_valid), // .valid + .src_data (id_router_016_src_data), // .data + .src_channel (id_router_016_src_channel), // .channel + .src_startofpacket (id_router_016_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_016_src_endofpacket) // .endofpacket + ); + + nios_system_id_router_002 id_router_017 ( + .sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_017_src_ready), // src.ready + .src_valid (id_router_017_src_valid), // .valid + .src_data (id_router_017_src_data), // .data + .src_channel (id_router_017_src_channel), // .channel + .src_startofpacket (id_router_017_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_017_src_endofpacket) // .endofpacket + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (2), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (1) + ) rst_controller ( + .reset_in0 (~reset_reset_n), // reset_in0.reset + .reset_in1 (nios2_processor_jtag_debug_module_reset_reset), // reset_in1.reset + .clk (clk_clk), // clk.clk + .reset_out (rst_controller_reset_out_reset), // reset_out.reset + .reset_req (rst_controller_reset_out_reset_req), // .reset_req + .reset_in2 (1'b0), // (terminated) + .reset_in3 (1'b0), // (terminated) + .reset_in4 (1'b0), // (terminated) + .reset_in5 (1'b0), // (terminated) + .reset_in6 (1'b0), // (terminated) + .reset_in7 (1'b0), // (terminated) + .reset_in8 (1'b0), // (terminated) + .reset_in9 (1'b0), // (terminated) + .reset_in10 (1'b0), // (terminated) + .reset_in11 (1'b0), // (terminated) + .reset_in12 (1'b0), // (terminated) + .reset_in13 (1'b0), // (terminated) + .reset_in14 (1'b0), // (terminated) + .reset_in15 (1'b0) // (terminated) + ); + + nios_system_cmd_xbar_demux cmd_xbar_demux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (addr_router_src_ready), // sink.ready + .sink_channel (addr_router_src_channel), // .channel + .sink_data (addr_router_src_data), // .data + .sink_startofpacket (addr_router_src_startofpacket), // .startofpacket + .sink_endofpacket (addr_router_src_endofpacket), // .endofpacket + .sink_valid (addr_router_src_valid), // .valid + .src0_ready (cmd_xbar_demux_src0_ready), // src0.ready + .src0_valid (cmd_xbar_demux_src0_valid), // .valid + .src0_data (cmd_xbar_demux_src0_data), // .data + .src0_channel (cmd_xbar_demux_src0_channel), // .channel + .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket + .src1_ready (cmd_xbar_demux_src1_ready), // src1.ready + .src1_valid (cmd_xbar_demux_src1_valid), // .valid + .src1_data (cmd_xbar_demux_src1_data), // .data + .src1_channel (cmd_xbar_demux_src1_channel), // .channel + .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_demux_001 cmd_xbar_demux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (addr_router_001_src_ready), // sink.ready + .sink_channel (addr_router_001_src_channel), // .channel + .sink_data (addr_router_001_src_data), // .data + .sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket + .sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket + .sink_valid (addr_router_001_src_valid), // .valid + .src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready + .src0_valid (cmd_xbar_demux_001_src0_valid), // .valid + .src0_data (cmd_xbar_demux_001_src0_data), // .data + .src0_channel (cmd_xbar_demux_001_src0_channel), // .channel + .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket + .src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready + .src1_valid (cmd_xbar_demux_001_src1_valid), // .valid + .src1_data (cmd_xbar_demux_001_src1_data), // .data + .src1_channel (cmd_xbar_demux_001_src1_channel), // .channel + .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket + .src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready + .src2_valid (cmd_xbar_demux_001_src2_valid), // .valid + .src2_data (cmd_xbar_demux_001_src2_data), // .data + .src2_channel (cmd_xbar_demux_001_src2_channel), // .channel + .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket + .src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket + .src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready + .src3_valid (cmd_xbar_demux_001_src3_valid), // .valid + .src3_data (cmd_xbar_demux_001_src3_data), // .data + .src3_channel (cmd_xbar_demux_001_src3_channel), // .channel + .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket + .src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket + .src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready + .src4_valid (cmd_xbar_demux_001_src4_valid), // .valid + .src4_data (cmd_xbar_demux_001_src4_data), // .data + .src4_channel (cmd_xbar_demux_001_src4_channel), // .channel + .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket + .src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket + .src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready + .src5_valid (cmd_xbar_demux_001_src5_valid), // .valid + .src5_data (cmd_xbar_demux_001_src5_data), // .data + .src5_channel (cmd_xbar_demux_001_src5_channel), // .channel + .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket + .src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket + .src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready + .src6_valid (cmd_xbar_demux_001_src6_valid), // .valid + .src6_data (cmd_xbar_demux_001_src6_data), // .data + .src6_channel (cmd_xbar_demux_001_src6_channel), // .channel + .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket + .src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket + .src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready + .src7_valid (cmd_xbar_demux_001_src7_valid), // .valid + .src7_data (cmd_xbar_demux_001_src7_data), // .data + .src7_channel (cmd_xbar_demux_001_src7_channel), // .channel + .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket + .src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket + .src8_ready (cmd_xbar_demux_001_src8_ready), // src8.ready + .src8_valid (cmd_xbar_demux_001_src8_valid), // .valid + .src8_data (cmd_xbar_demux_001_src8_data), // .data + .src8_channel (cmd_xbar_demux_001_src8_channel), // .channel + .src8_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket + .src8_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket + .src9_ready (cmd_xbar_demux_001_src9_ready), // src9.ready + .src9_valid (cmd_xbar_demux_001_src9_valid), // .valid + .src9_data (cmd_xbar_demux_001_src9_data), // .data + .src9_channel (cmd_xbar_demux_001_src9_channel), // .channel + .src9_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket + .src9_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket + .src10_ready (cmd_xbar_demux_001_src10_ready), // src10.ready + .src10_valid (cmd_xbar_demux_001_src10_valid), // .valid + .src10_data (cmd_xbar_demux_001_src10_data), // .data + .src10_channel (cmd_xbar_demux_001_src10_channel), // .channel + .src10_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket + .src10_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket + .src11_ready (cmd_xbar_demux_001_src11_ready), // src11.ready + .src11_valid (cmd_xbar_demux_001_src11_valid), // .valid + .src11_data (cmd_xbar_demux_001_src11_data), // .data + .src11_channel (cmd_xbar_demux_001_src11_channel), // .channel + .src11_startofpacket (cmd_xbar_demux_001_src11_startofpacket), // .startofpacket + .src11_endofpacket (cmd_xbar_demux_001_src11_endofpacket), // .endofpacket + .src12_ready (cmd_xbar_demux_001_src12_ready), // src12.ready + .src12_valid (cmd_xbar_demux_001_src12_valid), // .valid + .src12_data (cmd_xbar_demux_001_src12_data), // .data + .src12_channel (cmd_xbar_demux_001_src12_channel), // .channel + .src12_startofpacket (cmd_xbar_demux_001_src12_startofpacket), // .startofpacket + .src12_endofpacket (cmd_xbar_demux_001_src12_endofpacket), // .endofpacket + .src13_ready (cmd_xbar_demux_001_src13_ready), // src13.ready + .src13_valid (cmd_xbar_demux_001_src13_valid), // .valid + .src13_data (cmd_xbar_demux_001_src13_data), // .data + .src13_channel (cmd_xbar_demux_001_src13_channel), // .channel + .src13_startofpacket (cmd_xbar_demux_001_src13_startofpacket), // .startofpacket + .src13_endofpacket (cmd_xbar_demux_001_src13_endofpacket), // .endofpacket + .src14_ready (cmd_xbar_demux_001_src14_ready), // src14.ready + .src14_valid (cmd_xbar_demux_001_src14_valid), // .valid + .src14_data (cmd_xbar_demux_001_src14_data), // .data + .src14_channel (cmd_xbar_demux_001_src14_channel), // .channel + .src14_startofpacket (cmd_xbar_demux_001_src14_startofpacket), // .startofpacket + .src14_endofpacket (cmd_xbar_demux_001_src14_endofpacket), // .endofpacket + .src15_ready (cmd_xbar_demux_001_src15_ready), // src15.ready + .src15_valid (cmd_xbar_demux_001_src15_valid), // .valid + .src15_data (cmd_xbar_demux_001_src15_data), // .data + .src15_channel (cmd_xbar_demux_001_src15_channel), // .channel + .src15_startofpacket (cmd_xbar_demux_001_src15_startofpacket), // .startofpacket + .src15_endofpacket (cmd_xbar_demux_001_src15_endofpacket), // .endofpacket + .src16_ready (cmd_xbar_demux_001_src16_ready), // src16.ready + .src16_valid (cmd_xbar_demux_001_src16_valid), // .valid + .src16_data (cmd_xbar_demux_001_src16_data), // .data + .src16_channel (cmd_xbar_demux_001_src16_channel), // .channel + .src16_startofpacket (cmd_xbar_demux_001_src16_startofpacket), // .startofpacket + .src16_endofpacket (cmd_xbar_demux_001_src16_endofpacket), // .endofpacket + .src17_ready (cmd_xbar_demux_001_src17_ready), // src17.ready + .src17_valid (cmd_xbar_demux_001_src17_valid), // .valid + .src17_data (cmd_xbar_demux_001_src17_data), // .data + .src17_channel (cmd_xbar_demux_001_src17_channel), // .channel + .src17_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket + .src17_endofpacket (cmd_xbar_demux_001_src17_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_mux cmd_xbar_mux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (cmd_xbar_mux_src_ready), // src.ready + .src_valid (cmd_xbar_mux_src_valid), // .valid + .src_data (cmd_xbar_mux_src_data), // .data + .src_channel (cmd_xbar_mux_src_channel), // .channel + .src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket + .sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready + .sink0_valid (cmd_xbar_demux_src0_valid), // .valid + .sink0_channel (cmd_xbar_demux_src0_channel), // .channel + .sink0_data (cmd_xbar_demux_src0_data), // .data + .sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket + .sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready + .sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid + .sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel + .sink1_data (cmd_xbar_demux_001_src0_data), // .data + .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_mux cmd_xbar_mux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (cmd_xbar_mux_001_src_ready), // src.ready + .src_valid (cmd_xbar_mux_001_src_valid), // .valid + .src_data (cmd_xbar_mux_001_src_data), // .data + .src_channel (cmd_xbar_mux_001_src_channel), // .channel + .src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready + .sink0_valid (cmd_xbar_demux_src1_valid), // .valid + .sink0_channel (cmd_xbar_demux_src1_channel), // .channel + .sink0_data (cmd_xbar_demux_src1_data), // .data + .sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket + .sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready + .sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid + .sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel + .sink1_data (cmd_xbar_demux_001_src1_data), // .data + .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_demux rsp_xbar_demux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_src_ready), // sink.ready + .sink_channel (id_router_src_channel), // .channel + .sink_data (id_router_src_data), // .data + .sink_startofpacket (id_router_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_src_endofpacket), // .endofpacket + .sink_valid (id_router_src_valid), // .valid + .src0_ready (rsp_xbar_demux_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_src0_valid), // .valid + .src0_data (rsp_xbar_demux_src0_data), // .data + .src0_channel (rsp_xbar_demux_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket + .src1_ready (rsp_xbar_demux_src1_ready), // src1.ready + .src1_valid (rsp_xbar_demux_src1_valid), // .valid + .src1_data (rsp_xbar_demux_src1_data), // .data + .src1_channel (rsp_xbar_demux_src1_channel), // .channel + .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket + ); + + nios_system_cmd_xbar_demux rsp_xbar_demux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_001_src_ready), // sink.ready + .sink_channel (id_router_001_src_channel), // .channel + .sink_data (id_router_001_src_data), // .data + .sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket + .sink_valid (id_router_001_src_valid), // .valid + .src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_001_src0_valid), // .valid + .src0_data (rsp_xbar_demux_001_src0_data), // .data + .src0_channel (rsp_xbar_demux_001_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket + .src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready + .src1_valid (rsp_xbar_demux_001_src1_valid), // .valid + .src1_data (rsp_xbar_demux_001_src1_data), // .data + .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel + .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_002 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_002_src_ready), // sink.ready + .sink_channel (id_router_002_src_channel), // .channel + .sink_data (id_router_002_src_data), // .data + .sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket + .sink_valid (id_router_002_src_valid), // .valid + .src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_002_src0_valid), // .valid + .src0_data (rsp_xbar_demux_002_src0_data), // .data + .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_003 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_003_src_ready), // sink.ready + .sink_channel (id_router_003_src_channel), // .channel + .sink_data (id_router_003_src_data), // .data + .sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket + .sink_valid (id_router_003_src_valid), // .valid + .src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_003_src0_valid), // .valid + .src0_data (rsp_xbar_demux_003_src0_data), // .data + .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_004 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_004_src_ready), // sink.ready + .sink_channel (id_router_004_src_channel), // .channel + .sink_data (id_router_004_src_data), // .data + .sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket + .sink_valid (id_router_004_src_valid), // .valid + .src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_004_src0_valid), // .valid + .src0_data (rsp_xbar_demux_004_src0_data), // .data + .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_005 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_005_src_ready), // sink.ready + .sink_channel (id_router_005_src_channel), // .channel + .sink_data (id_router_005_src_data), // .data + .sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket + .sink_valid (id_router_005_src_valid), // .valid + .src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_005_src0_valid), // .valid + .src0_data (rsp_xbar_demux_005_src0_data), // .data + .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_006 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_006_src_ready), // sink.ready + .sink_channel (id_router_006_src_channel), // .channel + .sink_data (id_router_006_src_data), // .data + .sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket + .sink_valid (id_router_006_src_valid), // .valid + .src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_006_src0_valid), // .valid + .src0_data (rsp_xbar_demux_006_src0_data), // .data + .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_007 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_007_src_ready), // sink.ready + .sink_channel (id_router_007_src_channel), // .channel + .sink_data (id_router_007_src_data), // .data + .sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket + .sink_valid (id_router_007_src_valid), // .valid + .src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_007_src0_valid), // .valid + .src0_data (rsp_xbar_demux_007_src0_data), // .data + .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_008 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_008_src_ready), // sink.ready + .sink_channel (id_router_008_src_channel), // .channel + .sink_data (id_router_008_src_data), // .data + .sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket + .sink_valid (id_router_008_src_valid), // .valid + .src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_008_src0_valid), // .valid + .src0_data (rsp_xbar_demux_008_src0_data), // .data + .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_009 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_009_src_ready), // sink.ready + .sink_channel (id_router_009_src_channel), // .channel + .sink_data (id_router_009_src_data), // .data + .sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket + .sink_valid (id_router_009_src_valid), // .valid + .src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_009_src0_valid), // .valid + .src0_data (rsp_xbar_demux_009_src0_data), // .data + .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_010 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_010_src_ready), // sink.ready + .sink_channel (id_router_010_src_channel), // .channel + .sink_data (id_router_010_src_data), // .data + .sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket + .sink_valid (id_router_010_src_valid), // .valid + .src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_010_src0_valid), // .valid + .src0_data (rsp_xbar_demux_010_src0_data), // .data + .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_011 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_011_src_ready), // sink.ready + .sink_channel (id_router_011_src_channel), // .channel + .sink_data (id_router_011_src_data), // .data + .sink_startofpacket (id_router_011_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_011_src_endofpacket), // .endofpacket + .sink_valid (id_router_011_src_valid), // .valid + .src0_ready (rsp_xbar_demux_011_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_011_src0_valid), // .valid + .src0_data (rsp_xbar_demux_011_src0_data), // .data + .src0_channel (rsp_xbar_demux_011_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_012 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_012_src_ready), // sink.ready + .sink_channel (id_router_012_src_channel), // .channel + .sink_data (id_router_012_src_data), // .data + .sink_startofpacket (id_router_012_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_012_src_endofpacket), // .endofpacket + .sink_valid (id_router_012_src_valid), // .valid + .src0_ready (rsp_xbar_demux_012_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_012_src0_valid), // .valid + .src0_data (rsp_xbar_demux_012_src0_data), // .data + .src0_channel (rsp_xbar_demux_012_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_013 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_013_src_ready), // sink.ready + .sink_channel (id_router_013_src_channel), // .channel + .sink_data (id_router_013_src_data), // .data + .sink_startofpacket (id_router_013_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_013_src_endofpacket), // .endofpacket + .sink_valid (id_router_013_src_valid), // .valid + .src0_ready (rsp_xbar_demux_013_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_013_src0_valid), // .valid + .src0_data (rsp_xbar_demux_013_src0_data), // .data + .src0_channel (rsp_xbar_demux_013_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_013_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_014 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_014_src_ready), // sink.ready + .sink_channel (id_router_014_src_channel), // .channel + .sink_data (id_router_014_src_data), // .data + .sink_startofpacket (id_router_014_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_014_src_endofpacket), // .endofpacket + .sink_valid (id_router_014_src_valid), // .valid + .src0_ready (rsp_xbar_demux_014_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_014_src0_valid), // .valid + .src0_data (rsp_xbar_demux_014_src0_data), // .data + .src0_channel (rsp_xbar_demux_014_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_014_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_015 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_015_src_ready), // sink.ready + .sink_channel (id_router_015_src_channel), // .channel + .sink_data (id_router_015_src_data), // .data + .sink_startofpacket (id_router_015_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_015_src_endofpacket), // .endofpacket + .sink_valid (id_router_015_src_valid), // .valid + .src0_ready (rsp_xbar_demux_015_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_015_src0_valid), // .valid + .src0_data (rsp_xbar_demux_015_src0_data), // .data + .src0_channel (rsp_xbar_demux_015_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_015_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_016 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_016_src_ready), // sink.ready + .sink_channel (id_router_016_src_channel), // .channel + .sink_data (id_router_016_src_data), // .data + .sink_startofpacket (id_router_016_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_016_src_endofpacket), // .endofpacket + .sink_valid (id_router_016_src_valid), // .valid + .src0_ready (rsp_xbar_demux_016_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_016_src0_valid), // .valid + .src0_data (rsp_xbar_demux_016_src0_data), // .data + .src0_channel (rsp_xbar_demux_016_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_016_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_017 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_017_src_ready), // sink.ready + .sink_channel (id_router_017_src_channel), // .channel + .sink_data (id_router_017_src_data), // .data + .sink_startofpacket (id_router_017_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_017_src_endofpacket), // .endofpacket + .sink_valid (id_router_017_src_valid), // .valid + .src0_ready (rsp_xbar_demux_017_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_017_src0_valid), // .valid + .src0_data (rsp_xbar_demux_017_src0_data), // .data + .src0_channel (rsp_xbar_demux_017_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_mux rsp_xbar_mux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (rsp_xbar_mux_src_ready), // src.ready + .src_valid (rsp_xbar_mux_src_valid), // .valid + .src_data (rsp_xbar_mux_src_data), // .data + .src_channel (rsp_xbar_mux_src_channel), // .channel + .src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket + .sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready + .sink0_valid (rsp_xbar_demux_src0_valid), // .valid + .sink0_channel (rsp_xbar_demux_src0_channel), // .channel + .sink0_data (rsp_xbar_demux_src0_data), // .data + .sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket + .sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready + .sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid + .sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel + .sink1_data (rsp_xbar_demux_001_src0_data), // .data + .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket + ); + + nios_system_rsp_xbar_mux_001 rsp_xbar_mux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (rsp_xbar_mux_001_src_ready), // src.ready + .src_valid (rsp_xbar_mux_001_src_valid), // .valid + .src_data (rsp_xbar_mux_001_src_data), // .data + .src_channel (rsp_xbar_mux_001_src_channel), // .channel + .src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready + .sink0_valid (rsp_xbar_demux_src1_valid), // .valid + .sink0_channel (rsp_xbar_demux_src1_channel), // .channel + .sink0_data (rsp_xbar_demux_src1_data), // .data + .sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket + .sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready + .sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid + .sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel + .sink1_data (rsp_xbar_demux_001_src1_data), // .data + .sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket + .sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready + .sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid + .sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel + .sink2_data (rsp_xbar_demux_002_src0_data), // .data + .sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket + .sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket + .sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready + .sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid + .sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel + .sink3_data (rsp_xbar_demux_003_src0_data), // .data + .sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket + .sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket + .sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready + .sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid + .sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel + .sink4_data (rsp_xbar_demux_004_src0_data), // .data + .sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket + .sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket + .sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready + .sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid + .sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel + .sink5_data (rsp_xbar_demux_005_src0_data), // .data + .sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket + .sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket + .sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready + .sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid + .sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel + .sink6_data (rsp_xbar_demux_006_src0_data), // .data + .sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket + .sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket + .sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready + .sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid + .sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel + .sink7_data (rsp_xbar_demux_007_src0_data), // .data + .sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket + .sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket + .sink8_ready (rsp_xbar_demux_008_src0_ready), // sink8.ready + .sink8_valid (rsp_xbar_demux_008_src0_valid), // .valid + .sink8_channel (rsp_xbar_demux_008_src0_channel), // .channel + .sink8_data (rsp_xbar_demux_008_src0_data), // .data + .sink8_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket + .sink8_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket + .sink9_ready (rsp_xbar_demux_009_src0_ready), // sink9.ready + .sink9_valid (rsp_xbar_demux_009_src0_valid), // .valid + .sink9_channel (rsp_xbar_demux_009_src0_channel), // .channel + .sink9_data (rsp_xbar_demux_009_src0_data), // .data + .sink9_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket + .sink9_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket + .sink10_ready (rsp_xbar_demux_010_src0_ready), // sink10.ready + .sink10_valid (rsp_xbar_demux_010_src0_valid), // .valid + .sink10_channel (rsp_xbar_demux_010_src0_channel), // .channel + .sink10_data (rsp_xbar_demux_010_src0_data), // .data + .sink10_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket + .sink10_endofpacket (rsp_xbar_demux_010_src0_endofpacket), // .endofpacket + .sink11_ready (rsp_xbar_demux_011_src0_ready), // sink11.ready + .sink11_valid (rsp_xbar_demux_011_src0_valid), // .valid + .sink11_channel (rsp_xbar_demux_011_src0_channel), // .channel + .sink11_data (rsp_xbar_demux_011_src0_data), // .data + .sink11_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket + .sink11_endofpacket (rsp_xbar_demux_011_src0_endofpacket), // .endofpacket + .sink12_ready (rsp_xbar_demux_012_src0_ready), // sink12.ready + .sink12_valid (rsp_xbar_demux_012_src0_valid), // .valid + .sink12_channel (rsp_xbar_demux_012_src0_channel), // .channel + .sink12_data (rsp_xbar_demux_012_src0_data), // .data + .sink12_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket + .sink12_endofpacket (rsp_xbar_demux_012_src0_endofpacket), // .endofpacket + .sink13_ready (rsp_xbar_demux_013_src0_ready), // sink13.ready + .sink13_valid (rsp_xbar_demux_013_src0_valid), // .valid + .sink13_channel (rsp_xbar_demux_013_src0_channel), // .channel + .sink13_data (rsp_xbar_demux_013_src0_data), // .data + .sink13_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket + .sink13_endofpacket (rsp_xbar_demux_013_src0_endofpacket), // .endofpacket + .sink14_ready (rsp_xbar_demux_014_src0_ready), // sink14.ready + .sink14_valid (rsp_xbar_demux_014_src0_valid), // .valid + .sink14_channel (rsp_xbar_demux_014_src0_channel), // .channel + .sink14_data (rsp_xbar_demux_014_src0_data), // .data + .sink14_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket + .sink14_endofpacket (rsp_xbar_demux_014_src0_endofpacket), // .endofpacket + .sink15_ready (rsp_xbar_demux_015_src0_ready), // sink15.ready + .sink15_valid (rsp_xbar_demux_015_src0_valid), // .valid + .sink15_channel (rsp_xbar_demux_015_src0_channel), // .channel + .sink15_data (rsp_xbar_demux_015_src0_data), // .data + .sink15_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket + .sink15_endofpacket (rsp_xbar_demux_015_src0_endofpacket), // .endofpacket + .sink16_ready (rsp_xbar_demux_016_src0_ready), // sink16.ready + .sink16_valid (rsp_xbar_demux_016_src0_valid), // .valid + .sink16_channel (rsp_xbar_demux_016_src0_channel), // .channel + .sink16_data (rsp_xbar_demux_016_src0_data), // .data + .sink16_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket + .sink16_endofpacket (rsp_xbar_demux_016_src0_endofpacket), // .endofpacket + .sink17_ready (rsp_xbar_demux_017_src0_ready), // sink17.ready + .sink17_valid (rsp_xbar_demux_017_src0_valid), // .valid + .sink17_channel (rsp_xbar_demux_017_src0_channel), // .channel + .sink17_data (rsp_xbar_demux_017_src0_data), // .data + .sink17_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket + .sink17_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket + ); + + nios_system_irq_mapper irq_mapper ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq + .sender_irq (nios2_processor_d_irq_irq) // sender.irq + ); + +endmodule diff --git a/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v b/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v new file mode 100644 index 0000000..94e2787 --- /dev/null +++ b/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v @@ -0,0 +1,877 @@ +// ----------------------------------------------------------- +// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your +// use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any +// output files any of the foregoing (including device programming or +// simulation files), and any associated documentation or information are +// expressly subject to the terms and conditions of the Altera Program +// License Subscription Agreement or other applicable license agreement, +// including, without limitation, that your use is for the sole purpose +// of programming logic devices manufactured by Altera and sold by Altera +// or its authorized distributors. Please refer to the applicable +// agreement for further details. +// +// Description: Single clock Avalon-ST FIFO. +// ----------------------------------------------------------- + +`timescale 1 ns / 1 ns + + +//altera message_off 10036 +module altera_avalon_sc_fifo +#( + // -------------------------------------------------- + // Parameters + // -------------------------------------------------- + parameter SYMBOLS_PER_BEAT = 1, + parameter BITS_PER_SYMBOL = 8, + parameter FIFO_DEPTH = 16, + parameter CHANNEL_WIDTH = 0, + parameter ERROR_WIDTH = 0, + parameter USE_PACKETS = 0, + parameter USE_FILL_LEVEL = 0, + parameter USE_STORE_FORWARD = 0, + parameter USE_ALMOST_FULL_IF = 0, + parameter USE_ALMOST_EMPTY_IF = 0, + + // -------------------------------------------------- + // Empty latency is defined as the number of cycles + // required for a write to deassert the empty flag. + // For example, a latency of 1 means that the empty + // flag is deasserted on the cycle after a write. + // + // Another way to think of it is the latency for a + // write to propagate to the output. + // + // An empty latency of 0 implies lookahead, which is + // only implemented for the register-based FIFO. + // -------------------------------------------------- + parameter EMPTY_LATENCY = 3, + parameter USE_MEMORY_BLOCKS = 1, + + // -------------------------------------------------- + // Internal Parameters + // -------------------------------------------------- + parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, + parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) +) +( + // -------------------------------------------------- + // Ports + // -------------------------------------------------- + input clk, + input reset, + + input [DATA_WIDTH-1: 0] in_data, + input in_valid, + input in_startofpacket, + input in_endofpacket, + input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, + input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, + input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, + output in_ready, + + output [DATA_WIDTH-1 : 0] out_data, + output reg out_valid, + output out_startofpacket, + output out_endofpacket, + output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, + output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, + output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, + input out_ready, + + input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, + input csr_write, + input csr_read, + input [31 : 0] csr_writedata, + output reg [31 : 0] csr_readdata, + + output wire almost_full_data, + output wire almost_empty_data +); + + // -------------------------------------------------- + // Local Parameters + // -------------------------------------------------- + localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); + localparam DEPTH = FIFO_DEPTH; + localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; + localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? + 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; + + // -------------------------------------------------- + // Internal Signals + // -------------------------------------------------- + genvar i; + + reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; + reg [ADDR_WIDTH-1 : 0] wr_ptr; + reg [ADDR_WIDTH-1 : 0] rd_ptr; + reg [DEPTH-1 : 0] mem_used; + + wire [ADDR_WIDTH-1 : 0] next_wr_ptr; + wire [ADDR_WIDTH-1 : 0] next_rd_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; + + wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; + + wire read; + wire write; + + reg empty; + reg next_empty; + reg full; + reg next_full; + + wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; + wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; + wire [PAYLOAD_WIDTH-1 : 0] in_payload; + reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; + reg [PAYLOAD_WIDTH-1 : 0] out_payload; + + reg internal_out_valid; + wire internal_out_ready; + + reg [ADDR_WIDTH : 0] fifo_fill_level; + reg [ADDR_WIDTH : 0] fill_level; + + reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; + reg [23:0] almost_full_threshold; + reg [23:0] almost_empty_threshold; + reg [23:0] cut_through_threshold; + reg [15:0] pkt_cnt; + reg [15:0] pkt_cnt_r; + reg [15:0] pkt_cnt_plusone; + reg [15:0] pkt_cnt_minusone; + reg drop_on_error_en; + reg error_in_pkt; + reg pkt_has_started; + reg sop_has_left_fifo; + reg fifo_too_small_r; + reg pkt_cnt_eq_zero; + reg pkt_cnt_eq_one; + reg pkt_cnt_changed; + + wire wait_for_threshold; + reg pkt_mode; + wire wait_for_pkt; + wire ok_to_forward; + wire in_pkt_eop_arrive; + wire out_pkt_leave; + wire in_pkt_start; + wire in_pkt_error; + wire drop_on_error; + wire fifo_too_small; + wire out_pkt_sop_leave; + wire [31:0] max_fifo_size; + reg fifo_fill_level_lt_cut_through_threshold; + + // -------------------------------------------------- + // Define Payload + // + // Icky part where we decide which signals form the + // payload to the FIFO with generate blocks. + // -------------------------------------------------- + generate + if (EMPTY_WIDTH > 0) begin + assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; + assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; + end + else begin + assign out_empty = in_error; + assign in_packet_signals = {in_startofpacket, in_endofpacket}; + assign {out_startofpacket, out_endofpacket} = out_packet_signals; + end + endgenerate + + generate + if (USE_PACKETS) begin + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; + assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data, in_error}; + assign {out_packet_signals, out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_channel}; + assign {out_packet_signals, out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data}; + assign {out_packet_signals, out_data} = out_payload; + end + end + end + else begin + assign out_packet_signals = 0; + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_error, in_channel}; + assign {out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_data, in_error}; + assign {out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_channel}; + assign {out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = in_data; + assign out_data = out_payload; + end + end + end + endgenerate + + // -------------------------------------------------- + // Memory-based FIFO storage + // + // To allow a ready latency of 0, the read index is + // obtained from the next read pointer and memory + // outputs are unregistered. + // + // If the empty latency is 1, we infer bypass logic + // around the memory so writes propagate to the + // outputs on the next cycle. + // + // Do not change the way this is coded: Quartus needs + // a perfect match to the template, and any attempt to + // refactor the two always blocks into one will break + // memory inference. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + if (EMPTY_LATENCY == 1) begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] = in_payload; + + internal_out_payload = mem[mem_rd_ptr]; + end + + end else begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] <= in_payload; + + internal_out_payload <= mem[mem_rd_ptr]; + end + + end + + assign mem_rd_ptr = next_rd_ptr; + + end else begin + + // -------------------------------------------------- + // Register-based FIFO storage + // + // Uses a shift register as the storage element. Each + // shift register slot has a bit which indicates if + // the slot is occupied (credit to Sam H for the idea). + // The occupancy bits are contiguous and start from the + // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep + // FIFO. + // + // Each slot is enabled during a read or when it + // is unoccupied. New data is always written to every + // going-to-be-empty slot (we keep track of which ones + // are actually useful with the occupancy bits). On a + // read we shift occupied slots. + // + // The exception is the last slot, which always gets + // new data when it is unoccupied. + // -------------------------------------------------- + for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg + always @(posedge clk or posedge reset) begin + if (reset) begin + mem[i] <= 0; + end + else if (read || !mem_used[i]) begin + if (!mem_used[i+1]) + mem[i] <= in_payload; + else + mem[i] <= mem[i+1]; + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + mem[DEPTH-1] <= 0; + end + else begin + if (!mem_used[DEPTH-1]) + mem[DEPTH-1] <= in_payload; + + if (DEPTH == 1) begin + if (write) + mem[DEPTH-1] <= in_payload; + end + end + end + + end + endgenerate + + assign read = internal_out_ready && internal_out_valid && ok_to_forward; + assign write = in_ready && in_valid; + + // -------------------------------------------------- + // Pointer Management + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + assign incremented_wr_ptr = wr_ptr + 1'b1; + assign incremented_rd_ptr = rd_ptr + 1'b1; + assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; + assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; + + always @(posedge clk or posedge reset) begin + if (reset) begin + wr_ptr <= 0; + rd_ptr <= 0; + end + else begin + wr_ptr <= next_wr_ptr; + rd_ptr <= next_rd_ptr; + end + end + + end else begin + + // -------------------------------------------------- + // Shift Register Occupancy Bits + // + // Consider a 4-deep FIFO with 2 entries: 0011 + // On a read and write, do not modify the bits. + // On a write, left-shift the bits to get 0111. + // On a read, right-shift the bits to get 0001. + // + // Also, on a write we set bit0 (the head), while + // clearing the tail on a read. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[0] <= 0; + end + else begin + if (write ^ read) begin + if (read) begin + if (DEPTH > 1) + mem_used[0] <= mem_used[1]; + else + mem_used[0] <= 0; + end + if (write) + mem_used[0] <= 1; + end + end + end + + if (DEPTH > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[DEPTH-1] <= 0; + end + else begin + if (write ^ read) begin + mem_used[DEPTH-1] <= 0; + if (write) + mem_used[DEPTH-1] <= mem_used[DEPTH-2]; + end + end + end + end + + for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic + always @(posedge clk, posedge reset) begin + if (reset) begin + mem_used[i] <= 0; + end + else begin + if (write ^ read) begin + if (read) + mem_used[i] <= mem_used[i+1]; + if (write) + mem_used[i] <= mem_used[i-1]; + end + end + end + end + + end + endgenerate + + + // -------------------------------------------------- + // Memory FIFO Status Management + // + // Generates the full and empty signals from the + // pointers. The FIFO is full when the next write + // pointer will be equal to the read pointer after + // a write. Reading from a FIFO clears full. + // + // The FIFO is empty when the next read pointer will + // be equal to the write pointer after a read. Writing + // to a FIFO clears empty. + // + // A simultaneous read and write must not change any of + // the empty or full flags unless there is a drop on error event. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + always @* begin + next_full = full; + next_empty = empty; + + if (read && !write) begin + next_full = 1'b0; + + if (incremented_rd_ptr == wr_ptr) + next_empty = 1'b1; + end + + if (write && !read) begin + if (!drop_on_error) + next_empty = 1'b0; + else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo + next_empty = 1'b1; + + if (incremented_wr_ptr == rd_ptr && !drop_on_error) + next_full = 1'b1; + end + + if (write && read && drop_on_error) begin + if (sop_ptr == next_rd_ptr) + next_empty = 1'b1; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + empty <= 1; + full <= 0; + end + else begin + empty <= next_empty; + full <= next_full; + end + end + + end else begin + // -------------------------------------------------- + // Register FIFO Status Management + // + // Full when the tail occupancy bit is 1. Empty when + // the head occupancy bit is 0. + // -------------------------------------------------- + always @* begin + full = mem_used[DEPTH-1]; + empty = !mem_used[0]; + + // ------------------------------------------ + // For a single slot FIFO, reading clears the + // full status immediately. + // ------------------------------------------ + if (DEPTH == 1) + full = mem_used[0] && !read; + + internal_out_payload = mem[0]; + + // ------------------------------------------ + // Writes clear empty immediately for lookahead modes. + // Note that we use in_valid instead of write to avoid + // combinational loops (in lookahead mode, qualifying + // with in_ready is meaningless). + // + // In a 1-deep FIFO, a possible combinational loop runs + // from write -> out_valid -> out_ready -> write + // ------------------------------------------ + if (EMPTY_LATENCY == 0) begin + empty = !mem_used[0] && !in_valid; + + if (!mem_used[0] && in_valid) + internal_out_payload = in_payload; + end + end + + end + endgenerate + + // -------------------------------------------------- + // Avalon-ST Signals + // + // The in_ready signal is straightforward. + // + // To match memory latency when empty latency > 1, + // out_valid assertions must be delayed by one clock + // cycle. + // + // Note: out_valid deassertions must not be delayed or + // the FIFO will underflow. + // -------------------------------------------------- + assign in_ready = !full; + assign internal_out_ready = out_ready || !out_valid; + + generate if (EMPTY_LATENCY > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) + internal_out_valid <= 0; + else begin + internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; + + if (read) begin + if (incremented_rd_ptr == wr_ptr) + internal_out_valid <= 1'b0; + end + end + end + end else begin + always @* begin + internal_out_valid = !empty & ok_to_forward; + end + end + endgenerate + + // -------------------------------------------------- + // Single Output Pipeline Stage + // + // This output pipeline stage is enabled if the FIFO's + // empty latency is set to 3 (default). It is disabled + // for all other allowed latencies. + // + // Reason: The memory outputs are unregistered, so we have to + // register the output or fmax will drop if combinatorial + // logic is present on the output datapath. + // + // Q: The Avalon-ST spec says that I have to register my outputs + // But isn't the memory counted as a register? + // A: The path from the address lookup to the memory output is + // slow. Registering the memory outputs is a good idea. + // + // The registers get packed into the memory by the fitter + // which means minimal resources are consumed (the result + // is a altsyncram with registered outputs, available on + // all modern Altera devices). + // + // This output stage acts as an extra slot in the FIFO, + // and complicates the fill level. + // -------------------------------------------------- + generate if (EMPTY_LATENCY == 3) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + out_valid <= 0; + out_payload <= 0; + end + else begin + if (internal_out_ready) begin + out_valid <= internal_out_valid & ok_to_forward; + out_payload <= internal_out_payload; + end + end + end + end + else begin + always @* begin + out_valid = internal_out_valid; + out_payload = internal_out_payload; + end + end + endgenerate + + // -------------------------------------------------- + // Fill Level + // + // The fill level is calculated from the next write + // and read pointers to avoid unnecessary latency. + // + // If the output pipeline is enabled, the fill level + // must account for it, or we'll always be off by one. + // This may, or may not be important depending on the + // application. + // + // For now, we'll always calculate the exact fill level + // at the cost of an extra adder when the output stage + // is enabled. + // -------------------------------------------------- + generate if (USE_FILL_LEVEL) begin + wire [31:0] depth32; + assign depth32 = DEPTH; + always @(posedge clk or posedge reset) begin + if (reset) + fifo_fill_level <= 0; + else if (next_full & !drop_on_error) + fifo_fill_level <= depth32[ADDR_WIDTH:0]; + else begin + fifo_fill_level[ADDR_WIDTH] <= 1'b0; + fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; + end + end + + always @* begin + fill_level = fifo_fill_level; + + if (EMPTY_LATENCY == 3) + fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; + end + end + else begin + initial fill_level = 0; + end + endgenerate + + generate if (USE_ALMOST_FULL_IF) begin + assign almost_full_data = (fill_level >= almost_full_threshold); + end + else + assign almost_full_data = 0; + endgenerate + + generate if (USE_ALMOST_EMPTY_IF) begin + assign almost_empty_data = (fill_level <= almost_empty_threshold); + end + else + assign almost_empty_data = 0; + endgenerate + + // -------------------------------------------------- + // Avalon-MM Status & Control Connection Point + // + // Register map: + // + // | Addr | RW | 31 - 0 | + // | 0 | R | Fill level | + // + // The registering of this connection point means + // that there is a cycle of latency between + // reads/writes and the updating of the fill level. + // -------------------------------------------------- + generate if (USE_STORE_FORWARD) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + cut_through_threshold <= 0; + drop_on_error_en <= 0; + csr_readdata <= 0; + pkt_mode <= 1'b1; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b100) begin + cut_through_threshold <= csr_writedata[23:0]; + pkt_mode <= (csr_writedata[23:0] == 0); + end + if(csr_address == 3'b101) + drop_on_error_en <= csr_writedata[0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + if (csr_address == 4) + csr_readdata <= {8'b0, cut_through_threshold}; + if (csr_address == 5) + csr_readdata <= {31'b0, drop_on_error_en}; + end + end + end + end + else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + csr_readdata <= 0; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + end + end + end + end + else begin + always @(posedge clk or posedge reset) begin + if (reset) begin + csr_readdata <= 0; + end + else if (csr_read) begin + csr_readdata <= 0; + + if (csr_address == 0) + csr_readdata <= fill_level; + end + end + end + endgenerate + + // -------------------------------------------------- + // Store and forward logic + // -------------------------------------------------- + // if the fifo gets full before the entire packet or the + // cut-threshold condition is met then start sending out + // data in order to avoid dead-lock situation + + generate if (USE_STORE_FORWARD) begin + assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; + assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); + assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : + ~wait_for_threshold) | fifo_too_small_r; + assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; + assign in_pkt_start = in_valid & in_ready & in_startofpacket; + assign in_pkt_error = in_valid & in_ready & |in_error; + assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; + assign out_pkt_leave = out_valid & out_ready & out_endofpacket; + assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; + + // count packets coming and going into the fifo + always @(posedge clk or posedge reset) begin + if (reset) begin + pkt_cnt <= 0; + pkt_cnt_r <= 0; + pkt_cnt_plusone <= 1; + pkt_cnt_minusone <= 0; + pkt_cnt_changed <= 0; + pkt_has_started <= 0; + sop_has_left_fifo <= 0; + fifo_too_small_r <= 0; + pkt_cnt_eq_zero <= 1'b1; + pkt_cnt_eq_one <= 1'b0; + fifo_fill_level_lt_cut_through_threshold <= 1'b1; + end + else begin + fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; + fifo_too_small_r <= fifo_too_small; + pkt_cnt_plusone <= pkt_cnt + 1'b1; + pkt_cnt_minusone <= pkt_cnt - 1'b1; + pkt_cnt_r <= pkt_cnt; + pkt_cnt_changed <= 1'b0; + + if( in_pkt_eop_arrive ) + sop_has_left_fifo <= 1'b0; + else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) + sop_has_left_fifo <= 1'b1; + + if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; + pkt_cnt_eq_zero <= 0; + if (pkt_cnt == 0) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; + if (pkt_cnt == 1) + pkt_cnt_eq_zero <= 1'b1; + else + pkt_cnt_eq_zero <= 1'b0; + if (pkt_cnt == 2) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + + if (in_pkt_start) + pkt_has_started <= 1'b1; + else if (in_pkt_eop_arrive) + pkt_has_started <= 1'b0; + end + end + + // drop on error logic + always @(posedge clk or posedge reset) begin + if (reset) begin + sop_ptr <= 0; + error_in_pkt <= 0; + end + else begin + // save the location of the SOP + if ( in_pkt_start ) + sop_ptr <= wr_ptr; + + // remember if error in pkt + // log error only if packet has already started + if (in_pkt_eop_arrive) + error_in_pkt <= 1'b0; + else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) + error_in_pkt <= 1'b1; + end + end + assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & + ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); + + end + else begin + assign ok_to_forward = 1'b1; + assign drop_on_error = 1'b0; + end + endgenerate + + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + integer i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv b/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv new file mode 100644 index 0000000..00dc788 --- /dev/null +++ b/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv @@ -0,0 +1,270 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2010 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ +// $Revision: #3 $ +// $Date: 2010/07/07 $ +// $Author: jyeap $ + +/* ----------------------------------------------------------------------- +Round-robin/fixed arbitration implementation. + +Q: how do you find the least-significant set-bit in an n-bit binary number, X? + +A: M = X & (~X + 1) + +Example: X = 101000100 + 101000100 & + 010111011 + 1 = + + 101000100 & + 010111100 = + ----------- + 000000100 + +The method can be generalized to find the first set-bit +at a bit index no lower than bit-index N, simply by adding +2**N rather than 1. + + +Q: how does this relate to round-robin arbitration? +A: +Let X be the concatenation of all request signals. +Let the number to be added to X (hereafter called the +top_priority) initialize to 1, and be assigned from the +concatenation of the previous saved-grant, left-rotated +by one position, each time arbitration occurs. The +concatenation of grants is then M. + +Problem: consider this case: + +top_priority = 010000 +request = 001001 +~request + top_priority = 000110 +next_grant = 000000 <- no one is granted! + +There was no "set bit at a bit index no lower than bit-index 4", so +the result was 0. + +We need to propagate the carry out from (~request + top_priority) to the LSB, so +that the sum becomes 000111, and next_grant is 000001. This operation could be +called a "circular add". + +A bit of experimentation on the circular add reveals a significant amount of +delay in exiting and re-entering the carry chain - this will vary with device +family. Quartus also reports a combinational loop warning. Finally, +Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But +Modelsim _doesn't_ report a combinational loop!) + +An alternate solution: concatenate the request vector with itself, and OR +corresponding bits from the top and bottom halves to determine next_grant. + +Example: + +top_priority = 010000 +{request, request} = 001001 001001 +{~request, ~request} + top_priority = 110111 000110 +result of & operation = 000001 000000 +next_grant = 000001 + +Notice that if request = 0, the sum operation will overflow, but we can ignore +this; the next_grant result is 0 (no one granted), as you might expect. +In the implementation, the last-granted value must be maintained as +a non-zero value - best probably simply not to update it when no requests +occur. + +----------------------------------------------------------------------- */ + +`timescale 1 ns / 1 ns + +module altera_merlin_arbitrator +#( + parameter NUM_REQUESTERS = 8, + // -------------------------------------- + // Implemented schemes + // "round-robin" + // "fixed-priority" + // "no-arb" + // -------------------------------------- + parameter SCHEME = "round-robin", + parameter PIPELINE = 0 +) +( + input clk, + input reset, + + // -------------------------------------- + // Requests + // -------------------------------------- + input [NUM_REQUESTERS-1:0] request, + + // -------------------------------------- + // Grants + // -------------------------------------- + output [NUM_REQUESTERS-1:0] grant, + + // -------------------------------------- + // Control Signals + // -------------------------------------- + input increment_top_priority, + input save_top_priority +); + + // -------------------------------------- + // Signals + // -------------------------------------- + wire [NUM_REQUESTERS-1:0] top_priority; + reg [NUM_REQUESTERS-1:0] top_priority_reg; + reg [NUM_REQUESTERS-1:0] last_grant; + wire [2*NUM_REQUESTERS-1:0] result; + + // -------------------------------------- + // Scheme Selection + // -------------------------------------- + generate + if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin + assign top_priority = top_priority_reg; + end + else begin + // Fixed arbitration (or single-requester corner case) + assign top_priority = 1'b1; + end + endgenerate + + // -------------------------------------- + // Decision Logic + // -------------------------------------- + altera_merlin_arb_adder + #( + .WIDTH (2 * NUM_REQUESTERS) + ) + adder + ( + .a ({ ~request, ~request }), + .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), + .sum (result) + ); + + + generate if (SCHEME == "no-arb") begin + + // -------------------------------------- + // No arbitration: just wire request directly to grant + // -------------------------------------- + assign grant = request; + + end else begin + // Do the math in double-vector domain + wire [2*NUM_REQUESTERS-1:0] grant_double_vector; + assign grant_double_vector = {request, request} & result; + + // -------------------------------------- + // Extract grant from the top and bottom halves + // of the double vector. + // -------------------------------------- + assign grant = + grant_double_vector[NUM_REQUESTERS - 1 : 0] | + grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; + + end + endgenerate + + // -------------------------------------- + // Left-rotate the last grant vector to create top_priority. + // -------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + top_priority_reg <= 1'b1; + end + else begin + if (PIPELINE) begin + if (increment_top_priority) begin + top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1]} : top_priority_reg; + end + end else begin + if (save_top_priority) begin + top_priority_reg <= grant; + end + if (increment_top_priority) begin + if (|request) + top_priority_reg <= { grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1] }; + else + top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; + end + end + end + end + +endmodule + +// ---------------------------------------------- +// Adder for the standard arbitrator +// ---------------------------------------------- +module altera_merlin_arb_adder +#( + parameter WIDTH = 8 +) +( + input [WIDTH-1:0] a, + input [WIDTH-1:0] b, + + output [WIDTH-1:0] sum +); + + // ---------------------------------------------- + // Benchmarks indicate that for small widths, the full + // adder has higher fmax because synthesis can merge + // it with the mux, allowing partial decisions to be + // made early. + // + // The magic number is 4 requesters, which means an + // 8 bit adder. + // ---------------------------------------------- + genvar i; + generate if (WIDTH <= 8) begin : full_adder + + wire cout[WIDTH-1:0]; + + assign sum[0] = (a[0] ^ b[0]); + assign cout[0] = (a[0] & b[0]); + + for (i = 1; i < WIDTH; i = i+1) begin : arb + + assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; + assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); + + end + + end else begin : carry_chain + + assign sum = a + b; + + end + endgenerate + +endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv b/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv new file mode 100644 index 0000000..9b49c44 --- /dev/null +++ b/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv @@ -0,0 +1,286 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Burst Uncompressor +// +// Compressed read bursts -> uncompressed +// ------------------------------------------ + +`timescale 1 ns / 1 ns + +module altera_merlin_burst_uncompressor +#( + parameter ADDR_W = 16, + parameter BURSTWRAP_W = 3, + parameter BYTE_CNT_W = 4, + parameter PKT_SYMBOLS = 4, + parameter BURST_SIZE_W = 3 +) +( + input clk, + input reset, + + // sink ST signals + input sink_startofpacket, + input sink_endofpacket, + input sink_valid, + output sink_ready, + + // sink ST "data" + input [ADDR_W - 1: 0] sink_addr, + input [BURSTWRAP_W - 1 : 0] sink_burstwrap, + input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, + input sink_is_compressed, + input [BURST_SIZE_W-1 : 0] sink_burstsize, + + // source ST signals + output source_startofpacket, + output source_endofpacket, + output source_valid, + input source_ready, + + // source ST "data" + output [ADDR_W - 1: 0] source_addr, + output [BURSTWRAP_W - 1 : 0] source_burstwrap, + output [BYTE_CNT_W - 1 : 0] source_byte_cnt, + + // Note: in the slave agent, the output should always be uncompressed. In + // other applications, it may be required to leave-compressed or not. How to + // control? Seems like a simple mux - pass-through if no uncompression is + // required. + output source_is_compressed, + output [BURST_SIZE_W-1 : 0] source_burstsize +); + +//---------------------------------------------------- +// AXSIZE decoding +// +// Turns the axsize value into the actual number of bytes +// being transferred. +// --------------------------------------------------- +function reg[63:0] bytes_in_transfer; + input [2:0] axsize; + case (axsize) + 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; + 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; + 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; + 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; + 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; + 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; + 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; + default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + endcase + +endfunction + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + // def: Burst Compression. In a merlin network, a compressed burst is one + // which is transmitted in a single beat. Example: read burst. In + // constrast, an uncompressed burst (example: write burst) is transmitted in + // one beat per writedata item. + // + // For compressed bursts which require response packets, burst + // uncompression is required. Concrete example: a read burst of size 8 + // occupies one response-fifo position. When that fifo position reaches the + // front of the FIFO, the slave starts providing the required 8 readdatavalid + // pulses. The 8 return response beats must be provided in a single packet, + // with incrementing address and decrementing byte_cnt fields. Upon receipt + // of the final readdata item of the burst, the response FIFO item is + // retired. + // Burst uncompression logic provides: + // a) 2-state FSM (idle, busy) + // reset to idle state + // transition to busy state for 2nd and subsequent rdv pulses + // - a single-cycle burst (aka non-burst read) causes no transition to + // busy state. + // b) response startofpacket/endofpacket logic. The response FIFO item + // will have sop asserted, and may have eop asserted. (In the case of + // multiple read bursts transmit in the command fabric in a single packet, + // the eop assertion will come in a later FIFO item.) To support packet + // conservation, and emit a well-formed packet on the response fabric, + // i) response fabric startofpacket is asserted only for the first resp. + // beat; + // ii) response fabric endofpacket is asserted only for the last resp. + // beat. + // c) response address field. The response address field contains an + // incrementing sequence, such that each readdata item is associated with + // its slave-map location. N.b. a) computing the address correctly requires + // knowledge of burstwrap behavior b) there may be no clients of the address + // field, which makes this field a good target for optimization. See + // burst_uncompress_address_counter below. + // d) response byte_cnt field. The response byte_cnt field contains a + // decrementing sequence, such that each beat of the response contains the + // count of bytes to follow. In the case of sub-bursts in a single packet, + // the byte_cnt field may decrement down to num_symbols, then back up to + // some value, multiple times in the packet. + + reg burst_uncompress_busy; + reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; + wire first_packet_beat; + wire last_packet_beat; + + assign first_packet_beat = sink_valid & ~burst_uncompress_busy; + + // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to + // the output. + assign source_byte_cnt = + first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; + assign source_valid = sink_valid; + + // Last packet beat is set throughout receipt of an uncompressed read burst + // from the response FIFO - this forces all the burst uncompression machinery + // idle. + assign last_packet_beat = ~sink_is_compressed | + ( + burst_uncompress_busy ? + (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : + sink_valid & (sink_byte_cnt == num_symbols) + ); + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (source_valid & source_ready & sink_valid) begin + // No matter what the current state, last_packet_beat leads to + // idle. + if (last_packet_beat) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (burst_uncompress_busy) begin + burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? + (burst_uncompress_byte_counter - num_symbols) : + (sink_byte_cnt - num_symbols); + end + else begin // not busy, at least one more beat to go + burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; + // To do: should busy go true for numsymbols-size compressed + // bursts? + burst_uncompress_busy <= '1; + end + end + end + end + end + + wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; + reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; + reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; + + wire [63:0] decoded_burstsize_wire; + wire [ADDR_W-1:0] decoded_burstsize; + + // The input burstwrap value can be used as a mask against address values, + // but with one caveat: the address width may be (probably is) wider than + // the burstwrap width. The spec says: extend the msb of the burstwrap + // value out over the entire address width (but only if the address width + // actually is wider than the burstwrap width; otherwise it's a 0-width or + // negative range and concatenation multiplier). + assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; + generate + if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend + // Sign-extend, just wires: + assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = + {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; + end + endgenerate + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_base <= '0; + end + else if (first_packet_beat & source_ready) begin + burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; + end + end + + assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits + assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed + + wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = + ( + (first_packet_beat ? + sink_addr : + burst_uncompress_address_offset) + decoded_burstsize + ) & + addr_width_burstwrap; + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_offset <= '0; + end + else begin + if (source_ready & source_valid) begin + burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; + // if (first_packet_beat) begin + // burst_uncompress_address_offset <= + // (sink_addr + num_symbols) & addr_width_burstwrap; + // end + // else begin + // burst_uncompress_address_offset <= + // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; + // end + end + end + end + + // On the first packet beat, send the input address out unchanged, + // while values are computed/registered for 2nd and subsequent beats. + assign source_addr = first_packet_beat ? sink_addr : + burst_uncompress_address_base | burst_uncompress_address_offset; + assign source_burstwrap = sink_burstwrap; + assign source_burstsize = sink_burstsize; + + //------------------------------------------------------------------- + // A single (compressed) read burst will have sop/eop in the same beat. + // A sequence of read sub-bursts emitted by a burst adapter in response to a + // single read burst will have sop on the first sub-burst, eop on the last. + // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve + // packet conservation. + assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; + assign source_endofpacket = sink_endofpacket & last_packet_beat; + assign sink_ready = source_valid & source_ready & last_packet_beat; + + // This is correct for the slave agent usage, but won't always be true in the + // width adapter. To do: add an "please uncompress" input, and use it to + // pass-through or modify, and set source_is_compressed accordingly. + assign source_is_compressed = 1'b0; +endmodule + diff --git a/nios_system/synthesis/submodules/altera_merlin_master_agent.sv b/nios_system/synthesis/submodules/altera_merlin_master_agent.sv new file mode 100644 index 0000000..070f26f --- /dev/null +++ b/nios_system/synthesis/submodules/altera_merlin_master_agent.sv @@ -0,0 +1,309 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Agent +// +// Converts Avalon-MM transactions into +// Merlin network packets. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_master_agent +#( + // ------------------- + // Packet Format Parameters + // ------------------- + parameter PKT_QOS_H = 109, + PKT_QOS_L = 106, + PKT_DATA_SIDEBAND_H = 105, + PKT_DATA_SIDEBAND_L = 98, + PKT_ADDR_SIDEBAND_H = 97, + PKT_ADDR_SIDEBAND_L = 93, + PKT_CACHE_H = 92, + PKT_CACHE_L = 89, + PKT_THREAD_ID_H = 88, + PKT_THREAD_ID_L = 87, + PKT_BEGIN_BURST = 81, + PKT_PROTECTION_H = 80, + PKT_PROTECTION_L = 80, + PKT_BURSTWRAP_H = 79, + PKT_BURSTWRAP_L = 77, + PKT_BYTE_CNT_H = 76, + PKT_BYTE_CNT_L = 74, + PKT_ADDR_H = 73, + PKT_ADDR_L = 42, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + PKT_BURST_TYPE_H = 94, + PKT_BURST_TYPE_L = 93, + PKT_TRANS_EXCLUSIVE = 83, + PKT_TRANS_LOCK = 82, + PKT_TRANS_COMPRESSED_READ = 41, + PKT_TRANS_POSTED = 40, + PKT_TRANS_WRITE = 39, + PKT_TRANS_READ = 38, + PKT_DATA_H = 37, + PKT_DATA_L = 6, + PKT_BYTEEN_H = 5, + PKT_BYTEEN_L = 2, + PKT_SRC_ID_H = 1, + PKT_SRC_ID_L = 1, + PKT_DEST_ID_H = 0, + PKT_DEST_ID_L = 0, + PKT_RESPONSE_STATUS_L = 110, + PKT_RESPONSE_STATUS_H = 111, + ST_DATA_W = 112, + ST_CHANNEL_W = 1, + + // ------------------- + // Agent Parameters + // ------------------- + AV_BURSTCOUNT_W = 3, + ID = 1, + SUPPRESS_0_BYTEEN_RSP = 1, + BURSTWRAP_VALUE = 4, + CACHE_VALUE = 0, + SECURE_ACCESS_BIT = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + // ------------------- + // Derived Parameters + // ------------------- + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, + PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 +) +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Avalon-MM Anti-Master + // ------------------- + input [PKT_ADDR_W-1 : 0] av_address, + input av_write, + input av_read, + input [PKT_DATA_W-1 : 0] av_writedata, + output reg [PKT_DATA_W-1 : 0] av_readdata, + output reg av_waitrequest, + output reg av_readdatavalid, + input [PKT_BYTEEN_W-1 : 0] av_byteenable, + input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, + input av_debugaccess, + input av_lock, + output reg [1:0] av_response, + input av_writeresponserequest, + output reg av_writeresponsevalid, + + // ------------------- + // Command Source + // ------------------- + output reg cp_valid, + output reg [ST_DATA_W-1 : 0] cp_data, + output wire cp_startofpacket, + output wire cp_endofpacket, + input cp_ready, + + // ------------------- + // Response Sink + // ------------------- + input rp_valid, + input [ST_DATA_W-1 : 0] rp_data, + input [ST_CHANNEL_W-1 : 0] rp_channel, + input rp_startofpacket, + input rp_endofpacket, + output reg rp_ready +); + // ------------------------------------------------------------ + // Utility Functions + // ------------------------------------------------------------ + function integer clogb2; + input [31:0] value; + begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; + clogb2 = clogb2 - 1; + end + endfunction // clogb2 + + localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); + localparam NUMSYMBOLS = PKT_BYTEEN_W; + localparam BURSTING = (MAX_BURST > NUMSYMBOLS); + localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); + localparam BURST_SIZE = clogb2(NUMSYMBOLS); + + typedef enum bit [1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + OTHER_WRAP = 2'b11 + } MerlinBurstType; + + // -------------------------------------- + // Potential optimization: compare in words to save bits? + // -------------------------------------- + wire is_burst; + assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); + + wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; + wire [31:0] id_int = ID; + wire [2:0] burstsize_sig = BURST_SIZE[2:0]; + wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; + + // -------------------------------------- + // Address alignment + // + // The packet format requires that addresses be aligned to + // the transaction size. + // -------------------------------------- + wire [PKT_ADDR_W-1 : 0] av_address_aligned; + generate + if (NUMSYMBOLS > 1) begin + assign av_address_aligned = + {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; + end + else begin + assign av_address_aligned = av_address; + end + endgenerate + + // -------------------------------------- + // Command & Response Construction + // -------------------------------------- + always @* begin + cp_data = '0; // default assignment; override below as needed. + + cp_data[PKT_PROTECTION_L] = av_debugaccess; + cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // Default Non-secured (AXI) + cp_data[PKT_PROTECTION_L+2] = 1'b0; // Default Data access (AXI) + cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; + cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; + cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; + cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; + cp_data[PKT_TRANS_LOCK ] = av_lock; + cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; + cp_data[PKT_TRANS_READ ] = av_read; + cp_data[PKT_TRANS_WRITE ] = av_write; + // posted and non-posted write avaiable now + cp_data[PKT_TRANS_POSTED ] = av_write & !av_writeresponserequest; + cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; + cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; + cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; + cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; + cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; + cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; + cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE[3:0]; + cp_data[PKT_QOS_H : PKT_QOS_L] = '0; + cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; + cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; + + av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; + if (USE_WRITERESPONSE || USE_READRESPONSE) + av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; + else + av_response = '0; + + end + + // -------------------------------------- + // Command Control + // -------------------------------------- + always @* begin + cp_valid = 0; + + if (av_write || av_read) + cp_valid = 1; + end + + generate if (BURSTING) begin + reg sop_enable; + + always @(posedge clk, posedge reset) begin + if (reset) begin + sop_enable <= 1'b1; + end + else begin + if (cp_valid && cp_ready) begin + sop_enable <= 1'b0; + if (cp_endofpacket) + sop_enable <= 1'b1; + end + end + end + + assign cp_startofpacket = sop_enable; + assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); + + end + else begin + + assign cp_startofpacket = 1'b1; + assign cp_endofpacket = 1'b1; + + end + endgenerate + + // -------------------------------------- + // Backpressure & Readdatavalid + // -------------------------------------- + reg hold_waitrequest; + + always @ (posedge clk, posedge reset) begin + if (reset) + hold_waitrequest <= 1'b1; + else + hold_waitrequest <= 1'b0; + end + + always @* begin + rp_ready = 1; + av_readdatavalid = 0; + av_writeresponsevalid = 0; + av_waitrequest = hold_waitrequest | !cp_ready; + + // -------------------------------------- + // Currently, responses are _always_ read responses because + // this Avalon agent only issues posted writes, which do + // not have responses. -> not true for now + // Now Avalon supports response, so based on type of transaction + // return, assert correct thing + // -------------------------------------- + if (rp_data[PKT_TRANS_WRITE] == 1) + av_writeresponsevalid = rp_valid; + else + av_readdatavalid = rp_valid; + + if (SUPPRESS_0_BYTEEN_RSP) begin + if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) + av_readdatavalid = 0; + end + end + +endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_master_translator.sv b/nios_system/synthesis/submodules/altera_merlin_master_translator.sv new file mode 100644 index 0000000..a43760f --- /dev/null +++ b/nios_system/synthesis/submodules/altera_merlin_master_translator.sv @@ -0,0 +1,554 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Translator +// +// Converts Avalon-MM Master Interfaces into +// Avalon-MM Universal Master Interfaces +// -------------------------------------- + +`timescale 1 ns / 1 ns + + + +module altera_merlin_master_translator #( + parameter + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + + //Optional Port Declarations + + USE_BURSTCOUNT = 1, + USE_BEGINBURSTTRANSFER = 0, + USE_BEGINTRANSFER = 0, + USE_CHIPSELECT = 0, + USE_READ = 1, + USE_READDATAVALID = 1, + USE_WRITE = 1, + USE_WAITREQUEST = 1, + USE_WRITERESPONSE = 0, + USE_READRESPONSE = 0, + + AV_REGISTERINCOMINGSIGNALS = 0, + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_CONSTANT_BURST_BEHAVIOR = 1, + AV_BURSTCOUNT_SYMBOLS = 0, + AV_LINEWRAPBURSTS = 0, + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_CONSTANT_BURST_BEHAVIOR = 0 + )( + //Universal Avalon Master + input wire clk, + input wire reset, + output reg uav_write, + output reg uav_read, + output reg [UAV_ADDRESS_W -1 : 0] uav_address, + output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, + output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, + output wire [AV_DATA_W -1 : 0] uav_writedata, + output wire uav_lock, + output wire uav_debugaccess, + output wire uav_clken, + + input wire [ AV_DATA_W -1 : 0] uav_readdata, + input wire uav_readdatavalid, + input wire uav_waitrequest, + input wire [1:0] uav_response, + output reg uav_writeresponserequest, + input wire uav_writeresponsevalid, + + //Avalon-MM !Master + input reg av_write, + input reg av_read, + input wire [AV_ADDRESS_W -1 : 0] av_address, + input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, + input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, + input wire [AV_DATA_W -1 : 0] av_writedata, + input wire av_begintransfer, + input wire av_beginbursttransfer, + input wire av_lock, + input wire av_chipselect, + input wire av_debugaccess, + input wire av_clken, + + output wire [AV_DATA_W -1 : 0] av_readdata, + output wire av_readdatavalid, + output reg av_waitrequest, + output reg [1:0] av_response, + input wire av_writeresponserequest, + output reg av_writeresponsevalid + + ); + + + localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); + localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); + localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; + + localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; + localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; + + + // -1 for burstcount restriction 2^(n-1) + + localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; + localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; + + localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; + localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; + + localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; + localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; + + function integer flog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + if ( i <= 0 ) flog2 = 0; + else begin + for(flog2 = -1; i > 0; flog2 = flog2 + 1) + i = i >> 1; + end + end + + endfunction // flog2 + + function integer clog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2 = 0; i > 0; clog2 = clog2 + 1) + i = i >> 1; + end + + endfunction + + function integer pow2; + input [31:0] toShift; + begin + pow2=1; + pow2= pow2 << toShift; + end + endfunction // pow2 + + // ------------------------------------------------- + // Assign some constants to appropriately-sized signals to + // avoid synthesis warnings. This also helps some simulators + // with their inferred sensitivity lists. + // ------------------------------------------------- + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); + wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; + + + reg internal_beginbursttransfer; + reg internal_begintransfer; + reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; + reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; + + + + reg uav_read_pre; + reg uav_write_pre; + reg read_accepted; + + //Passthru assignmenst + + assign uav_writedata = av_writedata; + assign av_readdata = uav_readdata; + assign uav_byteenable = av_byteenable; + assign uav_lock = av_lock; + assign av_readdatavalid = uav_readdatavalid; + assign uav_debugaccess = av_debugaccess; + assign uav_clken = av_clken; + + //Response signals + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) + av_response = '0; + else + av_response = uav_response; + if (USE_WRITERESPONSE) begin + uav_writeresponserequest = av_writeresponserequest; + av_writeresponsevalid = uav_writeresponsevalid; + end else begin + uav_writeresponserequest = '0; + av_writeresponsevalid = '0; + end + end + + //address + burstcount assignment + + reg [UAV_ADDRESS_W - 1 : 0] address_register; + reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; + + always @* begin + uav_address=uav_address_pre; + uav_burstcount=uav_burstcount_pre; + + if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin + uav_address=address_register; + uav_burstcount=burstcount_register; + end + end + + reg first_burst_stalled; + reg burst_stalled; + + + wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; + wire [UAV_ADDRESS_W-1:0] combi_addr_reg; + generate + if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin + if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + end + else begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + end + end + else begin + assign combi_burst_addr_reg = + uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + assign combi_addr_reg = + address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + end + endgenerate + + always@(posedge clk, posedge reset) begin + + if(reset) begin + address_register <= '0; + burstcount_register <= '0; + first_burst_stalled <= 1'b0; + burst_stalled <= 1'b0; + end + else begin + address_register <= address_register; + burstcount_register <= burstcount_register; + + if(internal_beginbursttransfer||first_burst_stalled) begin + + if(av_waitrequest) begin + first_burst_stalled <= 1'b1; + address_register <= uav_address_pre; + burstcount_register <= uav_burstcount_pre; + end else begin + first_burst_stalled <= 1'b0; + address_register <= combi_burst_addr_reg; + burstcount_register <= uav_burstcount_pre - symbols_per_word; + end + end + + else if(internal_begintransfer || burst_stalled) begin + if(~av_waitrequest) begin + burst_stalled <= 1'b0; + address_register <= combi_addr_reg; + burstcount_register <= burstcount_register - symbols_per_word; + end else + burst_stalled<=1'b1; + end + end + + end + + //Address + always @* begin + uav_address_pre = '0; + + if(AV_ADDRESS_SYMBOLS) + uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; + else begin + uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; + end + end + + //Burstcount + always@* begin + uav_burstcount_pre = symbols_per_word; // default to a single transfer + + if(USE_BURSTCOUNT) begin + uav_burstcount_pre = '0; + + if(AV_BURSTCOUNT_SYMBOLS) + uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; + else begin + uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; + end + + end + + end + + + //waitrequest translation + + always@(posedge clk, posedge reset) begin + if(reset) + read_accepted <= 1'b0; + else begin + read_accepted <= read_accepted; + + if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives + read_accepted <= 1'b0; + + if(read_accepted == 0) + read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; + end + + end + + reg write_accepted = 0; + generate if (AV_REGISTERINCOMINGSIGNALS) begin + always@(posedge clk, posedge reset) begin + if(reset) + write_accepted <= 1'b0; + else begin + write_accepted <= + ~av_waitrequest ? 1'b0 : + uav_write & ~uav_waitrequest? 1'b1 : + write_accepted; + end + end + end endgenerate + + always@* begin + av_waitrequest = uav_waitrequest; + + if(USE_READDATAVALID == 0 ) begin + av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; + end + + if (AV_REGISTERINCOMINGSIGNALS) begin + av_waitrequest = + uav_read_pre ? ~uav_readdatavalid : + uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : + 1'b1; + end + + if(USE_WAITREQUEST == 0) begin + av_waitrequest = 0; + end + end + + //read/write generation + always@* begin + + uav_write = 1'b0; + uav_write_pre = 1'b0; + uav_read = 1'b0; + uav_read_pre = 1'b0; + + if(!USE_CHIPSELECT) begin + if (USE_READ) begin + uav_read_pre=av_read; + end + + if (USE_WRITE) begin + uav_write_pre=av_write; + end + end + else begin + if(!USE_WRITE && USE_READ) begin + uav_read_pre=av_read; + uav_write_pre=av_chipselect & ~av_read; + end + else if(!USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre = av_chipselect & ~av_write; + end + else if (USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre=av_read; + end + end + + if(USE_READDATAVALID == 0) + uav_read = uav_read_pre & ~read_accepted; + else + uav_read = uav_read_pre; + + if(AV_REGISTERINCOMINGSIGNALS == 0) + uav_write=uav_write_pre; + else + uav_write=uav_write_pre & ~write_accepted; + + + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + if(USE_BEGINTRANSFER) begin + internal_begintransfer = av_begintransfer; + end else begin + internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(internal_begintransfer == 1 && uav_waitrequest) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + wire last_burst_transfer_pre; + wire last_burst_transfer_reg; + wire last_burst_transfer; + + // compare values before the mux to shorten critical path; benchmark before changing + assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); + assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); + assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; + + always@* begin + if(USE_BEGINBURSTTRANSFER) begin + internal_beginbursttransfer = av_beginbursttransfer; + end else begin + internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_beginbursttransfer <= 1'b0; + end + else begin + end_beginbursttransfer <= end_beginbursttransfer; + if( last_burst_transfer && internal_begintransfer || uav_read ) begin + end_beginbursttransfer <= 1'b0; + end + else if(uav_write && internal_begintransfer) begin + end_beginbursttransfer <= 1'b1; + end + end + + end + + // synthesis translate_off + + // ------------------------------------------------ + // check_1 : for waitrequest signal violation + // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls + // Exception : begintransfer / beginbursttransfer + // : previously not in any transaction (idle) + // Note : Not checking clken which is not exactly part of Avalon controls/inputs + // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE + // ------------------------------------------------ + + reg av_waitrequest_r; + reg av_write_r,av_writeresponserequest_r,av_read_r,av_lock_r,av_chipselect_r,av_debugaccess_r; + reg [AV_ADDRESS_W-1:0] av_address_r; + reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; + reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; + reg [AV_DATA_W-1:0] av_writedata_r; + + always @(posedge clk or posedge reset) begin + if (reset) begin + av_waitrequest_r <= '0; + av_write_r <= '0; + av_writeresponserequest_r <= '0; + av_read_r <= '0; + av_lock_r <= '0; + av_chipselect_r <= '0; + av_debugaccess_r <= '0; + av_address_r <= '0; + av_byteenable_r <= '0; + av_burstcount_r <= '0; + av_writedata_r <= '0; + + end + else begin + av_waitrequest_r <= av_waitrequest; + av_write_r <= av_write; + av_writeresponserequest_r <= av_writeresponserequest; + av_read_r <= av_read; + av_lock_r <= av_lock; + av_chipselect_r <= av_chipselect; + av_debugaccess_r <= av_debugaccess; + av_address_r <= av_address; + av_byteenable_r <= av_byteenable; + av_burstcount_r <= av_burstcount; + av_writedata_r <= av_writedata; + + if ( av_waitrequest_r && // When waitrequest is asserted + ( (av_write != av_write_r) || // Checks that : Input controls/data does not change + (av_writeresponserequest != av_writeresponserequest_r) || + (av_read != av_read_r) || + (av_lock != av_lock_r) || + (av_debugaccess != av_debugaccess_r) || + (av_address != av_address_r) || + (av_byteenable != av_byteenable_r) || + (av_burstcount != av_burstcount_r) + ) && + (av_write_r | av_read_r) && // Check only when : previously initiated a write/read + (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) + ) + $display("%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.\nav_address %x --> %x\nav_byteenable %x --> %x\nav_burstcount %x --> %x\nav_writedata %x --> %x\nav_writeresponserequest %x --> %x\nav_write %x --> %x\nav_read %x --> %x\nav_lock %x --> %x\nav_chipselect %x --> %x\nav_debugaccess %x --> %x ", $time(), + av_address_r , av_address, + av_byteenable_r , av_byteenable, + av_burstcount_r , av_burstcount, + av_writedata_r , av_writedata, + av_writeresponserequest_r, av_writeresponserequest, + av_write_r , av_write, + av_read_r , av_read, + av_lock_r , av_lock, + av_chipselect_r, av_chipselect, + av_debugaccess_r, av_debugaccess); + end + + // end check_1 + + end + + // synthesis translate_on + + + endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv b/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv new file mode 100644 index 0000000..ea599eb --- /dev/null +++ b/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv @@ -0,0 +1,588 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2011 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_agent +#( + // Packet parameters + parameter PKT_BEGIN_BURST = 81, + parameter PKT_DATA_H = 31, + parameter PKT_DATA_L = 0, + parameter PKT_SYMBOL_W = 8, + parameter PKT_BYTEEN_H = 71, + parameter PKT_BYTEEN_L = 68, + parameter PKT_ADDR_H = 63, + parameter PKT_ADDR_L = 32, + parameter PKT_TRANS_LOCK = 87, + parameter PKT_TRANS_COMPRESSED_READ = 67, + parameter PKT_TRANS_POSTED = 66, + parameter PKT_TRANS_WRITE = 65, + parameter PKT_TRANS_READ = 64, + parameter PKT_SRC_ID_H = 74, + parameter PKT_SRC_ID_L = 72, + parameter PKT_DEST_ID_H = 77, + parameter PKT_DEST_ID_L = 75, + parameter PKT_BURSTWRAP_H = 85, + parameter PKT_BURSTWRAP_L = 82, + parameter PKT_BYTE_CNT_H = 81, + parameter PKT_BYTE_CNT_L = 78, + parameter PKT_PROTECTION_H = 86, + parameter PKT_PROTECTION_L = 86, + parameter PKT_RESPONSE_STATUS_H = 89, + parameter PKT_RESPONSE_STATUS_L = 88, + parameter PKT_BURST_SIZE_H = 92, + parameter PKT_BURST_SIZE_L = 90, + parameter ST_DATA_W = 93, + parameter ST_CHANNEL_W = 32, + + // Slave parameters + parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + parameter AVS_BURSTCOUNT_W = 4, + parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, + + // Slave agent parameters + parameter PREVENT_FIFO_OVERFLOW = 0, + parameter SUPPRESS_0_BYTEEN_CMD = 1, + parameter USE_READRESPONSE = 0, + parameter USE_WRITERESPONSE = 0, + + // Derived slave parameters + parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + parameter BURST_SIZE_W = 3, + + // Derived FIFO width + parameter FIFO_DATA_W = ST_DATA_W + 1 +) +( + + input clk, + input reset, + + // Universal-Avalon anti-slave + output [ADDR_W-1:0] m0_address, + output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, + output [AVS_BE_W-1:0] m0_byteenable, + output m0_read, + input [AVS_DATA_W-1:0] m0_readdata, + input m0_waitrequest, + output m0_write, + output [AVS_DATA_W-1:0] m0_writedata, + input m0_readdatavalid, + output m0_debugaccess, + output m0_lock, + input [1:0] m0_response, + output m0_writeresponserequest, + input m0_writeresponsevalid, + + // Avalon-ST FIFO interfaces. + // Note: there's no need to include the "data" field here, at least for + // reads, since readdata is filled in from slave info. To keep life + // simple, have a data field, but fill it with 0s. + // Av-st response fifo source interface + output reg [FIFO_DATA_W-1:0] rf_source_data, + output rf_source_valid, + output rf_source_startofpacket, + output rf_source_endofpacket, + input rf_source_ready, + + // Av-st response fifo sink interface + input [FIFO_DATA_W-1:0] rf_sink_data, + input rf_sink_valid, + input rf_sink_startofpacket, + input rf_sink_endofpacket, + output rf_sink_ready, + + // Av-st readdata fifo src interface, data and response + // extra 2 bits for storing RESPONSE STATUS + output [AVS_DATA_W+1:0] rdata_fifo_src_data, + output rdata_fifo_src_valid, + input rdata_fifo_src_ready, + + // Av-st readdata fifo sink interface + input [AVS_DATA_W+1:0] rdata_fifo_sink_data, + input rdata_fifo_sink_valid, + output rdata_fifo_sink_ready, + + // Av-st sink command packet interface + output cp_ready, + input cp_valid, + input [ST_DATA_W-1:0] cp_data, + input [ST_CHANNEL_W-1:0] cp_channel, + input cp_startofpacket, + input cp_endofpacket, + + // Av-st source response packet interface + input rp_ready, + output reg rp_valid, + output reg [ST_DATA_W-1:0] rp_data, + output rp_startofpacket, + output rp_endofpacket +); + + // -------------------------------------------------- + // Ceil(log2()) function log2ceil of 4 = 2 + // -------------------------------------------------- + function integer log2ceil; + input reg[63:0] val; + reg [63:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + // ------------------------------------------------ + // Local Parameters + // ------------------------------------------------ + localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; + localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; + localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; + localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; + localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; + localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; + localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); + + // ------------------------------------------------ + // Signals + // ------------------------------------------------ + wire [DATA_W-1:0] cmd_data; + wire [BE_W-1:0] cmd_byteen; + wire [ADDR_W-1:0] cmd_addr; + wire [MID_W-1:0] cmd_mid; + wire [SID_W-1:0] cmd_sid; + wire cmd_read; + wire cmd_write; + wire cmd_compressed; + wire cmd_posted; + wire [BYTE_CNT_W-1:0] cmd_byte_cnt; + wire [BURSTWRAP_W-1:0] cmd_burstwrap; + wire [BURSTSIZE_W-1:0] cmd_burstsize; + wire cmd_debugaccess; + + wire byteen_asserted; + wire needs_response_synthesis; + wire generate_response; + + // Assign command fields + assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; + assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; + assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; + assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; + assign cmd_posted = cp_data[PKT_TRANS_POSTED]; + assign cmd_write = cp_data[PKT_TRANS_WRITE]; + assign cmd_read = cp_data[PKT_TRANS_READ]; + assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; + assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; + assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; + + // Local "ready_for_command" signal: deasserted when the agent is unable to accept + // another command, e.g. rdv FIFO is full, (local readdata storage is full && + // ~rp_ready), ... + // Say, this could depend on the type of command, for example, even if the + // rdv FIFO is full, a write request can be accepted. For later. + wire ready_for_command; + + wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; + wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; + wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; + wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; + wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + generate + if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow + // --------------------------------------------------- + // Backpressure if the slave says to, or if FIFO overflow may occur. + // + // All commands are backpressured once the FIFO is full + // even if they don't need storage. This breaks a long + // combinatorial path from the master read/write through + // this logic and back to the master via the backpressure + // path. + // + // To avoid a loss of throughput the FIFO will be parameterized + // one slot deeper. The extra slot should never be used in normal + // operation, but should a slave misbehave and accept one more + // read than it should then backpressure will kick in. + // + // An example: assume a slave with MPRT = 2. It can accept a + // command sequence RRWW without backpressuring. If the FIFO is + // only 2 deep, we'd backpressure the writes leading to loss of + // throughput. If the FIFO is 3 deep, we'll only backpressure when + // RRR... which is an illegal condition anyway. + // --------------------------------------------------- + + assign ready_for_command = rf_source_ready; + assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; + + end else begin : no_prevent_fifo_overflow + + // Do not suppress the command or the slave will + // not be able to waitrequest + assign ready_for_command = 1'b1; + // Backpressure only if the slave says to. + assign cp_ready = ~m0_waitrequest | ~byteen_asserted; + + end + endgenerate + + generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd + assign byteen_asserted = |cmd_byteen; + end else begin : no_suppress_0_byteen_cmd + assign byteen_asserted = 1'b1; + end + endgenerate + + // ------------------------------------------------------------------- + // Extract avalon signals from command packet. + // ------------------------------------------------------------------- + // Mask off the lower bits of address. + // The burst adapter before this component will break narrow sized packets + // into sub-bursts of length 1. However, the packet addresses are preserved, + // which means this component may see size-aligned addresses. + // + // Masking ensures that the addresses seen by an Avalon slave are aligned to + // the full data width instead of the size. + // + // Example: + // output from burst adapter (datawidth=4, size=2 bytes): + // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 + // expected output from slave agent: + // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 + generate + if (BITS_TO_MASK > 0) begin : mask_address + + assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; + + end else begin : no_mask_address + + assign m0_address = cmd_addr; + + end + endgenerate + + assign m0_byteenable = cmd_byteen; + assign m0_writedata = cmd_data; + + // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - + // this sort of burst exists only in merlin fabric ST packets. What to do + // if we see such a burst? All beats in that burst need to be transmitted + // to the slave so we have enough space-time for byteenable expression. + // + // There can be multiple bursts in a packet, but only one beat per burst + // in cases. The exception is when we've decided not to insert a + // burst adapter for efficiency reasons, in which case this agent is also + // responsible for driving burstcount to 1 on each beat of an uncompressed + // read burst. + + assign m0_read = ready_for_command & byteen_asserted & + (local_compressed_read | local_read); + + generate + begin : m0_burstcount_zero_pad + // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount + // from a sub-range, or 0-pad, as appropriate. + if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin + wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = + {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; + assign m0_burstcount = (local_read & ~local_compressed_read) ? + {zero_pad, num_symbols} : + {zero_pad, cmd_byte_cnt}; + end + else begin : m0_burstcount_no_pad + assign m0_burstcount = (local_read & ~local_compressed_read) ? + num_symbols[AVS_BURSTCOUNT_W-1:0] : + cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; + end + end + endgenerate + + assign m0_write = ready_for_command & local_write & byteen_asserted; + assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); + assign m0_debugaccess = cmd_debugaccess; + // For now, to support write response + assign m0_writeresponserequest = ready_for_command & local_write & byteen_asserted & !cmd_posted; + //assign m0_writeresponserequest = '0; + + // ------------------------------------------------------------------- + // Indirection layer for response packet values. Some may always wire + // directly from the slave translator; others will no doubt emerge from + // various FIFOs. + // What to put in resp_data when a write occured? Answer: it does not + // matter, because only response status is needed for non-posted writes, + // and the packet already has a field for that. + + // tgngo:Use the rdata_fifo to store write response as well + // So that we wont lost response if master can back-pressured + // as well as it needs for write response merging + assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; + //assign rdata_fifo_src_valid = m0_readdatavalid; + assign rdata_fifo_src_data = {m0_response,m0_readdata}; + + // ------------------------------------------------------------------ + // Generate a token when read commands are suppressed. The token + // is stored in the response FIFO, and will be used to synthesize + // a read response. The same token is used for non-posted write + // response synthesis. + // + // Note: this token is not generated for suppressed uncompressed read cycles; + // the burst uncompression logic at the read side of the response FIFO + // generates the correct number of responses. + // ------------------------------------------------------------------ + // When the slave can return the response, let it does its works. Dont generate sysnthesis response + assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | (nonposted_write_endofpacket && !USE_WRITERESPONSE); + + // Avalon-ST interfaces to external response fifo: + // tgngo:Currently, with "generate response synthesis", only one write command is allowed to write in at eop of non-posted write + // To support response from slave, we need to store each sub-burst of write command into fifo. + // Each sub-burst will return a response and these two command and response are popped out together + // Resposne merging will happen and at end_of_packet of the command - the last sub-burst write + // the slave agent will send out the final merged response + + wire internal_cp_endofburst; + wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning + wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; + assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; + assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); + wire local_nonposted_write = ~cp_data[PKT_TRANS_POSTED] & local_write; + wire nonposted_end_of_subburst = local_nonposted_write & internal_cp_endofburst; + + assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && nonposted_end_of_subburst)) + & ready_for_command & cp_ready; + assign rf_source_startofpacket = cp_startofpacket; + assign rf_source_endofpacket = cp_endofpacket; + always @* begin + // default: assign every command packet field to the response FIFO... + rf_source_data = {1'b0, cp_data}; + + // ... and override select fields as needed. + rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; + rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; + rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; + rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; + //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; + rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; + rf_source_data[PKT_TRANS_POSTED] = cmd_posted; + rf_source_data[PKT_TRANS_WRITE] = cmd_write; + rf_source_data[PKT_TRANS_READ] = cmd_read; + rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; + rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; + rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; + rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; + rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; + rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; + rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; + end + + wire uncompressor_source_valid; + wire [BURSTSIZE_W-1:0] uncompressor_burstsize; + + //assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + // tgngo: last_write_response indicates the last response of the burst (incase need sub-burst) + // at this time, the final response merged will send out, and rp_valid is only asserted + // for one response for whole burst + generate + if (USE_READRESPONSE & USE_WRITERESPONSE) begin + wire last_write_response = rf_sink_data[PKT_TRANS_WRITE] & !rf_sink_data[PKT_TRANS_POSTED] & rf_sink_endofpacket; + always @* begin + if (rf_sink_data[PKT_TRANS_WRITE] == 1) + rp_valid = rdata_fifo_sink_valid & last_write_response; + else + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end else begin + always @* begin + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end + endgenerate + // ------------------------------------------------------------------ + // Response merging + // ------------------------------------------------------------------ + wire [1:0] current_response = rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W]; + reg [1:0] response_merged; + generate + begin: response_merging + if (USE_READRESPONSE & USE_WRITERESPONSE) begin + reg first_write_response; + reg reset_merged_output; + reg [1:0] previous_response_in; + reg [1:0] previous_response; + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + first_write_response <= 1'b1; + end + else begin // Merging work for write response, for read: previous_response_in = current_response + if (rf_sink_valid & rdata_fifo_sink_valid & rf_sink_data[PKT_TRANS_WRITE]) begin + first_write_response <= 1'b0; + if (rf_sink_endofpacket) + first_write_response <= 1'b1; + end + end + end + + always_comb begin + reset_merged_output = first_write_response && rdata_fifo_sink_valid; + previous_response_in = reset_merged_output ? current_response : previous_response; + response_merged = current_response >= previous_response ? current_response: previous_response_in; + end + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + previous_response <= 2'b00; + end + else begin + if (rf_sink_valid & rdata_fifo_sink_valid) begin + previous_response <= response_merged; + end + end + end + end else begin + always @* begin + response_merged = current_response; + end + end + end + endgenerate + + assign generate_response = rf_sink_data[FIFO_DATA_W-1]; + + wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; + // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo + wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; + + wire [BYTE_CNT_W-1:0] burst_byte_cnt; + wire [BURSTWRAP_W-1:0] rp_burstwrap; + wire [ADDR_W-1:0] rp_address; + wire rp_is_compressed; + + // ------------------------------------------------------------------ + // Backpressure the readdata fifo if we're supposed to synthesize a response. + // This may be a read response (for suppressed reads) or a write response + // (for non-posted writes). + // ------------------------------------------------------------------ + assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); + + always @* begin + // By default, return all fields... + rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; + + // ... and override specific fields. + rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; + // Assignments directly from the response fifo. + rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; + rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; + rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; + rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; + + // Burst uncompressor assignments + rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; + rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; + rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; + rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; + + // avalon slaves always respond with "okay" -> not true for now + //rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; + rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; + rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; + end + + // ------------------------------------------------------------------ + // Note: the burst uncompressor may be asked to generate responses for + // write packets; these are treated the same as single-cycle uncompressed + // reads. + // ------------------------------------------------------------------ + altera_merlin_burst_uncompressor #( + .ADDR_W (ADDR_W), + .BURSTWRAP_W (BURSTWRAP_W), + .BYTE_CNT_W (BYTE_CNT_W), + .PKT_SYMBOLS (PKT_SYMBOLS) + ) uncompressor + ( + .clk (clk), + .reset (reset), + .sink_startofpacket (rf_sink_startofpacket_wire), + .sink_endofpacket (rf_sink_endofpacket), + .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), + .sink_ready (rf_sink_ready), + .sink_addr (rf_sink_addr), + .sink_burstwrap (rf_sink_burstwrap), + .sink_byte_cnt (rf_sink_byte_cnt), + .sink_is_compressed (rf_sink_compressed), + .sink_burstsize (rf_sink_burstsize), + + .source_startofpacket (rp_startofpacket), + .source_endofpacket (rp_endofpacket), + .source_valid (uncompressor_source_valid), + .source_ready (rp_ready), + .source_addr (rp_address), + .source_burstwrap (rp_burstwrap), + .source_byte_cnt (burst_byte_cnt), + .source_is_compressed (rp_is_compressed), + .source_burstsize (uncompressor_burstsize) + ); + +//-------------------------------------- +// Assertion: In case slave support response. Yhe slave needs return response in order +// Ex: non-posted write followed by a read: write response must complete before read data +//-------------------------------------- +// synthesis translate_off +ERROR_write_response_and_read_response_cannot_happen_same_time: + assert property ( @(posedge clk) + disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) + ); + +// synthesis translate_on +endmodule + diff --git a/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv b/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv new file mode 100644 index 0000000..bcb2311 --- /dev/null +++ b/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv @@ -0,0 +1,533 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Slave Translator +// +// Translates Universal Avalon MM Slave +// to any Avalon MM Slave +// ------------------------------------- +// +//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one +//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero +//The key feature here is that no same cycle turnaround data is processed through the fabric. + +//import avalon_utilities_pkg::*; + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_translator + #( + parameter + //Widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + UAV_BYTEENABLE_W = 4, + + //Read Latency + AV_READLATENCY = 1, + + //Timing + AV_READ_WAIT_CYCLES = 0, + AV_WRITE_WAIT_CYCLES = 0, + AV_SETUP_WAIT_CYCLES = 0, + AV_DATA_HOLD_CYCLES = 0, + + //Optional Port Declarations + USE_READDATAVALID = 1, + USE_WAITREQUEST = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + //Variable Addressing + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_DATA_W = 32, + + AV_CONSTANT_BURST_BEHAVIOR = 0, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + CHIPSELECT_THROUGH_READLATENCY = 0, + + // Tightly-Coupled Options + USE_UAV_CLKEN = 0, + AV_REQUIRE_UNALIGNED_ADDRESSES = 0 + ) + ( + + // ------------------- + // Clock & Reset + // ------------------- + input wire clk, + input wire reset, + + // ------------------- + // Universal Avalon Slave + // ------------------- + + input wire [UAV_ADDRESS_W - 1 : 0] uav_address, + input wire [UAV_DATA_W - 1 : 0] uav_writedata, + input wire uav_write, + input wire uav_read, + input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, + input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, + input wire uav_lock, + input wire uav_debugaccess, + input wire uav_clken, + + output logic uav_readdatavalid, + output logic uav_waitrequest, + output logic [UAV_DATA_W - 1 : 0] uav_readdata, + output logic [1:0] uav_response, + input wire uav_writeresponserequest, + output logic uav_writeresponsevalid, + + // ------------------- + // Customizable Avalon Master + // ------------------- + output logic [AV_ADDRESS_W - 1 : 0] av_address, + output logic [AV_DATA_W - 1 : 0] av_writedata, + output logic av_write, + output logic av_read, + output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, + output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, + output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, + output logic av_begintransfer, + output wire av_chipselect, + output logic av_beginbursttransfer, + output logic av_lock, + output wire av_clken, + output wire av_debugaccess, + output wire av_outputenable, + + input logic [AV_DATA_W - 1 : 0] av_readdata, + input logic av_readdatavalid, + input logic av_waitrequest, + + input logic [1:0] av_response, + output logic av_writeresponserequest, + input wire av_writeresponsevalid + + ); + + function integer clog2_plusone; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) + i = i >> 1; + end + + endfunction + + function integer max; + //returns the larger of two passed arguments + input [31:0] one; + input [31:0] two; + + if(one > two) + max=one; + else + max=two; + endfunction // int + + localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); + localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); + localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); + localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); + localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; + + localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? + AV_ADDRESS_W : + UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; + + localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? + AV_BURSTCOUNT_W : + UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; + localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; + + + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); + wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; + + // +-------------------------------- + // |Backwards Compatibility Signals + // +-------------------------------- + assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; + assign av_debugaccess = uav_debugaccess; + + // +------------------- + // |Passthru Signals + // +------------------- + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin + uav_response = '0; + end else begin + uav_response = av_response; + end + end + assign av_writeresponserequest = uav_writeresponserequest; + assign uav_writeresponsevalid = av_writeresponsevalid; + + //------------------------- + //Writedata and Byteenable + //------------------------- + + always@* begin + av_byteenable = '0; + av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + always@* begin + av_writedata = '0; + av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; + end + + // +------------------- + // |Calculated Signals + // +------------------- + + logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; + + function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; + input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; + + for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin + if(byteenable[i] == 1) begin + return i; + end + end + + return '0; + + endfunction + + reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; + reg [AV_ADDRESS_W - 1 : 0] address_reg; + + + always@(posedge clk, posedge reset) begin + if(reset) begin + burstcount_reg <= '0; + address_reg <= '0; + end + else begin + burstcount_reg <= burstcount_reg; + address_reg <= address_reg; + + if(av_beginbursttransfer) begin + burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + end + end + end + + + logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; + + always@* begin + if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin + temp_wire = decode_byteenable(uav_byteenable); + + real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; + end + else begin + real_uav_address = uav_address; + end + + av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_address = address_reg; + end + + always@* begin + av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_burstcount = burstcount_reg; + end + + always@* begin + av_lock = uav_lock; + end + + // ------------------- + // Writebyteenable Assignment + // ------------------- + +always@* begin + av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; +end + + // ------------------- + // Waitrequest Assignment + // ------------------- + + reg av_waitrequest_generated; + reg av_waitrequest_generated_read; + reg av_waitrequest_generated_write; + reg waitrequest_reset_override; + + reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; + + always@(posedge reset, posedge clk) begin + + if(reset) begin + wait_latency_counter <= '0; + waitrequest_reset_override <= 1'h1; + end + else begin + waitrequest_reset_override <= 1'h0; + + wait_latency_counter <= '0; + + if( uav_read | uav_write ) + wait_latency_counter <= wait_latency_counter + 1'h1; + + if( ~uav_waitrequest | waitrequest_reset_override ) + wait_latency_counter <= '0; + + end + + end + + + always @* begin + + av_read = uav_read; + av_write = uav_write; + + av_waitrequest_generated = 1'h1; + av_waitrequest_generated_read = 1'h1; + av_waitrequest_generated_write = 1'h1; + + if(LOG2_OF_LATENCY_SUM == 1) + av_waitrequest_generated = 0; + + if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin + av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; + av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; + + av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; + av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; + + if(uav_write) + av_waitrequest_generated = av_waitrequest_generated_write; + else + av_waitrequest_generated = av_waitrequest_generated_read; + + end + + if(USE_WAITREQUEST) begin + uav_waitrequest = av_waitrequest; + end + else begin + uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; + end + + end + + // -------------- + // Readdata Assignment + // -------------- + + reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; + + always@(posedge clk, posedge reset) begin + if(reset) + av_readdata_pre <= 'b0; + else + av_readdata_pre <= av_readdata; + end + + always@* begin + uav_readdata = '0; + + if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin + uav_readdata = av_readdata; + end + else begin + uav_readdata = av_readdata_pre; + end + end + // ------------------- + // Readdatavalid Assigment + // ------------------- + + reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; + reg top_read_latency_shift_reg; + + + + always@* begin + + uav_readdatavalid=top_read_latency_shift_reg; + + if(USE_READDATAVALID) begin + uav_readdatavalid = av_readdatavalid; + end + + end + + always@* begin + + top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; + + if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin + top_read_latency_shift_reg=read_latency_shift_reg; + end + + if (AV_READLATENCY > 1) begin + top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; + end + + end + + always@(posedge reset, posedge clk) begin + + if (reset) begin + read_latency_shift_reg <= '0; + end + else if (av_clken) begin + + read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; + + for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin + read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; + end + + end + + end + + // ------------ + // Chipselect and OutputEnable + // ------------ + + reg av_chipselect_pre; + wire cs_extension; + reg av_outputenable_pre; + + + assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; + assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); + + assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; + + always@(posedge reset, posedge clk) begin + if(reset) + av_outputenable_pre <= 1'b0; + else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) + av_outputenable_pre <= 0; + else + av_outputenable_pre <= cs_extension | uav_read; + end + + always@(posedge reset, posedge clk) begin + if(reset) begin + av_chipselect_pre <= 1'b0; + end + else begin + av_chipselect_pre <= 1'b0; + + if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin + //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. + //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. + if(uav_read) begin + av_chipselect_pre <= 1'b1; + end + else if(cs_extension == 1) begin + av_chipselect_pre <= 1'b1; + end + + end + end + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + reg in_transfer; + + + + always@* begin + av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_beginbursttransfer <= 1'b0; + in_transfer <= 1'b0; + end + else begin + + end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); + + if(uav_write && uav_burstcount == symbols_per_word) + in_transfer <=1'b0; + else if(uav_write) + in_transfer <=1'b1; + + end + + end + +endmodule diff --git a/nios_system/synthesis/submodules/altera_reset_controller.sdc b/nios_system/synthesis/submodules/altera_reset_controller.sdc new file mode 100644 index 0000000..d58dd05 --- /dev/null +++ b/nios_system/synthesis/submodules/altera_reset_controller.sdc @@ -0,0 +1,33 @@ +# (C) 2001-2013 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +# +--------------------------------------------------- +# | Cut the async clear paths +# +--------------------------------------------------- +set aclr_counter 0 +set clrn_counter 0 +set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +foreach_in_collection aclr_pin $aclr_collection { + set aclr_counter [expr $aclr_counter + 1] +} +foreach_in_collection clrn_pin $clrn_collection { + set clrn_counter [expr $clrn_counter + 1] +} +if {$aclr_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +} + +if {$clrn_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +} diff --git a/nios_system/synthesis/submodules/altera_reset_controller.v b/nios_system/synthesis/submodules/altera_reset_controller.v new file mode 100644 index 0000000..7c250c7 --- /dev/null +++ b/nios_system/synthesis/submodules/altera_reset_controller.v @@ -0,0 +1,206 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $ +// $Revision: #2 $ +// $Date: 2013/06/03 $ +// $Author: wkleong $ + +// -------------------------------------- +// Reset controller +// +// Combines all the input resets and synchronizes +// the result to the clk. +// ACDS13.1 - Added reset request as part of reset sequencing +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_reset_controller +#( + parameter NUM_RESET_INPUTS = 6, + parameter OUTPUT_RESET_SYNC_EDGES = "deassert", + parameter SYNC_DEPTH = 2, + parameter RESET_REQUEST_PRESENT = 0 +) +( + // -------------------------------------- + // We support up to 16 reset inputs, for now + // -------------------------------------- + input reset_in0, + input reset_in1, + input reset_in2, + input reset_in3, + input reset_in4, + input reset_in5, + input reset_in6, + input reset_in7, + input reset_in8, + input reset_in9, + input reset_in10, + input reset_in11, + input reset_in12, + input reset_in13, + input reset_in14, + input reset_in15, + + input clk, + output reg reset_out, + output reg reset_req +); + + localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); + + localparam DEPTH = 2; + localparam CLKEN_LAGS_RESET = 0; + localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; + + wire merged_reset; + wire reset_out_pre; + + // Registers and Interconnect + (*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain; + reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain; + reg r_sync_rst_dly; + reg r_sync_rst; + reg r_early_rst; + + // -------------------------------------- + // "Or" all the input resets together + // -------------------------------------- + assign merged_reset = ( + reset_in0 | + reset_in1 | + reset_in2 | + reset_in3 | + reset_in4 | + reset_in5 | + reset_in6 | + reset_in7 | + reset_in8 | + reset_in9 | + reset_in10 | + reset_in11 | + reset_in12 | + reset_in13 | + reset_in14 | + reset_in15 + ); + + // -------------------------------------- + // And if required, synchronize it to the required clock domain, + // with the correct synchronization type + // -------------------------------------- + generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin + + assign reset_out_pre = merged_reset; + + end else begin + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(ASYNC_RESET) + ) + alt_rst_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset), + .reset_out (reset_out_pre) + ); + + end + endgenerate + + generate if (RESET_REQUEST_PRESENT == 0) begin + always @* begin + reset_out = reset_out_pre; + reset_req = 1'b0; + end + end + else begin + + // 3-FF Metastability Synchronizer + initial + begin + altera_reset_synchronizer_int_chain <= 3'b111; + end + + always @(posedge clk) + begin + altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre}; + end + + + // Synchronous reset pipe + initial + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + + always @(posedge clk) + begin + if (altera_reset_synchronizer_int_chain[2] == 1'b1) + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + else + begin + r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; + end + end + + // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition + // matches the early input. + initial + begin + r_sync_rst_dly <= 1'b1; + r_sync_rst <= 1'b1; + r_early_rst <= 1'b1; + end + + always @(posedge clk) + begin + // Delayed reset pipeline register + r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; + + case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) + 3'b000: r_sync_rst <= 1'b0; // Not reset + 3'b001: r_sync_rst <= 1'b0; + 3'b010: r_sync_rst <= 1'b0; + 3'b011: r_sync_rst <= 1'b1; + 3'b100: r_sync_rst <= 1'b1; + 3'b101: r_sync_rst <= 1'b1; + 3'b110: r_sync_rst <= 1'b1; + 3'b111: r_sync_rst <= 1'b1; // In Reset + default: r_sync_rst <= 1'b1; + endcase + + case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) + 2'b00: r_early_rst <= 1'b0; // Not reset + 2'b01: r_early_rst <= 1'b1; // Coming out of reset + 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. + 2'b11: r_early_rst <= 1'b1; // Held in reset + default: r_early_rst <= 1'b1; + endcase + end + + always @* begin + reset_out = r_sync_rst; + reset_req = r_early_rst; + end + + end + endgenerate + +endmodule diff --git a/nios_system/synthesis/submodules/altera_reset_synchronizer.v b/nios_system/synthesis/submodules/altera_reset_synchronizer.v new file mode 100644 index 0000000..14936c3 --- /dev/null +++ b/nios_system/synthesis/submodules/altera_reset_synchronizer.v @@ -0,0 +1,87 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_LEDRs.v b/nios_system/synthesis/submodules/nios_system_LEDRs.v new file mode 100644 index 0000000..63ed909 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_LEDRs.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_LEDRs ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 17: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 17: 0] data_out; + wire [ 17: 0] out_port; + wire [ 17: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[17 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_LEDs.v b/nios_system/synthesis/submodules/nios_system_LEDs.v new file mode 100644 index 0000000..4e22fe4 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_LEDs.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_LEDs ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 7: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 7: 0] data_out; + wire [ 7: 0] out_port; + wire [ 7: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {8 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[7 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_addr_router.sv b/nios_system/synthesis/submodules/nios_system_addr_router.sv new file mode 100644 index 0000000..3c8760e --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_addr_router.sv @@ -0,0 +1,224 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_addr_router_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 15 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_addr_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h40000 - 64'h0); + localparam PAD1 = log2ceil(64'h41000 - 64'h40800); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h41000; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_addr_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x40000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin + src_channel = 18'b10; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; + end + + // ( 0x40800 .. 0x41000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin + src_channel = 18'b01; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_addr_router_001.sv b/nios_system/synthesis/submodules/nios_system_addr_router_001.sv new file mode 100644 index 0000000..7b8c2d0 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_addr_router_001.sv @@ -0,0 +1,336 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_addr_router_001_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 15 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_addr_router_001 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h40000 - 64'h0); + localparam PAD1 = log2ceil(64'h41000 - 64'h40800); + localparam PAD2 = log2ceil(64'h41020 - 64'h41010); + localparam PAD3 = log2ceil(64'h41030 - 64'h41020); + localparam PAD4 = log2ceil(64'h41040 - 64'h41030); + localparam PAD5 = log2ceil(64'h41050 - 64'h41040); + localparam PAD6 = log2ceil(64'h41060 - 64'h41050); + localparam PAD7 = log2ceil(64'h41070 - 64'h41060); + localparam PAD8 = log2ceil(64'h41080 - 64'h41070); + localparam PAD9 = log2ceil(64'h41090 - 64'h41080); + localparam PAD10 = log2ceil(64'h410a0 - 64'h41090); + localparam PAD11 = log2ceil(64'h410b0 - 64'h410a0); + localparam PAD12 = log2ceil(64'h410c0 - 64'h410b0); + localparam PAD13 = log2ceil(64'h410d0 - 64'h410c0); + localparam PAD14 = log2ceil(64'h410e0 - 64'h410d0); + localparam PAD15 = log2ceil(64'h410f0 - 64'h410e0); + localparam PAD16 = log2ceil(64'h41100 - 64'h410f0); + localparam PAD17 = log2ceil(64'h41108 - 64'h41100); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h41108; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_addr_router_001_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x40000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin + src_channel = 18'b000000000000000010; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; + end + + // ( 0x40800 .. 0x41000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin + src_channel = 18'b000000000000000001; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; + end + + // ( 0x41010 .. 0x41020 ) + if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h41010 ) begin + src_channel = 18'b010000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13; + end + + // ( 0x41020 .. 0x41030 ) + if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h41020 ) begin + src_channel = 18'b100000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12; + end + + // ( 0x41030 .. 0x41040 ) + if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h41030 ) begin + src_channel = 18'b001000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11; + end + + // ( 0x41040 .. 0x41050 ) + if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h41040 ) begin + src_channel = 18'b000100000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; + end + + // ( 0x41050 .. 0x41060 ) + if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h41050 ) begin + src_channel = 18'b000010000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; + end + + // ( 0x41060 .. 0x41070 ) + if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h41060 ) begin + src_channel = 18'b000001000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; + end + + // ( 0x41070 .. 0x41080 ) + if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h41070 ) begin + src_channel = 18'b000000100000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; + end + + // ( 0x41080 .. 0x41090 ) + if ( {address[RG:PAD9],{PAD9{1'b0}}} == 19'h41080 ) begin + src_channel = 18'b000000010000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; + end + + // ( 0x41090 .. 0x410a0 ) + if ( {address[RG:PAD10],{PAD10{1'b0}}} == 19'h41090 ) begin + src_channel = 18'b000000001000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; + end + + // ( 0x410a0 .. 0x410b0 ) + if ( {address[RG:PAD11],{PAD11{1'b0}}} == 19'h410a0 ) begin + src_channel = 18'b000000000100000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; + end + + // ( 0x410b0 .. 0x410c0 ) + if ( {address[RG:PAD12],{PAD12{1'b0}}} == 19'h410b0 ) begin + src_channel = 18'b000000000010000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; + end + + // ( 0x410c0 .. 0x410d0 ) + if ( {address[RG:PAD13],{PAD13{1'b0}}} == 19'h410c0 ) begin + src_channel = 18'b000000000001000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16; + end + + // ( 0x410d0 .. 0x410e0 ) + if ( {address[RG:PAD14],{PAD14{1'b0}}} == 19'h410d0 ) begin + src_channel = 18'b000000000000100000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17; + end + + // ( 0x410e0 .. 0x410f0 ) + if ( {address[RG:PAD15],{PAD15{1'b0}}} == 19'h410e0 ) begin + src_channel = 18'b000000000000010000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; + end + + // ( 0x410f0 .. 0x41100 ) + if ( {address[RG:PAD16],{PAD16{1'b0}}} == 19'h410f0 ) begin + src_channel = 18'b000000000000000100; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x41100 .. 0x41108 ) + if ( {address[RG:PAD17],{PAD17{1'b0}}} == 19'h41100 ) begin + src_channel = 18'b000000000000001000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv new file mode 100644 index 0000000..0aef300 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv @@ -0,0 +1,116 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_demux +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_cmd_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv new file mode 100644 index 0000000..433e8d0 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv @@ -0,0 +1,356 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_demux_001 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 18 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_cmd_xbar_demux_001 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + output reg src2_valid, + output reg [96-1 : 0] src2_data, // ST_DATA_W=96 + output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18 + output reg src2_startofpacket, + output reg src2_endofpacket, + input src2_ready, + + output reg src3_valid, + output reg [96-1 : 0] src3_data, // ST_DATA_W=96 + output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18 + output reg src3_startofpacket, + output reg src3_endofpacket, + input src3_ready, + + output reg src4_valid, + output reg [96-1 : 0] src4_data, // ST_DATA_W=96 + output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18 + output reg src4_startofpacket, + output reg src4_endofpacket, + input src4_ready, + + output reg src5_valid, + output reg [96-1 : 0] src5_data, // ST_DATA_W=96 + output reg [18-1 : 0] src5_channel, // ST_CHANNEL_W=18 + output reg src5_startofpacket, + output reg src5_endofpacket, + input src5_ready, + + output reg src6_valid, + output reg [96-1 : 0] src6_data, // ST_DATA_W=96 + output reg [18-1 : 0] src6_channel, // ST_CHANNEL_W=18 + output reg src6_startofpacket, + output reg src6_endofpacket, + input src6_ready, + + output reg src7_valid, + output reg [96-1 : 0] src7_data, // ST_DATA_W=96 + output reg [18-1 : 0] src7_channel, // ST_CHANNEL_W=18 + output reg src7_startofpacket, + output reg src7_endofpacket, + input src7_ready, + + output reg src8_valid, + output reg [96-1 : 0] src8_data, // ST_DATA_W=96 + output reg [18-1 : 0] src8_channel, // ST_CHANNEL_W=18 + output reg src8_startofpacket, + output reg src8_endofpacket, + input src8_ready, + + output reg src9_valid, + output reg [96-1 : 0] src9_data, // ST_DATA_W=96 + output reg [18-1 : 0] src9_channel, // ST_CHANNEL_W=18 + output reg src9_startofpacket, + output reg src9_endofpacket, + input src9_ready, + + output reg src10_valid, + output reg [96-1 : 0] src10_data, // ST_DATA_W=96 + output reg [18-1 : 0] src10_channel, // ST_CHANNEL_W=18 + output reg src10_startofpacket, + output reg src10_endofpacket, + input src10_ready, + + output reg src11_valid, + output reg [96-1 : 0] src11_data, // ST_DATA_W=96 + output reg [18-1 : 0] src11_channel, // ST_CHANNEL_W=18 + output reg src11_startofpacket, + output reg src11_endofpacket, + input src11_ready, + + output reg src12_valid, + output reg [96-1 : 0] src12_data, // ST_DATA_W=96 + output reg [18-1 : 0] src12_channel, // ST_CHANNEL_W=18 + output reg src12_startofpacket, + output reg src12_endofpacket, + input src12_ready, + + output reg src13_valid, + output reg [96-1 : 0] src13_data, // ST_DATA_W=96 + output reg [18-1 : 0] src13_channel, // ST_CHANNEL_W=18 + output reg src13_startofpacket, + output reg src13_endofpacket, + input src13_ready, + + output reg src14_valid, + output reg [96-1 : 0] src14_data, // ST_DATA_W=96 + output reg [18-1 : 0] src14_channel, // ST_CHANNEL_W=18 + output reg src14_startofpacket, + output reg src14_endofpacket, + input src14_ready, + + output reg src15_valid, + output reg [96-1 : 0] src15_data, // ST_DATA_W=96 + output reg [18-1 : 0] src15_channel, // ST_CHANNEL_W=18 + output reg src15_startofpacket, + output reg src15_endofpacket, + input src15_ready, + + output reg src16_valid, + output reg [96-1 : 0] src16_data, // ST_DATA_W=96 + output reg [18-1 : 0] src16_channel, // ST_CHANNEL_W=18 + output reg src16_startofpacket, + output reg src16_endofpacket, + input src16_ready, + + output reg src17_valid, + output reg [96-1 : 0] src17_data, // ST_DATA_W=96 + output reg [18-1 : 0] src17_channel, // ST_CHANNEL_W=18 + output reg src17_startofpacket, + output reg src17_endofpacket, + input src17_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 18; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + src2_data = sink_data; + src2_startofpacket = sink_startofpacket; + src2_endofpacket = sink_endofpacket; + src2_channel = sink_channel >> NUM_OUTPUTS; + + src2_valid = sink_channel[2] && sink_valid; + + src3_data = sink_data; + src3_startofpacket = sink_startofpacket; + src3_endofpacket = sink_endofpacket; + src3_channel = sink_channel >> NUM_OUTPUTS; + + src3_valid = sink_channel[3] && sink_valid; + + src4_data = sink_data; + src4_startofpacket = sink_startofpacket; + src4_endofpacket = sink_endofpacket; + src4_channel = sink_channel >> NUM_OUTPUTS; + + src4_valid = sink_channel[4] && sink_valid; + + src5_data = sink_data; + src5_startofpacket = sink_startofpacket; + src5_endofpacket = sink_endofpacket; + src5_channel = sink_channel >> NUM_OUTPUTS; + + src5_valid = sink_channel[5] && sink_valid; + + src6_data = sink_data; + src6_startofpacket = sink_startofpacket; + src6_endofpacket = sink_endofpacket; + src6_channel = sink_channel >> NUM_OUTPUTS; + + src6_valid = sink_channel[6] && sink_valid; + + src7_data = sink_data; + src7_startofpacket = sink_startofpacket; + src7_endofpacket = sink_endofpacket; + src7_channel = sink_channel >> NUM_OUTPUTS; + + src7_valid = sink_channel[7] && sink_valid; + + src8_data = sink_data; + src8_startofpacket = sink_startofpacket; + src8_endofpacket = sink_endofpacket; + src8_channel = sink_channel >> NUM_OUTPUTS; + + src8_valid = sink_channel[8] && sink_valid; + + src9_data = sink_data; + src9_startofpacket = sink_startofpacket; + src9_endofpacket = sink_endofpacket; + src9_channel = sink_channel >> NUM_OUTPUTS; + + src9_valid = sink_channel[9] && sink_valid; + + src10_data = sink_data; + src10_startofpacket = sink_startofpacket; + src10_endofpacket = sink_endofpacket; + src10_channel = sink_channel >> NUM_OUTPUTS; + + src10_valid = sink_channel[10] && sink_valid; + + src11_data = sink_data; + src11_startofpacket = sink_startofpacket; + src11_endofpacket = sink_endofpacket; + src11_channel = sink_channel >> NUM_OUTPUTS; + + src11_valid = sink_channel[11] && sink_valid; + + src12_data = sink_data; + src12_startofpacket = sink_startofpacket; + src12_endofpacket = sink_endofpacket; + src12_channel = sink_channel >> NUM_OUTPUTS; + + src12_valid = sink_channel[12] && sink_valid; + + src13_data = sink_data; + src13_startofpacket = sink_startofpacket; + src13_endofpacket = sink_endofpacket; + src13_channel = sink_channel >> NUM_OUTPUTS; + + src13_valid = sink_channel[13] && sink_valid; + + src14_data = sink_data; + src14_startofpacket = sink_startofpacket; + src14_endofpacket = sink_endofpacket; + src14_channel = sink_channel >> NUM_OUTPUTS; + + src14_valid = sink_channel[14] && sink_valid; + + src15_data = sink_data; + src15_startofpacket = sink_startofpacket; + src15_endofpacket = sink_endofpacket; + src15_channel = sink_channel >> NUM_OUTPUTS; + + src15_valid = sink_channel[15] && sink_valid; + + src16_data = sink_data; + src16_startofpacket = sink_startofpacket; + src16_endofpacket = sink_endofpacket; + src16_channel = sink_channel >> NUM_OUTPUTS; + + src16_valid = sink_channel[16] && sink_valid; + + src17_data = sink_data; + src17_startofpacket = sink_startofpacket; + src17_endofpacket = sink_endofpacket; + src17_channel = sink_channel >> NUM_OUTPUTS; + + src17_valid = sink_channel[17] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + assign ready_vector[2] = src2_ready; + assign ready_vector[3] = src3_ready; + assign ready_vector[4] = src4_ready; + assign ready_vector[5] = src5_ready; + assign ready_vector[6] = src6_ready; + assign ready_vector[7] = src7_ready; + assign ready_vector[8] = src8_ready; + assign ready_vector[9] = src9_ready; + assign ready_vector[10] = src10_ready; + assign ready_vector[11] = src11_ready; + assign ready_vector[12] = src12_ready; + assign ready_vector[13] = src13_ready; + assign ready_vector[14] = src14_ready; + assign ready_vector[15] = src15_ready; + assign ready_vector[16] = src16_ready; + assign ready_vector[17] = src17_ready; + + assign sink_ready = |(sink_channel & ready_vector); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv new file mode 100644 index 0000000..76ec5b4 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv @@ -0,0 +1,308 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 1 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_cmd_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 1; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + wire [NUM_INPUTS - 1 : 0] eop; + assign eop[0] = sink0_endofpacket; + assign eop[1] = sink1_endofpacket; + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + end + reg [NUM_INPUTS - 1 : 0] locked = '0; + always @(posedge clk or posedge reset) begin + if (reset) begin + locked <= '0; + end + else begin + locked <= next_grant & lock; + end + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (update_grant) begin + share_count <= next_grant_share; + share_count_zero_flag <= (next_grant_share == '0); + end + else if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // The pipeline delays grant by one cycle, so + // we have to calculate the update_grant signal + // one cycle ahead of time. + // + // Possible optimization: omit the first clause + // "if (!packet_in_progress & ~src_valid) ..." + // cost: one idle cycle at the the beginning of each + // grant cycle. + // benefit: save a small amount of logic. + // ------------------------------------------ + if (!packet_in_progress & !src_valid) + update_grant = 1; + if (last_cycle && share_count_zero_flag) + update_grant = 1; + end + + wire save_grant; + assign save_grant = update_grant; + assign grant = saved_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] prev_request; + always @(posedge clk, posedge reset) begin + if (reset) + prev_request <= '0; + else + prev_request <= request & ~(valid & eop); + end + + assign request = (PIPELINE_ARB == 1) ? valid | locked : + prev_request | valid | locked; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("round-robin"), + .PIPELINE (1) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/nios_system/synthesis/submodules/nios_system_hex0.v b/nios_system/synthesis/submodules/nios_system_hex0.v new file mode 100644 index 0000000..365eed9 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_hex0.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_hex0 ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 6: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 6: 0] data_out; + wire [ 6: 0] out_port; + wire [ 6: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {7 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[6 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_id_router.sv b/nios_system/synthesis/submodules/nios_system_id_router.sv new file mode 100644 index 0000000..90937e8 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_id_router.sv @@ -0,0 +1,221 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 1 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 1 ) begin + src_channel = 18'b01; + end + + if (destid == 0 ) begin + src_channel = 18'b10; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_id_router_002.sv b/nios_system/synthesis/submodules/nios_system_id_router_002.sv new file mode 100644 index 0000000..a80e831 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_id_router_002.sv @@ -0,0 +1,217 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_002_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router_002 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_002_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 18'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_id_router_003.sv b/nios_system/synthesis/submodules/nios_system_id_router_003.sv new file mode 100644 index 0000000..5eb343c --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_id_router_003.sv @@ -0,0 +1,217 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_003_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router_003 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_003_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 18'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_irq_mapper.sv b/nios_system/synthesis/submodules/nios_system_irq_mapper.sv new file mode 100644 index 0000000..cc0a8bb --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_irq_mapper.sv @@ -0,0 +1,59 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Altera IRQ Mapper +// +// Parameters +// NUM_RCVRS : 1 +// SENDER_IRW_WIDTH : 32 +// IRQ_MAP : 0:5 +// +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_irq_mapper +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // IRQ Receivers + // ------------------- + input receiver0_irq, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg [31 : 0] sender_irq +); + + + always @* begin + sender_irq = 0; + + sender_irq[5] = receiver0_irq; + end + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_jtag_uart.v b/nios_system/synthesis/submodules/nios_system_jtag_uart.v new file mode 100644 index 0000000..0d02445 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_jtag_uart.v @@ -0,0 +1,583 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_sim_scfifo_w ( + // inputs: + clk, + fifo_wdata, + fifo_wr, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input [ 7: 0] fifo_wdata; + input fifo_wr; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + always @(posedge clk) + begin + if (fifo_wr) + $write("%c", fifo_wdata); + end + + + assign wfifo_used = {6{1'b0}}; + assign r_dat = {8{1'b0}}; + assign fifo_FF = 1'b0; + assign wfifo_empty = 1'b1; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_scfifo_w ( + // inputs: + clk, + fifo_clear, + fifo_wdata, + fifo_wr, + rd_wfifo, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input fifo_clear; + input [ 7: 0] fifo_wdata; + input fifo_wr; + input rd_wfifo; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo wfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (fifo_wdata), +// .empty (wfifo_empty), +// .full (fifo_FF), +// .q (r_dat), +// .rdreq (rd_wfifo), +// .usedw (wfifo_used), +// .wrreq (fifo_wr) +// ); +// +// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// wfifo.lpm_numwords = 64, +// wfifo.lpm_showahead = "OFF", +// wfifo.lpm_type = "scfifo", +// wfifo.lpm_width = 8, +// wfifo.lpm_widthu = 6, +// wfifo.overflow_checking = "OFF", +// wfifo.underflow_checking = "OFF", +// wfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_sim_scfifo_r ( + // inputs: + clk, + fifo_rd, + rst_n, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_rd; + input rst_n; + + reg [ 31: 0] bytes_left; + wire fifo_EF; + reg fifo_rd_d; + wire [ 7: 0] fifo_rdata; + wire new_rom; + wire [ 31: 0] num_bytes; + wire [ 6: 0] rfifo_entries; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Generate rfifo_entries for simulation + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + bytes_left <= 32'h0; + fifo_rd_d <= 1'b0; + end + else + begin + fifo_rd_d <= fifo_rd; + // decrement on read + if (fifo_rd_d) + bytes_left <= bytes_left - 1'b1; + // catch new contents + if (new_rom) + bytes_left <= num_bytes; + end + end + + + assign fifo_EF = bytes_left == 32'b0; + assign rfifo_full = bytes_left > 7'h40; + assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; + assign rfifo_used = rfifo_entries[5 : 0]; + assign new_rom = 1'b0; + assign num_bytes = 32'b0; + assign fifo_rdata = 8'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_scfifo_r ( + // inputs: + clk, + fifo_clear, + fifo_rd, + rst_n, + t_dat, + wr_rfifo, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_clear; + input fifo_rd; + input rst_n; + input [ 7: 0] t_dat; + input wr_rfifo; + + wire fifo_EF; + wire [ 7: 0] fifo_rdata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo rfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (t_dat), +// .empty (fifo_EF), +// .full (rfifo_full), +// .q (fifo_rdata), +// .rdreq (fifo_rd), +// .usedw (rfifo_used), +// .wrreq (wr_rfifo) +// ); +// +// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// rfifo.lpm_numwords = 64, +// rfifo.lpm_showahead = "OFF", +// rfifo.lpm_type = "scfifo", +// rfifo.lpm_width = 8, +// rfifo.lpm_widthu = 6, +// rfifo.overflow_checking = "OFF", +// rfifo.underflow_checking = "OFF", +// rfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart ( + // inputs: + av_address, + av_chipselect, + av_read_n, + av_write_n, + av_writedata, + clk, + rst_n, + + // outputs: + av_irq, + av_readdata, + av_waitrequest, + dataavailable, + readyfordata + ) + /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; + + output av_irq; + output [ 31: 0] av_readdata; + output av_waitrequest; + output dataavailable; + output readyfordata; + input av_address; + input av_chipselect; + input av_read_n; + input av_write_n; + input [ 31: 0] av_writedata; + input clk; + input rst_n; + + reg ac; + wire activity; + wire av_irq; + wire [ 31: 0] av_readdata; + reg av_waitrequest; + reg dataavailable; + reg fifo_AE; + reg fifo_AF; + wire fifo_EF; + wire fifo_FF; + wire fifo_clear; + wire fifo_rd; + wire [ 7: 0] fifo_rdata; + wire [ 7: 0] fifo_wdata; + reg fifo_wr; + reg ien_AE; + reg ien_AF; + wire ipen_AE; + wire ipen_AF; + reg pause_irq; + wire [ 7: 0] r_dat; + wire r_ena; + reg r_val; + wire rd_wfifo; + reg read_0; + reg readyfordata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + reg rvalid; + reg sim_r_ena; + reg sim_t_dat; + reg sim_t_ena; + reg sim_t_pause; + wire [ 7: 0] t_dat; + reg t_dav; + wire t_ena; + wire t_pause; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + reg woverflow; + wire wr_rfifo; + //avalon_jtag_slave, which is an e_avalon_slave + assign rd_wfifo = r_ena & ~wfifo_empty; + assign wr_rfifo = t_ena & ~rfifo_full; + assign fifo_clear = ~rst_n; + nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_clear (fifo_clear), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .rd_wfifo (rd_wfifo), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_clear (fifo_clear), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n), + .t_dat (t_dat), + .wr_rfifo (wr_rfifo) + ); + + assign ipen_AE = ien_AE & fifo_AE; + assign ipen_AF = ien_AF & (pause_irq | fifo_AF); + assign av_irq = ipen_AE | ipen_AF; + assign activity = t_pause | t_ena; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + pause_irq <= 1'b0; + else // only if fifo is not empty... + if (t_pause & ~fifo_EF) + pause_irq <= 1'b1; + else if (read_0) + pause_irq <= 1'b0; + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + r_val <= 1'b0; + t_dav <= 1'b1; + end + else + begin + r_val <= r_ena & ~wfifo_empty; + t_dav <= ~rfifo_full; + end + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + fifo_AE <= 1'b0; + fifo_AF <= 1'b0; + fifo_wr <= 1'b0; + rvalid <= 1'b0; + read_0 <= 1'b0; + ien_AE <= 1'b0; + ien_AF <= 1'b0; + ac <= 1'b0; + woverflow <= 1'b0; + av_waitrequest <= 1'b1; + end + else + begin + fifo_AE <= {fifo_FF,wfifo_used} <= 8; + fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; + fifo_wr <= 1'b0; + read_0 <= 1'b0; + av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); + if (activity) + ac <= 1'b1; + // write + if (av_chipselect & ~av_write_n & av_waitrequest) + // addr 1 is control; addr 0 is data + if (av_address) + begin + ien_AF <= av_writedata[0]; + ien_AE <= av_writedata[1]; + if (av_writedata[10] & ~activity) + ac <= 1'b0; + end + else + begin + fifo_wr <= ~fifo_FF; + woverflow <= fifo_FF; + end + // read + if (av_chipselect & ~av_read_n & av_waitrequest) + begin + // addr 1 is interrupt; addr 0 is data + if (~av_address) + rvalid <= ~fifo_EF; + read_0 <= ~av_address; + end + end + end + + + assign fifo_wdata = av_writedata[7 : 0]; + assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; + assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + readyfordata <= 0; + else + readyfordata <= ~fifo_FF; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Tie off Atlantic Interface signals not used for simulation + always @(posedge clk) + begin + sim_t_pause <= 1'b0; + sim_t_ena <= 1'b0; + sim_t_dat <= t_dav ? r_dat : {8{r_val}}; + sim_r_ena <= 1'b0; + end + + + assign r_ena = sim_r_ena; + assign t_ena = sim_t_ena; + assign t_dat = sim_t_dat; + assign t_pause = sim_t_pause; + always @(fifo_EF) + begin + dataavailable = ~fifo_EF; + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic +// ( +// .clk (clk), +// .r_dat (r_dat), +// .r_ena (r_ena), +// .r_val (r_val), +// .rst_n (rst_n), +// .t_dat (t_dat), +// .t_dav (t_dav), +// .t_ena (t_ena), +// .t_pause (t_pause) +// ); +// +// defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, +// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, +// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, +// nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; +// +// always @(posedge clk or negedge rst_n) +// begin +// if (rst_n == 0) +// dataavailable <= 0; +// else +// dataavailable <= ~fifo_EF; +// end +// +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_lcd.v b/nios_system/synthesis/submodules/nios_system_lcd.v new file mode 100644 index 0000000..18c2d15 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_lcd.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd ( + // inputs: + address, + begintransfer, + clk, + read, + reset_n, + write, + writedata, + + // outputs: + LCD_E, + LCD_RS, + LCD_RW, + LCD_data, + readdata + ) +; + + output LCD_E; + output LCD_RS; + output LCD_RW; + inout [ 7: 0] LCD_data; + output [ 7: 0] readdata; + input [ 1: 0] address; + input begintransfer; + input clk; + input read; + input reset_n; + input write; + input [ 7: 0] writedata; + + wire LCD_E; + wire LCD_RS; + wire LCD_RW; + wire [ 7: 0] LCD_data; + wire [ 7: 0] readdata; + assign LCD_RW = address[0]; + assign LCD_RS = address[1]; + assign LCD_E = read | write; + assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; + assign readdata = LCD_data; + //control_slave, which is an e_avalon_slave + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v b/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v new file mode 100644 index 0000000..f58d30f --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_16207_0 ( + // inputs: + address, + begintransfer, + clk, + read, + reset_n, + write, + writedata, + + // outputs: + LCD_E, + LCD_RS, + LCD_RW, + LCD_data, + readdata + ) +; + + output LCD_E; + output LCD_RS; + output LCD_RW; + inout [ 7: 0] LCD_data; + output [ 7: 0] readdata; + input [ 1: 0] address; + input begintransfer; + input clk; + input read; + input reset_n; + input write; + input [ 7: 0] writedata; + + wire LCD_E; + wire LCD_RS; + wire LCD_RW; + wire [ 7: 0] LCD_data; + wire [ 7: 0] readdata; + assign LCD_RW = address[0]; + assign LCD_RS = address[1]; + assign LCD_E = read | write; + assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; + assign readdata = LCD_data; + //control_slave, which is an e_avalon_slave + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_lcd_E.v b/nios_system/synthesis/submodules/nios_system_lcd_E.v new file mode 100644 index 0000000..c5680d0 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_lcd_E.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_E ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_lcd_on.v b/nios_system/synthesis/submodules/nios_system_lcd_on.v new file mode 100644 index 0000000..4e9a8dc --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_lcd_on.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_on ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc b/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc new file mode 100644 index 0000000..4848c5a --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc @@ -0,0 +1,53 @@ +# Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +# use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any +# output files any of the foregoing (including device programming or +# simulation files), and any associated documentation or information are +# expressly subject to the terms and conditions of the Altera Program +# License Subscription Agreement or other applicable license agreement, +# including, without limitation, that your use is for the sole purpose +# of programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +#************************************************************** +# Timequest JTAG clock definition +# Uncommenting the following lines will define the JTAG +# clock in TimeQuest Timing Analyzer +#************************************************************** + +#create_clock -period 10MHz {altera_reserved_tck} +#set_clock_groups -asynchronous -group {altera_reserved_tck} + +#************************************************************** +# Set TCL Path Variables +#************************************************************** + +set nios_system_nios2_processor nios_system_nios2_processor:* +set nios_system_nios2_processor_oci nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci +set nios_system_nios2_processor_oci_break nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break +set nios_system_nios2_processor_ocimem nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem +set nios_system_nios2_processor_oci_debug nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug +set nios_system_nios2_processor_wrapper nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper +set nios_system_nios2_processor_jtag_tck nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck +set nios_system_nios2_processor_jtag_sysclk nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk +set nios_system_nios2_processor_oci_path [format "%s|%s" $nios_system_nios2_processor $nios_system_nios2_processor_oci] +set nios_system_nios2_processor_oci_break_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_break] +set nios_system_nios2_processor_ocimem_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_ocimem] +set nios_system_nios2_processor_oci_debug_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_debug] +set nios_system_nios2_processor_jtag_tck_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_tck] +set nios_system_nios2_processor_jtag_sysclk_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_sysclk] +set nios_system_nios2_processor_jtag_sr [format "%s|*sr" $nios_system_nios2_processor_jtag_tck_path] + +#************************************************************** +# Set False Paths +#************************************************************** + +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_break_path|break_readreg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|*resetlatch] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[33]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_ready] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[0]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_error] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[34]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_ocimem_path|*MonDReg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] +set_false_path -from *$nios_system_nios2_processor_jtag_sr* -to *$nios_system_nios2_processor_jtag_sysclk_path|*jdo* +set_false_path -from sld_hub:*|irf_reg* -to *$nios_system_nios2_processor_jtag_sysclk_path|ir* +set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios_system_nios2_processor_oci_debug_path|monitor_go diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor.v b/nios_system/synthesis/submodules/nios_system_nios2_processor.v new file mode 100644 index 0000000..7e8e063 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor.v @@ -0,0 +1,5672 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_register_bank_a_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_register_bank_b_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_debug ( + // inputs: + clk, + dbrk_break, + debugreq, + hbreak_enabled, + jdo, + jrst_n, + ocireg_ers, + ocireg_mrs, + reset, + st_ready_test_idle, + take_action_ocimem_a, + take_action_ocireg, + xbrk_break, + + // outputs: + debugack, + monitor_error, + monitor_go, + monitor_ready, + oci_hbreak_req, + resetlatch, + resetrequest + ) +; + + output debugack; + output monitor_error; + output monitor_go; + output monitor_ready; + output oci_hbreak_req; + output resetlatch; + output resetrequest; + input clk; + input dbrk_break; + input debugreq; + input hbreak_enabled; + input [ 37: 0] jdo; + input jrst_n; + input ocireg_ers; + input ocireg_mrs; + input reset; + input st_ready_test_idle; + input take_action_ocimem_a; + input take_action_ocireg; + input xbrk_break; + + reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire debugack; + reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire oci_hbreak_req; + wire reset_sync; + reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire unxcomplemented_resetxx0; + assign unxcomplemented_resetxx0 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer + ( + .clk (clk), + .din (reset), + .dout (reset_sync), + .reset_n (unxcomplemented_resetxx0) + ); + + defparam the_altera_std_synchronizer.depth = 2; + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + break_on_reset <= 1'b0; + resetrequest <= 1'b0; + jtag_break <= 1'b0; + end + else if (take_action_ocimem_a) + begin + resetrequest <= jdo[22]; + jtag_break <= jdo[21] ? 1 + : jdo[20] ? 0 + : jtag_break; + + break_on_reset <= jdo[19] ? 1 + : jdo[18] ? 0 + : break_on_reset; + + resetlatch <= jdo[24] ? 0 : resetlatch; + end + else if (reset_sync) + begin + jtag_break <= break_on_reset; + resetlatch <= 1; + end + else if (debugreq & ~debugack & break_on_reset) + jtag_break <= 1'b1; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + monitor_ready <= 1'b0; + monitor_error <= 1'b0; + monitor_go <= 1'b0; + end + else + begin + if (take_action_ocimem_a && jdo[25]) + monitor_ready <= 1'b0; + else if (take_action_ocireg && ocireg_mrs) + monitor_ready <= 1'b1; + if (take_action_ocimem_a && jdo[25]) + monitor_error <= 1'b0; + else if (take_action_ocireg && ocireg_ers) + monitor_error <= 1'b1; + if (take_action_ocimem_a && jdo[23]) + monitor_go <= 1'b1; + else if (st_ready_test_idle) + monitor_go <= 1'b0; + end + end + + + assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq; + assign debugack = ~hbreak_enabled; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_ociram_sp_ram_module ( + // inputs: + address, + byteenable, + clock, + data, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input [ 7: 0] address; + input [ 3: 0] byteenable; + input clock; + input [ 31: 0] data; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clock), + .data_a (data), + .q_a (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 256, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 8; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_ocimem ( + // inputs: + address, + byteenable, + clk, + debugaccess, + jdo, + jrst_n, + read, + take_action_ocimem_a, + take_action_ocimem_b, + take_no_action_ocimem_a, + write, + writedata, + + // outputs: + MonDReg, + ociram_readdata, + waitrequest + ) +; + + output [ 31: 0] MonDReg; + output [ 31: 0] ociram_readdata; + output waitrequest; + input [ 8: 0] address; + input [ 3: 0] byteenable; + input clk; + input debugaccess; + input [ 37: 0] jdo; + input jrst_n; + input read; + input take_action_ocimem_a; + input take_action_ocimem_b; + input take_no_action_ocimem_a; + input write; + input [ 31: 0] writedata; + + reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 8: 0] MonARegAddrInc; + wire MonARegAddrIncAccessingRAM; + reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire avalon_ram_wr; + wire [ 31: 0] cfgrom_readdata; + reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 7: 0] ociram_addr; + wire [ 3: 0] ociram_byteenable; + wire [ 31: 0] ociram_readdata; + wire [ 31: 0] ociram_wr_data; + wire ociram_wr_en; + reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + jtag_rd <= 1'b0; + jtag_rd_d1 <= 1'b0; + jtag_ram_wr <= 1'b0; + jtag_ram_rd <= 1'b0; + jtag_ram_rd_d1 <= 1'b0; + jtag_ram_access <= 1'b0; + MonAReg <= 0; + MonDReg <= 0; + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + else + begin + if (take_no_action_ocimem_a) + begin + MonAReg[10 : 2] <= MonARegAddrInc; + jtag_rd <= 1'b1; + jtag_ram_rd <= MonARegAddrIncAccessingRAM; + jtag_ram_access <= MonARegAddrIncAccessingRAM; + end + else if (take_action_ocimem_a) + begin + MonAReg[10 : 2] <= { jdo[17], + jdo[33 : 26] }; + + jtag_rd <= 1'b1; + jtag_ram_rd <= ~jdo[17]; + jtag_ram_access <= ~jdo[17]; + end + else if (take_action_ocimem_b) + begin + MonAReg[10 : 2] <= MonARegAddrInc; + MonDReg <= jdo[34 : 3]; + jtag_ram_wr <= MonARegAddrIncAccessingRAM; + jtag_ram_access <= MonARegAddrIncAccessingRAM; + end + else + begin + jtag_rd <= 0; + jtag_ram_wr <= 0; + jtag_ram_rd <= 0; + jtag_ram_access <= 0; + if (jtag_rd_d1) + MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata; + end + jtag_rd_d1 <= jtag_rd; + jtag_ram_rd_d1 <= jtag_ram_rd; + if (~waitrequest) + begin + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + else if (write) + waitrequest <= ~address[8] & jtag_ram_access; + else if (read) + begin + avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access); + waitrequest <= ~avalon_ociram_readdata_ready; + end + else + begin + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + end + end + + + assign MonARegAddrInc = MonAReg[10 : 2]+1; + assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8]; + assign avalon_ram_wr = write & ~address[8] & debugaccess; + assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0]; + assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata; + assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable; + assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr; +//nios_system_nios2_processor_ociram_sp_ram, which is an nios_sp_ram +nios_system_nios2_processor_ociram_sp_ram_module nios_system_nios2_processor_ociram_sp_ram + ( + .address (ociram_addr), + .byteenable (ociram_byteenable), + .clock (clk), + .data (ociram_wr_data), + .q (ociram_readdata), + .wren (ociram_wr_en) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.dat"; +`else +defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.mif"; +//synthesis read_comments_as_HDL off + assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : + (MonAReg[4 : 2] == 3'd1)? 32'h00001313 : + (MonAReg[4 : 2] == 3'd2)? 32'h00040000 : + (MonAReg[4 : 2] == 3'd3)? 32'h00000000 : + (MonAReg[4 : 2] == 3'd4)? 32'h20000000 : + (MonAReg[4 : 2] == 3'd5)? 32'h00000000 : + (MonAReg[4 : 2] == 3'd6)? 32'h00000000 : + 32'h00000000; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_avalon_reg ( + // inputs: + address, + clk, + debugaccess, + monitor_error, + monitor_go, + monitor_ready, + reset_n, + write, + writedata, + + // outputs: + oci_ienable, + oci_reg_readdata, + oci_single_step_mode, + ocireg_ers, + ocireg_mrs, + take_action_ocireg + ) +; + + output [ 31: 0] oci_ienable; + output [ 31: 0] oci_reg_readdata; + output oci_single_step_mode; + output ocireg_ers; + output ocireg_mrs; + output take_action_ocireg; + input [ 8: 0] address; + input clk; + input debugaccess; + input monitor_error; + input monitor_go; + input monitor_ready; + input reset_n; + input write; + input [ 31: 0] writedata; + + reg [ 31: 0] oci_ienable; + wire oci_reg_00_addressed; + wire oci_reg_01_addressed; + wire [ 31: 0] oci_reg_readdata; + reg oci_single_step_mode; + wire ocireg_ers; + wire ocireg_mrs; + wire ocireg_sstep; + wire take_action_oci_intr_mask_reg; + wire take_action_ocireg; + wire write_strobe; + assign oci_reg_00_addressed = address == 9'h100; + assign oci_reg_01_addressed = address == 9'h101; + assign write_strobe = write & debugaccess; + assign take_action_ocireg = write_strobe & oci_reg_00_addressed; + assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed; + assign ocireg_ers = writedata[1]; + assign ocireg_mrs = writedata[0]; + assign ocireg_sstep = writedata[3]; + assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go, + monitor_ready, monitor_error} : + oci_reg_01_addressed ? oci_ienable : + 32'b0; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + oci_single_step_mode <= 1'b0; + else if (take_action_ocireg) + oci_single_step_mode <= ocireg_sstep; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + oci_ienable <= 32'b00000000000000000000000000100000; + else if (take_action_oci_intr_mask_reg) + oci_ienable <= writedata | ~(32'b00000000000000000000000000100000); + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_break ( + // inputs: + clk, + dbrk_break, + dbrk_goto0, + dbrk_goto1, + jdo, + jrst_n, + reset_n, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + xbrk_goto0, + xbrk_goto1, + + // outputs: + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + trigbrktype, + trigger_state_0, + trigger_state_1, + xbrk_ctrl0, + xbrk_ctrl1, + xbrk_ctrl2, + xbrk_ctrl3 + ) +; + + output [ 31: 0] break_readreg; + output dbrk_hit0_latch; + output dbrk_hit1_latch; + output dbrk_hit2_latch; + output dbrk_hit3_latch; + output trigbrktype; + output trigger_state_0; + output trigger_state_1; + output [ 7: 0] xbrk_ctrl0; + output [ 7: 0] xbrk_ctrl1; + output [ 7: 0] xbrk_ctrl2; + output [ 7: 0] xbrk_ctrl3; + input clk; + input dbrk_break; + input dbrk_goto0; + input dbrk_goto1; + input [ 37: 0] jdo; + input jrst_n; + input reset_n; + input take_action_break_a; + input take_action_break_b; + input take_action_break_c; + input take_no_action_break_a; + input take_no_action_break_b; + input take_no_action_break_c; + input xbrk_goto0; + input xbrk_goto1; + + wire [ 3: 0] break_a_wpr; + wire [ 1: 0] break_a_wpr_high_bits; + wire [ 1: 0] break_a_wpr_low_bits; + wire [ 1: 0] break_b_rr; + wire [ 1: 0] break_c_rr; + reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire dbrk0_high_value; + wire dbrk0_low_value; + wire dbrk1_high_value; + wire dbrk1_low_value; + wire dbrk2_high_value; + wire dbrk2_low_value; + wire dbrk3_high_value; + wire dbrk3_low_value; + wire dbrk_hit0_latch; + wire dbrk_hit1_latch; + wire dbrk_hit2_latch; + wire dbrk_hit3_latch; + wire take_action_any_break; + reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg trigger_state; + wire trigger_state_0; + wire trigger_state_1; + wire [ 31: 0] xbrk0_value; + wire [ 31: 0] xbrk1_value; + wire [ 31: 0] xbrk2_value; + wire [ 31: 0] xbrk3_value; + reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + assign break_a_wpr = jdo[35 : 32]; + assign break_a_wpr_high_bits = break_a_wpr[3 : 2]; + assign break_a_wpr_low_bits = break_a_wpr[1 : 0]; + assign break_b_rr = jdo[33 : 32]; + assign break_c_rr = jdo[33 : 32]; + assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + xbrk_ctrl0 <= 0; + xbrk_ctrl1 <= 0; + xbrk_ctrl2 <= 0; + xbrk_ctrl3 <= 0; + trigbrktype <= 0; + end + else + begin + if (take_action_any_break) + trigbrktype <= 0; + else if (dbrk_break) + trigbrktype <= 1; + if (take_action_break_b) + begin + if ((break_b_rr == 2'b00) && (0 >= 1)) + begin + xbrk_ctrl0[0] <= jdo[27]; + xbrk_ctrl0[1] <= jdo[28]; + xbrk_ctrl0[2] <= jdo[29]; + xbrk_ctrl0[3] <= jdo[30]; + xbrk_ctrl0[4] <= jdo[21]; + xbrk_ctrl0[5] <= jdo[20]; + xbrk_ctrl0[6] <= jdo[19]; + xbrk_ctrl0[7] <= jdo[18]; + end + if ((break_b_rr == 2'b01) && (0 >= 2)) + begin + xbrk_ctrl1[0] <= jdo[27]; + xbrk_ctrl1[1] <= jdo[28]; + xbrk_ctrl1[2] <= jdo[29]; + xbrk_ctrl1[3] <= jdo[30]; + xbrk_ctrl1[4] <= jdo[21]; + xbrk_ctrl1[5] <= jdo[20]; + xbrk_ctrl1[6] <= jdo[19]; + xbrk_ctrl1[7] <= jdo[18]; + end + if ((break_b_rr == 2'b10) && (0 >= 3)) + begin + xbrk_ctrl2[0] <= jdo[27]; + xbrk_ctrl2[1] <= jdo[28]; + xbrk_ctrl2[2] <= jdo[29]; + xbrk_ctrl2[3] <= jdo[30]; + xbrk_ctrl2[4] <= jdo[21]; + xbrk_ctrl2[5] <= jdo[20]; + xbrk_ctrl2[6] <= jdo[19]; + xbrk_ctrl2[7] <= jdo[18]; + end + if ((break_b_rr == 2'b11) && (0 >= 4)) + begin + xbrk_ctrl3[0] <= jdo[27]; + xbrk_ctrl3[1] <= jdo[28]; + xbrk_ctrl3[2] <= jdo[29]; + xbrk_ctrl3[3] <= jdo[30]; + xbrk_ctrl3[4] <= jdo[21]; + xbrk_ctrl3[5] <= jdo[20]; + xbrk_ctrl3[6] <= jdo[19]; + xbrk_ctrl3[7] <= jdo[18]; + end + end + end + end + + + assign dbrk_hit0_latch = 1'b0; + assign dbrk0_low_value = 0; + assign dbrk0_high_value = 0; + assign dbrk_hit1_latch = 1'b0; + assign dbrk1_low_value = 0; + assign dbrk1_high_value = 0; + assign dbrk_hit2_latch = 1'b0; + assign dbrk2_low_value = 0; + assign dbrk2_high_value = 0; + assign dbrk_hit3_latch = 1'b0; + assign dbrk3_low_value = 0; + assign dbrk3_high_value = 0; + assign xbrk0_value = 32'b0; + assign xbrk1_value = 32'b0; + assign xbrk2_value = 32'b0; + assign xbrk3_value = 32'b0; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + break_readreg <= 32'b0; + else if (take_action_any_break) + break_readreg <= jdo[31 : 0]; + else if (take_no_action_break_a) + case (break_a_wpr_high_bits) + + 2'd0: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= xbrk0_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= xbrk1_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= xbrk2_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= xbrk3_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd0 + + 2'd1: begin + break_readreg <= 32'b0; + end // 2'd1 + + 2'd2: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= dbrk0_low_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= dbrk1_low_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= dbrk2_low_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= dbrk3_low_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd2 + + 2'd3: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= dbrk0_high_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= dbrk1_high_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= dbrk2_high_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= dbrk3_high_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd3 + + endcase // break_a_wpr_high_bits + else if (take_no_action_break_b) + break_readreg <= jdo[31 : 0]; + else if (take_no_action_break_c) + break_readreg <= jdo[31 : 0]; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + trigger_state <= 0; + else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0)) + trigger_state <= 0; + else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1)) + trigger_state <= -1; + end + + + assign trigger_state_0 = ~trigger_state; + assign trigger_state_1 = trigger_state; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_xbrk ( + // inputs: + D_valid, + E_valid, + F_pc, + clk, + reset_n, + trigger_state_0, + trigger_state_1, + xbrk_ctrl0, + xbrk_ctrl1, + xbrk_ctrl2, + xbrk_ctrl3, + + // outputs: + xbrk_break, + xbrk_goto0, + xbrk_goto1, + xbrk_traceoff, + xbrk_traceon, + xbrk_trigout + ) +; + + output xbrk_break; + output xbrk_goto0; + output xbrk_goto1; + output xbrk_traceoff; + output xbrk_traceon; + output xbrk_trigout; + input D_valid; + input E_valid; + input [ 16: 0] F_pc; + input clk; + input reset_n; + input trigger_state_0; + input trigger_state_1; + input [ 7: 0] xbrk_ctrl0; + input [ 7: 0] xbrk_ctrl1; + input [ 7: 0] xbrk_ctrl2; + input [ 7: 0] xbrk_ctrl3; + + wire D_cpu_addr_en; + wire E_cpu_addr_en; + reg E_xbrk_goto0; + reg E_xbrk_goto1; + reg E_xbrk_traceoff; + reg E_xbrk_traceon; + reg E_xbrk_trigout; + wire [ 18: 0] cpu_i_address; + wire xbrk0_armed; + wire xbrk0_break_hit; + wire xbrk0_goto0_hit; + wire xbrk0_goto1_hit; + wire xbrk0_toff_hit; + wire xbrk0_ton_hit; + wire xbrk0_tout_hit; + wire xbrk1_armed; + wire xbrk1_break_hit; + wire xbrk1_goto0_hit; + wire xbrk1_goto1_hit; + wire xbrk1_toff_hit; + wire xbrk1_ton_hit; + wire xbrk1_tout_hit; + wire xbrk2_armed; + wire xbrk2_break_hit; + wire xbrk2_goto0_hit; + wire xbrk2_goto1_hit; + wire xbrk2_toff_hit; + wire xbrk2_ton_hit; + wire xbrk2_tout_hit; + wire xbrk3_armed; + wire xbrk3_break_hit; + wire xbrk3_goto0_hit; + wire xbrk3_goto1_hit; + wire xbrk3_toff_hit; + wire xbrk3_ton_hit; + wire xbrk3_tout_hit; + reg xbrk_break; + wire xbrk_break_hit; + wire xbrk_goto0; + wire xbrk_goto0_hit; + wire xbrk_goto1; + wire xbrk_goto1_hit; + wire xbrk_toff_hit; + wire xbrk_ton_hit; + wire xbrk_tout_hit; + wire xbrk_traceoff; + wire xbrk_traceon; + wire xbrk_trigout; + assign cpu_i_address = {F_pc, 2'b00}; + assign D_cpu_addr_en = D_valid; + assign E_cpu_addr_en = E_valid; + assign xbrk0_break_hit = 0; + assign xbrk0_ton_hit = 0; + assign xbrk0_toff_hit = 0; + assign xbrk0_tout_hit = 0; + assign xbrk0_goto0_hit = 0; + assign xbrk0_goto1_hit = 0; + assign xbrk1_break_hit = 0; + assign xbrk1_ton_hit = 0; + assign xbrk1_toff_hit = 0; + assign xbrk1_tout_hit = 0; + assign xbrk1_goto0_hit = 0; + assign xbrk1_goto1_hit = 0; + assign xbrk2_break_hit = 0; + assign xbrk2_ton_hit = 0; + assign xbrk2_toff_hit = 0; + assign xbrk2_tout_hit = 0; + assign xbrk2_goto0_hit = 0; + assign xbrk2_goto1_hit = 0; + assign xbrk3_break_hit = 0; + assign xbrk3_ton_hit = 0; + assign xbrk3_toff_hit = 0; + assign xbrk3_tout_hit = 0; + assign xbrk3_goto0_hit = 0; + assign xbrk3_goto1_hit = 0; + assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit); + assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit); + assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit); + assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit); + assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit); + assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + xbrk_break <= 0; + else if (E_cpu_addr_en) + xbrk_break <= xbrk_break_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_traceon <= 0; + else if (E_cpu_addr_en) + E_xbrk_traceon <= xbrk_ton_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_traceoff <= 0; + else if (E_cpu_addr_en) + E_xbrk_traceoff <= xbrk_toff_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_trigout <= 0; + else if (E_cpu_addr_en) + E_xbrk_trigout <= xbrk_tout_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_goto0 <= 0; + else if (E_cpu_addr_en) + E_xbrk_goto0 <= xbrk_goto0_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_goto1 <= 0; + else if (E_cpu_addr_en) + E_xbrk_goto1 <= xbrk_goto1_hit; + end + + + assign xbrk_traceon = 1'b0; + assign xbrk_traceoff = 1'b0; + assign xbrk_trigout = 1'b0; + assign xbrk_goto0 = 1'b0; + assign xbrk_goto1 = 1'b0; + assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) || + (xbrk_ctrl0[5] & trigger_state_1); + + assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) || + (xbrk_ctrl1[5] & trigger_state_1); + + assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) || + (xbrk_ctrl2[5] & trigger_state_1); + + assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) || + (xbrk_ctrl3[5] & trigger_state_1); + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_dbrk ( + // inputs: + E_st_data, + av_ld_data_aligned_filtered, + clk, + d_address, + d_read, + d_waitrequest, + d_write, + debugack, + reset_n, + + // outputs: + cpu_d_address, + cpu_d_read, + cpu_d_readdata, + cpu_d_wait, + cpu_d_write, + cpu_d_writedata, + dbrk_break, + dbrk_goto0, + dbrk_goto1, + dbrk_traceme, + dbrk_traceoff, + dbrk_traceon, + dbrk_trigout + ) +; + + output [ 18: 0] cpu_d_address; + output cpu_d_read; + output [ 31: 0] cpu_d_readdata; + output cpu_d_wait; + output cpu_d_write; + output [ 31: 0] cpu_d_writedata; + output dbrk_break; + output dbrk_goto0; + output dbrk_goto1; + output dbrk_traceme; + output dbrk_traceoff; + output dbrk_traceon; + output dbrk_trigout; + input [ 31: 0] E_st_data; + input [ 31: 0] av_ld_data_aligned_filtered; + input clk; + input [ 18: 0] d_address; + input d_read; + input d_waitrequest; + input d_write; + input debugack; + input reset_n; + + wire [ 18: 0] cpu_d_address; + wire cpu_d_read; + wire [ 31: 0] cpu_d_readdata; + wire cpu_d_wait; + wire cpu_d_write; + wire [ 31: 0] cpu_d_writedata; + wire dbrk0_armed; + wire dbrk0_break_pulse; + wire dbrk0_goto0; + wire dbrk0_goto1; + wire dbrk0_traceme; + wire dbrk0_traceoff; + wire dbrk0_traceon; + wire dbrk0_trigout; + wire dbrk1_armed; + wire dbrk1_break_pulse; + wire dbrk1_goto0; + wire dbrk1_goto1; + wire dbrk1_traceme; + wire dbrk1_traceoff; + wire dbrk1_traceon; + wire dbrk1_trigout; + wire dbrk2_armed; + wire dbrk2_break_pulse; + wire dbrk2_goto0; + wire dbrk2_goto1; + wire dbrk2_traceme; + wire dbrk2_traceoff; + wire dbrk2_traceon; + wire dbrk2_trigout; + wire dbrk3_armed; + wire dbrk3_break_pulse; + wire dbrk3_goto0; + wire dbrk3_goto1; + wire dbrk3_traceme; + wire dbrk3_traceoff; + wire dbrk3_traceon; + wire dbrk3_trigout; + reg dbrk_break; + reg dbrk_break_pulse; + wire [ 31: 0] dbrk_data; + reg dbrk_goto0; + reg dbrk_goto1; + reg dbrk_traceme; + reg dbrk_traceoff; + reg dbrk_traceon; + reg dbrk_trigout; + assign cpu_d_address = d_address; + assign cpu_d_readdata = av_ld_data_aligned_filtered; + assign cpu_d_read = d_read; + assign cpu_d_writedata = E_st_data; + assign cpu_d_write = d_write; + assign cpu_d_wait = d_waitrequest; + assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + dbrk_break <= 0; + else + dbrk_break <= dbrk_break ? ~debugack + : dbrk_break_pulse; + + end + + + assign dbrk0_armed = 1'b0; + assign dbrk0_trigout = 1'b0; + assign dbrk0_break_pulse = 1'b0; + assign dbrk0_traceoff = 1'b0; + assign dbrk0_traceon = 1'b0; + assign dbrk0_traceme = 1'b0; + assign dbrk0_goto0 = 1'b0; + assign dbrk0_goto1 = 1'b0; + assign dbrk1_armed = 1'b0; + assign dbrk1_trigout = 1'b0; + assign dbrk1_break_pulse = 1'b0; + assign dbrk1_traceoff = 1'b0; + assign dbrk1_traceon = 1'b0; + assign dbrk1_traceme = 1'b0; + assign dbrk1_goto0 = 1'b0; + assign dbrk1_goto1 = 1'b0; + assign dbrk2_armed = 1'b0; + assign dbrk2_trigout = 1'b0; + assign dbrk2_break_pulse = 1'b0; + assign dbrk2_traceoff = 1'b0; + assign dbrk2_traceon = 1'b0; + assign dbrk2_traceme = 1'b0; + assign dbrk2_goto0 = 1'b0; + assign dbrk2_goto1 = 1'b0; + assign dbrk3_armed = 1'b0; + assign dbrk3_trigout = 1'b0; + assign dbrk3_break_pulse = 1'b0; + assign dbrk3_traceoff = 1'b0; + assign dbrk3_traceon = 1'b0; + assign dbrk3_traceme = 1'b0; + assign dbrk3_goto0 = 1'b0; + assign dbrk3_goto1 = 1'b0; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + dbrk_trigout <= 0; + dbrk_break_pulse <= 0; + dbrk_traceoff <= 0; + dbrk_traceon <= 0; + dbrk_traceme <= 0; + dbrk_goto0 <= 0; + dbrk_goto1 <= 0; + end + else + begin + dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout; + dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse; + dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff; + dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon; + dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme; + dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0; + dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1; + end + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_itrace ( + // inputs: + clk, + dbrk_traceoff, + dbrk_traceon, + jdo, + jrst_n, + take_action_tracectrl, + trc_enb, + xbrk_traceoff, + xbrk_traceon, + xbrk_wrap_traceoff, + + // outputs: + dct_buffer, + dct_count, + itm, + trc_ctrl, + trc_on + ) +; + + output [ 29: 0] dct_buffer; + output [ 3: 0] dct_count; + output [ 35: 0] itm; + output [ 15: 0] trc_ctrl; + output trc_on; + input clk; + input dbrk_traceoff; + input dbrk_traceon; + input [ 15: 0] jdo; + input jrst_n; + input take_action_tracectrl; + input trc_enb; + input xbrk_traceoff; + input xbrk_traceon; + input xbrk_wrap_traceoff; + + wire curr_pid; + reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 1: 0] dct_code; + reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire dct_is_taken; + wire [ 31: 0] excaddr; + wire instr_retired; + wire is_advanced_exception; + wire is_cond_dct; + wire is_dct; + wire is_exception_no_break; + wire is_fast_tlb_miss_exception; + wire is_idct; + reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire not_in_debug_mode; + reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire record_dct_outcome_in_sync; + wire record_itrace; + wire [ 31: 0] retired_pcb; + reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 1: 0] sync_code; + wire [ 6: 0] sync_interval; + wire sync_pending; + reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 6: 0] sync_timer_next; + reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire [ 15: 0] trc_ctrl; + reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire trc_on; + assign is_cond_dct = 1'b0; + assign is_dct = 1'b0; + assign dct_is_taken = 1'b0; + assign is_idct = 1'b0; + assign retired_pcb = 32'b0; + assign not_in_debug_mode = 1'b0; + assign instr_retired = 1'b0; + assign is_advanced_exception = 1'b0; + assign is_exception_no_break = 1'b0; + assign is_fast_tlb_miss_exception = 1'b0; + assign curr_pid = 1'b0; + assign excaddr = 32'b0; + assign sync_code = trc_ctrl[3 : 2]; + assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 }; + assign sync_pending = sync_timer == 0; + assign record_dct_outcome_in_sync = dct_is_taken & sync_pending; + assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1); + assign record_itrace = trc_on & trc_ctrl[4]; + assign dct_code = {is_cond_dct, dct_is_taken}; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + trc_clear <= 0; + else + trc_clear <= ~trc_enb & + take_action_tracectrl & jdo[4]; + + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + itm <= 0; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= 0; + pending_frametype <= 4'b0000; + pending_exctype <= 1'b0; + pending_excaddr <= 0; + prev_pid <= 0; + prev_pid_valid <= 0; + snapped_pid <= 0; + snapped_curr_pid <= 0; + snapped_prev_pid <= 0; + pending_curr_pid <= 0; + pending_prev_pid <= 0; + end + else if (trc_clear || (!0 && !0)) + begin + itm <= 0; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= 0; + pending_frametype <= 4'b0000; + pending_exctype <= 1'b0; + pending_excaddr <= 0; + prev_pid <= 0; + prev_pid_valid <= 0; + snapped_pid <= 0; + snapped_curr_pid <= 0; + snapped_prev_pid <= 0; + pending_curr_pid <= 0; + pending_prev_pid <= 0; + end + else + begin + if (!prev_pid_valid) + begin + prev_pid <= curr_pid; + prev_pid_valid <= 1; + end + if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid) + begin + snapped_pid <= 1; + snapped_curr_pid <= curr_pid; + snapped_prev_pid <= prev_pid; + prev_pid <= curr_pid; + prev_pid_valid <= 1; + end + if (instr_retired | is_advanced_exception) + begin + if (~record_itrace) + pending_frametype <= 4'b1010; + else if (is_exception_no_break) + begin + pending_frametype <= 4'b0010; + pending_excaddr <= excaddr; + if (is_fast_tlb_miss_exception) + pending_exctype <= 1'b1; + else + pending_exctype <= 1'b0; + end + else if (is_idct) + pending_frametype <= 4'b1001; + else if (record_dct_outcome_in_sync) + pending_frametype <= 4'b1000; + else if (!is_dct & snapped_pid) + begin + pending_frametype <= 4'b0011; + pending_curr_pid <= snapped_curr_pid; + pending_prev_pid <= snapped_prev_pid; + snapped_pid <= 0; + end + else + pending_frametype <= 4'b0000; + if ((dct_count != 0) & + (~record_itrace | + is_exception_no_break | + is_idct | + record_dct_outcome_in_sync | + (!is_dct & snapped_pid))) + begin + itm <= {4'b0001, dct_buffer, 2'b00}; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= sync_timer_next; + end + else + begin + if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception) + begin + dct_buffer <= {dct_code, dct_buffer[29 : 2]}; + dct_count <= dct_count + 1; + end + if (record_itrace & (pending_frametype == 4'b0010)) + itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype}; + else if (record_itrace & ( + (pending_frametype == 4'b1000) | + (pending_frametype == 4'b1010) | + (pending_frametype == 4'b1001))) + begin + itm <= {pending_frametype, retired_pcb}; + sync_timer <= sync_interval; + if (0 & + ((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) & + !snapped_pid & prev_pid_valid) + begin + snapped_pid <= 1; + snapped_curr_pid <= curr_pid; + snapped_prev_pid <= prev_pid; + end + end + else if (record_itrace & + 0 & (pending_frametype == 4'b0011)) + itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid}; + else if (record_itrace & is_dct) + begin + if (dct_count == 4'd15) + begin + itm <= {4'b0001, dct_code, dct_buffer}; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= sync_timer_next; + end + else + itm <= 4'b0000; + end + else + itm <= {4'b0000, 32'b0}; + end + end + else + itm <= {4'b0000, 32'b0}; + end + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + trc_ctrl_reg[0] <= 1'b0; + trc_ctrl_reg[1] <= 1'b0; + trc_ctrl_reg[3 : 2] <= 2'b00; + trc_ctrl_reg[4] <= 1'b0; + trc_ctrl_reg[7 : 5] <= 3'b000; + trc_ctrl_reg[8] <= 0; + trc_ctrl_reg[9] <= 1'b0; + trc_ctrl_reg[10] <= 1'b0; + end + else if (take_action_tracectrl) + begin + trc_ctrl_reg[0] <= jdo[5]; + trc_ctrl_reg[1] <= jdo[6]; + trc_ctrl_reg[3 : 2] <= jdo[8 : 7]; + trc_ctrl_reg[4] <= jdo[9]; + trc_ctrl_reg[9] <= jdo[14]; + trc_ctrl_reg[10] <= jdo[2]; + if (0) + trc_ctrl_reg[7 : 5] <= jdo[12 : 10]; + if (0 & 0) + trc_ctrl_reg[8] <= jdo[13]; + end + else if (xbrk_wrap_traceoff) + begin + trc_ctrl_reg[1] <= 0; + trc_ctrl_reg[0] <= 0; + end + else if (dbrk_traceoff | xbrk_traceoff) + trc_ctrl_reg[1] <= 0; + else if (trc_ctrl_reg[0] & + (dbrk_traceon | xbrk_traceon)) + trc_ctrl_reg[1] <= 1; + end + + + assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0; + assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode); + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_td_mode ( + // inputs: + ctrl, + + // outputs: + td_mode + ) +; + + output [ 3: 0] td_mode; + input [ 8: 0] ctrl; + + wire [ 2: 0] ctrl_bits_for_mux; + reg [ 3: 0] td_mode; + assign ctrl_bits_for_mux = ctrl[7 : 5]; + always @(ctrl_bits_for_mux) + begin + case (ctrl_bits_for_mux) + + 3'b000: begin + td_mode = 4'b0000; + end // 3'b000 + + 3'b001: begin + td_mode = 4'b1000; + end // 3'b001 + + 3'b010: begin + td_mode = 4'b0100; + end // 3'b010 + + 3'b011: begin + td_mode = 4'b1100; + end // 3'b011 + + 3'b100: begin + td_mode = 4'b0010; + end // 3'b100 + + 3'b101: begin + td_mode = 4'b1010; + end // 3'b101 + + 3'b110: begin + td_mode = 4'b0101; + end // 3'b110 + + 3'b111: begin + td_mode = 4'b1111; + end // 3'b111 + + endcase // ctrl_bits_for_mux + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_dtrace ( + // inputs: + clk, + cpu_d_address, + cpu_d_read, + cpu_d_readdata, + cpu_d_wait, + cpu_d_write, + cpu_d_writedata, + jrst_n, + trc_ctrl, + + // outputs: + atm, + dtm + ) +; + + output [ 35: 0] atm; + output [ 35: 0] dtm; + input clk; + input [ 18: 0] cpu_d_address; + input cpu_d_read; + input [ 31: 0] cpu_d_readdata; + input cpu_d_wait; + input cpu_d_write; + input [ 31: 0] cpu_d_writedata; + input jrst_n; + input [ 15: 0] trc_ctrl; + + reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 31: 0] cpu_d_address_0_padded; + wire [ 31: 0] cpu_d_readdata_0_padded; + wire [ 31: 0] cpu_d_writedata_0_padded; + reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire record_load_addr; + wire record_load_data; + wire record_store_addr; + wire record_store_data; + wire [ 3: 0] td_mode_trc_ctrl; + assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0; + assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0; + assign cpu_d_address_0_padded = cpu_d_address | 32'b0; + //nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode, which is an e_instance + nios_system_nios2_processor_nios2_oci_td_mode nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode + ( + .ctrl (trc_ctrl[8 : 0]), + .td_mode (td_mode_trc_ctrl) + ); + + assign {record_load_addr, record_store_addr, + record_load_data, record_store_data} = td_mode_trc_ctrl; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + atm <= 0; + dtm <= 0; + end + else if (0) + begin + if (cpu_d_write & ~cpu_d_wait & record_store_addr) + atm <= {4'b0101, cpu_d_address_0_padded}; + else if (cpu_d_read & ~cpu_d_wait & record_load_addr) + atm <= {4'b0100, cpu_d_address_0_padded}; + else + atm <= {4'b0000, cpu_d_address_0_padded}; + if (cpu_d_write & ~cpu_d_wait & record_store_data) + dtm <= {4'b0111, cpu_d_writedata_0_padded}; + else if (cpu_d_read & ~cpu_d_wait & record_load_data) + dtm <= {4'b0110, cpu_d_readdata_0_padded}; + else + dtm <= {4'b0000, cpu_d_readdata_0_padded}; + end + else + begin + atm <= 0; + dtm <= 0; + end + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_compute_tm_count ( + // inputs: + atm_valid, + dtm_valid, + itm_valid, + + // outputs: + compute_tm_count + ) +; + + output [ 1: 0] compute_tm_count; + input atm_valid; + input dtm_valid; + input itm_valid; + + reg [ 1: 0] compute_tm_count; + wire [ 2: 0] switch_for_mux; + assign switch_for_mux = {itm_valid, atm_valid, dtm_valid}; + always @(switch_for_mux) + begin + case (switch_for_mux) + + 3'b000: begin + compute_tm_count = 0; + end // 3'b000 + + 3'b001: begin + compute_tm_count = 1; + end // 3'b001 + + 3'b010: begin + compute_tm_count = 1; + end // 3'b010 + + 3'b011: begin + compute_tm_count = 2; + end // 3'b011 + + 3'b100: begin + compute_tm_count = 1; + end // 3'b100 + + 3'b101: begin + compute_tm_count = 2; + end // 3'b101 + + 3'b110: begin + compute_tm_count = 2; + end // 3'b110 + + 3'b111: begin + compute_tm_count = 3; + end // 3'b111 + + endcase // switch_for_mux + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifowp_inc ( + // inputs: + free2, + free3, + tm_count, + + // outputs: + fifowp_inc + ) +; + + output [ 3: 0] fifowp_inc; + input free2; + input free3; + input [ 1: 0] tm_count; + + reg [ 3: 0] fifowp_inc; + always @(free2 or free3 or tm_count) + begin + if (free3 & (tm_count == 3)) + fifowp_inc = 3; + else if (free2 & (tm_count >= 2)) + fifowp_inc = 2; + else if (tm_count >= 1) + fifowp_inc = 1; + else + fifowp_inc = 0; + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifocount_inc ( + // inputs: + empty, + free2, + free3, + tm_count, + + // outputs: + fifocount_inc + ) +; + + output [ 4: 0] fifocount_inc; + input empty; + input free2; + input free3; + input [ 1: 0] tm_count; + + reg [ 4: 0] fifocount_inc; + always @(empty or free2 or free3 or tm_count) + begin + if (empty) + fifocount_inc = tm_count[1 : 0]; + else if (free3 & (tm_count == 3)) + fifocount_inc = 2; + else if (free2 & (tm_count >= 2)) + fifocount_inc = 1; + else if (tm_count >= 1) + fifocount_inc = 0; + else + fifocount_inc = {5{1'b1}}; + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifo ( + // inputs: + atm, + clk, + dbrk_traceme, + dbrk_traceoff, + dbrk_traceon, + dct_buffer, + dct_count, + dtm, + itm, + jrst_n, + reset_n, + test_ending, + test_has_ended, + trc_on, + + // outputs: + tw + ) +; + + output [ 35: 0] tw; + input [ 35: 0] atm; + input clk; + input dbrk_traceme; + input dbrk_traceoff; + input dbrk_traceon; + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input [ 35: 0] dtm; + input [ 35: 0] itm; + input jrst_n; + input reset_n; + input test_ending; + input test_has_ended; + input trc_on; + + wire atm_valid; + wire [ 1: 0] compute_tm_count_tm_count; + wire dtm_valid; + wire empty; + reg [ 35: 0] fifo_0; + wire fifo_0_enable; + wire [ 35: 0] fifo_0_mux; + reg [ 35: 0] fifo_1; + reg [ 35: 0] fifo_10; + wire fifo_10_enable; + wire [ 35: 0] fifo_10_mux; + reg [ 35: 0] fifo_11; + wire fifo_11_enable; + wire [ 35: 0] fifo_11_mux; + reg [ 35: 0] fifo_12; + wire fifo_12_enable; + wire [ 35: 0] fifo_12_mux; + reg [ 35: 0] fifo_13; + wire fifo_13_enable; + wire [ 35: 0] fifo_13_mux; + reg [ 35: 0] fifo_14; + wire fifo_14_enable; + wire [ 35: 0] fifo_14_mux; + reg [ 35: 0] fifo_15; + wire fifo_15_enable; + wire [ 35: 0] fifo_15_mux; + wire fifo_1_enable; + wire [ 35: 0] fifo_1_mux; + reg [ 35: 0] fifo_2; + wire fifo_2_enable; + wire [ 35: 0] fifo_2_mux; + reg [ 35: 0] fifo_3; + wire fifo_3_enable; + wire [ 35: 0] fifo_3_mux; + reg [ 35: 0] fifo_4; + wire fifo_4_enable; + wire [ 35: 0] fifo_4_mux; + reg [ 35: 0] fifo_5; + wire fifo_5_enable; + wire [ 35: 0] fifo_5_mux; + reg [ 35: 0] fifo_6; + wire fifo_6_enable; + wire [ 35: 0] fifo_6_mux; + reg [ 35: 0] fifo_7; + wire fifo_7_enable; + wire [ 35: 0] fifo_7_mux; + reg [ 35: 0] fifo_8; + wire fifo_8_enable; + wire [ 35: 0] fifo_8_mux; + reg [ 35: 0] fifo_9; + wire fifo_9_enable; + wire [ 35: 0] fifo_9_mux; + wire [ 35: 0] fifo_read_mux; + reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 4: 0] fifocount_inc_fifocount; + wire [ 35: 0] fifohead; + reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 3: 0] fifowp1; + wire [ 3: 0] fifowp2; + wire [ 3: 0] fifowp_inc_fifowp; + wire free2; + wire free3; + wire itm_valid; + reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 35: 0] ovr_pending_atm; + wire [ 35: 0] ovr_pending_dtm; + wire [ 1: 0] tm_count; + wire tm_count_ge1; + wire tm_count_ge2; + wire tm_count_ge3; + wire trc_this; + wire [ 35: 0] tw; + assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme; + assign itm_valid = |itm[35 : 32]; + assign atm_valid = |atm[35 : 32] & trc_this; + assign dtm_valid = |dtm[35 : 32] & trc_this; + assign free2 = ~fifocount[4]; + assign free3 = ~fifocount[4] & ~&fifocount[3 : 0]; + assign empty = ~|fifocount; + assign fifowp1 = fifowp + 1; + assign fifowp2 = fifowp + 2; + //nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count, which is an e_instance + nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count + ( + .atm_valid (atm_valid), + .compute_tm_count (compute_tm_count_tm_count), + .dtm_valid (dtm_valid), + .itm_valid (itm_valid) + ); + + assign tm_count = compute_tm_count_tm_count; + //nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp, which is an e_instance + nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp + ( + .fifowp_inc (fifowp_inc_fifowp), + .free2 (free2), + .free3 (free3), + .tm_count (tm_count) + ); + + //nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount, which is an e_instance + nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount + ( + .empty (empty), + .fifocount_inc (fifocount_inc_fifocount), + .free2 (free2), + .free3 (free3), + .tm_count (tm_count) + ); + + //the_nios_system_nios2_processor_oci_test_bench, which is an e_instance + nios_system_nios2_processor_oci_test_bench the_nios_system_nios2_processor_oci_test_bench + ( + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .test_ending (test_ending), + .test_has_ended (test_has_ended) + ); + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + fiforp <= 0; + fifowp <= 0; + fifocount <= 0; + ovf_pending <= 1; + end + else + begin + fifowp <= fifowp + fifowp_inc_fifowp; + fifocount <= fifocount + fifocount_inc_fifocount; + if (~empty) + fiforp <= fiforp + 1; + if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count))) + ovf_pending <= 1; + else if (atm_valid | dtm_valid) + ovf_pending <= 0; + end + end + + + assign fifohead = fifo_read_mux; + assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm; + assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_0 <= 0; + else if (fifo_0_enable) + fifo_0 <= fifo_0_mux; + end + + + assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm : + (((fifowp == 4'd0) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_1 <= 0; + else if (fifo_1_enable) + fifo_1 <= fifo_1_mux; + end + + + assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm : + (((fifowp == 4'd1) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_2 <= 0; + else if (fifo_2_enable) + fifo_2 <= fifo_2_mux; + end + + + assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm : + (((fifowp == 4'd2) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_3 <= 0; + else if (fifo_3_enable) + fifo_3 <= fifo_3_mux; + end + + + assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm : + (((fifowp == 4'd3) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_4 <= 0; + else if (fifo_4_enable) + fifo_4 <= fifo_4_mux; + end + + + assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm : + (((fifowp == 4'd4) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_5 <= 0; + else if (fifo_5_enable) + fifo_5 <= fifo_5_mux; + end + + + assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm : + (((fifowp == 4'd5) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_6 <= 0; + else if (fifo_6_enable) + fifo_6 <= fifo_6_mux; + end + + + assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm : + (((fifowp == 4'd6) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_7 <= 0; + else if (fifo_7_enable) + fifo_7 <= fifo_7_mux; + end + + + assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm : + (((fifowp == 4'd7) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_8 <= 0; + else if (fifo_8_enable) + fifo_8 <= fifo_8_mux; + end + + + assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm : + (((fifowp == 4'd8) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_9 <= 0; + else if (fifo_9_enable) + fifo_9 <= fifo_9_mux; + end + + + assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm : + (((fifowp == 4'd9) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_10 <= 0; + else if (fifo_10_enable) + fifo_10 <= fifo_10_mux; + end + + + assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm : + (((fifowp == 4'd10) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_11 <= 0; + else if (fifo_11_enable) + fifo_11 <= fifo_11_mux; + end + + + assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm : + (((fifowp == 4'd11) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_12 <= 0; + else if (fifo_12_enable) + fifo_12 <= fifo_12_mux; + end + + + assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm : + (((fifowp == 4'd12) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_13 <= 0; + else if (fifo_13_enable) + fifo_13 <= fifo_13_mux; + end + + + assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm : + (((fifowp == 4'd13) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_14 <= 0; + else if (fifo_14_enable) + fifo_14 <= fifo_14_mux; + end + + + assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm : + (((fifowp == 4'd14) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_15 <= 0; + else if (fifo_15_enable) + fifo_15 <= fifo_15_mux; + end + + + assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm : + (((fifowp == 4'd15) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign tm_count_ge1 = |tm_count; + assign tm_count_ge2 = tm_count[1]; + assign tm_count_ge3 = &tm_count; + assign ovr_pending_atm = {ovf_pending, atm[34 : 0]}; + assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]}; + assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 : + (fiforp == 4'd1)? fifo_1 : + (fiforp == 4'd2)? fifo_2 : + (fiforp == 4'd3)? fifo_3 : + (fiforp == 4'd4)? fifo_4 : + (fiforp == 4'd5)? fifo_5 : + (fiforp == 4'd6)? fifo_6 : + (fiforp == 4'd7)? fifo_7 : + (fiforp == 4'd8)? fifo_8 : + (fiforp == 4'd9)? fifo_9 : + (fiforp == 4'd10)? fifo_10 : + (fiforp == 4'd11)? fifo_11 : + (fiforp == 4'd12)? fifo_12 : + (fiforp == 4'd13)? fifo_13 : + (fiforp == 4'd14)? fifo_14 : + fifo_15; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_pib ( + // inputs: + clk, + clkx2, + jrst_n, + tw, + + // outputs: + tr_clk, + tr_data + ) +; + + output tr_clk; + output [ 17: 0] tr_data; + input clk; + input clkx2; + input jrst_n; + input [ 35: 0] tw; + + wire phase; + wire tr_clk; + reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 17: 0] tr_data; + reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + assign phase = x1^x2; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + x1 <= 0; + else + x1 <= ~x1; + end + + + always @(posedge clkx2 or negedge jrst_n) + begin + if (jrst_n == 0) + begin + x2 <= 0; + tr_clk_reg <= 0; + tr_data_reg <= 0; + end + else + begin + x2 <= x1; + tr_clk_reg <= ~phase; + tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18]; + end + end + + + assign tr_clk = 0 ? tr_clk_reg : 0; + assign tr_data = 0 ? tr_data_reg : 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_im ( + // inputs: + clk, + jdo, + jrst_n, + reset_n, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_tracemem_a, + trc_ctrl, + tw, + + // outputs: + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_enb, + trc_im_addr, + trc_wrap, + xbrk_wrap_traceoff + ) +; + + output tracemem_on; + output [ 35: 0] tracemem_trcdata; + output tracemem_tw; + output trc_enb; + output [ 6: 0] trc_im_addr; + output trc_wrap; + output xbrk_wrap_traceoff; + input clk; + input [ 37: 0] jdo; + input jrst_n; + input reset_n; + input take_action_tracectrl; + input take_action_tracemem_a; + input take_action_tracemem_b; + input take_no_action_tracemem_a; + input [ 15: 0] trc_ctrl; + input [ 35: 0] tw; + + wire tracemem_on; + wire [ 35: 0] tracemem_trcdata; + wire tracemem_tw; + wire trc_enb; + reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 35: 0] trc_im_data; + reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire trc_on_chip; + reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire tw_valid; + wire xbrk_wrap_traceoff; + assign trc_im_data = tw; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + trc_im_addr <= 0; + trc_wrap <= 0; + end + else if (!0) + begin + trc_im_addr <= 0; + trc_wrap <= 0; + end + else if (take_action_tracectrl && + (jdo[4] | jdo[3])) + begin + if (jdo[4]) + trc_im_addr <= 0; + if (jdo[3]) + trc_wrap <= 0; + end + else if (trc_enb & trc_on_chip & tw_valid) + begin + trc_im_addr <= trc_im_addr+1; + if (&trc_im_addr) + trc_wrap <= 1; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + trc_jtag_addr <= 0; + else if (take_action_tracemem_a || + take_no_action_tracemem_a || + take_action_tracemem_b) + trc_jtag_addr <= take_action_tracemem_a ? + jdo[35 : 19] : + trc_jtag_addr + 1; + + end + + + assign trc_enb = trc_ctrl[0]; + assign trc_on_chip = ~trc_ctrl[8]; + assign tw_valid = |trc_im_data[35 : 32]; + assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap; + assign tracemem_tw = trc_wrap; + assign tracemem_on = trc_enb; + assign tracemem_trcdata = 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_performance_monitors +; + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci ( + // inputs: + D_valid, + E_st_data, + E_valid, + F_pc, + address_nxt, + av_ld_data_aligned_filtered, + byteenable_nxt, + clk, + d_address, + d_read, + d_waitrequest, + d_write, + debugaccess_nxt, + hbreak_enabled, + read_nxt, + reset, + reset_n, + test_ending, + test_has_ended, + write_nxt, + writedata_nxt, + + // outputs: + jtag_debug_module_debugaccess_to_roms, + oci_hbreak_req, + oci_ienable, + oci_single_step_mode, + readdata, + resetrequest, + waitrequest + ) +; + + output jtag_debug_module_debugaccess_to_roms; + output oci_hbreak_req; + output [ 31: 0] oci_ienable; + output oci_single_step_mode; + output [ 31: 0] readdata; + output resetrequest; + output waitrequest; + input D_valid; + input [ 31: 0] E_st_data; + input E_valid; + input [ 16: 0] F_pc; + input [ 8: 0] address_nxt; + input [ 31: 0] av_ld_data_aligned_filtered; + input [ 3: 0] byteenable_nxt; + input clk; + input [ 18: 0] d_address; + input d_read; + input d_waitrequest; + input d_write; + input debugaccess_nxt; + input hbreak_enabled; + input read_nxt; + input reset; + input reset_n; + input test_ending; + input test_has_ended; + input write_nxt; + input [ 31: 0] writedata_nxt; + + wire [ 31: 0] MonDReg; + reg [ 8: 0] address; + wire [ 35: 0] atm; + wire [ 31: 0] break_readreg; + reg [ 3: 0] byteenable; + wire clkx2; + wire [ 18: 0] cpu_d_address; + wire cpu_d_read; + wire [ 31: 0] cpu_d_readdata; + wire cpu_d_wait; + wire cpu_d_write; + wire [ 31: 0] cpu_d_writedata; + wire dbrk_break; + wire dbrk_goto0; + wire dbrk_goto1; + wire dbrk_hit0_latch; + wire dbrk_hit1_latch; + wire dbrk_hit2_latch; + wire dbrk_hit3_latch; + wire dbrk_traceme; + wire dbrk_traceoff; + wire dbrk_traceon; + wire dbrk_trigout; + wire [ 29: 0] dct_buffer; + wire [ 3: 0] dct_count; + reg debugaccess; + wire debugack; + wire debugreq; + wire [ 35: 0] dtm; + wire dummy_sink; + wire [ 35: 0] itm; + wire [ 37: 0] jdo; + wire jrst_n; + wire jtag_debug_module_debugaccess_to_roms; + wire monitor_error; + wire monitor_go; + wire monitor_ready; + wire oci_hbreak_req; + wire [ 31: 0] oci_ienable; + wire [ 31: 0] oci_reg_readdata; + wire oci_single_step_mode; + wire [ 31: 0] ociram_readdata; + wire ocireg_ers; + wire ocireg_mrs; + reg read; + reg [ 31: 0] readdata; + wire resetlatch; + wire resetrequest; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_ocireg; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire tr_clk; + wire [ 17: 0] tr_data; + wire tracemem_on; + wire [ 35: 0] tracemem_trcdata; + wire tracemem_tw; + wire [ 15: 0] trc_ctrl; + wire trc_enb; + wire [ 6: 0] trc_im_addr; + wire trc_on; + wire trc_wrap; + wire trigbrktype; + wire trigger_state_0; + wire trigger_state_1; + wire trigout; + wire [ 35: 0] tw; + wire waitrequest; + reg write; + reg [ 31: 0] writedata; + wire xbrk_break; + wire [ 7: 0] xbrk_ctrl0; + wire [ 7: 0] xbrk_ctrl1; + wire [ 7: 0] xbrk_ctrl2; + wire [ 7: 0] xbrk_ctrl3; + wire xbrk_goto0; + wire xbrk_goto1; + wire xbrk_traceoff; + wire xbrk_traceon; + wire xbrk_trigout; + wire xbrk_wrap_traceoff; + nios_system_nios2_processor_nios2_oci_debug the_nios_system_nios2_processor_nios2_oci_debug + ( + .clk (clk), + .dbrk_break (dbrk_break), + .debugack (debugack), + .debugreq (debugreq), + .hbreak_enabled (hbreak_enabled), + .jdo (jdo), + .jrst_n (jrst_n), + .monitor_error (monitor_error), + .monitor_go (monitor_go), + .monitor_ready (monitor_ready), + .oci_hbreak_req (oci_hbreak_req), + .ocireg_ers (ocireg_ers), + .ocireg_mrs (ocireg_mrs), + .reset (reset), + .resetlatch (resetlatch), + .resetrequest (resetrequest), + .st_ready_test_idle (st_ready_test_idle), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocireg (take_action_ocireg), + .xbrk_break (xbrk_break) + ); + + nios_system_nios2_processor_nios2_ocimem the_nios_system_nios2_processor_nios2_ocimem + ( + .MonDReg (MonDReg), + .address (address), + .byteenable (byteenable), + .clk (clk), + .debugaccess (debugaccess), + .jdo (jdo), + .jrst_n (jrst_n), + .ociram_readdata (ociram_readdata), + .read (read), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .waitrequest (waitrequest), + .write (write), + .writedata (writedata) + ); + + nios_system_nios2_processor_nios2_avalon_reg the_nios_system_nios2_processor_nios2_avalon_reg + ( + .address (address), + .clk (clk), + .debugaccess (debugaccess), + .monitor_error (monitor_error), + .monitor_go (monitor_go), + .monitor_ready (monitor_ready), + .oci_ienable (oci_ienable), + .oci_reg_readdata (oci_reg_readdata), + .oci_single_step_mode (oci_single_step_mode), + .ocireg_ers (ocireg_ers), + .ocireg_mrs (ocireg_mrs), + .reset_n (reset_n), + .take_action_ocireg (take_action_ocireg), + .write (write), + .writedata (writedata) + ); + + nios_system_nios2_processor_nios2_oci_break the_nios_system_nios2_processor_nios2_oci_break + ( + .break_readreg (break_readreg), + .clk (clk), + .dbrk_break (dbrk_break), + .dbrk_goto0 (dbrk_goto0), + .dbrk_goto1 (dbrk_goto1), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .jdo (jdo), + .jrst_n (jrst_n), + .reset_n (reset_n), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .trigbrktype (trigbrktype), + .trigger_state_0 (trigger_state_0), + .trigger_state_1 (trigger_state_1), + .xbrk_ctrl0 (xbrk_ctrl0), + .xbrk_ctrl1 (xbrk_ctrl1), + .xbrk_ctrl2 (xbrk_ctrl2), + .xbrk_ctrl3 (xbrk_ctrl3), + .xbrk_goto0 (xbrk_goto0), + .xbrk_goto1 (xbrk_goto1) + ); + + nios_system_nios2_processor_nios2_oci_xbrk the_nios_system_nios2_processor_nios2_oci_xbrk + ( + .D_valid (D_valid), + .E_valid (E_valid), + .F_pc (F_pc), + .clk (clk), + .reset_n (reset_n), + .trigger_state_0 (trigger_state_0), + .trigger_state_1 (trigger_state_1), + .xbrk_break (xbrk_break), + .xbrk_ctrl0 (xbrk_ctrl0), + .xbrk_ctrl1 (xbrk_ctrl1), + .xbrk_ctrl2 (xbrk_ctrl2), + .xbrk_ctrl3 (xbrk_ctrl3), + .xbrk_goto0 (xbrk_goto0), + .xbrk_goto1 (xbrk_goto1), + .xbrk_traceoff (xbrk_traceoff), + .xbrk_traceon (xbrk_traceon), + .xbrk_trigout (xbrk_trigout) + ); + + nios_system_nios2_processor_nios2_oci_dbrk the_nios_system_nios2_processor_nios2_oci_dbrk + ( + .E_st_data (E_st_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .clk (clk), + .cpu_d_address (cpu_d_address), + .cpu_d_read (cpu_d_read), + .cpu_d_readdata (cpu_d_readdata), + .cpu_d_wait (cpu_d_wait), + .cpu_d_write (cpu_d_write), + .cpu_d_writedata (cpu_d_writedata), + .d_address (d_address), + .d_read (d_read), + .d_waitrequest (d_waitrequest), + .d_write (d_write), + .dbrk_break (dbrk_break), + .dbrk_goto0 (dbrk_goto0), + .dbrk_goto1 (dbrk_goto1), + .dbrk_traceme (dbrk_traceme), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dbrk_trigout (dbrk_trigout), + .debugack (debugack), + .reset_n (reset_n) + ); + + nios_system_nios2_processor_nios2_oci_itrace the_nios_system_nios2_processor_nios2_oci_itrace + ( + .clk (clk), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .itm (itm), + .jdo (jdo), + .jrst_n (jrst_n), + .take_action_tracectrl (take_action_tracectrl), + .trc_ctrl (trc_ctrl), + .trc_enb (trc_enb), + .trc_on (trc_on), + .xbrk_traceoff (xbrk_traceoff), + .xbrk_traceon (xbrk_traceon), + .xbrk_wrap_traceoff (xbrk_wrap_traceoff) + ); + + nios_system_nios2_processor_nios2_oci_dtrace the_nios_system_nios2_processor_nios2_oci_dtrace + ( + .atm (atm), + .clk (clk), + .cpu_d_address (cpu_d_address), + .cpu_d_read (cpu_d_read), + .cpu_d_readdata (cpu_d_readdata), + .cpu_d_wait (cpu_d_wait), + .cpu_d_write (cpu_d_write), + .cpu_d_writedata (cpu_d_writedata), + .dtm (dtm), + .jrst_n (jrst_n), + .trc_ctrl (trc_ctrl) + ); + + nios_system_nios2_processor_nios2_oci_fifo the_nios_system_nios2_processor_nios2_oci_fifo + ( + .atm (atm), + .clk (clk), + .dbrk_traceme (dbrk_traceme), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .dtm (dtm), + .itm (itm), + .jrst_n (jrst_n), + .reset_n (reset_n), + .test_ending (test_ending), + .test_has_ended (test_has_ended), + .trc_on (trc_on), + .tw (tw) + ); + + nios_system_nios2_processor_nios2_oci_pib the_nios_system_nios2_processor_nios2_oci_pib + ( + .clk (clk), + .clkx2 (clkx2), + .jrst_n (jrst_n), + .tr_clk (tr_clk), + .tr_data (tr_data), + .tw (tw) + ); + + nios_system_nios2_processor_nios2_oci_im the_nios_system_nios2_processor_nios2_oci_im + ( + .clk (clk), + .jdo (jdo), + .jrst_n (jrst_n), + .reset_n (reset_n), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_ctrl (trc_ctrl), + .trc_enb (trc_enb), + .trc_im_addr (trc_im_addr), + .trc_wrap (trc_wrap), + .tw (tw), + .xbrk_wrap_traceoff (xbrk_wrap_traceoff) + ); + + assign trigout = dbrk_trigout | xbrk_trigout; + assign jtag_debug_module_debugaccess_to_roms = debugack; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + address <= 0; + else + address <= address_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + byteenable <= 0; + else + byteenable <= byteenable_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + writedata <= 0; + else + writedata <= writedata_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + debugaccess <= 0; + else + debugaccess <= debugaccess_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + read <= 0; + else + read <= read ? waitrequest : read_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + write <= 0; + else + write <= write ? waitrequest : write_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + readdata <= 0; + else + readdata <= address[8] ? oci_reg_readdata : ociram_readdata; + end + + + nios_system_nios2_processor_jtag_debug_module_wrapper the_nios_system_nios2_processor_jtag_debug_module_wrapper + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .clk (clk), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .jdo (jdo), + .jrst_n (jrst_n), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .st_ready_test_idle (st_ready_test_idle), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1) + ); + + //dummy sink, which is an e_mux + assign dummy_sink = tr_clk | + tr_data | + trigout | + debugack; + + assign debugreq = 0; + assign clkx2 = 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor ( + // inputs: + clk, + d_irq, + d_readdata, + d_waitrequest, + i_readdata, + i_waitrequest, + jtag_debug_module_address, + jtag_debug_module_byteenable, + jtag_debug_module_debugaccess, + jtag_debug_module_read, + jtag_debug_module_write, + jtag_debug_module_writedata, + reset_n, + + // outputs: + d_address, + d_byteenable, + d_read, + d_write, + d_writedata, + i_address, + i_read, + jtag_debug_module_debugaccess_to_roms, + jtag_debug_module_readdata, + jtag_debug_module_resetrequest, + jtag_debug_module_waitrequest, + no_ci_readra + ) +; + + output [ 18: 0] d_address; + output [ 3: 0] d_byteenable; + output d_read; + output d_write; + output [ 31: 0] d_writedata; + output [ 18: 0] i_address; + output i_read; + output jtag_debug_module_debugaccess_to_roms; + output [ 31: 0] jtag_debug_module_readdata; + output jtag_debug_module_resetrequest; + output jtag_debug_module_waitrequest; + output no_ci_readra; + input clk; + input [ 31: 0] d_irq; + input [ 31: 0] d_readdata; + input d_waitrequest; + input [ 31: 0] i_readdata; + input i_waitrequest; + input [ 8: 0] jtag_debug_module_address; + input [ 3: 0] jtag_debug_module_byteenable; + input jtag_debug_module_debugaccess; + input jtag_debug_module_read; + input jtag_debug_module_write; + input [ 31: 0] jtag_debug_module_writedata; + input reset_n; + + wire [ 1: 0] D_compare_op; + wire D_ctrl_alu_force_xor; + wire D_ctrl_alu_signed_comparison; + wire D_ctrl_alu_subtract; + wire D_ctrl_b_is_dst; + wire D_ctrl_br; + wire D_ctrl_br_cmp; + wire D_ctrl_br_uncond; + wire D_ctrl_break; + wire D_ctrl_crst; + wire D_ctrl_custom; + wire D_ctrl_custom_multi; + wire D_ctrl_exception; + wire D_ctrl_force_src2_zero; + wire D_ctrl_hi_imm16; + wire D_ctrl_ignore_dst; + wire D_ctrl_implicit_dst_eretaddr; + wire D_ctrl_implicit_dst_retaddr; + wire D_ctrl_jmp_direct; + wire D_ctrl_jmp_indirect; + wire D_ctrl_ld; + wire D_ctrl_ld_io; + wire D_ctrl_ld_non_io; + wire D_ctrl_ld_signed; + wire D_ctrl_logic; + wire D_ctrl_rdctl_inst; + wire D_ctrl_retaddr; + wire D_ctrl_rot_right; + wire D_ctrl_shift_logical; + wire D_ctrl_shift_right_arith; + wire D_ctrl_shift_rot; + wire D_ctrl_shift_rot_right; + wire D_ctrl_src2_choose_imm; + wire D_ctrl_st; + wire D_ctrl_uncond_cti_non_br; + wire D_ctrl_unsigned_lo_imm16; + wire D_ctrl_wrctl_inst; + wire [ 4: 0] D_dst_regnum; + wire [ 55: 0] D_inst; + reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 4: 0] D_iw_a; + wire [ 4: 0] D_iw_b; + wire [ 4: 0] D_iw_c; + wire [ 2: 0] D_iw_control_regnum; + wire [ 7: 0] D_iw_custom_n; + wire D_iw_custom_readra; + wire D_iw_custom_readrb; + wire D_iw_custom_writerc; + wire [ 15: 0] D_iw_imm16; + wire [ 25: 0] D_iw_imm26; + wire [ 4: 0] D_iw_imm5; + wire [ 1: 0] D_iw_memsz; + wire [ 5: 0] D_iw_op; + wire [ 5: 0] D_iw_opx; + wire [ 4: 0] D_iw_shift_imm5; + wire [ 4: 0] D_iw_trap_break_imm5; + wire [ 16: 0] D_jmp_direct_target_waddr; + wire [ 1: 0] D_logic_op; + wire [ 1: 0] D_logic_op_raw; + wire D_mem16; + wire D_mem32; + wire D_mem8; + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + reg D_valid; + wire [ 55: 0] D_vinst; + wire D_wr_dst_reg; + wire [ 31: 0] E_alu_result; + reg E_alu_sub; + wire [ 32: 0] E_arith_result; + wire [ 31: 0] E_arith_src1; + wire [ 31: 0] E_arith_src2; + wire E_ci_multi_stall; + wire [ 31: 0] E_ci_result; + wire E_cmp_result; + wire [ 31: 0] E_control_rd_data; + wire E_eq; + reg E_invert_arith_src_msb; + wire E_ld_stall; + wire [ 31: 0] E_logic_result; + wire E_logic_result_is_0; + wire E_lt; + wire [ 18: 0] E_mem_baddr; + wire [ 3: 0] E_mem_byte_en; + reg E_new_inst; + reg [ 4: 0] E_shift_rot_cnt; + wire [ 4: 0] E_shift_rot_cnt_nxt; + wire E_shift_rot_done; + wire E_shift_rot_fill_bit; + reg [ 31: 0] E_shift_rot_result; + wire [ 31: 0] E_shift_rot_result_nxt; + wire E_shift_rot_stall; + reg [ 31: 0] E_src1; + reg [ 31: 0] E_src2; + wire [ 31: 0] E_st_data; + wire E_st_stall; + wire E_stall; + reg E_valid; + wire [ 55: 0] E_vinst; + wire E_wrctl_bstatus; + wire E_wrctl_estatus; + wire E_wrctl_ienable; + wire E_wrctl_status; + wire [ 31: 0] F_av_iw; + wire [ 4: 0] F_av_iw_a; + wire [ 4: 0] F_av_iw_b; + wire [ 4: 0] F_av_iw_c; + wire [ 2: 0] F_av_iw_control_regnum; + wire [ 7: 0] F_av_iw_custom_n; + wire F_av_iw_custom_readra; + wire F_av_iw_custom_readrb; + wire F_av_iw_custom_writerc; + wire [ 15: 0] F_av_iw_imm16; + wire [ 25: 0] F_av_iw_imm26; + wire [ 4: 0] F_av_iw_imm5; + wire [ 1: 0] F_av_iw_memsz; + wire [ 5: 0] F_av_iw_op; + wire [ 5: 0] F_av_iw_opx; + wire [ 4: 0] F_av_iw_shift_imm5; + wire [ 4: 0] F_av_iw_trap_break_imm5; + wire F_av_mem16; + wire F_av_mem32; + wire F_av_mem8; + wire [ 55: 0] F_inst; + wire [ 31: 0] F_iw; + wire [ 4: 0] F_iw_a; + wire [ 4: 0] F_iw_b; + wire [ 4: 0] F_iw_c; + wire [ 2: 0] F_iw_control_regnum; + wire [ 7: 0] F_iw_custom_n; + wire F_iw_custom_readra; + wire F_iw_custom_readrb; + wire F_iw_custom_writerc; + wire [ 15: 0] F_iw_imm16; + wire [ 25: 0] F_iw_imm26; + wire [ 4: 0] F_iw_imm5; + wire [ 1: 0] F_iw_memsz; + wire [ 5: 0] F_iw_op; + wire [ 5: 0] F_iw_opx; + wire [ 4: 0] F_iw_shift_imm5; + wire [ 4: 0] F_iw_trap_break_imm5; + wire F_mem16; + wire F_mem32; + wire F_mem8; + wire F_op_add; + wire F_op_addi; + wire F_op_and; + wire F_op_andhi; + wire F_op_andi; + wire F_op_beq; + wire F_op_bge; + wire F_op_bgeu; + wire F_op_blt; + wire F_op_bltu; + wire F_op_bne; + wire F_op_br; + wire F_op_break; + wire F_op_bret; + wire F_op_call; + wire F_op_callr; + wire F_op_cmpeq; + wire F_op_cmpeqi; + wire F_op_cmpge; + wire F_op_cmpgei; + wire F_op_cmpgeu; + wire F_op_cmpgeui; + wire F_op_cmplt; + wire F_op_cmplti; + wire F_op_cmpltu; + wire F_op_cmpltui; + wire F_op_cmpne; + wire F_op_cmpnei; + wire F_op_crst; + wire F_op_custom; + wire F_op_div; + wire F_op_divu; + wire F_op_eret; + wire F_op_flushd; + wire F_op_flushda; + wire F_op_flushi; + wire F_op_flushp; + wire F_op_hbreak; + wire F_op_initd; + wire F_op_initda; + wire F_op_initi; + wire F_op_intr; + wire F_op_jmp; + wire F_op_jmpi; + wire F_op_ldb; + wire F_op_ldbio; + wire F_op_ldbu; + wire F_op_ldbuio; + wire F_op_ldh; + wire F_op_ldhio; + wire F_op_ldhu; + wire F_op_ldhuio; + wire F_op_ldl; + wire F_op_ldw; + wire F_op_ldwio; + wire F_op_mul; + wire F_op_muli; + wire F_op_mulxss; + wire F_op_mulxsu; + wire F_op_mulxuu; + wire F_op_nextpc; + wire F_op_nor; + wire F_op_opx; + wire F_op_or; + wire F_op_orhi; + wire F_op_ori; + wire F_op_rdctl; + wire F_op_rdprs; + wire F_op_ret; + wire F_op_rol; + wire F_op_roli; + wire F_op_ror; + wire F_op_rsv02; + wire F_op_rsv09; + wire F_op_rsv10; + wire F_op_rsv17; + wire F_op_rsv18; + wire F_op_rsv25; + wire F_op_rsv26; + wire F_op_rsv33; + wire F_op_rsv34; + wire F_op_rsv41; + wire F_op_rsv42; + wire F_op_rsv49; + wire F_op_rsv57; + wire F_op_rsv61; + wire F_op_rsv62; + wire F_op_rsv63; + wire F_op_rsvx00; + wire F_op_rsvx10; + wire F_op_rsvx15; + wire F_op_rsvx17; + wire F_op_rsvx21; + wire F_op_rsvx25; + wire F_op_rsvx33; + wire F_op_rsvx34; + wire F_op_rsvx35; + wire F_op_rsvx42; + wire F_op_rsvx43; + wire F_op_rsvx44; + wire F_op_rsvx47; + wire F_op_rsvx50; + wire F_op_rsvx51; + wire F_op_rsvx55; + wire F_op_rsvx56; + wire F_op_rsvx60; + wire F_op_rsvx63; + wire F_op_sll; + wire F_op_slli; + wire F_op_sra; + wire F_op_srai; + wire F_op_srl; + wire F_op_srli; + wire F_op_stb; + wire F_op_stbio; + wire F_op_stc; + wire F_op_sth; + wire F_op_sthio; + wire F_op_stw; + wire F_op_stwio; + wire F_op_sub; + wire F_op_sync; + wire F_op_trap; + wire F_op_wrctl; + wire F_op_wrprs; + wire F_op_xor; + wire F_op_xorhi; + wire F_op_xori; + reg [ 16: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire F_pc_en; + wire [ 16: 0] F_pc_no_crst_nxt; + wire [ 16: 0] F_pc_nxt; + wire [ 16: 0] F_pc_plus_one; + wire [ 1: 0] F_pc_sel_nxt; + wire [ 18: 0] F_pcb; + wire [ 18: 0] F_pcb_nxt; + wire [ 18: 0] F_pcb_plus_four; + wire F_valid; + wire [ 55: 0] F_vinst; + reg [ 1: 0] R_compare_op; + reg R_ctrl_alu_force_xor; + wire R_ctrl_alu_force_xor_nxt; + reg R_ctrl_alu_signed_comparison; + wire R_ctrl_alu_signed_comparison_nxt; + reg R_ctrl_alu_subtract; + wire R_ctrl_alu_subtract_nxt; + reg R_ctrl_b_is_dst; + wire R_ctrl_b_is_dst_nxt; + reg R_ctrl_br; + reg R_ctrl_br_cmp; + wire R_ctrl_br_cmp_nxt; + wire R_ctrl_br_nxt; + reg R_ctrl_br_uncond; + wire R_ctrl_br_uncond_nxt; + reg R_ctrl_break; + wire R_ctrl_break_nxt; + reg R_ctrl_crst; + wire R_ctrl_crst_nxt; + reg R_ctrl_custom; + reg R_ctrl_custom_multi; + wire R_ctrl_custom_multi_nxt; + wire R_ctrl_custom_nxt; + reg R_ctrl_exception; + wire R_ctrl_exception_nxt; + reg R_ctrl_force_src2_zero; + wire R_ctrl_force_src2_zero_nxt; + reg R_ctrl_hi_imm16; + wire R_ctrl_hi_imm16_nxt; + reg R_ctrl_ignore_dst; + wire R_ctrl_ignore_dst_nxt; + reg R_ctrl_implicit_dst_eretaddr; + wire R_ctrl_implicit_dst_eretaddr_nxt; + reg R_ctrl_implicit_dst_retaddr; + wire R_ctrl_implicit_dst_retaddr_nxt; + reg R_ctrl_jmp_direct; + wire R_ctrl_jmp_direct_nxt; + reg R_ctrl_jmp_indirect; + wire R_ctrl_jmp_indirect_nxt; + reg R_ctrl_ld; + reg R_ctrl_ld_io; + wire R_ctrl_ld_io_nxt; + reg R_ctrl_ld_non_io; + wire R_ctrl_ld_non_io_nxt; + wire R_ctrl_ld_nxt; + reg R_ctrl_ld_signed; + wire R_ctrl_ld_signed_nxt; + reg R_ctrl_logic; + wire R_ctrl_logic_nxt; + reg R_ctrl_rdctl_inst; + wire R_ctrl_rdctl_inst_nxt; + reg R_ctrl_retaddr; + wire R_ctrl_retaddr_nxt; + reg R_ctrl_rot_right; + wire R_ctrl_rot_right_nxt; + reg R_ctrl_shift_logical; + wire R_ctrl_shift_logical_nxt; + reg R_ctrl_shift_right_arith; + wire R_ctrl_shift_right_arith_nxt; + reg R_ctrl_shift_rot; + wire R_ctrl_shift_rot_nxt; + reg R_ctrl_shift_rot_right; + wire R_ctrl_shift_rot_right_nxt; + reg R_ctrl_src2_choose_imm; + wire R_ctrl_src2_choose_imm_nxt; + reg R_ctrl_st; + wire R_ctrl_st_nxt; + reg R_ctrl_uncond_cti_non_br; + wire R_ctrl_uncond_cti_non_br_nxt; + reg R_ctrl_unsigned_lo_imm16; + wire R_ctrl_unsigned_lo_imm16_nxt; + reg R_ctrl_wrctl_inst; + wire R_ctrl_wrctl_inst_nxt; + reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire R_en; + reg [ 1: 0] R_logic_op; + wire [ 31: 0] R_rf_a; + wire [ 31: 0] R_rf_b; + wire [ 31: 0] R_src1; + wire [ 31: 0] R_src2; + wire [ 15: 0] R_src2_hi; + wire [ 15: 0] R_src2_lo; + reg R_src2_use_imm; + wire [ 7: 0] R_stb_data; + wire [ 15: 0] R_sth_data; + reg R_valid; + wire [ 55: 0] R_vinst; + reg R_wr_dst_reg; + reg [ 31: 0] W_alu_result; + wire W_br_taken; + reg W_bstatus_reg; + wire W_bstatus_reg_inst_nxt; + wire W_bstatus_reg_nxt; + reg W_cmp_result; + reg [ 31: 0] W_control_rd_data; + reg W_estatus_reg; + wire W_estatus_reg_inst_nxt; + wire W_estatus_reg_nxt; + reg [ 31: 0] W_ienable_reg; + wire [ 31: 0] W_ienable_reg_nxt; + reg [ 31: 0] W_ipending_reg; + wire [ 31: 0] W_ipending_reg_nxt; + wire [ 18: 0] W_mem_baddr; + wire [ 31: 0] W_rf_wr_data; + wire W_rf_wren; + wire W_status_reg; + reg W_status_reg_pie; + wire W_status_reg_pie_inst_nxt; + wire W_status_reg_pie_nxt; + reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 55: 0] W_vinst; + wire [ 31: 0] W_wr_data; + wire [ 31: 0] W_wr_data_non_zero; + wire av_fill_bit; + reg [ 1: 0] av_ld_align_cycle; + wire [ 1: 0] av_ld_align_cycle_nxt; + wire av_ld_align_one_more_cycle; + reg av_ld_aligning_data; + wire av_ld_aligning_data_nxt; + reg [ 7: 0] av_ld_byte0_data; + wire [ 7: 0] av_ld_byte0_data_nxt; + reg [ 7: 0] av_ld_byte1_data; + wire av_ld_byte1_data_en; + wire [ 7: 0] av_ld_byte1_data_nxt; + reg [ 7: 0] av_ld_byte2_data; + wire [ 7: 0] av_ld_byte2_data_nxt; + reg [ 7: 0] av_ld_byte3_data; + wire [ 7: 0] av_ld_byte3_data_nxt; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire [ 31: 0] av_ld_data_aligned_unfiltered; + wire av_ld_done; + wire av_ld_extend; + wire av_ld_getting_data; + wire av_ld_rshift8; + reg av_ld_waiting_for_data; + wire av_ld_waiting_for_data_nxt; + wire av_sign_bit; + wire [ 18: 0] d_address; + reg [ 3: 0] d_byteenable; + reg d_read; + wire d_read_nxt; + wire d_write; + wire d_write_nxt; + reg [ 31: 0] d_writedata; + reg hbreak_enabled; + reg hbreak_pending; + wire hbreak_pending_nxt; + wire hbreak_req; + wire [ 18: 0] i_address; + reg i_read; + wire i_read_nxt; + wire [ 31: 0] iactive; + wire intr_req; + wire jtag_debug_module_clk; + wire jtag_debug_module_debugaccess_to_roms; + wire [ 31: 0] jtag_debug_module_readdata; + wire jtag_debug_module_reset; + wire jtag_debug_module_resetrequest; + wire jtag_debug_module_waitrequest; + wire no_ci_readra; + wire oci_hbreak_req; + wire [ 31: 0] oci_ienable; + wire oci_single_step_mode; + wire oci_tb_hbreak_req; + wire test_ending; + wire test_has_ended; + reg wait_for_one_post_bret_inst; + //the_nios_system_nios2_processor_test_bench, which is an e_instance + nios_system_nios2_processor_test_bench the_nios_system_nios2_processor_test_bench + ( + .D_iw (D_iw), + .D_iw_op (D_iw_op), + .D_iw_opx (D_iw_opx), + .D_valid (D_valid), + .E_valid (E_valid), + .F_pcb (F_pcb), + .F_valid (F_valid), + .R_ctrl_ld (R_ctrl_ld), + .R_ctrl_ld_non_io (R_ctrl_ld_non_io), + .R_dst_regnum (R_dst_regnum), + .R_wr_dst_reg (R_wr_dst_reg), + .W_valid (W_valid), + .W_vinst (W_vinst), + .W_wr_data (W_wr_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), + .clk (clk), + .d_address (d_address), + .d_byteenable (d_byteenable), + .d_read (d_read), + .d_write (d_write), + .d_write_nxt (d_write_nxt), + .i_address (i_address), + .i_read (i_read), + .i_readdata (i_readdata), + .i_waitrequest (i_waitrequest), + .reset_n (reset_n), + .test_has_ended (test_has_ended) + ); + + assign F_av_iw_a = F_av_iw[31 : 27]; + assign F_av_iw_b = F_av_iw[26 : 22]; + assign F_av_iw_c = F_av_iw[21 : 17]; + assign F_av_iw_custom_n = F_av_iw[13 : 6]; + assign F_av_iw_custom_readra = F_av_iw[16]; + assign F_av_iw_custom_readrb = F_av_iw[15]; + assign F_av_iw_custom_writerc = F_av_iw[14]; + assign F_av_iw_opx = F_av_iw[16 : 11]; + assign F_av_iw_op = F_av_iw[5 : 0]; + assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm16 = F_av_iw[21 : 6]; + assign F_av_iw_imm26 = F_av_iw[31 : 6]; + assign F_av_iw_memsz = F_av_iw[4 : 3]; + assign F_av_iw_control_regnum = F_av_iw[8 : 6]; + assign F_av_mem8 = F_av_iw_memsz == 2'b00; + assign F_av_mem16 = F_av_iw_memsz == 2'b01; + assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; + assign F_iw_a = F_iw[31 : 27]; + assign F_iw_b = F_iw[26 : 22]; + assign F_iw_c = F_iw[21 : 17]; + assign F_iw_custom_n = F_iw[13 : 6]; + assign F_iw_custom_readra = F_iw[16]; + assign F_iw_custom_readrb = F_iw[15]; + assign F_iw_custom_writerc = F_iw[14]; + assign F_iw_opx = F_iw[16 : 11]; + assign F_iw_op = F_iw[5 : 0]; + assign F_iw_shift_imm5 = F_iw[10 : 6]; + assign F_iw_trap_break_imm5 = F_iw[10 : 6]; + assign F_iw_imm5 = F_iw[10 : 6]; + assign F_iw_imm16 = F_iw[21 : 6]; + assign F_iw_imm26 = F_iw[31 : 6]; + assign F_iw_memsz = F_iw[4 : 3]; + assign F_iw_control_regnum = F_iw[8 : 6]; + assign F_mem8 = F_iw_memsz == 2'b00; + assign F_mem16 = F_iw_memsz == 2'b01; + assign F_mem32 = F_iw_memsz[1] == 1'b1; + assign D_iw_a = D_iw[31 : 27]; + assign D_iw_b = D_iw[26 : 22]; + assign D_iw_c = D_iw[21 : 17]; + assign D_iw_custom_n = D_iw[13 : 6]; + assign D_iw_custom_readra = D_iw[16]; + assign D_iw_custom_readrb = D_iw[15]; + assign D_iw_custom_writerc = D_iw[14]; + assign D_iw_opx = D_iw[16 : 11]; + assign D_iw_op = D_iw[5 : 0]; + assign D_iw_shift_imm5 = D_iw[10 : 6]; + assign D_iw_trap_break_imm5 = D_iw[10 : 6]; + assign D_iw_imm5 = D_iw[10 : 6]; + assign D_iw_imm16 = D_iw[21 : 6]; + assign D_iw_imm26 = D_iw[31 : 6]; + assign D_iw_memsz = D_iw[4 : 3]; + assign D_iw_control_regnum = D_iw[8 : 6]; + assign D_mem8 = D_iw_memsz == 2'b00; + assign D_mem16 = D_iw_memsz == 2'b01; + assign D_mem32 = D_iw_memsz[1] == 1'b1; + assign F_op_call = F_iw_op == 0; + assign F_op_jmpi = F_iw_op == 1; + assign F_op_ldbu = F_iw_op == 3; + assign F_op_addi = F_iw_op == 4; + assign F_op_stb = F_iw_op == 5; + assign F_op_br = F_iw_op == 6; + assign F_op_ldb = F_iw_op == 7; + assign F_op_cmpgei = F_iw_op == 8; + assign F_op_ldhu = F_iw_op == 11; + assign F_op_andi = F_iw_op == 12; + assign F_op_sth = F_iw_op == 13; + assign F_op_bge = F_iw_op == 14; + assign F_op_ldh = F_iw_op == 15; + assign F_op_cmplti = F_iw_op == 16; + assign F_op_initda = F_iw_op == 19; + assign F_op_ori = F_iw_op == 20; + assign F_op_stw = F_iw_op == 21; + assign F_op_blt = F_iw_op == 22; + assign F_op_ldw = F_iw_op == 23; + assign F_op_cmpnei = F_iw_op == 24; + assign F_op_flushda = F_iw_op == 27; + assign F_op_xori = F_iw_op == 28; + assign F_op_stc = F_iw_op == 29; + assign F_op_bne = F_iw_op == 30; + assign F_op_ldl = F_iw_op == 31; + assign F_op_cmpeqi = F_iw_op == 32; + assign F_op_ldbuio = F_iw_op == 35; + assign F_op_muli = F_iw_op == 36; + assign F_op_stbio = F_iw_op == 37; + assign F_op_beq = F_iw_op == 38; + assign F_op_ldbio = F_iw_op == 39; + assign F_op_cmpgeui = F_iw_op == 40; + assign F_op_ldhuio = F_iw_op == 43; + assign F_op_andhi = F_iw_op == 44; + assign F_op_sthio = F_iw_op == 45; + assign F_op_bgeu = F_iw_op == 46; + assign F_op_ldhio = F_iw_op == 47; + assign F_op_cmpltui = F_iw_op == 48; + assign F_op_initd = F_iw_op == 51; + assign F_op_orhi = F_iw_op == 52; + assign F_op_stwio = F_iw_op == 53; + assign F_op_bltu = F_iw_op == 54; + assign F_op_ldwio = F_iw_op == 55; + assign F_op_rdprs = F_iw_op == 56; + assign F_op_flushd = F_iw_op == 59; + assign F_op_xorhi = F_iw_op == 60; + assign F_op_rsv02 = F_iw_op == 2; + assign F_op_rsv09 = F_iw_op == 9; + assign F_op_rsv10 = F_iw_op == 10; + assign F_op_rsv17 = F_iw_op == 17; + assign F_op_rsv18 = F_iw_op == 18; + assign F_op_rsv25 = F_iw_op == 25; + assign F_op_rsv26 = F_iw_op == 26; + assign F_op_rsv33 = F_iw_op == 33; + assign F_op_rsv34 = F_iw_op == 34; + assign F_op_rsv41 = F_iw_op == 41; + assign F_op_rsv42 = F_iw_op == 42; + assign F_op_rsv49 = F_iw_op == 49; + assign F_op_rsv57 = F_iw_op == 57; + assign F_op_rsv61 = F_iw_op == 61; + assign F_op_rsv62 = F_iw_op == 62; + assign F_op_rsv63 = F_iw_op == 63; + assign F_op_eret = F_op_opx & (F_iw_opx == 1); + assign F_op_roli = F_op_opx & (F_iw_opx == 2); + assign F_op_rol = F_op_opx & (F_iw_opx == 3); + assign F_op_flushp = F_op_opx & (F_iw_opx == 4); + assign F_op_ret = F_op_opx & (F_iw_opx == 5); + assign F_op_nor = F_op_opx & (F_iw_opx == 6); + assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); + assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); + assign F_op_bret = F_op_opx & (F_iw_opx == 9); + assign F_op_ror = F_op_opx & (F_iw_opx == 11); + assign F_op_flushi = F_op_opx & (F_iw_opx == 12); + assign F_op_jmp = F_op_opx & (F_iw_opx == 13); + assign F_op_and = F_op_opx & (F_iw_opx == 14); + assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); + assign F_op_slli = F_op_opx & (F_iw_opx == 18); + assign F_op_sll = F_op_opx & (F_iw_opx == 19); + assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); + assign F_op_or = F_op_opx & (F_iw_opx == 22); + assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); + assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); + assign F_op_srli = F_op_opx & (F_iw_opx == 26); + assign F_op_srl = F_op_opx & (F_iw_opx == 27); + assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); + assign F_op_callr = F_op_opx & (F_iw_opx == 29); + assign F_op_xor = F_op_opx & (F_iw_opx == 30); + assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); + assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); + assign F_op_divu = F_op_opx & (F_iw_opx == 36); + assign F_op_div = F_op_opx & (F_iw_opx == 37); + assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); + assign F_op_mul = F_op_opx & (F_iw_opx == 39); + assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); + assign F_op_initi = F_op_opx & (F_iw_opx == 41); + assign F_op_trap = F_op_opx & (F_iw_opx == 45); + assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); + assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); + assign F_op_add = F_op_opx & (F_iw_opx == 49); + assign F_op_break = F_op_opx & (F_iw_opx == 52); + assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); + assign F_op_sync = F_op_opx & (F_iw_opx == 54); + assign F_op_sub = F_op_opx & (F_iw_opx == 57); + assign F_op_srai = F_op_opx & (F_iw_opx == 58); + assign F_op_sra = F_op_opx & (F_iw_opx == 59); + assign F_op_intr = F_op_opx & (F_iw_opx == 61); + assign F_op_crst = F_op_opx & (F_iw_opx == 62); + assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); + assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); + assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); + assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); + assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); + assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); + assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); + assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); + assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); + assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); + assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); + assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); + assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); + assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); + assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); + assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); + assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); + assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); + assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); + assign F_op_opx = F_iw_op == 58; + assign F_op_custom = F_iw_op == 50; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + assign R_en = 1'b1; + assign E_ci_result = 0; + //custom_instruction_master, which is an e_custom_instruction_master + assign no_ci_readra = 1'b0; + assign E_ci_multi_stall = 1'b0; + assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000100000; + assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : + R_ctrl_break ? 2'b01 : + (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : + 2'b11; + + assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : + (F_pc_sel_nxt == 2'b01)? 66056 : + (F_pc_sel_nxt == 2'b10)? E_arith_result[18 : 2] : + F_pc_plus_one; + + assign F_pc_nxt = F_pc_no_crst_nxt; + assign F_pcb_nxt = {F_pc_nxt, 2'b00}; + assign F_pc_en = W_valid; + assign F_pc_plus_one = F_pc + 1; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + F_pc <= 0; + else if (F_pc_en) + F_pc <= F_pc_nxt; + end + + + assign F_pcb = {F_pc, 2'b00}; + assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; + assign F_valid = i_read & ~i_waitrequest; + assign i_read_nxt = W_valid | (i_read & i_waitrequest); + assign i_address = {F_pc, 2'b00}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + i_read <= 1'b1; + else + i_read <= i_read_nxt; + end + + + assign oci_tb_hbreak_req = oci_hbreak_req; + assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid); + assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled + : hbreak_req; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + wait_for_one_post_bret_inst <= 1'b0; + else + wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + hbreak_pending <= 1'b0; + else + hbreak_pending <= hbreak_pending_nxt; + end + + + assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); + assign F_av_iw = i_readdata; + assign F_iw = hbreak_req ? 4040762 : + 1'b0 ? 127034 : + intr_req ? 3926074 : + F_av_iw; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_iw <= 0; + else if (F_valid) + D_iw <= F_iw; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_valid <= 0; + else + D_valid <= F_valid; + end + + + assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : + D_ctrl_implicit_dst_eretaddr ? 5'd29 : + D_ctrl_b_is_dst ? D_iw_b : + D_iw_c; + + assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; + assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; + assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_jmp_direct_target_waddr = D_iw[31 : 6]; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_valid <= 0; + else + R_valid <= D_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_wr_dst_reg <= 0; + else + R_wr_dst_reg <= D_wr_dst_reg; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_dst_regnum <= 0; + else + R_dst_regnum <= D_dst_regnum; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_logic_op <= 0; + else + R_logic_op <= D_logic_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_compare_op <= 0; + else + R_compare_op <= D_compare_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_src2_use_imm <= 0; + else + R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); + end + + + assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; + assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; +//nios_system_nios2_processor_register_bank_a, which is an nios_sdp_ram +nios_system_nios2_processor_register_bank_a_module nios_system_nios2_processor_register_bank_a + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_a), + .rdaddress (D_iw_a), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.dat"; +`else +defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.mif"; +//synthesis read_comments_as_HDL off +//nios_system_nios2_processor_register_bank_b, which is an nios_sdp_ram +nios_system_nios2_processor_register_bank_b_module nios_system_nios2_processor_register_bank_b + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_b), + .rdaddress (D_iw_b), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.dat"; +`else +defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.mif"; +//synthesis read_comments_as_HDL off + assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : + ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : + R_rf_a; + + assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : + (R_src2_use_imm)? D_iw_imm16 : + R_rf_b[15 : 0]; + + assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : + (R_ctrl_hi_imm16)? D_iw_imm16 : + (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : + R_rf_b[31 : 16]; + + assign R_src2 = {R_src2_hi, R_src2_lo}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_valid <= 0; + else + E_valid <= R_valid | E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_new_inst <= 0; + else + E_new_inst <= R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src1 <= 0; + else + E_src1 <= R_src1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src2 <= 0; + else + E_src2 <= R_src2; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_invert_arith_src_msb <= 0; + else + E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_alu_sub <= 0; + else + E_alu_sub <= D_ctrl_alu_subtract & R_valid; + end + + + assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; + assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, + E_src1[30 : 0]}; + + assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, + E_src2[30 : 0]}; + + assign E_arith_result = E_alu_sub ? + E_arith_src1 - E_arith_src2 : + E_arith_src1 + E_arith_src2; + + assign E_mem_baddr = E_arith_result[18 : 0]; + assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : + (R_logic_op == 2'b01)? (E_src1 & E_src2) : + (R_logic_op == 2'b10)? (E_src1 | E_src2) : + (E_src1 ^ E_src2); + + assign E_logic_result_is_0 = E_logic_result == 0; + assign E_eq = E_logic_result_is_0; + assign E_lt = E_arith_result[32]; + assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : + (R_compare_op == 2'b01)? ~E_lt : + (R_compare_op == 2'b10)? E_lt : + ~E_eq; + + assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; + assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; + assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; + assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : + (R_ctrl_rot_right ? E_shift_rot_result[0] : + E_shift_rot_result[31]); + + assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : + (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : + {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_result <= 0; + else + E_shift_rot_result <= E_shift_rot_result_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_cnt <= 0; + else + E_shift_rot_cnt <= E_shift_rot_cnt_nxt; + end + + + assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : + (D_iw_control_regnum == 3'd1)? W_estatus_reg : + (D_iw_control_regnum == 3'd2)? W_bstatus_reg : + (D_iw_control_regnum == 3'd3)? W_ienable_reg : + (D_iw_control_regnum == 3'd4)? W_ipending_reg : + 0; + + assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : + (R_ctrl_shift_rot)? E_shift_rot_result : + (R_ctrl_logic)? E_logic_result : + (R_ctrl_custom)? E_ci_result : + E_arith_result; + + assign R_stb_data = R_rf_b[7 : 0]; + assign R_sth_data = R_rf_b[15 : 0]; + assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : + (D_mem16)? {R_sth_data, R_sth_data} : + R_rf_b; + + assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : + 4'b1111; + + assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); + assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); + assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); + assign E_st_stall = d_write_nxt; + assign d_address = W_mem_baddr; + assign av_ld_getting_data = d_read & ~d_waitrequest; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_read <= 0; + else + d_read <= d_read_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_writedata <= 0; + else + d_writedata <= E_st_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_byteenable <= 0; + else + d_byteenable <= E_mem_byte_en; + end + + + assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); + assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); + assign av_ld_aligning_data_nxt = av_ld_aligning_data ? + ~av_ld_align_one_more_cycle : + (~D_mem32 & av_ld_getting_data); + + assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? + ~av_ld_getting_data : + (R_ctrl_ld & E_new_inst); + + assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); + assign av_ld_rshift8 = av_ld_aligning_data & + (av_ld_align_cycle < (W_mem_baddr[1 : 0])); + + assign av_ld_extend = av_ld_aligning_data; + assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : + av_ld_extend ? av_ld_byte0_data : + d_readdata[7 : 0]; + + assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[15 : 8]; + + assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[23 : 16]; + + assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[31 : 24]; + + assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); + assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, + av_ld_byte1_data, av_ld_byte0_data}; + + assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; + assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_align_cycle <= 0; + else + av_ld_align_cycle <= av_ld_align_cycle_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_waiting_for_data <= 0; + else + av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_aligning_data <= 0; + else + av_ld_aligning_data <= av_ld_aligning_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte0_data <= 0; + else + av_ld_byte0_data <= av_ld_byte0_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte1_data <= 0; + else if (av_ld_byte1_data_en) + av_ld_byte1_data <= av_ld_byte1_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte2_data <= 0; + else + av_ld_byte2_data <= av_ld_byte2_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte3_data <= 0; + else + av_ld_byte3_data <= av_ld_byte3_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_valid <= 0; + else + W_valid <= E_valid & ~E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_control_rd_data <= 0; + else + W_control_rd_data <= E_control_rd_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_cmp_result <= 0; + else + W_cmp_result <= E_cmp_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_alu_result <= 0; + else + W_alu_result <= E_alu_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_status_reg_pie <= 0; + else + W_status_reg_pie <= W_status_reg_pie_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_estatus_reg <= 0; + else + W_estatus_reg <= W_estatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_bstatus_reg <= 0; + else + W_bstatus_reg <= W_bstatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ienable_reg <= 0; + else + W_ienable_reg <= W_ienable_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ipending_reg <= 0; + else + W_ipending_reg <= W_ipending_reg_nxt; + end + + + assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : + R_ctrl_rdctl_inst ? W_control_rd_data : + W_alu_result[31 : 0]; + + assign W_wr_data = W_wr_data_non_zero; + assign W_br_taken = R_ctrl_br & W_cmp_result; + assign W_mem_baddr = W_alu_result[18 : 0]; + assign W_status_reg = W_status_reg_pie; + assign E_wrctl_status = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd0); + + assign E_wrctl_estatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd1); + + assign E_wrctl_bstatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd2); + + assign E_wrctl_ienable = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd3); + + assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : + (D_op_eret) ? W_estatus_reg : + (D_op_bret) ? W_bstatus_reg : + (E_wrctl_status) ? E_src1[0] : + W_status_reg_pie; + + assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; + assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : + (R_ctrl_exception) ? W_status_reg : + (E_wrctl_estatus) ? E_src1[0] : + W_estatus_reg; + + assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; + assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : + (E_wrctl_bstatus) ? E_src1[0] : + W_bstatus_reg; + + assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; + assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? + E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000100000; + + assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000100000; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + hbreak_enabled <= 1'b1; + else if (E_valid) + hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled; + end + + + nios_system_nios2_processor_nios2_oci the_nios_system_nios2_processor_nios2_oci + ( + .D_valid (D_valid), + .E_st_data (E_st_data), + .E_valid (E_valid), + .F_pc (F_pc), + .address_nxt (jtag_debug_module_address), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .byteenable_nxt (jtag_debug_module_byteenable), + .clk (jtag_debug_module_clk), + .d_address (d_address), + .d_read (d_read), + .d_waitrequest (d_waitrequest), + .d_write (d_write), + .debugaccess_nxt (jtag_debug_module_debugaccess), + .hbreak_enabled (hbreak_enabled), + .jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms), + .oci_hbreak_req (oci_hbreak_req), + .oci_ienable (oci_ienable), + .oci_single_step_mode (oci_single_step_mode), + .read_nxt (jtag_debug_module_read), + .readdata (jtag_debug_module_readdata), + .reset (jtag_debug_module_reset), + .reset_n (reset_n), + .resetrequest (jtag_debug_module_resetrequest), + .test_ending (test_ending), + .test_has_ended (test_has_ended), + .waitrequest (jtag_debug_module_waitrequest), + .write_nxt (jtag_debug_module_write), + .writedata_nxt (jtag_debug_module_writedata) + ); + + //jtag_debug_module, which is an e_avalon_slave + assign jtag_debug_module_clk = clk; + assign jtag_debug_module_reset = ~reset_n; + assign D_ctrl_custom = 1'b0; + assign R_ctrl_custom_nxt = D_ctrl_custom; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom <= 0; + else if (R_en) + R_ctrl_custom <= R_ctrl_custom_nxt; + end + + + assign D_ctrl_custom_multi = 1'b0; + assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom_multi <= 0; + else if (R_en) + R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; + end + + + assign D_ctrl_jmp_indirect = D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_indirect <= 0; + else if (R_en) + R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; + end + + + assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; + assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_direct <= 0; + else if (R_en) + R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; + end + + + assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; + assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_retaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; + end + + + assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; + assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_eretaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; + end + + + assign D_ctrl_exception = D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60; + + assign R_ctrl_exception_nxt = D_ctrl_exception; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_exception <= 0; + else if (R_en) + R_ctrl_exception <= R_ctrl_exception_nxt; + end + + + assign D_ctrl_break = D_op_break|D_op_hbreak; + assign R_ctrl_break_nxt = D_ctrl_break; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_break <= 0; + else if (R_en) + R_ctrl_break <= R_ctrl_break_nxt; + end + + + assign D_ctrl_crst = D_op_crst|D_op_rsvx63; + assign R_ctrl_crst_nxt = D_ctrl_crst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_crst <= 0; + else if (R_en) + R_ctrl_crst <= R_ctrl_crst_nxt; + end + + + assign D_ctrl_uncond_cti_non_br = D_op_call| + D_op_jmpi| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_uncond_cti_non_br <= 0; + else if (R_en) + R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; + end + + + assign D_ctrl_retaddr = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak; + + assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_retaddr <= 0; + else if (R_en) + R_ctrl_retaddr <= R_ctrl_retaddr_nxt; + end + + + assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; + assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_logical <= 0; + else if (R_en) + R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; + end + + + assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; + assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_right_arith <= 0; + else if (R_en) + R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; + end + + + assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; + assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rot_right <= 0; + else if (R_en) + R_ctrl_rot_right <= R_ctrl_rot_right_nxt; + end + + + assign D_ctrl_shift_rot_right = D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot_right <= 0; + else if (R_en) + R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; + end + + + assign D_ctrl_shift_rot = D_op_slli| + D_op_rsvx50| + D_op_sll| + D_op_rsvx51| + D_op_roli| + D_op_rsvx34| + D_op_rol| + D_op_rsvx35| + D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot <= 0; + else if (R_en) + R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; + end + + + assign D_ctrl_logic = D_op_and| + D_op_or| + D_op_xor| + D_op_nor| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori; + + assign R_ctrl_logic_nxt = D_ctrl_logic; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_logic <= 0; + else if (R_en) + R_ctrl_logic <= R_ctrl_logic_nxt; + end + + + assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; + assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_hi_imm16 <= 0; + else if (R_en) + R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; + end + + + assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| + D_op_cmpltui| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_unsigned_lo_imm16 <= 0; + else if (R_en) + R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; + end + + + assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; + assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_uncond <= 0; + else if (R_en) + R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; + end + + + assign D_ctrl_br = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62; + + assign R_ctrl_br_nxt = D_ctrl_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br <= 0; + else if (R_en) + R_ctrl_br <= R_ctrl_br_nxt; + end + + + assign D_ctrl_alu_subtract = D_op_sub| + D_op_rsvx25| + D_op_cmplti| + D_op_cmpltui| + D_op_cmplt| + D_op_cmpltu| + D_op_blt| + D_op_bltu| + D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpge| + D_op_cmpgeu| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42; + + assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_subtract <= 0; + else if (R_en) + R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; + end + + + assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; + assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_signed_comparison <= 0; + else if (R_en) + R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; + end + + + assign D_ctrl_br_cmp = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_rsvx00| + D_op_cmpge| + D_op_cmplt| + D_op_cmpne| + D_op_cmpgeu| + D_op_cmpltu| + D_op_cmpeq| + D_op_rsvx56; + + assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_cmp <= 0; + else if (R_en) + R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; + end + + + assign D_ctrl_ld_signed = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63; + + assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_signed <= 0; + else if (R_en) + R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; + end + + + assign D_ctrl_ld = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio; + + assign R_ctrl_ld_nxt = D_ctrl_ld; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld <= 0; + else if (R_en) + R_ctrl_ld <= R_ctrl_ld_nxt; + end + + + assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; + assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_non_io <= 0; + else if (R_en) + R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; + end + + + assign D_ctrl_st = D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61; + + assign R_ctrl_st_nxt = D_ctrl_st; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_st <= 0; + else if (R_en) + R_ctrl_st <= R_ctrl_st_nxt; + end + + + assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; + assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_io <= 0; + else if (R_en) + R_ctrl_ld_io <= R_ctrl_ld_io_nxt; + end + + + assign D_ctrl_b_is_dst = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda; + + assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_b_is_dst <= 0; + else if (R_en) + R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; + end + + + assign D_ctrl_ignore_dst = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57; + + assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ignore_dst <= 0; + else if (R_en) + R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; + end + + + assign D_ctrl_src2_choose_imm = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_src2_choose_imm <= 0; + else if (R_en) + R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; + end + + + assign D_ctrl_wrctl_inst = D_op_wrctl; + assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_wrctl_inst <= 0; + else if (R_en) + R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; + end + + + assign D_ctrl_rdctl_inst = D_op_rdctl; + assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rdctl_inst <= 0; + else if (R_en) + R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; + end + + + assign D_ctrl_force_src2_zero = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_jmpi; + + assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_force_src2_zero <= 0; + else if (R_en) + R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; + end + + + assign D_ctrl_alu_force_xor = D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpeqi| + D_op_cmpge| + D_op_cmpgeu| + D_op_cmpeq| + D_op_cmpnei| + D_op_cmpne| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42| + D_op_beq| + D_op_rsv34| + D_op_bne| + D_op_rsv62| + D_op_br| + D_op_rsv02; + + assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_force_xor <= 0; + else if (R_en) + R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; + end + + + //data_master, which is an e_avalon_master + //instruction_master, which is an e_avalon_master + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign F_inst = (F_op_call)? 56'h20202063616c6c : + (F_op_jmpi)? 56'h2020206a6d7069 : + (F_op_ldbu)? 56'h2020206c646275 : + (F_op_addi)? 56'h20202061646469 : + (F_op_stb)? 56'h20202020737462 : + (F_op_br)? 56'h20202020206272 : + (F_op_ldb)? 56'h202020206c6462 : + (F_op_cmpgei)? 56'h20636d70676569 : + (F_op_ldhu)? 56'h2020206c646875 : + (F_op_andi)? 56'h202020616e6469 : + (F_op_sth)? 56'h20202020737468 : + (F_op_bge)? 56'h20202020626765 : + (F_op_ldh)? 56'h202020206c6468 : + (F_op_cmplti)? 56'h20636d706c7469 : + (F_op_initda)? 56'h20696e69746461 : + (F_op_ori)? 56'h202020206f7269 : + (F_op_stw)? 56'h20202020737477 : + (F_op_blt)? 56'h20202020626c74 : + (F_op_ldw)? 56'h202020206c6477 : + (F_op_cmpnei)? 56'h20636d706e6569 : + (F_op_flushda)? 56'h666c7573686461 : + (F_op_xori)? 56'h202020786f7269 : + (F_op_bne)? 56'h20202020626e65 : + (F_op_cmpeqi)? 56'h20636d70657169 : + (F_op_ldbuio)? 56'h206c646275696f : + (F_op_muli)? 56'h2020206d756c69 : + (F_op_stbio)? 56'h2020737462696f : + (F_op_beq)? 56'h20202020626571 : + (F_op_ldbio)? 56'h20206c6462696f : + (F_op_cmpgeui)? 56'h636d7067657569 : + (F_op_ldhuio)? 56'h206c646875696f : + (F_op_andhi)? 56'h2020616e646869 : + (F_op_sthio)? 56'h2020737468696f : + (F_op_bgeu)? 56'h20202062676575 : + (F_op_ldhio)? 56'h20206c6468696f : + (F_op_cmpltui)? 56'h636d706c747569 : + (F_op_initd)? 56'h2020696e697464 : + (F_op_orhi)? 56'h2020206f726869 : + (F_op_stwio)? 56'h2020737477696f : + (F_op_bltu)? 56'h202020626c7475 : + (F_op_ldwio)? 56'h20206c6477696f : + (F_op_flushd)? 56'h20666c75736864 : + (F_op_xorhi)? 56'h2020786f726869 : + (F_op_eret)? 56'h20202065726574 : + (F_op_roli)? 56'h202020726f6c69 : + (F_op_rol)? 56'h20202020726f6c : + (F_op_flushp)? 56'h20666c75736870 : + (F_op_ret)? 56'h20202020726574 : + (F_op_nor)? 56'h202020206e6f72 : + (F_op_mulxuu)? 56'h206d756c787575 : + (F_op_cmpge)? 56'h2020636d706765 : + (F_op_bret)? 56'h20202062726574 : + (F_op_ror)? 56'h20202020726f72 : + (F_op_flushi)? 56'h20666c75736869 : + (F_op_jmp)? 56'h202020206a6d70 : + (F_op_and)? 56'h20202020616e64 : + (F_op_cmplt)? 56'h2020636d706c74 : + (F_op_slli)? 56'h202020736c6c69 : + (F_op_sll)? 56'h20202020736c6c : + (F_op_or)? 56'h20202020206f72 : + (F_op_mulxsu)? 56'h206d756c787375 : + (F_op_cmpne)? 56'h2020636d706e65 : + (F_op_srli)? 56'h20202073726c69 : + (F_op_srl)? 56'h2020202073726c : + (F_op_nextpc)? 56'h206e6578747063 : + (F_op_callr)? 56'h202063616c6c72 : + (F_op_xor)? 56'h20202020786f72 : + (F_op_mulxss)? 56'h206d756c787373 : + (F_op_cmpeq)? 56'h2020636d706571 : + (F_op_divu)? 56'h20202064697675 : + (F_op_div)? 56'h20202020646976 : + (F_op_rdctl)? 56'h2020726463746c : + (F_op_mul)? 56'h202020206d756c : + (F_op_cmpgeu)? 56'h20636d70676575 : + (F_op_initi)? 56'h2020696e697469 : + (F_op_trap)? 56'h20202074726170 : + (F_op_wrctl)? 56'h2020777263746c : + (F_op_cmpltu)? 56'h20636d706c7475 : + (F_op_add)? 56'h20202020616464 : + (F_op_break)? 56'h2020627265616b : + (F_op_hbreak)? 56'h2068627265616b : + (F_op_sync)? 56'h20202073796e63 : + (F_op_sub)? 56'h20202020737562 : + (F_op_srai)? 56'h20202073726169 : + (F_op_sra)? 56'h20202020737261 : + (F_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign D_inst = (D_op_call)? 56'h20202063616c6c : + (D_op_jmpi)? 56'h2020206a6d7069 : + (D_op_ldbu)? 56'h2020206c646275 : + (D_op_addi)? 56'h20202061646469 : + (D_op_stb)? 56'h20202020737462 : + (D_op_br)? 56'h20202020206272 : + (D_op_ldb)? 56'h202020206c6462 : + (D_op_cmpgei)? 56'h20636d70676569 : + (D_op_ldhu)? 56'h2020206c646875 : + (D_op_andi)? 56'h202020616e6469 : + (D_op_sth)? 56'h20202020737468 : + (D_op_bge)? 56'h20202020626765 : + (D_op_ldh)? 56'h202020206c6468 : + (D_op_cmplti)? 56'h20636d706c7469 : + (D_op_initda)? 56'h20696e69746461 : + (D_op_ori)? 56'h202020206f7269 : + (D_op_stw)? 56'h20202020737477 : + (D_op_blt)? 56'h20202020626c74 : + (D_op_ldw)? 56'h202020206c6477 : + (D_op_cmpnei)? 56'h20636d706e6569 : + (D_op_flushda)? 56'h666c7573686461 : + (D_op_xori)? 56'h202020786f7269 : + (D_op_bne)? 56'h20202020626e65 : + (D_op_cmpeqi)? 56'h20636d70657169 : + (D_op_ldbuio)? 56'h206c646275696f : + (D_op_muli)? 56'h2020206d756c69 : + (D_op_stbio)? 56'h2020737462696f : + (D_op_beq)? 56'h20202020626571 : + (D_op_ldbio)? 56'h20206c6462696f : + (D_op_cmpgeui)? 56'h636d7067657569 : + (D_op_ldhuio)? 56'h206c646875696f : + (D_op_andhi)? 56'h2020616e646869 : + (D_op_sthio)? 56'h2020737468696f : + (D_op_bgeu)? 56'h20202062676575 : + (D_op_ldhio)? 56'h20206c6468696f : + (D_op_cmpltui)? 56'h636d706c747569 : + (D_op_initd)? 56'h2020696e697464 : + (D_op_orhi)? 56'h2020206f726869 : + (D_op_stwio)? 56'h2020737477696f : + (D_op_bltu)? 56'h202020626c7475 : + (D_op_ldwio)? 56'h20206c6477696f : + (D_op_flushd)? 56'h20666c75736864 : + (D_op_xorhi)? 56'h2020786f726869 : + (D_op_eret)? 56'h20202065726574 : + (D_op_roli)? 56'h202020726f6c69 : + (D_op_rol)? 56'h20202020726f6c : + (D_op_flushp)? 56'h20666c75736870 : + (D_op_ret)? 56'h20202020726574 : + (D_op_nor)? 56'h202020206e6f72 : + (D_op_mulxuu)? 56'h206d756c787575 : + (D_op_cmpge)? 56'h2020636d706765 : + (D_op_bret)? 56'h20202062726574 : + (D_op_ror)? 56'h20202020726f72 : + (D_op_flushi)? 56'h20666c75736869 : + (D_op_jmp)? 56'h202020206a6d70 : + (D_op_and)? 56'h20202020616e64 : + (D_op_cmplt)? 56'h2020636d706c74 : + (D_op_slli)? 56'h202020736c6c69 : + (D_op_sll)? 56'h20202020736c6c : + (D_op_or)? 56'h20202020206f72 : + (D_op_mulxsu)? 56'h206d756c787375 : + (D_op_cmpne)? 56'h2020636d706e65 : + (D_op_srli)? 56'h20202073726c69 : + (D_op_srl)? 56'h2020202073726c : + (D_op_nextpc)? 56'h206e6578747063 : + (D_op_callr)? 56'h202063616c6c72 : + (D_op_xor)? 56'h20202020786f72 : + (D_op_mulxss)? 56'h206d756c787373 : + (D_op_cmpeq)? 56'h2020636d706571 : + (D_op_divu)? 56'h20202064697675 : + (D_op_div)? 56'h20202020646976 : + (D_op_rdctl)? 56'h2020726463746c : + (D_op_mul)? 56'h202020206d756c : + (D_op_cmpgeu)? 56'h20636d70676575 : + (D_op_initi)? 56'h2020696e697469 : + (D_op_trap)? 56'h20202074726170 : + (D_op_wrctl)? 56'h2020777263746c : + (D_op_cmpltu)? 56'h20636d706c7475 : + (D_op_add)? 56'h20202020616464 : + (D_op_break)? 56'h2020627265616b : + (D_op_hbreak)? 56'h2068627265616b : + (D_op_sync)? 56'h20202073796e63 : + (D_op_sub)? 56'h20202020737562 : + (D_op_srai)? 56'h20202073726169 : + (D_op_sra)? 56'h20202020737261 : + (D_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; + assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; + assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; + assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; + assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v new file mode 100644 index 0000000..7daaec7 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v @@ -0,0 +1,181 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_sysclk ( + // inputs: + clk, + ir_in, + sr, + vs_udr, + vs_uir, + + // outputs: + jdo, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input clk; + input [ 1: 0] ir_in; + input [ 37: 0] sr; + input vs_udr; + input vs_uir; + + reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + wire sync_udr; + wire sync_uir; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire unxunused_resetxx3; + wire unxunused_resetxx4; + reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + assign unxunused_resetxx3 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer3 + ( + .clk (clk), + .din (vs_udr), + .dout (sync_udr), + .reset_n (unxunused_resetxx3) + ); + + defparam the_altera_std_synchronizer3.depth = 2; + + assign unxunused_resetxx4 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer4 + ( + .clk (clk), + .din (vs_uir), + .dout (sync_uir), + .reset_n (unxunused_resetxx4) + ); + + defparam the_altera_std_synchronizer4.depth = 2; + + always @(posedge clk) + begin + sync2_udr <= sync_udr; + update_jdo_strobe <= sync_udr & ~sync2_udr; + enable_action_strobe <= update_jdo_strobe; + sync2_uir <= sync_uir; + jxuir <= sync_uir & ~sync2_uir; + end + + + assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && jdo[34]; + + assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && ~jdo[34]; + + assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && + jdo[35]; + + assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + jdo[36]; + + assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + ~jdo[36]; + + assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && + jdo[37]; + + assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + jdo[37]; + + assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + ~jdo[37]; + + assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + jdo[37]; + + assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + ~jdo[37]; + + assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + jdo[37]; + + assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + ~jdo[37]; + + assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && + jdo[15]; + + always @(posedge clk) + begin + if (jxuir) + ir <= ir_in; + if (update_jdo_strobe) + jdo <= sr; + end + + + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v new file mode 100644 index 0000000..8e3a593 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v @@ -0,0 +1,239 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_tck ( + // inputs: + MonDReg, + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + ir_in, + jtag_state_rti, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tck, + tdi, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + vs_cdr, + vs_sdr, + vs_uir, + + // outputs: + ir_out, + jrst_n, + sr, + st_ready_test_idle, + tdo + ) +; + + output [ 1: 0] ir_out; + output jrst_n; + output [ 37: 0] sr; + output st_ready_test_idle; + output tdo; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input [ 1: 0] ir_in; + input jtag_state_rti; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tck; + input tdi; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + input vs_cdr; + input vs_sdr; + input vs_uir; + + reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire debugack_sync; + reg [ 1: 0] ir_out; + wire jrst_n; + wire monitor_ready_sync; + reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire st_ready_test_idle; + wire tdo; + wire unxcomplemented_resetxx1; + wire unxcomplemented_resetxx2; + always @(posedge tck) + begin + if (vs_cdr) + case (ir_in) + + 2'b00: begin + sr[35] <= debugack_sync; + sr[34] <= monitor_error; + sr[33] <= resetlatch; + sr[32 : 1] <= MonDReg; + sr[0] <= monitor_ready_sync; + end // 2'b00 + + 2'b01: begin + sr[35 : 0] <= tracemem_trcdata; + sr[37] <= tracemem_tw; + sr[36] <= tracemem_on; + end // 2'b01 + + 2'b10: begin + sr[37] <= trigger_state_1; + sr[36] <= dbrk_hit3_latch; + sr[35] <= dbrk_hit2_latch; + sr[34] <= dbrk_hit1_latch; + sr[33] <= dbrk_hit0_latch; + sr[32 : 1] <= break_readreg; + sr[0] <= trigbrktype; + end // 2'b10 + + 2'b11: begin + sr[15 : 12] <= 1'b0; + sr[11 : 2] <= trc_im_addr; + sr[1] <= trc_wrap; + sr[0] <= trc_on; + end // 2'b11 + + endcase // ir_in + if (vs_sdr) + case (DRsize) + + 3'b000: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // 3'b000 + + 3'b001: begin + sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; + end // 3'b001 + + 3'b010: begin + sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; + end // 3'b010 + + 3'b011: begin + sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; + end // 3'b011 + + 3'b100: begin + sr <= {tdi, sr[37], tdi, sr[35 : 1]}; + end // 3'b100 + + 3'b101: begin + sr <= {tdi, sr[37 : 1]}; + end // 3'b101 + + default: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // default + + endcase // DRsize + if (vs_uir) + case (ir_in) + + 2'b00: begin + DRsize <= 3'b100; + end // 2'b00 + + 2'b01: begin + DRsize <= 3'b101; + end // 2'b01 + + 2'b10: begin + DRsize <= 3'b101; + end // 2'b10 + + 2'b11: begin + DRsize <= 3'b010; + end // 2'b11 + + endcase // ir_in + end + + + assign tdo = sr[0]; + assign st_ready_test_idle = jtag_state_rti; + assign unxcomplemented_resetxx1 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer1 + ( + .clk (tck), + .din (debugack), + .dout (debugack_sync), + .reset_n (unxcomplemented_resetxx1) + ); + + defparam the_altera_std_synchronizer1.depth = 2; + + assign unxcomplemented_resetxx2 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer2 + ( + .clk (tck), + .din (monitor_ready), + .dout (monitor_ready_sync), + .reset_n (unxcomplemented_resetxx2) + ); + + defparam the_altera_std_synchronizer2.depth = 2; + + always @(posedge tck or negedge jrst_n) + begin + if (jrst_n == 0) + ir_out <= 2'b0; + else + ir_out <= {debugack_sync, monitor_ready_sync}; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign jrst_n = reset_n; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// assign jrst_n = 1; +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v new file mode 100644 index 0000000..1fd5cb7 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v @@ -0,0 +1,233 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_wrapper ( + // inputs: + MonDReg, + break_readreg, + clk, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + + // outputs: + jdo, + jrst_n, + st_ready_test_idle, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output jrst_n; + output st_ready_test_idle; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input clk; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + + wire [ 37: 0] jdo; + wire jrst_n; + wire [ 37: 0] sr; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire vji_cdr; + wire [ 1: 0] vji_ir_in; + wire [ 1: 0] vji_ir_out; + wire vji_rti; + wire vji_sdr; + wire vji_tck; + wire vji_tdi; + wire vji_tdo; + wire vji_udr; + wire vji_uir; + //Change the sld_virtual_jtag_basic's defparams to + //switch between a regular Nios II or an internally embedded Nios II. + //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. + //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. + nios_system_nios2_processor_jtag_debug_module_tck the_nios_system_nios2_processor_jtag_debug_module_tck + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .ir_in (vji_ir_in), + .ir_out (vji_ir_out), + .jrst_n (jrst_n), + .jtag_state_rti (vji_rti), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .sr (sr), + .st_ready_test_idle (st_ready_test_idle), + .tck (vji_tck), + .tdi (vji_tdi), + .tdo (vji_tdo), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1), + .vs_cdr (vji_cdr), + .vs_sdr (vji_sdr), + .vs_uir (vji_uir) + ); + + nios_system_nios2_processor_jtag_debug_module_sysclk the_nios_system_nios2_processor_jtag_debug_module_sysclk + ( + .clk (clk), + .ir_in (vji_ir_in), + .jdo (jdo), + .sr (sr), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .vs_udr (vji_udr), + .vs_uir (vji_uir) + ); + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign vji_tck = 1'b0; + assign vji_tdi = 1'b0; + assign vji_sdr = 1'b0; + assign vji_cdr = 1'b0; + assign vji_rti = 1'b0; + assign vji_uir = 1'b0; + assign vji_udr = 1'b0; + assign vji_ir_in = 2'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// sld_virtual_jtag_basic nios_system_nios2_processor_jtag_debug_module_phy +// ( +// .ir_in (vji_ir_in), +// .ir_out (vji_ir_out), +// .jtag_state_rti (vji_rti), +// .tck (vji_tck), +// .tdi (vji_tdi), +// .tdo (vji_tdo), +// .virtual_state_cdr (vji_cdr), +// .virtual_state_sdr (vji_sdr), +// .virtual_state_udr (vji_udr), +// .virtual_state_uir (vji_uir) +// ); +// +// defparam nios_system_nios2_processor_jtag_debug_module_phy.sld_auto_instance_index = "YES", +// nios_system_nios2_processor_jtag_debug_module_phy.sld_instance_index = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_ir_width = 2, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_mfg_id = 70, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_action = "", +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_n_scan = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_total_length = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_type_id = 34, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_version = 3; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v new file mode 100644 index 0000000..0046686 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v @@ -0,0 +1,37 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_oci_test_bench ( + // inputs: + dct_buffer, + dct_count, + test_ending, + test_has_ended + ) +; + + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input test_ending; + input test_has_ended; + + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif new file mode 100644 index 0000000..44481aa --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif @@ -0,0 +1,267 @@ +-- Contents are randomly generated during RTL generation. +WIDTH=32; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : 88997af9; +01 : abaae595; +02 : 32fd14d1; +03 : b66193c4; +04 : c6a6aa09; +05 : 0b43de5b; +06 : d1d93028; +07 : bcd08e2a; +08 : 1c8bae85; +09 : b11dad63; +0a : 864ddf62; +0b : 68301486; +0c : 51a3d8d0; +0d : 7af7d39e; +0e : 4761b503; +0f : 2a976e14; +10 : 98141041; +11 : 4c1f6471; +12 : 41dc0a35; +13 : 7d484ae3; +14 : 2a1329f3; +15 : 44ecf499; +16 : dccdd125; +17 : 240142e9; +18 : 3b7e4b05; +19 : bb92e762; +1a : 4594a3c5; +1b : ea0d940f; +1c : 66525d7c; +1d : 0f552242; +1e : 452bd52d; +1f : d1f4ed11; +20 : 5d590422; +21 : c8016b5f; +22 : 9ab94f07; +23 : 16bac9b4; +24 : fe569ae3; +25 : c6e1e6e7; +26 : 2ff19932; +27 : feb058ad; +28 : 1dcce651; +29 : e18b9bfb; +2a : e2f4fc64; +2b : 05d34847; +2c : 077a8143; +2d : 2ce4207f; +2e : 3f3e5113; +2f : c24d2803; +30 : e289b503; +31 : d16bcd4e; +32 : 57a841cf; +33 : 1194f754; +34 : 5c925a31; +35 : 40fd6946; +36 : e397e5d7; +37 : eada7553; +38 : eba8ec01; +39 : f5b39d0b; +3a : 88af39a3; +3b : 5b7f243e; +3c : 4f2bb4ba; +3d : 9451a234; +3e : 10fd984d; +3f : ad4ef4f7; +40 : 7fe97f8b; +41 : 08ea614d; +42 : 9f2c5cf4; +43 : 3f90b7a2; +44 : 8c2bc774; +45 : 45dd63a5; +46 : 3204329c; +47 : 9909be0d; +48 : be65c97b; +49 : 78f3d4a4; +4a : 3ee8b71c; +4b : 9e9a0de4; +4c : 56db426b; +4d : e6869d81; +4e : 20ab0652; +4f : 05d247ed; +50 : 1edccf12; +51 : 1e483b5a; +52 : 8e48ef1e; +53 : f19aefbf; +54 : 98335d23; +55 : 954ac923; +56 : 4679ced6; +57 : ae18d9b8; +58 : be57db48; +59 : 2af933e3; +5a : 3f04e244; +5b : 5d11c958; +5c : 65bda8cb; +5d : c53fe664; +5e : 797ceac8; +5f : aaa406e5; +60 : f785e24e; +61 : 95510077; +62 : 5b6f55a3; +63 : 2a3c749a; +64 : a92e6ae6; +65 : b2117fb0; +66 : 262a254e; +67 : b8c4da74; +68 : f69070ee; +69 : 9e7f80b8; +6a : 834528b4; +6b : 4aaf6d98; +6c : 96023372; +6d : d11663ed; +6e : 33a3c007; +6f : 0e7f06ee; +70 : 34385787; +71 : 2edfd7b0; +72 : 00d60e4b; +73 : 49535c30; +74 : e83f5c14; +75 : 5e0c4c59; +76 : 1d7b944a; +77 : 6ae69731; +78 : bf8414e4; +79 : 7451c212; +7a : 74ede6d2; +7b : 080eafa5; +7c : f21052d8; +7d : cc0819fb; +7e : 8993e5b6; +7f : e20f2df6; +80 : 0f267a65; +81 : 7a8e8407; +82 : e7be656d; +83 : 01ba4ca3; +84 : 7f998e44; +85 : 29d83420; +86 : 149f9a73; +87 : 643ae51e; +88 : 125714d3; +89 : 6e49dc21; +8a : 0b227946; +8b : 360a837d; +8c : b2187074; +8d : 17b0bdbd; +8e : 938fc73d; +8f : e73f501e; +90 : 70b5b87e; +91 : 2a2aed8a; +92 : f96cc881; +93 : 021b49e1; +94 : 8691600d; +95 : b45e1d12; +96 : 64d9644e; +97 : 486cbaf9; +98 : 386acf20; +99 : 0d1384d4; +9a : 62455f77; +9b : 866fde20; +9c : 006fecec; +9d : 94e84514; +9e : 7babc333; +9f : afaa8445; +a0 : b1175e3a; +a1 : e08de629; +a2 : 7f12a52d; +a3 : 0e322909; +a4 : 18784dc6; +a5 : b23bcc20; +a6 : 266c9e34; +a7 : c857eaf3; +a8 : 2ae3b164; +a9 : 038acf2a; +aa : c1abc60d; +ab : 8af787bd; +ac : 043723a9; +ad : c37c952d; +ae : 693a361f; +af : da4b8e99; +b0 : fb8fdb10; +b1 : 4d6365f2; +b2 : 712358e9; +b3 : 85dae0fa; +b4 : 7e82a418; +b5 : d3493768; +b6 : 739c65ec; +b7 : 73b66b19; +b8 : 22142816; +b9 : ff498322; +ba : 3266495e; +bb : e26e8214; +bc : c8c47131; +bd : 660793d8; +be : 689f8d69; +bf : faae340b; +c0 : 37518ba7; +c1 : f2865fe5; +c2 : 1bb44f3d; +c3 : 3bce44c5; +c4 : aff2d188; +c5 : 985442da; +c6 : 85bb58bd; +c7 : 0c53135d; +c8 : 495f80bc; +c9 : 853c95dc; +ca : dde937f1; +cb : 418f9452; +cc : 7669641c; +cd : 0e752434; +ce : b0fe17a7; +cf : d1be9b88; +d0 : cfbfeb76; +d1 : 80b48a11; +d2 : 9327c69e; +d3 : beca5a88; +d4 : e71d428f; +d5 : b318d275; +d6 : 56fea35e; +d7 : 140cd6bd; +d8 : b8c937ce; +d9 : 540eea36; +da : ee58fc7f; +db : 5615c389; +dc : 46692ad0; +dd : 5c713e51; +de : 6ba95f60; +df : 0e166732; +e0 : ac0e49f5; +e1 : c9a5ea76; +e2 : 05b04d86; +e3 : b29ac712; +e4 : 4e344493; +e5 : d45ede48; +e6 : 3da7e426; +e7 : 4d6a8937; +e8 : 99b59bd4; +e9 : 1f8a5751; +ea : 8b07e64e; +eb : b4dcd496; +ec : 42f84fe6; +ed : f1d5952f; +ee : a2e5a42d; +ef : 15b1af16; +f0 : 168012bc; +f1 : 2e276612; +f2 : 89913eaa; +f3 : c607a1a2; +f4 : fd8b544d; +f5 : aec31a53; +f6 : 25f958ad; +f7 : 365903ec; +f8 : 14761865; +f9 : 568cc23b; +fa : b0386305; +fb : fb9ebd8a; +fc : a25911d4; +fd : 806e3fbb; +fe : 9df35264; +ff : d62b3814; + +END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif new file mode 100644 index 0000000..7969f10 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif @@ -0,0 +1,42 @@ +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif new file mode 100644 index 0000000..7969f10 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif @@ -0,0 +1,42 @@ +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v new file mode 100644 index 0000000..9ce093e --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v @@ -0,0 +1,667 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_test_bench ( + // inputs: + D_iw, + D_iw_op, + D_iw_opx, + D_valid, + E_valid, + F_pcb, + F_valid, + R_ctrl_ld, + R_ctrl_ld_non_io, + R_dst_regnum, + R_wr_dst_reg, + W_valid, + W_vinst, + W_wr_data, + av_ld_data_aligned_unfiltered, + clk, + d_address, + d_byteenable, + d_read, + d_write_nxt, + i_address, + i_read, + i_readdata, + i_waitrequest, + reset_n, + + // outputs: + av_ld_data_aligned_filtered, + d_write, + test_has_ended + ) +; + + output [ 31: 0] av_ld_data_aligned_filtered; + output d_write; + output test_has_ended; + input [ 31: 0] D_iw; + input [ 5: 0] D_iw_op; + input [ 5: 0] D_iw_opx; + input D_valid; + input E_valid; + input [ 18: 0] F_pcb; + input F_valid; + input R_ctrl_ld; + input R_ctrl_ld_non_io; + input [ 4: 0] R_dst_regnum; + input R_wr_dst_reg; + input W_valid; + input [ 55: 0] W_vinst; + input [ 31: 0] W_wr_data; + input [ 31: 0] av_ld_data_aligned_unfiltered; + input clk; + input [ 18: 0] d_address; + input [ 3: 0] d_byteenable; + input d_read; + input d_write_nxt; + input [ 18: 0] i_address; + input i_read; + input [ 31: 0] i_readdata; + input i_waitrequest; + input reset_n; + + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire av_ld_data_aligned_unfiltered_0_is_x; + wire av_ld_data_aligned_unfiltered_10_is_x; + wire av_ld_data_aligned_unfiltered_11_is_x; + wire av_ld_data_aligned_unfiltered_12_is_x; + wire av_ld_data_aligned_unfiltered_13_is_x; + wire av_ld_data_aligned_unfiltered_14_is_x; + wire av_ld_data_aligned_unfiltered_15_is_x; + wire av_ld_data_aligned_unfiltered_16_is_x; + wire av_ld_data_aligned_unfiltered_17_is_x; + wire av_ld_data_aligned_unfiltered_18_is_x; + wire av_ld_data_aligned_unfiltered_19_is_x; + wire av_ld_data_aligned_unfiltered_1_is_x; + wire av_ld_data_aligned_unfiltered_20_is_x; + wire av_ld_data_aligned_unfiltered_21_is_x; + wire av_ld_data_aligned_unfiltered_22_is_x; + wire av_ld_data_aligned_unfiltered_23_is_x; + wire av_ld_data_aligned_unfiltered_24_is_x; + wire av_ld_data_aligned_unfiltered_25_is_x; + wire av_ld_data_aligned_unfiltered_26_is_x; + wire av_ld_data_aligned_unfiltered_27_is_x; + wire av_ld_data_aligned_unfiltered_28_is_x; + wire av_ld_data_aligned_unfiltered_29_is_x; + wire av_ld_data_aligned_unfiltered_2_is_x; + wire av_ld_data_aligned_unfiltered_30_is_x; + wire av_ld_data_aligned_unfiltered_31_is_x; + wire av_ld_data_aligned_unfiltered_3_is_x; + wire av_ld_data_aligned_unfiltered_4_is_x; + wire av_ld_data_aligned_unfiltered_5_is_x; + wire av_ld_data_aligned_unfiltered_6_is_x; + wire av_ld_data_aligned_unfiltered_7_is_x; + wire av_ld_data_aligned_unfiltered_8_is_x; + wire av_ld_data_aligned_unfiltered_9_is_x; + reg d_write; + wire test_has_ended; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_write <= 0; + else + d_write <= d_write_nxt; + end + + + assign test_has_ended = 1'b0; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //Clearing 'X' data bits + assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; + + assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; + assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; + assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; + assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; + assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; + assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; + assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; + assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; + assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; + assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; + assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; + assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; + assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; + assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; + assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; + assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; + assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; + assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; + assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; + assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; + assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; + assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; + assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; + assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; + assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; + assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; + assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; + assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; + assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; + assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; + assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; + assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; + assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; + assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; + assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; + assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; + assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; + assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; + assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; + assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; + assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; + assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; + assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; + assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; + assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; + assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; + assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; + assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; + assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; + assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; + assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; + assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; + assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; + assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; + assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; + assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; + assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; + assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; + assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; + assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; + assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; + assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; + assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; + always @(posedge clk) + begin + if (reset_n) + if (^(F_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/F_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(D_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/D_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(E_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/E_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(W_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid) + if (^(R_wr_dst_reg) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_wr_dst_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(R_dst_regnum) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_dst_regnum is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_write) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_write is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write) + if (^(d_byteenable) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_byteenable is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write | d_read) + if (^(d_address) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_read) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(i_read) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read) + if (^(i_address) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read & ~i_waitrequest) + if (^(i_readdata) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_readdata is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_ctrl_ld) + if (^(av_ld_data_aligned_unfiltered) === 1'bx) + begin + $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); + end + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// +// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_onchip_memory.hex b/nios_system/synthesis/submodules/nios_system_onchip_memory.hex new file mode 100644 index 0000000..e265501 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_onchip_memory.hex @@ -0,0 +1,51201 @@ +:0400000000000000FC +:0400010000000000FB +:0400020000000000FA +:0400030000000000F9 +:0400040000000000F8 +:0400050000000000F7 +:0400060000000000F6 +:0400070000000000F5 +:0400080000000000F4 +:0400090000000000F3 +:04000A0000000000F2 +:04000B0000000000F1 +:04000C0000000000F0 +:04000D0000000000EF +:04000E0000000000EE +:04000F0000000000ED +:0400100000000000EC +:0400110000000000EB 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a/nios_system/synthesis/submodules/nios_system_onchip_memory.v b/nios_system/synthesis/submodules/nios_system_onchip_memory.v new file mode 100644 index 0000000..c12e1cd --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_onchip_memory.v @@ -0,0 +1,85 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_onchip_memory ( + // inputs: + address, + byteenable, + chipselect, + clk, + clken, + reset, + reset_req, + write, + writedata, + + // outputs: + readdata + ) +; + + parameter INIT_FILE = "nios_system_onchip_memory.hex"; + + + output [ 31: 0] readdata; + input [ 15: 0] address; + input [ 3: 0] byteenable; + input chipselect; + input clk; + input clken; + input reset; + input reset_req; + input write; + input [ 31: 0] writedata; + + wire clocken0; + wire [ 31: 0] readdata; + wire wren; + assign wren = chipselect & write; + assign clocken0 = clken & ~reset_req; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clk), + .clocken0 (clocken0), + .data_a (writedata), + .q_a (readdata), + .wren_a (wren) + ); + + defparam the_altsyncram.byte_size = 8, + the_altsyncram.init_file = INIT_FILE, + the_altsyncram.lpm_type = "altsyncram", + the_altsyncram.maximum_depth = 51200, + the_altsyncram.numwords_a = 51200, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 16; + + //s1, which is an e_avalon_slave + //s2, which is an e_avalon_slave + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_pio_0.v b/nios_system/synthesis/submodules/nios_system_pio_0.v new file mode 100644 index 0000000..9cd2e61 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_pio_0.v @@ -0,0 +1,58 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_pio_0 ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 17: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 17: 0] data_in; + wire [ 17: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_push_switches.v b/nios_system/synthesis/submodules/nios_system_push_switches.v new file mode 100644 index 0000000..5b3cb8d --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_push_switches.v @@ -0,0 +1,58 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_push_switches ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 2: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 2: 0] data_in; + wire [ 2: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {3 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv new file mode 100644 index 0000000..44c4d45 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv @@ -0,0 +1,116 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv new file mode 100644 index 0000000..52411df --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv @@ -0,0 +1,101 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux_002 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux_002 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv new file mode 100644 index 0000000..755ac9e --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv @@ -0,0 +1,101 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux_003 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux_003 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv new file mode 100644 index 0000000..6f30bfb --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv @@ -0,0 +1,331 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_rsp_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv new file mode 100644 index 0000000..ce9f7a1 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv @@ -0,0 +1,651 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_mux_001 +// NUM_INPUTS: 18 +// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_rsp_xbar_mux_001 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + input sink2_valid, + input [96-1 : 0] sink2_data, + input [18-1: 0] sink2_channel, + input sink2_startofpacket, + input sink2_endofpacket, + output sink2_ready, + + input sink3_valid, + input [96-1 : 0] sink3_data, + input [18-1: 0] sink3_channel, + input sink3_startofpacket, + input sink3_endofpacket, + output sink3_ready, + + input sink4_valid, + input [96-1 : 0] sink4_data, + input [18-1: 0] sink4_channel, + input sink4_startofpacket, + input sink4_endofpacket, + output sink4_ready, + + input sink5_valid, + input [96-1 : 0] sink5_data, + input [18-1: 0] sink5_channel, + input sink5_startofpacket, + input sink5_endofpacket, + output sink5_ready, + + input sink6_valid, + input [96-1 : 0] sink6_data, + input [18-1: 0] sink6_channel, + input sink6_startofpacket, + input sink6_endofpacket, + output sink6_ready, + + input sink7_valid, + input [96-1 : 0] sink7_data, + input [18-1: 0] sink7_channel, + input sink7_startofpacket, + input sink7_endofpacket, + output sink7_ready, + + input sink8_valid, + input [96-1 : 0] sink8_data, + input [18-1: 0] sink8_channel, + input sink8_startofpacket, + input sink8_endofpacket, + output sink8_ready, + + input sink9_valid, + input [96-1 : 0] sink9_data, + input [18-1: 0] sink9_channel, + input sink9_startofpacket, + input sink9_endofpacket, + output sink9_ready, + + input sink10_valid, + input [96-1 : 0] sink10_data, + input [18-1: 0] sink10_channel, + input sink10_startofpacket, + input sink10_endofpacket, + output sink10_ready, + + input sink11_valid, + input [96-1 : 0] sink11_data, + input [18-1: 0] sink11_channel, + input sink11_startofpacket, + input sink11_endofpacket, + output sink11_ready, + + input sink12_valid, + input [96-1 : 0] sink12_data, + input [18-1: 0] sink12_channel, + input sink12_startofpacket, + input sink12_endofpacket, + output sink12_ready, + + input sink13_valid, + input [96-1 : 0] sink13_data, + input [18-1: 0] sink13_channel, + input sink13_startofpacket, + input sink13_endofpacket, + output sink13_ready, + + input sink14_valid, + input [96-1 : 0] sink14_data, + input [18-1: 0] sink14_channel, + input sink14_startofpacket, + input sink14_endofpacket, + output sink14_ready, + + input sink15_valid, + input [96-1 : 0] sink15_data, + input [18-1: 0] sink15_channel, + input sink15_startofpacket, + input sink15_endofpacket, + output sink15_ready, + + input sink16_valid, + input [96-1 : 0] sink16_data, + input [18-1: 0] sink16_channel, + input sink16_startofpacket, + input sink16_endofpacket, + output sink16_ready, + + input sink17_valid, + input [96-1 : 0] sink17_data, + input [18-1: 0] sink17_channel, + input sink17_startofpacket, + input sink17_endofpacket, + output sink17_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 18; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + wire [PAYLOAD_W - 1 : 0] sink2_payload; + wire [PAYLOAD_W - 1 : 0] sink3_payload; + wire [PAYLOAD_W - 1 : 0] sink4_payload; + wire [PAYLOAD_W - 1 : 0] sink5_payload; + wire [PAYLOAD_W - 1 : 0] sink6_payload; + wire [PAYLOAD_W - 1 : 0] sink7_payload; + wire [PAYLOAD_W - 1 : 0] sink8_payload; + wire [PAYLOAD_W - 1 : 0] sink9_payload; + wire [PAYLOAD_W - 1 : 0] sink10_payload; + wire [PAYLOAD_W - 1 : 0] sink11_payload; + wire [PAYLOAD_W - 1 : 0] sink12_payload; + wire [PAYLOAD_W - 1 : 0] sink13_payload; + wire [PAYLOAD_W - 1 : 0] sink14_payload; + wire [PAYLOAD_W - 1 : 0] sink15_payload; + wire [PAYLOAD_W - 1 : 0] sink16_payload; + wire [PAYLOAD_W - 1 : 0] sink17_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + assign valid[2] = sink2_valid; + assign valid[3] = sink3_valid; + assign valid[4] = sink4_valid; + assign valid[5] = sink5_valid; + assign valid[6] = sink6_valid; + assign valid[7] = sink7_valid; + assign valid[8] = sink8_valid; + assign valid[9] = sink9_valid; + assign valid[10] = sink10_valid; + assign valid[11] = sink11_valid; + assign valid[12] = sink12_valid; + assign valid[13] = sink13_valid; + assign valid[14] = sink14_valid; + assign valid[15] = sink15_valid; + assign valid[16] = sink16_valid; + assign valid[17] = sink17_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + lock[2] = sink2_data[59]; + lock[3] = sink3_data[59]; + lock[4] = sink4_data[59]; + lock[5] = sink5_data[59]; + lock[6] = sink6_data[59]; + lock[7] = sink7_data[59]; + lock[8] = sink8_data[59]; + lock[9] = sink9_data[59]; + lock[10] = sink10_data[59]; + lock[11] = sink11_data[59]; + lock[12] = sink12_data[59]; + lock[13] = sink13_data[59]; + lock[14] = sink14_data[59]; + lock[15] = sink15_data[59]; + lock[16] = sink16_data[59]; + lock[17] = sink17_data[59]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + // 2 | 1 | 0 + // 3 | 1 | 0 + // 4 | 1 | 0 + // 5 | 1 | 0 + // 6 | 1 | 0 + // 7 | 1 | 0 + // 8 | 1 | 0 + // 9 | 1 | 0 + // 10 | 1 | 0 + // 11 | 1 | 0 + // 12 | 1 | 0 + // 13 | 1 | 0 + // 14 | 1 | 0 + // 15 | 1 | 0 + // 16 | 1 | 0 + // 17 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} } | + share_2 & { SHARE_COUNTER_W {next_grant[2]} } | + share_3 & { SHARE_COUNTER_W {next_grant[3]} } | + share_4 & { SHARE_COUNTER_W {next_grant[4]} } | + share_5 & { SHARE_COUNTER_W {next_grant[5]} } | + share_6 & { SHARE_COUNTER_W {next_grant[6]} } | + share_7 & { SHARE_COUNTER_W {next_grant[7]} } | + share_8 & { SHARE_COUNTER_W {next_grant[8]} } | + share_9 & { SHARE_COUNTER_W {next_grant[9]} } | + share_10 & { SHARE_COUNTER_W {next_grant[10]} } | + share_11 & { SHARE_COUNTER_W {next_grant[11]} } | + share_12 & { SHARE_COUNTER_W {next_grant[12]} } | + share_13 & { SHARE_COUNTER_W {next_grant[13]} } | + share_14 & { SHARE_COUNTER_W {next_grant[14]} } | + share_15 & { SHARE_COUNTER_W {next_grant[15]} } | + share_16 & { SHARE_COUNTER_W {next_grant[16]} } | + share_17 & { SHARE_COUNTER_W {next_grant[17]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + wire final_packet_2 = 1'b1; + + wire final_packet_3 = 1'b1; + + wire final_packet_4 = 1'b1; + + wire final_packet_5 = 1'b1; + + wire final_packet_6 = 1'b1; + + wire final_packet_7 = 1'b1; + + wire final_packet_8 = 1'b1; + + wire final_packet_9 = 1'b1; + + wire final_packet_10 = 1'b1; + + wire final_packet_11 = 1'b1; + + wire final_packet_12 = 1'b1; + + wire final_packet_13 = 1'b1; + + wire final_packet_14 = 1'b1; + + wire final_packet_15 = 1'b1; + + wire final_packet_16 = 1'b1; + + wire final_packet_17 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_17, + final_packet_16, + final_packet_15, + final_packet_14, + final_packet_13, + final_packet_12, + final_packet_11, + final_packet_10, + final_packet_9, + final_packet_8, + final_packet_7, + final_packet_6, + final_packet_5, + final_packet_4, + final_packet_3, + final_packet_2, + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + assign sink2_ready = src_ready && grant[2]; + assign sink3_ready = src_ready && grant[3]; + assign sink4_ready = src_ready && grant[4]; + assign sink5_ready = src_ready && grant[5]; + assign sink6_ready = src_ready && grant[6]; + assign sink7_ready = src_ready && grant[7]; + assign sink8_ready = src_ready && grant[8]; + assign sink9_ready = src_ready && grant[9]; + assign sink10_ready = src_ready && grant[10]; + assign sink11_ready = src_ready && grant[11]; + assign sink12_ready = src_ready && grant[12]; + assign sink13_ready = src_ready && grant[13]; + assign sink14_ready = src_ready && grant[14]; + assign sink15_ready = src_ready && grant[15]; + assign sink16_ready = src_ready && grant[16]; + assign sink17_ready = src_ready && grant[17]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} } | + sink2_payload & {PAYLOAD_W {grant[2]} } | + sink3_payload & {PAYLOAD_W {grant[3]} } | + sink4_payload & {PAYLOAD_W {grant[4]} } | + sink5_payload & {PAYLOAD_W {grant[5]} } | + sink6_payload & {PAYLOAD_W {grant[6]} } | + sink7_payload & {PAYLOAD_W {grant[7]} } | + sink8_payload & {PAYLOAD_W {grant[8]} } | + sink9_payload & {PAYLOAD_W {grant[9]} } | + sink10_payload & {PAYLOAD_W {grant[10]} } | + sink11_payload & {PAYLOAD_W {grant[11]} } | + sink12_payload & {PAYLOAD_W {grant[12]} } | + sink13_payload & {PAYLOAD_W {grant[13]} } | + sink14_payload & {PAYLOAD_W {grant[14]} } | + sink15_payload & {PAYLOAD_W {grant[15]} } | + sink16_payload & {PAYLOAD_W {grant[16]} } | + sink17_payload & {PAYLOAD_W {grant[17]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + assign sink2_payload = {sink2_channel,sink2_data, + sink2_startofpacket,sink2_endofpacket}; + assign sink3_payload = {sink3_channel,sink3_data, + sink3_startofpacket,sink3_endofpacket}; + assign sink4_payload = {sink4_channel,sink4_data, + sink4_startofpacket,sink4_endofpacket}; + assign sink5_payload = {sink5_channel,sink5_data, + sink5_startofpacket,sink5_endofpacket}; + assign sink6_payload = {sink6_channel,sink6_data, + sink6_startofpacket,sink6_endofpacket}; + assign sink7_payload = {sink7_channel,sink7_data, + sink7_startofpacket,sink7_endofpacket}; + assign sink8_payload = {sink8_channel,sink8_data, + sink8_startofpacket,sink8_endofpacket}; + assign sink9_payload = {sink9_channel,sink9_data, + sink9_startofpacket,sink9_endofpacket}; + assign sink10_payload = {sink10_channel,sink10_data, + sink10_startofpacket,sink10_endofpacket}; + assign sink11_payload = {sink11_channel,sink11_data, + sink11_startofpacket,sink11_endofpacket}; + assign sink12_payload = {sink12_channel,sink12_data, + sink12_startofpacket,sink12_endofpacket}; + assign sink13_payload = {sink13_channel,sink13_data, + sink13_startofpacket,sink13_endofpacket}; + assign sink14_payload = {sink14_channel,sink14_data, + sink14_startofpacket,sink14_endofpacket}; + assign sink15_payload = {sink15_channel,sink15_data, + sink15_startofpacket,sink15_endofpacket}; + assign sink16_payload = {sink16_channel,sink16_data, + sink16_startofpacket,sink16_endofpacket}; + assign sink17_payload = {sink17_channel,sink17_data, + sink17_startofpacket,sink17_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/nios_system/synthesis/submodules/nios_system_switches.v b/nios_system/synthesis/submodules/nios_system_switches.v new file mode 100644 index 0000000..1fd0e98 --- /dev/null +++ b/nios_system/synthesis/submodules/nios_system_switches.v @@ -0,0 +1,58 @@ +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_switches ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 17: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 17: 0] data_in; + wire [ 17: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/nios_system_generation.rpt b/nios_system_generation.rpt new file mode 100644 index 0000000..b559a41 --- /dev/null +++ b/nios_system_generation.rpt @@ -0,0 +1,319 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys +Progress: Loading qsys_tutorial/nios_system.qsys +Progress: Reading input file +Progress: Adding clk_0 [clock_source 13.0] +Progress: Parameterizing module clk_0 +Progress: Adding nios2_processor [altera_nios2_qsys 13.0] +Progress: Parameterizing module nios2_processor +Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] +Progress: Parameterizing module onchip_memory +Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] +Progress: Parameterizing module jtag_uart +Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module LEDs +Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module LEDRs +Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module switches +Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module push_switches +Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex0 +Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex1 +Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex2 +Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex3 +Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex4 +Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex5 +Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex6 +Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex7 +Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] +Progress: Parameterizing module lcd_16207_0 +Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module lcd_on +Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module lcd_blon +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG +Progress: Loading qsys_tutorial/nios_system.qsys +Progress: Reading input file +Progress: Adding clk_0 [clock_source 13.0] +Progress: Parameterizing module clk_0 +Progress: Adding nios2_processor [altera_nios2_qsys 13.0] +Progress: Parameterizing module nios2_processor +Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] +Progress: Parameterizing module onchip_memory +Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] +Progress: Parameterizing module jtag_uart +Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module LEDs +Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module LEDRs +Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module switches +Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module push_switches +Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex0 +Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex1 +Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex2 +Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex3 +Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex4 +Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex5 +Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex6 +Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex7 +Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] +Progress: Parameterizing module lcd_16207_0 +Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module lcd_on +Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module lcd_blon +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 39 modules, 155 connections +Info: merlin_domain_transform: After transform: 78 modules, 423 connections +Info: merlin_router_transform: After transform: 98 modules, 503 connections +Info: reset_adaptation_transform: After transform: 99 modules, 390 connections +Info: merlin_network_to_switch_transform: After transform: 138 modules, 470 connections +Info: merlin_mm_transform: After transform: 138 modules, 470 connections +Info: merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' +Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: nios2_processor: # 2016.12.22 10:06:19 (*) Starting Nios II generation +Info: nios2_processor: # 2016.12.22 10:06:19 (*) Checking for plaintext license. +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: nios2_processor: # 2016.12.22 10:06:20 (*) LM_LICENSE_FILE environment variable is empty +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Plaintext license not found. +Info: nios2_processor: # 2016.12.22 10:06:20 (*) No license required to generate encrypted Nios II/e. +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Elaborating CPU configuration settings +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Creating all objects for CPU +Info: nios2_processor: # 2016.12.22 10:06:21 (*) Generating RTL from CPU objects +Info: nios2_processor: # 2016.12.22 10:06:21 (*) Creating plain-text RTL +Info: nios2_processor: # 2016.12.22 10:06:23 (*) Done Nios II generation +Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' +Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" +Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' +Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] +Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' +Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" +Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' +Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] +Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' +Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" +Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' +Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] +Info: LEDs: Done RTL generation for module 'nios_system_LEDs' +Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" +Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' +Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] +Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' +Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" +Info: switches: Starting RTL generation for module 'nios_system_switches' +Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] +Info: switches: Done RTL generation for module 'nios_system_switches' +Info: switches: "nios_system" instantiated altera_avalon_pio "switches" +Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' +Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] +Info: push_switches: Done RTL generation for module 'nios_system_push_switches' +Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" +Info: hex0: Starting RTL generation for module 'nios_system_hex0' +Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] +Info: hex0: Done RTL generation for module 'nios_system_hex0' +Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" +Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' +Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] +Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' +Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" +Info: lcd_on: Starting RTL generation for module 'nios_system_lcd_on' +Info: lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] +Info: lcd_on: Done RTL generation for module 'nios_system_lcd_on' +Info: lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" +Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" +Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" +Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" +Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" +Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" +Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" +Info: nios_system: Done nios_system" with 28 modules, 155 files, 4086283 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/output_file.map b/output_file.map new file mode 100644 index 0000000..86095a4 --- /dev/null +++ b/output_file.map @@ -0,0 +1,11 @@ +BLOCK START ADDRESS END ADDRESS + +Page_0 0x00000000 0x00367F05 + + + +Notes: + +- Data checksum for this conversion is 0xC97DDCE0 + +- All the addresses in this file are byte addresses \ No newline at end of file diff --git a/output_files/lights.cdf b/output_files/lights.cdf new file mode 100644 index 0000000..6c83ca5 --- /dev/null +++ b/output_files/lights.cdf @@ -0,0 +1,13 @@ +/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EPCQ32) Path("C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/") File("output_file.pof") MfrSpec(OpMask(7) Child_OpMask(1 7)); + +ChainEnd; + +AlteraBegin; + ChainType(asc); +AlteraEnd; diff --git a/output_files/lights.done b/output_files/lights.done new file mode 100644 index 0000000..2394977 --- /dev/null +++ b/output_files/lights.done @@ -0,0 +1 @@ +Sat Jan 28 15:11:28 2017 diff --git a/output_files/output_file.cof b/output_files/output_file.cof new file mode 100644 index 0000000..f82fd65 --- /dev/null +++ b/output_files/output_file.cof @@ -0,0 +1,20 @@ + + + EPCQ32 + output_files/output_file.pof + 1 + 1 + 7 + + Page_0 + 1 + + output_files/lights.sof + + + 5 + 0 + + 1 + + \ No newline at end of file diff --git a/output_files/output_file.map b/output_files/output_file.map new file mode 100644 index 0000000..775b07c --- /dev/null +++ b/output_files/output_file.map @@ -0,0 +1,11 @@ +BLOCK START ADDRESS END ADDRESS + +Page_0 0x00000000 0x00367F05 + + + +Notes: + +- Data checksum for this conversion is 0x0A2C6A95 + +- All the addresses in this file are byte addresses \ No newline at end of file diff --git a/output_files/output_file.pof b/output_files/output_file.pof new file mode 100644 index 0000000..66f0fb4 --- /dev/null +++ b/output_files/output_file.pof Binary files differ diff --git a/software/DE2_115_ASM/.project b/software/DE2_115_ASM/.project new file mode 100644 index 0000000..ed311e5 --- /dev/null +++ b/software/DE2_115_ASM/.project @@ -0,0 +1,96 @@ + + + DE2_115_ASM + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/software/DE2_115_ASM2/.project b/software/DE2_115_ASM2/.project new file mode 100644 index 0000000..499f976 --- /dev/null +++ b/software/DE2_115_ASM2/.project @@ -0,0 +1,96 @@ + + + DE2_115_ASM2 + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM2} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/software/DE2_115_ASM2_bsp/.project b/software/DE2_115_ASM2_bsp/.project new file mode 100644 index 0000000..4001808 --- /dev/null +++ b/software/DE2_115_ASM2_bsp/.project @@ -0,0 +1,85 @@ + + + DE2_115_ASM2_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM2_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/software/DE2_115_ASM3_debug/.project b/software/DE2_115_ASM3_debug/.project new file mode 100644 index 0000000..7d94c46 --- /dev/null +++ b/software/DE2_115_ASM3_debug/.project @@ -0,0 +1,96 @@ + + + DE2_115_ASM3_debug + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM3_debug} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/software/DE2_115_ASM3_debug_bsp/.project b/software/DE2_115_ASM3_debug_bsp/.project new file mode 100644 index 0000000..9d18999 --- /dev/null +++ b/software/DE2_115_ASM3_debug_bsp/.project @@ -0,0 +1,85 @@ + + + DE2_115_ASM3_debug_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM3_debug_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/software/DE2_115_ASM3_release/.cproject b/software/DE2_115_ASM3_release/.cproject new file mode 100644 index 0000000..29e777e --- /dev/null +++ b/software/DE2_115_ASM3_release/.cproject @@ -0,0 +1,508 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + mem_init_install + true + false + false + + + make + + mem_init_generate + true + false + false + + + make + + help + true + false + false + + + + diff --git a/software/DE2_115_ASM3_release/.force_relink b/software/DE2_115_ASM3_release/.force_relink new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/software/DE2_115_ASM3_release/.force_relink diff --git a/software/DE2_115_ASM3_release/.project b/software/DE2_115_ASM3_release/.project new file mode 100644 index 0000000..20f8238 --- /dev/null +++ b/software/DE2_115_ASM3_release/.project @@ -0,0 +1,96 @@ + + + DE2_115_ASM3_release + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM3_release} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/software/DE2_115_ASM3_release/DE2_115_ASM3_release.elf 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c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__gtdf2) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_ge_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__gedf2) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_lt_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (__ltdf2) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_si_to_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__floatsidf) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_df_to_si.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__fixdfsi) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_thenan_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) (__thenan_df) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_usi_to_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__floatunsidf) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_muldi3.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_mul_df.o) (__muldi3) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clz.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_udivdi3.o) (__clz_tab) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clzsi2.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_si_to_df.o) (__clzsi2) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_pack_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) (__pack_d) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_unpack_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) (__unpack_d) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_fpcmp_parts_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_eq_df.o) (__fpcmp_parts_d) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_close.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-closer.o) (close) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_dev.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_close.o) (alt_fd_list) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_errno.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_close.o) (alt_errno) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_fstat.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) (fstat) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_isatty.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) (isatty) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_load.o) + ../DE2_115_ASM3_release_bsp//obj/HAL/src/crt0.o (alt_load) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_lseek.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o) (lseek) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_main.o) + ../DE2_115_ASM3_release_bsp//obj/HAL/src/crt0.o (alt_main) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_malloc_lock.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-freer.o) (__malloc_lock) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_read.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) (read) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_release_fd.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_close.o) (alt_release_fd) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sbrk.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) (sbrk) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_usleep.o) + obj/default/LCD.o (usleep) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_write.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o) (write) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sys_init.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_main.o) (alt_irq_init) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_lcd_16207.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_lcd_16207_init) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_lcd_16207_fd.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_lcd_16207_write_fd) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_alarm_start.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_busy_sleep.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_usleep.o) (alt_busy_sleep) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_load.o) (alt_dcache_flush_all) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sys_init.o) (alt_dev_llist_insert) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_do_ctors.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_main.o) (_do_ctors) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_do_dtors.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_main.o) (_do_dtors) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_load.o) (alt_icache_flush_all) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_ic_isr_register) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic.o) (alt_iic_isr_register) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_io_redirect.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_main.o) (alt_io_redirect) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_entry) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_handler.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_handler) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_vars.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic.o) (alt_irq_active) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_open.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_io_redirect.o) (open) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_tick.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_nios2_qsys_irq.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_nios2_qsys_irq_init) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exception_entry.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) (alt_exception) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_find_dev.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_open.o) (alt_find_dev) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_find_file.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_open.o) (alt_find_file) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_get_fd.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_open.o) (alt_get_fd) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_main.o) (atexit) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_main.o) (exit) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) + ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_find_dev.o) (memcmp) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) (__register_exitproc) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (__call_exitprocs) +../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exit.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (_exit) + +Allocating common symbols +Common symbol size file + +alt_irq 0x100 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_handler.o) +errno 0x4 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o) +stack 0x5 obj/default/hello_world_small.o +global_registers 0xf obj/default/sys_register.o +_atexit0 0x190 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + +Memory Configuration + +Name Origin Length Attributes +reset 0x00000000 0x00000020 +onchip_memory 0x00000020 0x00031fe0 +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD ../DE2_115_ASM3_release_bsp//obj/HAL/src/crt0.o +LOAD obj/default/LCD.o +LOAD obj/default/hello_world_small.o +LOAD obj/default/hex_encoder.o +LOAD obj/default/hex_out.o +LOAD obj/default/input_int.o +LOAD obj/default/inst_decoder.o +LOAD obj/default/lcd_out.o +LOAD obj/default/sys_debug.o +LOAD obj/default/sys_except.o +LOAD obj/default/sys_memory.o +LOAD obj/default/sys_prog.o +LOAD obj/default/sys_register.o +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libstdc++.a +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libm.a +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a +START GROUP +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a +LOAD ../DE2_115_ASM3_release_bsp/\libhal_bsp.a +END GROUP +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a + 0x00000000 __alt_mem_onchip_memory = 0x0 + +.entry 0x00000000 0x20 + *(.entry) + .entry 0x00000000 0x20 ../DE2_115_ASM3_release_bsp//obj/HAL/src/crt0.o + 0x00000000 __reset + +.exceptions 0x00000020 0x194 + 0x00000020 PROVIDE (__ram_exceptions_start, ABSOLUTE (.)) + 0x00000020 . = ALIGN (0x20) + *(.irq) + *(.exceptions.entry.label) + .exceptions.entry.label + 0x00000020 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + 0x00000020 alt_irq_entry + .exceptions.entry.label + 0x00000020 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exception_entry.o) + 0x00000020 alt_exception + *(.exceptions.entry.user) + *(.exceptions.entry) + .exceptions.entry + 0x00000020 0x54 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.irqtest.user) + *(.exceptions.irqtest) + .exceptions.irqtest + 0x00000074 0x10 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.irqhandler.user) + *(.exceptions.irqhandler) + .exceptions.irqhandler + 0x00000084 0x4 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.irqreturn.user) + *(.exceptions.irqreturn) + .exceptions.irqreturn + 0x00000088 0x4 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.label) + .exceptions.notirq.label + 0x0000008c 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.user) + *(.exceptions.notirq) + .exceptions.notirq + 0x0000008c 0x8 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.soft.user) + *(.exceptions.soft) + *(.exceptions.unknown.user) + *(.exceptions.unknown) + .exceptions.unknown + 0x00000094 0x4 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.label) + .exceptions.exit.label + 0x00000098 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + .exceptions.exit.label + 0x00000098 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.user) + *(.exceptions.exit) + .exceptions.exit + 0x00000098 0x54 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions) + .exceptions 0x000000ec 0xc8 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_handler.o) + 0x000000ec alt_irq_handler + 0x000001b4 PROVIDE (__ram_exceptions_end, ABSOLUTE (.)) + 0x00000020 PROVIDE (__flash_exceptions_start, LOADADDR (.exceptions)) + +.text 0x000001b4 0xfdf4 + 0x000001b4 PROVIDE (stext, ABSOLUTE (.)) + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + *(.init) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + .text 0x000001b4 0x3c ../DE2_115_ASM3_release_bsp//obj/HAL/src/crt0.o + 0x000001b4 _start + .text 0x000001f0 0x1ec obj/default/LCD.o + 0x000001f0 LCD_Init + 0x0000028c LCD_Show_Text + 0x00000314 LCD_Line2 + 0x00000350 LCD_Test + .text 0x000003dc 0x7cc obj/default/hello_world_small.o + 0x0000049c store_value + 0x00000580 store_inst + 0x000006e4 print_change_memory + 0x00000920 main + .text 0x00000ba8 0x630 obj/default/hex_encoder.o + 0x00000ba8 encodeNumHex + 0x00000d84 encodeLatHex + .text 0x000011d8 0x318 obj/default/hex_out.o + 0x000011d8 print_block + 0x00001368 clear_block + 0x000013f8 print_number + .text 0x000014f0 0x2c0 obj/default/input_int.o + 0x000014f0 in_int + 0x00001600 push_decode + 0x000016ac push_int + .text 0x000017b0 0x75c obj/default/inst_decoder.o + 0x000017b0 inst_fetch + 0x000017fc inst_decode + 0x00001a74 inst_jump + 0x00001ad0 inst_output + 0x00001b40 inst_load + 0x00001b78 inst_store + 0x00001bb0 inst_delay + 0x00001c0c inst_add + 0x00001c68 inst_sub + 0x00001cc4 inst_comp + 0x00001d94 inst_jeq + 0x00001e00 inst_jne + 0x00001e6c inst_jieq + 0x00001ebc inst_jine + .text 0x00001f0c 0xc8 obj/default/lcd_out.o + 0x00001f0c lcd_init + 0x00001f54 lcd_caret_reset + 0x00001f7c lcd_caret_reset2 + 0x00001fa4 lcd_print + .text 0x00001fd4 0x588 obj/default/sys_debug.o + 0x00001fd4 display_inst + 0x00002080 display_mem + 0x000020ec convertRegName + 0x0000225c convertInstName + 0x00002520 delay10ms + .text 0x0000255c 0x40 obj/default/sys_except.o + 0x0000255c panic + .text 0x0000259c 0x240 obj/default/sys_memory.o + 0x0000259c memory_init + 0x00002618 inst_memory_store + 0x00002668 inst_memory_load + 0x000026b0 memory_store + 0x0000274c memory_load + .text 0x000027dc 0x2c4 obj/default/sys_prog.o + 0x000027dc inc_pc + 0x00002860 add_pc + 0x000028b0 set_pc + 0x000028e8 get_pc + 0x00002950 run_proc + .text 0x00002aa0 0x50 obj/default/sys_register.o + 0x00002aa0 registers_init + .text 0x00002af0 0x14c c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(lib2-divmod.o) + 0x00002b6c __divsi3 + 0x00002bcc __modsi3 + 0x00002c2c __udivsi3 + 0x00002c34 __umodsi3 + .text 0x00002c3c 0x38 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(lib2-mul.o) + 0x00002c3c __mulsi3 + .text 0x00002c74 0x0 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-ctype_.o) + .text 0x00002c74 0xd4 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sprintf.o) + 0x00002c74 sprintf + 0x00002ce8 _sprintf_r + .text 0x00002d48 0x74 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-strlen.o) + 0x00002d48 strlen + .text 0x00002dbc 0x1f40 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) + 0x00002e14 ___vfprintf_internal_r + 0x00004cd8 __vfprintf_internal + .text 0x00004cfc 0x13c c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o) + 0x00004cfc __swsetup_r + .text 0x00004e38 0x17f8 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) + 0x0000507c _dtoa_r + .text 0x00006630 0x230 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o) + 0x00006630 _fflush_r + 0x0000682c fflush + .text 0x00006860 0x2f4 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) + 0x000068b8 __sfp_lock_acquire + 0x000068bc __sfp_lock_release + 0x000068c0 __sinit_lock_acquire + 0x000068c4 __sinit_lock_release + 0x000068c8 __sinit + 0x0000697c __fp_unlock_all + 0x00006994 __fp_lock_all + 0x000069ac _cleanup_r + 0x000069b8 _cleanup + 0x000069c8 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c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_thenan_df.o) + .text 0x0000bcb8 0x194 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_usi_to_df.o) + 0x0000bcb8 __floatunsidf + .text 0x0000be4c 0x124 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_muldi3.o) + 0x0000be4c __muldi3 + .text 0x0000bf70 0x0 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clz.o) + .text 0x0000bf70 0x80 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clzsi2.o) + 0x0000bf70 __clzsi2 + .text 0x0000bff0 0x314 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_pack_df.o) + 0x0000bff0 __pack_d + .text 0x0000c304 0x138 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_unpack_df.o) + 0x0000c304 __unpack_d + .text 0x0000c43c 0xc8 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_fpcmp_parts_df.o) + 0x0000c43c __fpcmp_parts_d + .text 0x0000c504 0x160 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_close.o) + 0x0000c504 close + .text 0x0000c664 0x2c ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_dev.o) + .text 0x0000c690 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_errno.o) + .text 0x0000c690 0x138 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_fstat.o) + 0x0000c690 fstat + .text 0x0000c7c8 0x124 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_isatty.o) + 0x0000c7c8 isatty + .text 0x0000c8ec 0xec ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_load.o) + 0x0000c8ec alt_load + .text 0x0000c9d8 0x154 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_lseek.o) + 0x0000c9d8 lseek + .text 0x0000cb2c 0x6c ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_main.o) + 0x0000cb2c alt_main + .text 0x0000cb98 0x40 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_malloc_lock.o) + 0x0000cb98 __malloc_lock + 0x0000cbb8 __malloc_unlock + .text 0x0000cbd8 0x184 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_read.o) + 0x0000cbd8 read + .text 0x0000cd5c 0x78 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_release_fd.o) + 0x0000cd5c alt_release_fd + .text 0x0000cdd4 0xbc ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sbrk.o) + 0x0000cdd4 sbrk + .text 0x0000ce90 0x30 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_usleep.o) + 0x0000ce90 usleep + .text 0x0000cec0 0x184 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_write.o) + 0x0000cec0 write + .text 0x0000d044 0xc8 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_sys_init.o) + 0x0000d044 alt_irq_init + 0x0000d078 alt_sys_init + .text 0x0000d10c 0x148 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) + 0x0000d10c altera_avalon_jtag_uart_read_fd + 0x0000d164 altera_avalon_jtag_uart_write_fd + 0x0000d1bc altera_avalon_jtag_uart_close_fd + 0x0000d204 altera_avalon_jtag_uart_ioctl_fd + .text 0x0000d254 0x40c ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) + 0x0000d254 altera_avalon_jtag_uart_init + 0x0000d5ec altera_avalon_jtag_uart_close + .text 0x0000d660 0xf4 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) + 0x0000d660 altera_avalon_jtag_uart_ioctl + .text 0x0000d754 0x224 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + 0x0000d754 altera_avalon_jtag_uart_read + .text 0x0000d978 0x240 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + 0x0000d978 altera_avalon_jtag_uart_write + .text 0x0000dbb8 0xf80 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_lcd_16207.o) + 0x0000e3f4 altera_avalon_lcd_16207_write + 0x0000e9fc altera_avalon_lcd_16207_init + .text 0x0000eb38 0x58 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_lcd_16207_fd.o) + 0x0000eb38 altera_avalon_lcd_16207_write_fd + .text 0x0000eb90 0x154 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_alarm_start.o) + 0x0000eb90 alt_alarm_start + .text 0x0000ece4 0x15c ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_busy_sleep.o) + 0x0000ece4 alt_busy_sleep + .text 0x0000ee40 0x1c ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) + 0x0000ee40 alt_dcache_flush_all + .text 0x0000ee5c 0x114 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + 0x0000ee5c alt_dev_llist_insert + .text 0x0000ef70 0x64 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_do_ctors.o) + 0x0000ef70 _do_ctors + .text 0x0000efd4 0x64 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_do_dtors.o) + 0x0000efd4 _do_dtors + .text 0x0000f038 0x1c ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + 0x0000f038 alt_icache_flush_all + .text 0x0000f054 0x1d4 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic.o) + 0x0000f054 alt_ic_isr_register + 0x0000f0a4 alt_ic_irq_enable + 0x0000f140 alt_ic_irq_disable + 0x0000f1e0 alt_ic_irq_enabled + .text 0x0000f228 0xf8 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + 0x0000f228 alt_iic_isr_register + .text 0x0000f320 0x150 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_io_redirect.o) + 0x0000f3f8 alt_io_redirect + .text 0x0000f470 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + .text 0x0000f470 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_handler.o) + .text 0x0000f470 0x0 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_vars.o) + .text 0x0000f470 0x2e4 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_open.o) + 0x0000f568 open + .text 0x0000f754 0x1a4 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_tick.o) + 0x0000f754 alt_alarm_stop + 0x0000f7ec alt_tick + .text 0x0000f8f8 0x20 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_nios2_qsys_irq.o) + 0x0000f8f8 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../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_avalon_lcd_16207_fd.o) + .debug_loc 0x0000bef8 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_alarm_start.o) + .debug_loc 0x0000bf23 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_busy_sleep.o) + .debug_loc 0x0000bf4e 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) + .debug_loc 0x0000bf79 0x56 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + .debug_loc 0x0000bfcf 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_do_ctors.o) + .debug_loc 0x0000bffa 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_do_dtors.o) + .debug_loc 0x0000c025 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + .debug_loc 0x0000c050 0xac ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic.o) + .debug_loc 0x0000c0fc 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + .debug_loc 0x0000c127 0x56 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_io_redirect.o) + .debug_loc 0x0000c17d 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_handler.o) + .debug_loc 0x0000c1a8 0x81 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_open.o) + .debug_loc 0x0000c229 0x56 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_tick.o) + .debug_loc 0x0000c27f 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(altera_nios2_qsys_irq.o) + .debug_loc 0x0000c2aa 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_find_dev.o) + .debug_loc 0x0000c2d5 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_find_file.o) + .debug_loc 0x0000c300 0x2b ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_get_fd.o) + .debug_loc 0x0000c32b 0x1e c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + .debug_loc 0x0000c349 0x3d c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) + .debug_loc 0x0000c386 0x114 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) + .debug_loc 0x0000c49a 0x120 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + .debug_loc 0x0000c5ba 0x1cb c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + .debug_loc 0x0000c785 0x56 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exit.o) + +.debug_macinfo + *(.debug_macinfo) + +.debug_weaknames + *(.debug_weaknames) + +.debug_funcnames + *(.debug_funcnames) + +.debug_typenames + *(.debug_typenames) + +.debug_varnames + *(.debug_varnames) + +.debug_alt_sim_info + 0x00000000 0x40 + *(.debug_alt_sim_info) + .debug_alt_sim_info + 0x00000000 0x10 ../DE2_115_ASM3_release_bsp//obj/HAL/src/crt0.o + .debug_alt_sim_info + 0x00000010 0x30 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_busy_sleep.o) + 0x00032000 __alt_data_end = 0x32000 + 0x00032000 PROVIDE (__alt_stack_pointer, __alt_data_end) + 0x000145f4 PROVIDE (__alt_stack_limit, __alt_stack_base) + 0x000145f4 PROVIDE (__alt_heap_start, end) + 0x00032000 PROVIDE (__alt_heap_limit, 0x32000) +OUTPUT(DE2_115_ASM3_release.elf elf32-littlenios2) + +.debug_ranges 0x00000000 0x9e0 + .debug_ranges 0x00000000 0x20 ../DE2_115_ASM3_release_bsp//obj/HAL/src/crt0.o + .debug_ranges 0x00000020 0x168 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) + .debug_ranges 0x00000188 0x20 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o) + .debug_ranges 0x000001a8 0x28 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) + .debug_ranges 0x000001d0 0xa0 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fwalk.o) + .debug_ranges 0x00000270 0x70 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o) + .debug_ranges 0x000002e0 0x110 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-reallocr.o) + .debug_ranges 0x000003f0 0x38 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-callocr.o) + .debug_ranges 0x00000428 0x190 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_udivdi3.o) + .debug_ranges 0x000005b8 0x1c0 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_umoddi3.o) + .debug_ranges 0x00000778 0x30 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) + .debug_ranges 0x000007a8 0x88 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_mul_df.o) + .debug_ranges 0x00000830 0x50 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_div_df.o) + .debug_ranges 0x00000880 0x18 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_usi_to_df.o) + .debug_ranges 0x00000898 0x88 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_muldi3.o) + .debug_ranges 0x00000920 0x28 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clzsi2.o) + .debug_ranges 0x00000948 0x28 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_pack_df.o) + .debug_ranges 0x00000970 0x28 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_irq_entry.o) + .debug_ranges 0x00000998 0x30 ../DE2_115_ASM3_release_bsp/\libhal_bsp.a(alt_exception_entry.o) + .debug_ranges 0x000009c8 0x18 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) diff --git a/software/DE2_115_ASM3_release/LCD.c b/software/DE2_115_ASM3_release/LCD.c new file mode 100644 index 0000000..10ff2ea --- /dev/null +++ b/software/DE2_115_ASM3_release/LCD.c @@ -0,0 +1,50 @@ +#include +#include +#include +#include "system.h" +#include "LCD.h" +//------------------------------------------------------------------------- +void LCD_Init() +{ + lcd_write_cmd(LCD_16207_0_BASE,0x38); + usleep(2000); + lcd_write_cmd(LCD_16207_0_BASE,0x0C); + usleep(2000); + lcd_write_cmd(LCD_16207_0_BASE,0x01); + usleep(2000); + lcd_write_cmd(LCD_16207_0_BASE,0x06); + usleep(2000); + lcd_write_cmd(LCD_16207_0_BASE,0x80); + usleep(2000); +} +//------------------------------------------------------------------------- +void LCD_Show_Text(const char* Text) +{ + int i; + for(i=0;i /c/dir). This will ensture +# paths are readable by GNU Make. +# +# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no +# adjustment is necessary +# +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # COMSPEC + +ifdef COMSPEC # if Windows OS + +ifeq ($(MAKE_VERSION),3.81) +# +# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows +# +# Example Usage: +# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb +# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb +# + +# +# adjust-path +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not contain the string ":/", then return input arg +# - using sed, convert mixed path [c:/...] into mingw path [/c/...] +define adjust-path +$(strip \ +$(if $1,\ +$(if $(findstring :/,$(subst \,/,$1)),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^$[a-zA-Z]$:/,/\1/,'),\ +$(subst \,/,$1)))) +endef + +# +# adjust-path-mixed +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not begin with a forward slash '/' char, then +# return input arg +# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] +# into a mixed path [c:/...] +define adjust-path-mixed +$(strip \ +$(if $1,\ +$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ +$(subst \,/,$1),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/$[a-zA-Z]$/,\1:/,' -e 's,^/$[a-zA-Z]$/,\1:/,')))) +endef + +else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) +# +# adjust-path for Cygwin Gnu Make +# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb +# +adjust-path = $(if $1,$(shell cygpath -u "$1"),) +adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),) +endif + +else # !COMSPEC + +adjust-path = $1 +adjust-path-mixed = $1 + +endif # COMSPEC + + +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv +# GENERATED SETTINGS START v +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv + +#START GENERATED +ACTIVE_BUILD_CONFIG := default +BUILD_CONFIGS := default + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: APP_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +# Define path to the application ELF. +# It may be used by the makefile fragments so is defined before including them. +# +ELF := DE2_115_ASM3_release.elf + +# Paths to C, C++, and assembly source files. +C_SRCS += LCD.c +C_SRCS += hello_world_small.c +C_SRCS += hex_encoder.c +C_SRCS += hex_out.c +C_SRCS += input_int.c +C_SRCS += inst_decoder.c +C_SRCS += lcd_out.c +C_SRCS += sys_debug.c +C_SRCS += sys_except.c +C_SRCS += sys_memory.c +C_SRCS += sys_prog.c +C_SRCS += sys_register.c +CXX_SRCS := +ASM_SRCS := + + +# Path to root of object file tree. +OBJ_ROOT_DIR := obj + +# Options to control objdump. +CREATE_OBJDUMP := 1 +OBJDUMP_INCLUDE_SOURCE := 1 +OBJDUMP_FULL_CONTENTS := 0 + +# Options to enable/disable optional files. +CREATE_ELF_DERIVED_FILES := 0 +CREATE_LINKER_MAP := 1 + +# Common arguments for ALT_CFLAGSs +APP_CFLAGS_DEFINED_SYMBOLS := +APP_CFLAGS_UNDEFINED_SYMBOLS := +APP_CFLAGS_OPTIMIZATION := -O0 +APP_CFLAGS_DEBUG_LEVEL := -g +APP_CFLAGS_WARNINGS := -Wall +APP_CFLAGS_USER_FLAGS := + +APP_ASFLAGS_USER := +APP_LDFLAGS_USER := + +# Linker options that have default values assigned later if not +# assigned here. +LINKER_SCRIPT := +CRT0 := +SYS_LIB := + +# Define path to the root of the BSP. +BSP_ROOT_DIR := ../DE2_115_ASM3_release_bsp/ + +# List of application specific include directories, library directories and library names +APP_INCLUDE_DIRS := +APP_LIBRARY_DIRS := +APP_LIBRARY_NAMES := + +# Pre- and post- processor settings. +BUILD_PRE_PROCESS := +BUILD_POST_PROCESS := + +QUARTUS_PROJECT_DIR := ../../ + + +#END GENERATED + +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +# GENERATED SETTINGS END ^ +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +#------------------------------------------------------------------------------ + +# Define the variable used to echo output if not already defined. +ifeq ($(ECHO),) +ECHO := echo +endif + +# Put "all" rule before included makefile fragments because they may +# define rules and we don't want one of those to become the default rule. +.PHONY : all + +all: + @$(ECHO) [$(APP_NAME) build complete] + +all : build_pre_process libs app build_post_process + + +#------------------------------------------------------------------------------ +# VARIABLES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ + +# Define object file directory per build configuration +CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG) + +ifeq ($(BSP_ROOT_DIR),) +$(error Edit Makefile and provide a value for BSP_ROOT_DIR) +endif + +ifeq ($(wildcard $(BSP_ROOT_DIR)),) +$(error BSP directory does not exist: $(BSP_ROOT_DIR)) +endif + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) + +# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before +# including each makefile fragment so that it knows the path to itself. +BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk +ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) +include $(BSP_INCLUDE_FILE) +# C2H will need this to touch the BSP public.mk and avoid the sopc file +# out-of-date error during a BSP make +ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk + + +ifneq ($(WARNING.SMALL_STACK_SIZE),) +# This WARNING is here to protect you from unknowingly using a very small stack +# If the warning is set, increase your stack size or enable the BSP small stack +# setting to eliminate the warning +$(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) +endif + + +# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF +# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. +ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) +ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) +endif + +# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to +# download_elf target +ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) +GMON_OUT_FILENAME := gmon.out +WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME) +endif + +# Name of ELF application. +APP_NAME := $(basename $(ELF)) + +# Set to defaults if variables not already defined in settings. +ifeq ($(LINKER_SCRIPT),) +LINKER_SCRIPT := $(BSP_LINKER_SCRIPT) +endif +ifeq ($(CRT0),) +CRT0 := $(BSP_CRT0) +endif +ifeq ($(SYS_LIB),) +SYS_LIB := $(BSP_SYS_LIB) +endif + +OBJDUMP_NAME := $(APP_NAME).objdump +OBJDUMP_FLAGS := --disassemble --syms --all-header +ifeq ($(OBJDUMP_INCLUDE_SOURCE),1) +OBJDUMP_FLAGS += --source +endif +ifeq ($(OBJDUMP_FULL_CONTENTS),1) +OBJDUMP_FLAGS += --full-contents +endif + +# Create list of linker dependencies (*.a files). +APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS) + +# Take lists and add required prefixes. +APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +ASM_INC_PREFIX := -Wa,-I +APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS)) +APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS)) + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# +# Avoid Nios II GCC 3.X options. +# + +# Detect if small newlib C library is requested. +# If yes, remove the -msmallc option because it is +# now handled by other means. +ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),) + ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS)) + ALT_C_LIBRARY := smallc +else + ALT_C_LIBRARY := c +endif + +# Put each BSP dependent library in a group to avoid circular dependencies. +APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group) + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# +# Use Nios II GCC 3.X options. +# +APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES)) + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker. +APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \ + $(APP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(APP_CFLAGS_OPTIMIZATION) \ + $(APP_CFLAGS_DEBUG_LEVEL) \ + $(APP_CFLAGS_WARNINGS) \ + $(APP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Arguments only for the C++ compiler. +APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS) + +# Arguments only for the C preprocessor. +# Prefix each include directory with -I. +APP_CPPFLAGS := $(APP_INC_DIRS) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Arguments only for the assembler. +APP_ASFLAGS := $(APP_ASM_INC_DIRS) \ + $(ALT_ASFLAGS) \ + $(APP_ASFLAGS_USER) \ + $(ASFLAGS) + +# Arguments only for the linker. +APP_LDFLAGS := $(APP_LDFLAGS_USER) + +ifneq ($(LINKER_SCRIPT),) +APP_LDFLAGS += -T'$(LINKER_SCRIPT)' +endif + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# Avoid Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += $(CRT0) +endif + +# The equivalent of the -msys-lib option is provided +# by the GROUP() command in the linker script. +# Note this means the SYS_LIB variable is now ignored. + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# Use Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += -msys-crt0='$(CRT0)' +endif +ifneq ($(SYS_LIB),) +APP_LDFLAGS += -msys-lib=$(SYS_LIB) +endif + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +APP_LDFLAGS += \ + $(APP_LIB_DIRS) \ + $(ALT_LDFLAGS) \ + $(LDFLAGS) + +LINKER_MAP_NAME := $(APP_NAME).map +ifeq ($(CREATE_LINKER_MAP), 1) +APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) +endif + +# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the +# mem_init_install target of the mem_init.mk (located in the associated BSP) +# to know how to copy memory initialization files (e.g. .dat, .hex) into +# directories required for Quartus compilation or RTL simulation. + +# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory +# initialization files into your Quartus project directory. This is required +# to provide the initial memory contents of FPGA memories that can be +# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used +# for VHDL simulation of on-chip memories. + +# Defining SOPC_NAME causes the mem_init_install target to copy memory +# initialization files into your RTL simulation directory. This is required +# to provide the initial memory contents of all memories that can be +# initialized by RTL simulation. This variable should be set to the same name +# as your SOPC Builder system name. For example, if you have a system called +# "foo.sopc", this variable should be set to "foo". + +# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. +ifeq ($(SOPC_NAME),) +ifneq ($(QUARTUS_PROJECT_DIR),) +SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) +endif +endif + +# Defining JDI_FILE is required to specify the JTAG Debug Information File +# path. This file is generated by Quartus, and is needed along with the +# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU +# systems. For multi-CPU systems, the processor instance ID is used to select +# from multiple CPU's during ELF download. + +# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during +# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then +# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be +# multiple .sopcinfo files in a Quartus project. +ifeq ($(JDI_FILE),) +ifneq ($(QUARTUS_PROJECT_DIR),) +JDI_FILE := $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi) +endif +endif + +# Path to root runtime directory used for hdl simulation +RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime + + + +#------------------------------------------------------------------------------ +# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ +# mem_init.mk is a generated makefile fragment. This file defines all targets +# used to generate HDL initialization simulation files and pre-initialized +# onchip memory files. +MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk +include $(MEM_INIT_FILE) + +# Create list of object files to be built using the list of source files. +# The source file hierarchy is preserved in the object tree. +# The supported file extensions are: +# +# .c - for C files +# .cxx .cc .cpp - for C++ files +# .S .s - for assembler files +# +# Handle source files specified by --src-dir & --src-rdir differently, to +# save some processing time in calling the adjust-path macro. + +OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS))) +OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS))) +OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS))) +OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS))) +OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS))) +OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS))) + +OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \ + $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS)) + +SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS))) +SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS))) +SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS))) + +SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ + $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \ + $(SDIR_OBJ_LIST_SS)) + +# Relative-pathed objects that being with "../" are handled differently. +# +# Regular objects are created as +# $(CONFIG_OBJ_DIR)//.o +# where the path structure is maintained under the obj directory. This +# applies for both absolute and relative paths; in the absolute path +# case this means the entire source path will be recreated under the obj +# directory. This is done to allow two source files with the same name +# to be included as part of the project. +# +# Note: On Cygwin, the path recreated under the obj directory will be +# the cygpath -u output path. +# +# Relative-path objects that begin with "../" cause problems under this +# scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object +# files anywhere in the system, creating clutter and polluting the source tree. +# As such, their paths are flattened - the object file created will be +# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with +# "../" in the beginning cannot have the same name in the project. VPATH +# will be set for these sources to allow make to relocate the source file +# via %.o rules. +# +# The following lines separate the object list into the flatten and regular +# lists, and then handles them as appropriate. + +FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST)) +FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST))) + +REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST)) +REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST)) + +FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST)) +FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST))) + +REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST)) + +VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST))) + +APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_C) \ + $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s))) + +APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CPP) \ + $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s))) + +APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CXX) \ + $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s))) + +APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CC) \ + $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s))) + +APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_S) \ + $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s))) + +APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_SS) \ + $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s))) + +APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \ + $(APP_OBJS_S) $(APP_OBJS_SS) \ + $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS) + +# Add any extra user-provided object files. +APP_OBJS += $(OBJS) + +# Create list of dependancy files for each object file. +APP_DEPS := $(APP_OBJS:.o=.d) + +# Patch the Elf file with system specific information + +# Patch the Elf with the name of the sopc system +ifneq ($(SOPC_NAME),) +ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME) +endif + +# Patch the Elf with the absolute path to the Quartus Project Directory +ifneq ($(QUARTUS_PROJECT_DIR),) +ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd)) +ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)" +endif + +# Patch the Elf and download args with the JDI_FILE if specified +ifneq ($(wildcard $(JDI_FILE)),) +ELF_PATCH_FLAG += --jdi $(JDI_FILE) +DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE) +endif + +# Patch the Elf with the SOPCINFO_FILE if specified +ifneq ($(wildcard $(SOPCINFO_FILE)),) +ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) +endif + +# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. +# This is not needed if you only have one cable. +ifneq ($(DOWNLOAD_CABLE),) +DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' +endif + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +# +# Set tool default variables if not already defined. +# If these are defined, they would typically be defined in an +# included makefile fragment. +# +ifeq ($(DEFAULT_CROSS_COMPILE),) +DEFAULT_CROSS_COMPILE := nios2-elf- +endif + +ifeq ($(DEFAULT_STACK_REPORT),) +DEFAULT_STACKREPORT := nios2-stackreport +endif + +ifeq ($(DEFAULT_DOWNLOAD),) +DEFAULT_DOWNLOAD := nios2-download +endif + +ifeq ($(DEFAULT_FLASHPROG),) +DEFAULT_FLASHPROG := nios2-flash-programmer +endif + +ifeq ($(DEFAULT_ELFPATCH),) +DEFAULT_ELFPATCH := nios2-elf-insert +endif + +ifeq ($(DEFAULT_RM),) +DEFAULT_RM := rm -f +endif + +ifeq ($(DEFAULT_CP),) +DEFAULT_CP := cp -f +endif + +ifeq ($(DEFAULT_MKDIR),) +DEFAULT_MKDIR := mkdir -p +endif + +# +# Set tool variables to defaults if not already defined. +# If these are defined, they would typically be defined by a +# setting in the generated portion of this makefile. +# +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE) +endif + +ifeq ($(origin CC),default) +CC := $(CROSS_COMPILE)gcc -xc +endif + +ifeq ($(origin CXX),default) +CXX := $(CROSS_COMPILE)gcc -xc++ +endif + +ifeq ($(origin AS),default) +AS := $(CROSS_COMPILE)gcc +endif + +ifeq ($(origin AR),default) +AR := $(CROSS_COMPILE)ar +endif + +ifeq ($(origin LD),default) +LD := $(CROSS_COMPILE)g++ +endif + +ifeq ($(origin NM),default) +NM := $(CROSS_COMPILE)nm +endif + +ifeq ($(origin RM),default) +RM := $(DEFAULT_RM) +endif + +ifeq ($(origin CP),default) +CP := $(DEFAULT_CP) +endif + +ifeq ($(OBJDUMP),) +OBJDUMP := $(CROSS_COMPILE)objdump +endif + +ifeq ($(OBJCOPY),) +OBJCOPY := $(CROSS_COMPILE)objcopy +endif + +ifeq ($(STACKREPORT),) +ifeq ($(CROSS_COMPILE),nios2-elf-) +STACKREPORT := $(DEFAULT_STACKREPORT) +else +DISABLE_STACKREPORT := 1 +endif +endif + +ifeq ($(DOWNLOAD),) +DOWNLOAD := $(DEFAULT_DOWNLOAD) +endif + +ifeq ($(FLASHPROG),) +FLASHPROG := $(DEFAULT_FLASHPROG) +endif + +ifeq ($(ELFPATCH),) +ELFPATCH := $(DEFAULT_ELFPATCH) +endif + +ifeq ($(MKDIR),) +MKDIR := $(DEFAULT_MKDIR) +endif + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ + +define compile.c +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< +$(CC_POST_PROCESS) +endef + +define compile.cpp +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< +$(CXX_POST_PROCESS) +endef + +# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS +ifeq ($(AS),$(patsubst %as,%,$(AS))) +COMMA := , +APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS)))) +endif + +define compile.s +@$(ECHO) Info: Assembling $< to $@ +@$(MKDIR) $(@D) +$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< +$(AS_POST_PROCESS) +endef + +ifeq ($(MAKE_VERSION),3.81) +.SECONDEXPANSION: + +$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) + $(compile.c) + +$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp) + $(compile.cpp) + +$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc) + $(compile.cpp) + +$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx) + $(compile.cpp) + +$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S) + $(compile.s) + +$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s) + $(compile.s) + +endif # MAKE_VERSION != 3.81 + +$(CONFIG_OBJ_DIR)/%.o: %.c + $(compile.c) + +$(CONFIG_OBJ_DIR)/%.o: %.cpp + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cc + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cxx + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.S + $(compile.s) + +$(CONFIG_OBJ_DIR)/%.o: %.s + $(compile.s) + + +#------------------------------------------------------------------------------ +# PATTERN RULES TO INTERMEDIATE FILES +#------------------------------------------------------------------------------ + +$(CONFIG_OBJ_DIR)/%.s: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + + +#------------------------------------------------------------------------------ +# TARGET RULES +#------------------------------------------------------------------------------ + +.PHONY : help +help : + @$(ECHO) "Summary of Makefile targets" + @$(ECHO) " Build targets:" + @$(ECHO) " all (default) - Application and all libraries (including BSP)" + @$(ECHO) " bsp - Just the BSP" + @$(ECHO) " libs - All libraries (including BSP)" + @$(ECHO) " flash - All flash files" + @$(ECHO) " mem_init_generate - All memory initialization files" +ifeq ($(QSYS),1) + @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" + @$(ECHO) " --> Use the mem_init_generate target and then" + @$(ECHO) " add the generated meminit.qip file to your" + @$(ECHO) " Quartus II Project." +else # if QSYS != 1 + @$(ECHO) " mem_init_install - Copy memory initialization files to Quartus II project" +endif # QSYS == 1 + @$(ECHO) + @$(ECHO) " Clean targets:" + @$(ECHO) " clean_all - Application and all libraries (including BSP)" + @$(ECHO) " clean - Just the application" + @$(ECHO) " clean_bsp - Just the BSP" + @$(ECHO) " clean_libs - All libraries (including BSP)" + @$(ECHO) + @$(ECHO) " Run targets:" + @$(ECHO) " download-elf - Download and run your elf executable" + @$(ECHO) " program-flash - Program flash contents to the board" + +# Handy rule to skip making libraries and just make application. +.PHONY : app +app : $(ELF) + +ifeq ($(CREATE_OBJDUMP), 1) +app : $(OBJDUMP_NAME) +endif + +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +app : elf_derived_files +endif + +.PHONY: elf_derived_files +elf_derived_files: default_mem_init + +# Handy rule for making just the BSP. +.PHONY : bsp +bsp : + @$(ECHO) Info: Building $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) + + +# Make sure all makeable libraries (including the BSP) are up-to-date. +LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : libs +libs : $(LIB_TARGETS) + +ifneq ($(strip $(LIB_TARGETS)),) +$(LIB_TARGETS): %-recurs-make-lib: + @$(ECHO) Info: Building $* + $(MAKE) --no-print-directory -C $* +endif + +ifneq ($(strip $(APP_LDDEPS)),) +$(APP_LDDEPS): libs + @true +endif + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS))) + +$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS))) + + +# Clean just the application. +.PHONY : clean +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +clean : clean_elf_derived_files +endif + +clean : + @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) + @$(ECHO) [$(APP_NAME) clean complete] + +# Clean just the BSP. +.PHONY : clean_bsp +clean_bsp : + @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean + +# Clean all makeable libraries including the BSP. +LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : clean_libs +clean_libs : $(LIB_CLEAN_TARGETS) + +ifneq ($(strip $(LIB_CLEAN_TARGETS)),) +$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib: + @$(ECHO) Info: Cleaning $* + $(MAKE) --no-print-directory -C $* clean +endif + +.PHONY: clean_elf_derived_files +clean_elf_derived_files: mem_init_clean + +# Clean application and all makeable libraries including the BSP. +.PHONY : clean_all +clean_all : clean mem_init_clean clean_libs + +# Include the dependency files unless the make goal is performing a clean +# of the application. +ifneq ($(firstword $(MAKECMDGOALS)),clean) +ifneq ($(firstword $(MAKECMDGOALS)),clean_all) +-include $(APP_DEPS) +endif +endif + +.PHONY : download-elf +download-elf : $(ELF) + @if [ "$(DOWNLOAD)" = "none" ]; \ + then \ + $(ECHO) Downloading $(ELF) not supported; \ + else \ + $(ECHO) Info: Downloading $(ELF); \ + $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ + fi + +# Delete the target of a rule if it has changed and its commands exit +# with a nonzero exit status. +.DELETE_ON_ERROR: + +# Rules for flash programming commands +PROGRAM_FLASH_SUFFIX := -program +PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES)) + +.PHONY : program-flash +program-flash : $(PROGRAM_FLASH_TARGET) + +.PHONY : $(PROGRAM_FLASH_TARGET) +$(PROGRAM_FLASH_TARGET) : flash + @if [ "$(FLASHPROG)" = "none" ]; \ + then \ + $(ECHO) Programming flash not supported; \ + else \ + $(ECHO) Info: Programming $(basename $@).flash; \ + if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \ + then \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + else \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + fi \ + fi + + +# Rules for simulating with an HDL Simulator [QSYS only] +ifeq ($(QSYS),1) +IP_MAKE_SIMSCRIPT := ip-make-simscript + +ifeq ($(VSIM),) +VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim" +ifeq ($(ENABLE_VSIM_GUI),1) +VSIM := $(VSIM_EXE) -gui +else +VSIM := $(VSIM_EXE) -c +endif # ENABLE_VSIM_GUI == 1 +endif # VSIM not set + +ifeq ($(SPD),) +ifneq ($(ABS_QUARTUS_PROJECT_DIR),) +ifneq ($(SOPC_NAME),) +SPD := $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd +endif # SOPC_NAME set +endif # ABS_QUARTUS_PROJECT_DIR set +endif # SPD == empty string + +ifeq ($(MSIM_SCRIPT),) +SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim +MSIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/msim_setup.tcl +endif # MSIM_SCRIPT == empty string + +ifeq ($(MAKE_VERSION),3.81) +ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE)) +else +ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE) +endif + +$(MSIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE) +ifeq ($(SPD),) + $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set) +endif + @$(MKDIR) $(SIM_SCRIPT_DIR) + $(IP_MAKE_SIMSCRIPT) --spd=$(SPD) --spd=$(MEM_INIT_DESCRIPTOR_FILE) --output-directory=$(SIM_SCRIPT_DIR) + +VSIM_COMMAND = \ + cd $(dir $(MSIM_SCRIPT)) && \ + $(VSIM) -do "do $(notdir $(MSIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)" + +.PHONY: sim +sim: $(MSIM_SCRIPT) mem_init_generate +ifeq ($(MSIM_SCRIPT),) + $(error MSIM_SCRIPT not set) +endif + $(VSIM_COMMAND) + +endif # QSYS == 1 + + +#------------------------------------------------------------------------------ +# ELF TARGET RULE +#------------------------------------------------------------------------------ +# Rule for constructing the executable elf file. +$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS) + @$(ECHO) Info: Linking $@ + $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS) +ifneq ($(DISABLE_ELFPATCH),1) + $(ELFPATCH) $@ $(ELF_PATCH_FLAG) +endif +ifneq ($(DISABLE_STACKREPORT),1) + @bash -c "$(STACKREPORT) $@" +endif + +$(OBJDUMP_NAME) : $(ELF) + @$(ECHO) Info: Creating $@ + $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@ + +# Rule for printing the name of the elf file +.PHONY: print-elf-name +print-elf-name: + @$(ECHO) $(ELF) + + diff --git a/software/DE2_115_ASM3_release/create-this-app b/software/DE2_115_ASM3_release/create-this-app new file mode 100644 index 0000000..275882c --- /dev/null +++ b/software/DE2_115_ASM3_release/create-this-app @@ -0,0 +1,114 @@ +#!/bin/bash +# +# This script creates the hello_world application in this directory. + + +BSP_DIR=../DE2_115_ASM3_release_bsp +QUARTUS_PROJECT_DIR=../../ +NIOS2_APP_GEN_ARGS="--elf-name DE2_115_ASM3_release.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_world.c" + + +# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set. +# This variable is required for the command line tools to execute correctly. +if [ -z "${SOPC_KIT_NIOS2}" ] +then + echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set! + exit 1 +fi + + +# Also make sure that the APP has not been created already. Check for +# existence of Makefile in the app directory +if [ -f ./Makefile ] +then + echo Application has already been created! Delete Makefile if you want to create a new application makefile + exit 1 +fi + + +# We are selecting hal_default bsp because it supports this application. +# Check to see if the hal_default has already been generated by checking for +# existence of the public.mk file. If not, we need to run +# create-this-bsp file to generate the bsp. +if [ ! -f ${BSP_DIR}/public.mk ]; then + # Since BSP doesn't exist, create the BSP + # Pass any command line arguments passed to this script to the BSP. + pushd ${BSP_DIR} >> /dev/null + ./create-this-bsp "$@" || { + echo "create-this-bsp failed" + exit 1 + } + popd >> /dev/null +fi + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + esac + shift +done + + +# Now we also need to go copy the sources for this application to the +# local directory. +find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || { + echo "failed during copying example source files" + exit 1 +} + +find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || { + echo "failed copying readme file" +} + +if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" ] +then + cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" . || { + echo "failed during copying project support files" + exit 1 + } +fi + +chmod -R +w . || { + echo "failed during changing file permissions" + exit 1 +} + +cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}" + +echo "create-this-app: Running \"${cmd}\"" +$cmd || { + echo "nios2-app-generate-makefile failed" + exit 1 +} + +if [ -z "$SKIP_MAKE" ]; then + cmd="make" + + echo "create-this-app: Running \"$cmd\"" + $cmd || { + echo "make failed" + exit 1 + } + + echo + echo "To download and run the application:" + echo " 1. Make sure the board is connected to the system." + echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design." + echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell." + echo " 4. Run 'make download-elf' from the application directory." + echo + echo "To debug the application:" + echo " Import the project into Nios II Software Build Tools for Eclipse." + echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information." + echo + echo -e "" +fi + + +exit 0 diff --git a/software/DE2_115_ASM3_release/hello_world_small.c b/software/DE2_115_ASM3_release/hello_world_small.c new file mode 100644 index 0000000..eafc378 --- /dev/null +++ b/software/DE2_115_ASM3_release/hello_world_small.c @@ -0,0 +1,216 @@ +#include "sys/alt_stdio.h" +#include +#include "system.h" +#include "hex_out.h" +#include "lcd_out.h" +#include "sys_register.h" +#include "sys_memory.h" +#include "input_int.h" +#include "sys_debug.h" +#include "sys_prog.h" + +#define ledrs (volatile int *) LEDRS_BASE + +static void init() { + // lcd + lcd_init(); + lcd_print("Starting now..."); + + registers_init(); + memory_init(); + // hex + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + print_block("ve", 2, HEX6_7); + print_block("r-", 2, HEX4_5); + print_block("0003", 4, HEX0_3); + delay10ms(200); + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + + lcd_caret_reset2(); + lcd_print("Ok!"); +} + +char stack[5]; + +void store_value(){ + unsigned int memi = global_registers[Ssw_memi]; + memory_store(memi, Ssw_data); + + { // �f�o�b�N�\�� + char buf[5]; + sprintf(buf, "%02x", (unsigned char)memi); + print_block(buf, 2, HEX6_7); + print_block("--", 2, HEX4_5); + sprintf(buf, "%04d", global_registers[Ssw_data]); + print_block(buf, 4, HEX0_3); + + display_mem((unsigned char)memi, global_registers[Ssw_data]); + } +} +void store_inst(){ + char inst; + char mem_index; + char reg_index; + unsigned int stored_pc; + struct InstRec inst_rec; + + // �K�v�ȏ��̎擾 + inst = global_registers[Ssw_inst]; + mem_index = global_registers[Ssw_memi]; + reg_index = global_registers[Ssw_regi]; + inst_rec.inst = (unsigned int)inst; + inst_rec.memi = (unsigned int)mem_index; + inst_rec.regi = (unsigned int)reg_index; + + // �X�g�A�� + stored_pc = get_pc(); + inst_memory_store(get_pc(), inst_rec); + { // �f�o�b�N�\�� + char buf[5]; + sprintf(buf, "0x%02x", inst_rec.inst); + print_block(buf, 4, HEX0_3); + sprintf(buf, "--"); + print_block(buf, 2, HEX4_5); + sprintf(buf, "%02x", get_pc()); + print_block(buf, 2, HEX6_7); + + display_inst(inst_rec, stored_pc); + } + inc_pc(); +} + +void print_change_memory(unsigned int current_memory) { + char buf[17]; + sprintf(buf, "Current page:%2d", current_memory); + lcd_caret_reset(); + lcd_print("Change program"); + lcd_caret_reset2(); + lcd_print(buf); + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); +} + +static void reset_mem_cancel() { + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again -> NG"); +} +static char reset_mem(char confirmed) { + if (confirmed == 0) { + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again"); + // �m�F�v�� + return 1; + } else { + int i; + for (i = 0; i < MEM_SIZE; i++){ + memory_store(i,Szero); + } + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again -> OK"); + + // PC��Z�b�g�� + return 0; + } +} +static void reset_pc_cancel() { + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again -> NG"); +} +static char reset_pc(char confirmed) { + if (confirmed == 0) { + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again"); + // �m�F�v�� + return 1; + } else { + set_pc(0); + + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again -> OK"); + + // PC��Z�b�g�� + return 0; + } +} + + +int main() +{ + init(); + + enum RunMode fRun = RUN_STOP; + char reset_pc_confirmed = 0; + char reset_mem_confirmed = 0; + + while(1) { + // interrupt + in_int(); + + // event + // CANCEL + if (global_registers[Ssw_rw] == 0 + || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_VALSTR))) { + if (reset_mem_confirmed == 1) { + reset_mem_confirmed = 0; //�m�F�L��Z�� + reset_mem_cancel(); + } + } + if (global_registers[Ssw_rw] == 0 + || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_INSSTR))) { + if (reset_pc_confirmed == 1) { + reset_pc_confirmed = 0; //�m�F�L��Z�� + reset_pc_cancel(); + } + } + // CONFIRM + if (PUSH_EVENT & PUSH_VALSTR) { + // �l�̃X�g�A + if (global_registers[Ssw_rw] == 1) { + //�폜 + char res = reset_mem(reset_mem_confirmed);//��m�F�̏��F + if (1 == res) reset_mem_confirmed = 1; //��m�F + if (0 == res) reset_mem_confirmed = 0; //��Z�b�g�̊m�F + } else { + store_value(); + } + } + if (PUSH_EVENT & PUSH_INSSTR) { + // ��߂̃X�g�A + if (global_registers[Ssw_rw] == 1) { + //PC�̃��Z�b�g + char res = reset_pc(reset_pc_confirmed);//��m�F�̏��F + if (1 == res) reset_pc_confirmed = 1; //��m�F + if (0 == res) reset_pc_confirmed = 0; //��Z�b�g�̊m�F + } else { + store_inst(); + } + } + // RUN + if (PUSH_EVENT & PUSH_RUN) { + if (global_current_memory != (unsigned int)global_registers[Ssw_psel]) { + global_current_memory = (unsigned int)global_registers[Ssw_psel]; + print_change_memory(global_current_memory); + } + else { + // �v��O��ݒ� + fRun = RUN_INIT; + } + } + if (fRun != RUN_STOP) { + // �v��O��s��荞�� & ��s��[�h�X�V + fRun = run_proc(fRun); + } + } + return 0; +} diff --git a/software/DE2_115_ASM3_release/hex_encoder.c b/software/DE2_115_ASM3_release/hex_encoder.c new file mode 100644 index 0000000..9639775 --- /dev/null +++ b/software/DE2_115_ASM3_release/hex_encoder.c @@ -0,0 +1,205 @@ +/* + * hex_encoder.c + * + * Created on: 2016/11/17 + * Author: takayun + */ + +#include "hex_encoder.h" +#include + +void encodeNumHex(int hex_i, int num) { + char encoded = 0; + switch (num) { + case 0: + encoded = (char)0x40; // 100 0000 + break; + case 1: + encoded = (char)0xF9; // 111 1001 + break; + case 2: + encoded = (char)0x24; // 010 0100 + break; + case 3: + encoded = (char)0x30; // 011 0000 + break; + case 4: + encoded = (char)0x19; // 001 1001 + break; + case 5: + encoded = (char)0x12; // 001 0010 + break; + case 6: + encoded = (char)0x02; // 000 0010 + break; + case 7: + encoded = (char)0x58; // 101 1000 + break; + case 8: + encoded = (char)0x00; // 000 0000 + break; + case 9: + encoded = (char)0x10; // 001 0000 + break; + default: + encoded = 0; + break; + } + + switch (hex_i) { + case 0: + *hex0 = encoded; + break; + case 1: + *hex1 = encoded; + break; + case 2: + *hex2 = encoded; + break; + case 3: + *hex3 = encoded; + break; + case 4: + *hex4 = encoded; + break; + case 5: + *hex5 = encoded; + break; + case 6: + *hex6 = encoded; + break; + case 7: + *hex7 = encoded; + break; + default: + break; + } +} + +void encodeLatHex(int hex_i, char c) { + char encoded = 0; + + if (isdigit(c)) { + encodeNumHex(hex_i, c-'0'); + return; + } + + switch (c) { + case ' ': + encoded = (char)0xFF; // 111 1111 + break; + case '-': + encoded = (char)0x3F; // 011 1111 + break; + case 'a': + encoded = (char)0x08; // 000 1000 + break; + case 'b': + encoded = (char)0x03; // 000 0011 + break; + case 'c': + encoded = (char)0x27; // 010 0111 + break; + case 'd': + encoded = (char)0x21; // 010 0001 + break; + case 'e': + encoded = (char)0x06; // 000 0110 + break; + case 'f': + encoded = (char)0x0E; // 000 1110 + break; + case 'g': + encoded = (char)0x42; // 100 0010 + break; + case 'h': + encoded = (char)0x0B; // 000 1011 + break; + case 'i': + encoded = (char)0xFB; // 111 1011 + break; + case 'j': + encoded = (char)0x61; // 110 0001 + break; + case 'k': + encoded = (char)0x0A; // 000 1010 + break; + case 'l': + encoded = (char)0x47; // 100 0111 + break; + case 'm': + encoded = (char)0x48; // 100 1000 + break; + case 'n': + encoded = (char)0x2B; // 010 1011 + break; + case 'o': + encoded = (char)0x23; // 010 0011 + break; + case 'p': + encoded = (char)0x0C; // 000 1100 + break; + case 'q': + encoded = (char)0x04; // 000 0100 + break; + case 'r': + encoded = (char)0x2F; // 010 1111 + break; + case 's': + encoded = (char)0x13; // 001 0011 + break; + case 't': + encoded = (char)0x07; // 000 0111 + break; + case 'u': + encoded = (char)0x63; // 110 0011 + break; + case 'v': + encoded = (char)0x41; // 100 0001 + break; + case 'w': + encoded = (char)0x01; // 000 0001 + break; + case 'x': + encoded = (char)0x09; // 000 1001 + break; + case 'y': + encoded = (char)0x11; // 001 0001 + break; + case 'z': + encoded = (char)0x64; // 110 0100 + break; + default: + encoded = 0; + break; + } + + switch (hex_i) { + case 0: + *hex0 = encoded; + break; + case 1: + *hex1 = encoded; + break; + case 2: + *hex2 = encoded; + break; + case 3: + *hex3 = encoded; + break; + case 4: + *hex4 = encoded; + break; + case 5: + *hex5 = encoded; + break; + case 6: + *hex6 = encoded; + break; + case 7: + *hex7 = encoded; + break; + default: + break; + } +} diff --git a/software/DE2_115_ASM3_release/hex_encoder.h b/software/DE2_115_ASM3_release/hex_encoder.h new file mode 100644 index 0000000..7909cf8 --- /dev/null +++ b/software/DE2_115_ASM3_release/hex_encoder.h @@ -0,0 +1,38 @@ +/* + * hex_encoder.h + * + * Created on: 2016/11/17 + * Author: takayun + */ + +#ifndef HEX_ENCODER_H_ +#define HEX_ENCODER_H_ + +#include "system.h" + +/************************************************** + * Defines + **************************************************/ + +#define hex0 (volatile char *) HEX0_BASE +#define hex1 (volatile char *) HEX1_BASE +#define hex2 (volatile char *) HEX2_BASE +#define hex3 (volatile char *) HEX3_BASE +#define hex4 (volatile char *) HEX4_BASE +#define hex5 (volatile char *) HEX5_BASE +#define hex6 (volatile char *) HEX6_BASE +#define hex7 (volatile char *) HEX7_BASE + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void encodeNumHex(int hex_i, int num); +void encodeLatHex(int hex_i, char c); + +#endif /* HEX_ENCODER_H_ */ diff --git a/software/DE2_115_ASM3_release/hex_out.c b/software/DE2_115_ASM3_release/hex_out.c new file mode 100644 index 0000000..874dbac --- /dev/null +++ b/software/DE2_115_ASM3_release/hex_out.c @@ -0,0 +1,67 @@ +/* + * hex_out.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "hex_out.h" +#include "hex_encoder.h" +#include "sys_except.h" + +void print_block(char * str, unsigned int size, enum BLOCK_N block_i) { + int i; + if (block_i == HEX0_3) { + if (size > 4) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i,str[size-1-i]); + } + } + else if (block_i == HEX4_5) { + if (size > 2) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i+4,str[size-1-i]); + } + } + else if (block_i == HEX6_7) { + if (size > 2) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i+6,str[size-1-i]); + } + } +} + +void clear_block(enum BLOCK_N block_i) { + if (block_i == HEX0_3) { + print_block(" ", 4, HEX0_3); + } + else if (block_i == HEX4_5) { + print_block(" ", 2, HEX4_5); + } + else if (block_i == HEX6_7) { + print_block(" ", 2, HEX6_7); + } +} + +void print_number(char num) { + int i; + char buf[5]; + char val; + for (i = 0; i < 4; i++) { + if (num < 0) { + buf[0] = '-'; + val = -num; + } else { + buf[0] = ' '; + val = num; + } + buf[1] = val/100%10 + '0'; + buf[2] = val/10%10 + '0'; + buf[3] = val%10 + '0'; + } + clear_block(HEX0_3); + print_block(buf, 4, HEX0_3); +} + + + + diff --git a/software/DE2_115_ASM3_release/hex_out.h b/software/DE2_115_ASM3_release/hex_out.h new file mode 100644 index 0000000..99219b5 --- /dev/null +++ b/software/DE2_115_ASM3_release/hex_out.h @@ -0,0 +1,33 @@ +/* + * hex_out.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef HEX_IO_H_ +#define HEX_IO_H_ + +/************************************************** + * Defines + **************************************************/ + +enum BLOCK_N { + HEX0_3, HEX4_5, HEX6_7 +}; + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void print_block(char * str, unsigned int size, enum BLOCK_N block_i); +void clear_block(enum BLOCK_N block_i); +void print_number(char num); + + +#endif /* HEX_IO_H_ */ diff --git a/software/DE2_115_ASM3_release/input_int.c b/software/DE2_115_ASM3_release/input_int.c new file mode 100644 index 0000000..0145286 --- /dev/null +++ b/software/DE2_115_ASM3_release/input_int.c @@ -0,0 +1,71 @@ +/* + * input_int.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "input_int.h" +#include "sys_register.h" + +unsigned char PUSH_EVENT = PUSH_NONE; + +void in_int() { + push_int(); +} + +static void update_sw_reg(sw_t s) { + global_registers[Ssw_data] = (char)s.data.value; + global_registers[Ssw_inst] = (char)s.splited.instruction_code; + global_registers[Ssw_memi] = (char)s.splited.memory_index; + global_registers[Ssw_regi] = (char)s.splited.register_index; + global_registers[Ssw_psel] = (char)s.splited.program_selecter; + global_registers[Ssw_rw] = (char)s.splited.rw_mode; + global_registers[Ssw_run] = (char)s.splited.run_mode; +} + +enum PushEvent push_decode(char psw) { + int result = PUSH_NONE; + switch(psw) { + case 0x3: + result += PUSH_ANY; + result += PUSH_VALSTR; + break; + case 0x5: + result += PUSH_ANY; + result += PUSH_INSSTR; + break; + case 0x6: + result += PUSH_ANY; + result += PUSH_RUN; + break; + } + return result; +} + +void push_int() { + static unsigned char status = 0; + static enum PushEvent event_code; + volatile sw_t s; + s.sw = *switches; + + switch (status) { + case 0: + PUSH_EVENT = PUSH_NONE; + if (*push_switches != 7) { + event_code = push_decode(*push_switches); + status = 1; + } + update_sw_reg(s); // �X�C�b�`��W�X�^�X�V + break; + case 1: + if (*push_switches == 7) status = 2; + break; + case 2: + PUSH_EVENT = event_code; + status = 0; + break; + default: + status = 0; + break; + } +} diff --git a/software/DE2_115_ASM3_release/input_int.h b/software/DE2_115_ASM3_release/input_int.h new file mode 100644 index 0000000..e1d0612 --- /dev/null +++ b/software/DE2_115_ASM3_release/input_int.h @@ -0,0 +1,62 @@ +/* + * input_int.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SWITCHES_INT_H_ +#define SWITCHES_INT_H_ + +#include "system.h" + +/************************************************** + * Defines + **************************************************/ + +#define switches (volatile int *) SWITCHES_BASE +#define push_switches (volatile char *) PUSH_SWITCHES_BASE + +typedef union { + int sw; + struct { + unsigned int run_mode : 1; + unsigned int rw_mode : 1; + unsigned int program_selecter : 4; + unsigned int memory_index : 4; + unsigned int register_index : 4; + unsigned int instruction_code : 4; + } splited; + struct { + unsigned int : 10; + unsigned int value : 8; + } data; +} sw_t; + +enum PushEvent{ + PUSH_NONE = 1<<0, + PUSH_ANY = 1<<1, + PUSH_VALSTR = 1<<2, + PUSH_INSSTR = 1<<3, + PUSH_RUN = 1<<4 +}; + +/************************************************** + * Variables + **************************************************/ + +extern unsigned char PUSH_EVENT; + +/************************************************** + * Functions + **************************************************/ + +/* Function: in_int + * Sammary: + * �S�Ă̓��͊��荞�݂��s�� + * */ +void in_int(); + +void push_int(); + +#endif /* SWITCHES_INT_H_ */ diff --git a/software/DE2_115_ASM3_release/inst_decoder.c b/software/DE2_115_ASM3_release/inst_decoder.c new file mode 100644 index 0000000..3e6e8a9 --- /dev/null +++ b/software/DE2_115_ASM3_release/inst_decoder.c @@ -0,0 +1,120 @@ +/* + * inst_decoder.c + * + * Created on: 2016/11/25 + * Author: takayun + */ + +#include "inst_decoder.h" +#include "sys_memory.h" +#include "sys_register.h" +#include "hex_out.h" +#include "sys_prog.h" +#include +#include + +struct InstRec inst_fetch(){ + struct InstRec rec = inst_memory_load((unsigned int)global_registers[Spc]); + inc_pc(); + return rec; +} + +void inst_decode(struct InstRec inst_rec){ + switch(inst_rec.inst) { + case INST_END: + break; + case INST_JUMP: + inst_jump(inst_rec.regi, inst_rec.memi); + break; + case INST_OUTPUT: + inst_output(inst_rec.regi, inst_rec.memi); + break; + case INST_LOAD: + inst_load(inst_rec.regi, inst_rec.memi); + break; + case INST_STORE: + inst_store(inst_rec.regi, inst_rec.memi); + break; + case INST_DELAY: + inst_delay(inst_rec.regi, inst_rec.memi); + break; + case INST_ADD: + inst_add(inst_rec.regi, inst_rec.memi); + break; + case INST_SUB: + inst_sub(inst_rec.regi, inst_rec.memi); + break; + case INST_COMP: + inst_comp(inst_rec.regi, inst_rec.memi); + break; + case INST_JEQ: + inst_jeq(inst_rec.regi, inst_rec.memi); + break; + case INST_JNE: + inst_jne(inst_rec.regi, inst_rec.memi); + break; + case INST_JIEQ: + inst_jieq(inst_rec.regi, inst_rec.memi); + break; + case INST_JINE: + inst_jine(inst_rec.regi, inst_rec.memi); + break; + } +} + +void inst_jump(enum Register reg, unsigned char memory_index){ + set_pc(global_registers[reg]+memory_index); +} +void inst_output(enum Register reg, unsigned char memory_index){ + //��̒l��7�Z�O�ɕ\�� + char buf[5]; + memory_load(memory_index, Sseg); + sprintf(buf, "%04d", global_registers[Sseg]); + print_block(buf, 4, HEX0_3); +} +void inst_load(enum Register reg, unsigned char memory_index){ + memory_load(memory_index, reg); +} +void inst_store(enum Register reg, unsigned char memory_index){ + memory_store(memory_index, reg); +} +void inst_delay(enum Register reg, unsigned char memory_index){ + //��W�X�^�̒l*10ms�҂� + usleep((int)global_registers[reg]*10000); +} +void inst_add(enum Register reg, unsigned char memory_index){ + global_registers[Sacc]+=global_registers[reg]; +} +void inst_sub(enum Register reg, unsigned char memory_index){ + global_registers[Sacc]-=global_registers[reg]; +} +void inst_comp(enum Register reg, unsigned char memory_index){ + if(global_registers[Sacc]==global_registers[reg]){ + global_registers[Sflg]=0; + } else if(global_registers[Sacc] > global_registers[reg]){ + global_registers[Sflg]=-1; + }else{ + global_registers[Sflg]=1; + } +} +void inst_jeq(enum Register reg, unsigned char memory_index){ + if(global_registers[Sflg]==global_registers[reg]){ + inc_pc(); + } +} +void inst_jne(enum Register reg, unsigned char memory_index){ + if(global_registers[Sflg]!=global_registers[reg]){ + inc_pc(); + } +} +void inst_jieq(char im, unsigned char memory_index){ + if(global_registers[Sflg]==im){ + inc_pc(); + } +} +void inst_jine(char im, unsigned char memory_index){ + if(global_registers[Sflg]!=im){ + inc_pc(); + } +} + diff --git a/software/DE2_115_ASM3_release/inst_decoder.h b/software/DE2_115_ASM3_release/inst_decoder.h new file mode 100644 index 0000000..036e179 --- /dev/null +++ b/software/DE2_115_ASM3_release/inst_decoder.h @@ -0,0 +1,51 @@ +/* + * inst_decoder.h + * + * Created on: 2016/11/25 + * Author: takayun + */ + +#ifndef INST_DECODER_H_ +#define INST_DECODER_H_ + +#include "sys_register.h" + +#define INST_END 0x0 +#define INST_JUMP 0x1 +#define INST_OUTPUT 0x2 +#define INST_LOAD 0x3 +#define INST_STORE 0x4 +#define INST_DELAY 0x5 +#define INST_ADD 0x6 +#define INST_COMP 0x7 +#define INST_JEQ 0x8 +#define INST_JNE 0x9 +#define INST_JIEQ 0xA +#define INST_JINE 0xB +#define INST_SUB 0xC + +struct InstRec { + unsigned int inst : 4; + unsigned int memi : 4; + unsigned int regi : 4; +}; + +struct InstRec inst_fetch(); + +void inst_decode(struct InstRec inst_rec); + +void inst_jump(enum Register reg, unsigned char memory_index); +void inst_output(enum Register reg, unsigned char memory_index); +void inst_load(enum Register reg, unsigned char memory_index); +void inst_store(enum Register reg, unsigned char memory_index); +void inst_delay(enum Register reg, unsigned char memory_index); +void inst_add(enum Register reg, unsigned char memory_index); +void inst_sub(enum Register reg, unsigned char memory_index); +void inst_comp(enum Register reg, unsigned char memory_index); +void inst_jeq(enum Register reg, unsigned char memory_index); +void inst_jne(enum Register reg, unsigned char memory_index); +void inst_jieq(char im, unsigned char memory_index); +void inst_jine(char im, unsigned char memory_index); + + +#endif /* INST_DECODER_H_ */ diff --git a/software/DE2_115_ASM3_release/lcd_out.c b/software/DE2_115_ASM3_release/lcd_out.c new file mode 100644 index 0000000..b09a0bb --- /dev/null +++ b/software/DE2_115_ASM3_release/lcd_out.c @@ -0,0 +1,29 @@ +#include "lcd_out.h" +#include +#include +#include +#include +#include "system.h" +#include "LCD.h" + +// LCD�̏�� +void lcd_init() { + *lcd_on = 1; + *lcd_blon = 1; + LCD_Init(); +} + +// LCD�̃L��b�g��P�s�ڂ̂͂��߂Ɉړ�� +void lcd_caret_reset() { + LCD_Init(); +} + +// LCD�̃L��b�g��Q�s�ڂ̂͂��߂Ɉړ�� +void lcd_caret_reset2() { + LCD_Line2(); +} + +// LCD�ɕ��\�� +void lcd_print(const char *str) { + LCD_Show_Text(str); +} diff --git a/software/DE2_115_ASM3_release/lcd_out.h b/software/DE2_115_ASM3_release/lcd_out.h new file mode 100644 index 0000000..7c51dd4 --- /dev/null +++ b/software/DE2_115_ASM3_release/lcd_out.h @@ -0,0 +1,28 @@ +/* + * lcd_out.h + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#ifndef LCD_OUT_H_ +#define LCD_OUT_H_ + +#include "system.h" + +#define lcd_on (volatile char *) LCD_ON_BASE +#define lcd_blon (volatile char *) LCD_BLON_BASE + +// LCD�̏�� +void lcd_init(); + +// LCD�̃L��b�g��P�s�ڂ̂͂��߂Ɉړ�� +void lcd_caret_reset(); + +// LCD�̃L��b�g��Q�s�ڂ̂͂��߂Ɉړ�� +void lcd_caret_reset2(); + +// LCD�ɕ��\�� +void lcd_print(const char *str); + +#endif /* LCD_OUT_H_ */ diff --git a/software/DE2_115_ASM3_release/mem_init/hdl_sim/nios_system_onchip_memory.dat b/software/DE2_115_ASM3_release/mem_init/hdl_sim/nios_system_onchip_memory.dat new file mode 100644 index 0000000..3f4f6ca --- /dev/null +++ b/software/DE2_115_ASM3_release/mem_init/hdl_sim/nios_system_onchip_memory.dat @@ -0,0 +1,18583 @@ +@0000 00400034 +@0001 08406D14 +@0002 0800683A +@0003 00000000 +@0004 00000000 +@0005 00000000 +@0006 00000000 +@0007 00000000 +@0008 DEFFED04 +@0009 DFC00015 +@000A D8400215 +@000B D8800315 +@000C D8C00415 +@000D D9000515 +@000E D9400615 +@000F D9800715 +@0010 D9C00815 +@0011 000B307A +@0012 DA000915 +@0013 DA400A15 +@0014 DA800B15 +@0015 DAC00C15 +@0016 DB000D15 +@0017 DB400E15 +@0018 DB800F15 +@0019 DBC01015 +@001A D9401115 +@001B EBFFFF04 +@001C DBC01215 +@001D 0009313A +@001E 2880004C +@001F 10000326 +@0020 20000226 +@0021 00000EC0 +@0022 00000306 +@0023 DF401215 +@0024 E8BFFF17 +@0025 003DA03A +@0026 D9401117 +@0027 DF401217 +@0028 DFC00017 +@0029 2801707A +@002A D8400217 +@002B D8800317 +@002C D8C00417 +@002D D9000517 +@002E D9400617 +@002F D9800717 +@0030 D9C00817 +@0031 DA000917 +@0032 DA400A17 +@0033 DA800B17 +@0034 DAC00C17 +@0035 DB000D17 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+:20C7E800000000000000000000000000000000000000000000000000000000000000000031 +:20C7F000000000000000000000000000000000000000000000000000000000000000000029 +:20C7F800000000000000000000000000000000000000000000000000000000000000000021 +:00000001FF diff --git a/software/DE2_115_ASM3_release/obj/default/.force_relink b/software/DE2_115_ASM3_release/obj/default/.force_relink new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/.force_relink diff --git a/software/DE2_115_ASM3_release/obj/default/LCD.d b/software/DE2_115_ASM3_release/obj/default/LCD.d new file mode 100644 index 0000000..2bf9553 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/LCD.d @@ -0,0 +1,14 @@ +obj/default/LCD.o: LCD.c ../DE2_115_ASM3_release_bsp//HAL/inc/io.h \ + ../DE2_115_ASM3_release_bsp//HAL/inc/alt_types.h \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h LCD.h + +../DE2_115_ASM3_release_bsp//HAL/inc/io.h: + +../DE2_115_ASM3_release_bsp//HAL/inc/alt_types.h: + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: + +LCD.h: diff --git a/software/DE2_115_ASM3_release/obj/default/LCD.o b/software/DE2_115_ASM3_release/obj/default/LCD.o new file mode 100644 index 0000000..233bdd5 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/LCD.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/hello_world_small.d b/software/DE2_115_ASM3_release/obj/default/hello_world_small.d new file mode 100644 index 0000000..96f5344 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/hello_world_small.d @@ -0,0 +1,27 @@ +obj/default/hello_world_small.o: hello_world_small.c \ + ../DE2_115_ASM3_release_bsp//HAL/inc/sys/alt_stdio.h \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h hex_out.h lcd_out.h sys_register.h \ + sys_memory.h inst_decoder.h input_int.h sys_debug.h sys_prog.h + +../DE2_115_ASM3_release_bsp//HAL/inc/sys/alt_stdio.h: + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: + +hex_out.h: + +lcd_out.h: + +sys_register.h: + +sys_memory.h: + +inst_decoder.h: + +input_int.h: + +sys_debug.h: + +sys_prog.h: diff --git a/software/DE2_115_ASM3_release/obj/default/hello_world_small.o b/software/DE2_115_ASM3_release/obj/default/hello_world_small.o new file mode 100644 index 0000000..cd9e916 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/hello_world_small.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/hex_encoder.d b/software/DE2_115_ASM3_release/obj/default/hex_encoder.d new file mode 100644 index 0000000..d8948cd --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/hex_encoder.d @@ -0,0 +1,9 @@ +obj/default/hex_encoder.o: hex_encoder.c hex_encoder.h \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h + +hex_encoder.h: + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: diff --git a/software/DE2_115_ASM3_release/obj/default/hex_encoder.o b/software/DE2_115_ASM3_release/obj/default/hex_encoder.o new file mode 100644 index 0000000..b2ed14f --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/hex_encoder.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/hex_out.d b/software/DE2_115_ASM3_release/obj/default/hex_out.d new file mode 100644 index 0000000..bc37dd5 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/hex_out.d @@ -0,0 +1,13 @@ +obj/default/hex_out.o: hex_out.c hex_out.h hex_encoder.h \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h sys_except.h + +hex_out.h: + +hex_encoder.h: + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: + +sys_except.h: diff --git a/software/DE2_115_ASM3_release/obj/default/hex_out.o b/software/DE2_115_ASM3_release/obj/default/hex_out.o new file mode 100644 index 0000000..7e85f03 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/hex_out.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/input_int.d b/software/DE2_115_ASM3_release/obj/default/input_int.d new file mode 100644 index 0000000..0288388 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/input_int.d @@ -0,0 +1,11 @@ +obj/default/input_int.o: input_int.c input_int.h \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h sys_register.h + +input_int.h: + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: + +sys_register.h: diff --git a/software/DE2_115_ASM3_release/obj/default/input_int.o b/software/DE2_115_ASM3_release/obj/default/input_int.o new file mode 100644 index 0000000..3a9935b --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/input_int.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/inst_decoder.d b/software/DE2_115_ASM3_release/obj/default/inst_decoder.d new file mode 100644 index 0000000..760a64b --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/inst_decoder.d @@ -0,0 +1,12 @@ +obj/default/inst_decoder.o: inst_decoder.c inst_decoder.h sys_register.h \ + sys_memory.h hex_out.h sys_prog.h + +inst_decoder.h: + +sys_register.h: + +sys_memory.h: + +hex_out.h: + +sys_prog.h: diff --git a/software/DE2_115_ASM3_release/obj/default/inst_decoder.o b/software/DE2_115_ASM3_release/obj/default/inst_decoder.o new file mode 100644 index 0000000..176e2c4 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/inst_decoder.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/lcd_out.d b/software/DE2_115_ASM3_release/obj/default/lcd_out.d new file mode 100644 index 0000000..54a828b --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/lcd_out.d @@ -0,0 +1,11 @@ +obj/default/lcd_out.o: lcd_out.c lcd_out.h \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h LCD.h + +lcd_out.h: + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: + +LCD.h: diff --git a/software/DE2_115_ASM3_release/obj/default/lcd_out.o b/software/DE2_115_ASM3_release/obj/default/lcd_out.o new file mode 100644 index 0000000..e0b65ba --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/lcd_out.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/sys_debug.d b/software/DE2_115_ASM3_release/obj/default/sys_debug.d new file mode 100644 index 0000000..2d0d0ae --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_debug.d @@ -0,0 +1,15 @@ +obj/default/sys_debug.o: sys_debug.c sys_debug.h inst_decoder.h \ + sys_register.h lcd_out.h ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h + +sys_debug.h: + +inst_decoder.h: + +sys_register.h: + +lcd_out.h: + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: diff --git a/software/DE2_115_ASM3_release/obj/default/sys_debug.o b/software/DE2_115_ASM3_release/obj/default/sys_debug.o new file mode 100644 index 0000000..ee2f77a --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_debug.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/sys_except.d b/software/DE2_115_ASM3_release/obj/default/sys_except.d new file mode 100644 index 0000000..726749a --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_except.d @@ -0,0 +1,9 @@ +obj/default/sys_except.o: sys_except.c \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h hex_out.h + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: + +hex_out.h: diff --git a/software/DE2_115_ASM3_release/obj/default/sys_except.o b/software/DE2_115_ASM3_release/obj/default/sys_except.o new file mode 100644 index 0000000..e4bdb77 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_except.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/sys_memory.d b/software/DE2_115_ASM3_release/obj/default/sys_memory.d new file mode 100644 index 0000000..32a357c --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_memory.d @@ -0,0 +1,16 @@ +obj/default/sys_memory.o: sys_memory.c \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h sys_memory.h sys_register.h \ + inst_decoder.h sys_except.h + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: + +sys_memory.h: + +sys_register.h: + +inst_decoder.h: + +sys_except.h: diff --git a/software/DE2_115_ASM3_release/obj/default/sys_memory.o b/software/DE2_115_ASM3_release/obj/default/sys_memory.o new file mode 100644 index 0000000..8c3125a --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_memory.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/sys_prog.d b/software/DE2_115_ASM3_release/obj/default/sys_prog.d new file mode 100644 index 0000000..335afca --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_prog.d @@ -0,0 +1,22 @@ +obj/default/sys_prog.o: sys_prog.c sys_prog.h sys_debug.h inst_decoder.h \ + sys_register.h sys_memory.h hex_out.h lcd_out.h \ + ../DE2_115_ASM3_release_bsp/system.h \ + ../DE2_115_ASM3_release_bsp/linker.h + +sys_prog.h: + +sys_debug.h: + +inst_decoder.h: + +sys_register.h: + +sys_memory.h: + +hex_out.h: + +lcd_out.h: + +../DE2_115_ASM3_release_bsp/system.h: + +../DE2_115_ASM3_release_bsp/linker.h: diff --git a/software/DE2_115_ASM3_release/obj/default/sys_prog.o b/software/DE2_115_ASM3_release/obj/default/sys_prog.o new file mode 100644 index 0000000..3d7b999 --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_prog.o Binary files differ diff --git a/software/DE2_115_ASM3_release/obj/default/sys_register.d b/software/DE2_115_ASM3_release/obj/default/sys_register.d new file mode 100644 index 0000000..42e349a --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_register.d @@ -0,0 +1,3 @@ +obj/default/sys_register.o: sys_register.c sys_register.h + +sys_register.h: diff --git a/software/DE2_115_ASM3_release/obj/default/sys_register.o b/software/DE2_115_ASM3_release/obj/default/sys_register.o new file mode 100644 index 0000000..9e9919c --- /dev/null +++ b/software/DE2_115_ASM3_release/obj/default/sys_register.o Binary files differ diff --git a/software/DE2_115_ASM3_release/readme.txt b/software/DE2_115_ASM3_release/readme.txt new file mode 100644 index 0000000..a949aa6 --- /dev/null +++ b/software/DE2_115_ASM3_release/readme.txt @@ -0,0 +1,26 @@ +Readme - Hello World Software Example + +DESCRIPTION: +Simple program that prints "Hello from Nios II" + +The memory footprint of this hosted application is intended to be small (under 100 kbytes) by default +using a standard reference deisgn. + +For an even smaller, reduced footprint version of this template, and an explanation of how +to reduce the memory footprint for a given application, see the +"small_hello_world" template. + + +PERIPHERALS USED: +This example exercises the following peripherals: +- STDOUT device (UART or JTAG UART) + +SOFTWARE SOURCE FILES: +This example includes the following software source files: +- hello_world.c: Everyone needs a Hello World program, right? + +BOARD/HOST REQUIREMENTS: +This example requires only a JTAG connection with a Nios Development board. If +the host communication settings are changed from JTAG UART (default) to use a +conventional UART, a serial cable between board DB-9 connector and the host is +required. diff --git a/software/DE2_115_ASM3_release/sys_debug.c b/software/DE2_115_ASM3_release/sys_debug.c new file mode 100644 index 0000000..190b908 --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_debug.c @@ -0,0 +1,121 @@ +/* + * sys_debug.c + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#include "sys_debug.h" +#include +#include "lcd_out.h" +#include + +void display_inst(struct InstRec inst, unsigned int pc) { + char inst_name[INST_NAME_ARRAY_LEN]; // ��ߖ� + char reg_name[REG_NAME_ARRAY_LEN]; // ��W�X�^�� + char buf[17]; + + // ��߂̖��O�̎擾 + convertInstName(inst_name, inst.inst); + // ��W�X�^�̖��O�̎擾 + convertRegName(reg_name, inst.regi); + + lcd_caret_reset(); + sprintf(buf, "PC:0x%02x -> %4s",pc,inst_name); + lcd_print(buf); + lcd_caret_reset2(); + sprintf(buf, "REG:%3s,MEM:0x%1x",reg_name,inst.memi); + lcd_print(buf); +} + +void display_mem(unsigned char memi, char memv) { + char buf[17]; + + lcd_caret_reset(); + sprintf(buf, "MEM:0x%1x",memi); + lcd_print(buf); + lcd_caret_reset2(); + sprintf(buf, "value:%d",memv); + lcd_print(buf); +} + +void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code) { + switch(reg_code) { + case Szero: + sprintf(reg_name, STRING_REG_ZERO); + break; + case Spc: + sprintf(reg_name, STRING_REG_PC); + break; + case Ssp: + sprintf(reg_name, STRING_REG_SP); + break; + case Sgp0: + sprintf(reg_name, STRING_REG_GP0); + break; + case Sgp1: + sprintf(reg_name, STRING_REG_GP1); + break; + case Sacc: + sprintf(reg_name, STRING_REG_ACC); + break; + case Sflg: + sprintf(reg_name, STRING_REG_FLG); + break; + default: + sprintf(reg_name, "non"); + break; + } +} + + +void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code) { + switch(inst_code) { + case INST_END: + sprintf(inst_name, STRING_INST_END); + break; + case INST_JUMP: + sprintf(inst_name, STRING_INST_JUMP); + break; + case INST_OUTPUT: + sprintf(inst_name, STRING_INST_OUTPUT); + break; + case INST_LOAD: + sprintf(inst_name, STRING_INST_LOAD); + break; + case INST_STORE: + sprintf(inst_name, STRING_INST_STORE); + break; + case INST_DELAY: + sprintf(inst_name, STRING_INST_DELAY); + break; + case INST_ADD: + sprintf(inst_name, STRING_INST_ADD); + break; + case INST_SUB: + sprintf(inst_name, STRING_INST_SUB); + break; + case INST_COMP: + sprintf(inst_name, STRING_INST_COMP); + break; + case INST_JEQ: + sprintf(inst_name, STRING_INST_JEQ); + break; + case INST_JNE: + sprintf(inst_name, STRING_INST_JNE); + break; + case INST_JIEQ: + sprintf(inst_name, STRING_INST_JIEQ); + break; + case INST_JINE: + sprintf(inst_name, STRING_INST_JINE); + break; + default: + sprintf(inst_name, "NoOp"); + break; + } +} + +void delay10ms(unsigned int s) { + usleep(s*10000); +} diff --git a/software/DE2_115_ASM3_release/sys_debug.h b/software/DE2_115_ASM3_release/sys_debug.h new file mode 100644 index 0000000..bb1fb1c --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_debug.h @@ -0,0 +1,62 @@ +/* + * sys_debug.h + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#ifndef SYS_DEBUG_H_ +#define SYS_DEBUG_H_ + +#include "inst_decoder.h" +#include "sys_register.h" + +/************************************************** + * Defines + **************************************************/ + +#define INST_NAME_ARRAY_LEN 5 + +#define STRING_INST_END "END" +#define STRING_INST_JUMP "JUMP" +#define STRING_INST_OUTPUT "OUT" +#define STRING_INST_LOAD "LOAD" +#define STRING_INST_STORE "STOR" +#define STRING_INST_DELAY "DELY" +#define STRING_INST_ADD "ADD" +#define STRING_INST_COMP "COMP" +#define STRING_INST_JEQ "JEQ" +#define STRING_INST_JNE "JNE" +#define STRING_INST_JIEQ "JIEQ" +#define STRING_INST_JINE "JINE" +#define STRING_INST_SUB "SUB" + + +#define REG_NAME_ARRAY_LEN 4 + +#define STRING_REG_ZERO "ZE" +#define STRING_REG_PC "PC" +#define STRING_REG_SP "SP" +#define STRING_REG_GP0 "GP0" +#define STRING_REG_GP1 "GP1" +#define STRING_REG_ACC "ACC" +#define STRING_REG_FLG "FLG" + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code); +void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code); + +void display_inst(struct InstRec inst, unsigned int pc); +void display_mem(unsigned char memi, char memv); + +void delay10ms(unsigned int s); + +#endif /* SYS_DEBUG_H_ */ diff --git a/software/DE2_115_ASM3_release/sys_except.c b/software/DE2_115_ASM3_release/sys_except.c new file mode 100644 index 0000000..82420a4 --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_except.c @@ -0,0 +1,14 @@ +/* + * sys_except.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "system.h" +#include "hex_out.h" + +void panic() { + clear_block(HEX0_3); + print_block("err ", 4, HEX0_3); +} + diff --git a/software/DE2_115_ASM3_release/sys_except.h b/software/DE2_115_ASM3_release/sys_except.h new file mode 100644 index 0000000..fa6f420 --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_except.h @@ -0,0 +1,13 @@ +/* + * sys_except.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYSTEM_H_ +#define SYSTEM_H_ + +void panic(); + +#endif /* SYSTEM_H_ */ diff --git a/software/DE2_115_ASM3_release/sys_memory.c b/software/DE2_115_ASM3_release/sys_memory.c new file mode 100644 index 0000000..71b9d69 --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_memory.c @@ -0,0 +1,59 @@ +/* + * sys_memory.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "system.h" +#include "sys_memory.h" +#include "sys_register.h" +#include "sys_except.h" + +/************************************************** + * Public + **************************************************/ + +// ��̂ǂ̃��(0 < global_current_memory < MEMS_COUNT) +unsigned int global_current_memory = 0; + +/************************************************** + * Private + **************************************************/ + +// ��̕ϐ� +static char memory[MEMS_COUNT][MEM_SIZE]; + +static struct InstRec inst_memory[MEMS_COUNT][MEM_SIZE]; + + +/************************************************** + * Impl + **************************************************/ + +void memory_init() { + int i, j; + for (i = 0; i < MEMS_COUNT; i++) + for (j = 0; j < MEM_SIZE; j++) { + memory[i][j] = 0; + } +} + +void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec){ + inst_memory[global_current_memory][mem_addr] = inst_rec; +} +struct InstRec inst_memory_load(unsigned int mem_addr){ + return inst_memory[global_current_memory][mem_addr]; +} + +char memory_store(unsigned int mem_addr, enum Register reg) { + if (!(mem_addr < MEM_SIZE)) panic(); + memory[global_current_memory][mem_addr] = global_registers[reg]; + return memory[global_current_memory][mem_addr]; +} + +char memory_load(unsigned int mem_addr, enum Register reg) { + if (!(mem_addr < MEM_SIZE)) panic(); + global_registers[reg] = memory[global_current_memory][mem_addr]; + return global_registers[reg]; +} + diff --git a/software/DE2_115_ASM3_release/sys_memory.h b/software/DE2_115_ASM3_release/sys_memory.h new file mode 100644 index 0000000..f67c9a4 --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_memory.h @@ -0,0 +1,67 @@ +/* + * sys_memory.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYS_MEMORY_H_ +#define SYS_MEMORY_H_ + +#include "sys_register.h" +#include "inst_decoder.h" + +/************************************************** + * Defines + **************************************************/ + +// ��̐� +#define MEMS_COUNT 16 + +// 1��̃T�C�Y +#define MEM_SIZE 16 + +/************************************************** + * Variables + **************************************************/ + +extern unsigned int global_current_memory; + +/************************************************** + * Functions + **************************************************/ + +/* Function: memory_init + * Sammary: + * ��(All 0) */ +void memory_init(); + +/* ��ߗp��ɖ��߂̃X�g�A&��[�h */ + +/* Function: memory_store -> char + * Sammary: + * ��̎w��Ԓn�Ɏw�肵��W�X�^��l��i�[�� + * Return: + * ��Ɋi�[��ꂽ�l */ +void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec); +struct InstRec inst_memory_load(unsigned int mem_addr); + + +/* ��-��W�X�^�Ԃ̑�� */ + +/* Function: memory_store -> char + * Sammary: + * ��̎w��Ԓn�Ɏw�肵��W�X�^��l��i�[�� + * Return: + * ��Ɋi�[��ꂽ�l */ +char memory_store(unsigned int mem_addr, enum Register reg); + +/* Function: memory_store -> char + * Sammary: + * �w�肵��W�X�^�Ƀ��̎w��Ԓn��l��i�[�� + * Return: + * ��W�X�^�Ɋi�[��ꂽ�l */ +char memory_load(unsigned int mem_addr, enum Register reg); + + +#endif /* SYS_MEMORY_H_ */ diff --git a/software/DE2_115_ASM3_release/sys_prog.c b/software/DE2_115_ASM3_release/sys_prog.c new file mode 100644 index 0000000..6530e74 --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_prog.c @@ -0,0 +1,84 @@ +/* + * sys_prog.c + * + * Created on: 2016/12/15 + * Author: takayun + */ + +#include "sys_prog.h" +#include +#include "sys_debug.h" +#include "sys_register.h" +#include "sys_memory.h" +#include "hex_out.h" +#include "lcd_out.h" + +unsigned int inc_pc() { + if ((unsigned char)global_registers[Spc]+1 < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { + global_registers[Spc] = (unsigned char)global_registers[Spc] + 1; + } else { + global_registers[Spc] = 0; + } + return 0; +} +unsigned int add_pc(unsigned int cnt) { + int i; + for (i = 0; i < cnt; i++) inc_pc(); + return 0; +} +unsigned int set_pc(unsigned int cnt) { + global_registers[Spc]=cnt; + return 0; +} +unsigned int get_pc() { + if ((unsigned char)global_registers[Spc] < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { + return (unsigned int)((unsigned char)global_registers[Spc]); + } else { + return 0; + } +} + +enum RunMode run_proc(enum RunMode mode) { + volatile struct InstRec inst_rec; + + if (RUN_INIT == mode) { + lcd_caret_reset(); + lcd_print("Run...now"); + + global_registers[Spc] = 0; + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + + // �v��O��s��֑J�� + return RUN_PROC; + } + + if (RUN_PROC == mode) { + // ��߃t�F�b�` + inst_rec = inst_fetch(); + // ��߃f�R�[�h��s + inst_decode(inst_rec); + // pc�\�� + { + char buf[5]; + sprintf(buf, "%02x", (unsigned char)global_registers[Spc]); + print_block("pc", 2, HEX6_7); + print_block(buf, 2, HEX4_5); + } + + // �f�o�b�N�p + if ( global_registers[Ssw_run] ) delay10ms(100U); + + // �v��O��I�� + if (inst_rec.inst != INST_END) return RUN_PROC; + return RUN_TERM; + } + + if (RUN_TERM == mode) { + lcd_caret_reset(); + lcd_print("Run...Exit"); + return RUN_STOP; + } + + // Default + return RUN_STOP; +} diff --git a/software/DE2_115_ASM3_release/sys_prog.h b/software/DE2_115_ASM3_release/sys_prog.h new file mode 100644 index 0000000..b112e4c --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_prog.h @@ -0,0 +1,34 @@ +/* + * sys_prog.h + * + * Created on: 2016/12/15 + * Author: takayun + */ + +#ifndef SYS_PROG_H_ +#define SYS_PROG_H_ + +/************************************************** + * Defines + **************************************************/ + +// �v��O��s�� +enum RunMode { RUN_STOP, RUN_INIT, RUN_PROC, RUN_TERM }; + +/************************************************** + * Variables + **************************************************/ + +/************************************************** + * Functions + **************************************************/ + +// ��S��PC�̃J�E��g�A�b�v��s�� +unsigned int inc_pc(); +unsigned int add_pc(unsigned int); +unsigned int set_pc(unsigned int); +unsigned int get_pc(); + +enum RunMode run_proc(enum RunMode mode); + +#endif /* SYS_PROG_H_ */ diff --git a/software/DE2_115_ASM3_release/sys_register.c b/software/DE2_115_ASM3_release/sys_register.c new file mode 100644 index 0000000..26ba99b --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_register.c @@ -0,0 +1,17 @@ +/* + * sys_register.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "sys_register.h" + +char global_registers[REG_MAX_COUNT]; + +void registers_init() { + int i; + for (i = 0; i < REG_MAX_COUNT; i++) global_registers[i] = 0; +} + + + diff --git a/software/DE2_115_ASM3_release/sys_register.h b/software/DE2_115_ASM3_release/sys_register.h new file mode 100644 index 0000000..2603f26 --- /dev/null +++ b/software/DE2_115_ASM3_release/sys_register.h @@ -0,0 +1,54 @@ +/* + * sys_register.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYS_REGISTER_H_ +#define SYS_REGISTER_H_ + +/************************************************** + * Defines + **************************************************/ + +// ��W�X�^�̒�` +enum Register { + /* �ʏ�̃��W�X�^ */ + Szero, //�[��W�X�^ + Spc, //�v��O��J�E��^ + Ssp, //�X�^�b�N�|�C��^ + Sgp0, //�ėp��W�X�^0 + Sgp1, //�ėp��W�X�^1 + Sacc, //�A�L��[�^ + Sflg, //�t��O��W�X�^ + /* �X�C�b�`�ǂݏo��p��W�X�^ */ + Ssw_data, //�f�[�^(8bit) + Ssw_inst, //��(4bit) + Ssw_regi, //��W�X�^�ԍ�(4bit) + Ssw_memi, //��Ԓn(4bit) + Ssw_psel, //�v��O��Z��N�^(4bit) + Ssw_rw, //�ǂݏ��[�h(1bit) + Ssw_run, //��s��[�h(1bit) + /* 7�Z�O�p��W�X�^ */ + Sseg, + + /* �z��錾�p */ + REG_MAX_COUNT +}; + +/************************************************** + * Variables + **************************************************/ + +// ��W�X�^�p�̕ϐ� +extern char global_registers[REG_MAX_COUNT]; + +/************************************************** + * Functions + **************************************************/ + +void registers_init(); + + +#endif /* SYS_REGISTER_H_ */ diff --git a/software/DE2_115_ASM3_release_bsp/.cproject b/software/DE2_115_ASM3_release_bsp/.cproject new file mode 100644 index 0000000..180f8e0 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/.cproject @@ -0,0 +1,481 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/DE2_115_ASM3_release_bsp/.project b/software/DE2_115_ASM3_release_bsp/.project new file mode 100644 index 0000000..601fad7 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/.project @@ -0,0 +1,85 @@ + + + DE2_115_ASM3_release_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM3_release_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/alt_types.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/alt_types.h new file mode 100644 index 0000000..8eb438f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/alt_types.h @@ -0,0 +1,54 @@ +#ifndef __ALT_TYPES_H__ +#define __ALT_TYPES_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Don't declare these typedefs if this file is included by assembly source. + */ +#ifndef ALT_ASM_SRC +typedef signed char alt_8; +typedef unsigned char alt_u8; +typedef signed short alt_16; +typedef unsigned short alt_u16; +typedef signed long alt_32; +typedef unsigned long alt_u32; +typedef long long alt_64; +typedef unsigned long long alt_u64; +#endif + +#define ALT_INLINE __inline__ +#define ALT_ALWAYS_INLINE __attribute__ ((always_inline)) +#define ALT_WEAK __attribute__((weak)) + +#endif /* __ALT_TYPES_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/altera_nios2_qsys_irq.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/altera_nios2_qsys_irq.h new file mode 100644 index 0000000..910c91c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/altera_nios2_qsys_irq.h @@ -0,0 +1,80 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * Support for the Nios II internal interrupt controller. + */ + +#ifndef __ALT_NIOS2_QSYS_IRQ_H__ +#define __ALT_NIOS2_QSYS_IRQ_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The macro ALTERA_NIOS2_IRQ_INSTANCE is used by the alt_irq_init() + * function in the auto-generated file alt_sys_init.c to create an + * instance of this interrupt controller device driver state if this + * module contains an interrupt controller. + * Only one instance of a Nios II is allowed so this macro is just empty. + */ + +#define ALTERA_NIOS2_QSYS_IRQ_INSTANCE(name, state) + +/* + * altera_nios2_irq_init() is called by the auto-generated function + * alt_irq_init() once for the Nios II if it contains an interrupt controller. + * The altera_nios2_irq_init() routine is called using the + * ALTERA_NIOS2_IRQ_INIT macro given below. + * + * This function initializes the internal interrupt controller + * so is not called if the Nios II contains an external interrupt + * controller port (because the internal interrupt controller + * is removed if this port is present). + */ + +extern void altera_nios2_qsys_irq_init( void ); + +/* + * The macro ALTERA_NIOS2_IRQ_INIT is used by the alt_irq_init() routine + * in the auto-generated file alt_sys_init.c to initialize an instance + * of the interrupt controller device driver state. + */ + +#define ALTERA_NIOS2_QSYS_IRQ_INIT(name, state) altera_nios2_qsys_irq_init() + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_NIOS2_QSYS_IRQ_H__ */ + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/io.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/io.h new file mode 100644 index 0000000..867e87d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/io.h @@ -0,0 +1,81 @@ +#ifndef __IO_H__ +#define __IO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* IO Header file for Nios II Toolchain */ + +#include "alt_types.h" +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#ifndef SYSTEM_BUS_WIDTH +#error SYSTEM_BUS_WIDTH undefined +#endif + +/* Dynamic bus access functions */ + +#define __IO_CALC_ADDRESS_DYNAMIC(BASE, OFFSET) \ + ((void *)(((alt_u8*)BASE) + (OFFSET))) + +#define IORD_32DIRECT(BASE, OFFSET) \ + __builtin_ldwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_16DIRECT(BASE, OFFSET) \ + __builtin_ldhuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_8DIRECT(BASE, OFFSET) \ + __builtin_ldbuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) + +#define IOWR_32DIRECT(BASE, OFFSET, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_16DIRECT(BASE, OFFSET, DATA) \ + __builtin_sthio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_8DIRECT(BASE, OFFSET, DATA) \ + __builtin_stbio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) + +/* Native bus access functions */ + +#define __IO_CALC_ADDRESS_NATIVE(BASE, REGNUM) \ + ((void *)(((alt_u8*)BASE) + ((REGNUM) * (SYSTEM_BUS_WIDTH/8)))) + +#define IORD(BASE, REGNUM) \ + __builtin_ldwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM))) +#define IOWR(BASE, REGNUM, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)), (DATA)) + +#ifdef __cplusplus +} +#endif + +#endif /* __IO_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/nios2.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/nios2.h new file mode 100644 index 0000000..eec4e35 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/nios2.h @@ -0,0 +1,230 @@ +#ifndef __NIOS2_H__ +#define __NIOS2_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This header provides processor specific macros for accessing the Nios2 + * control registers. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros for accessing selected processor registers + */ + +#define NIOS2_READ_ET(et) \ + do { __asm ("mov %0, et" : "=r" (et) ); } while (0) + +#define NIOS2_WRITE_ET(et) \ + do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0) + +#define NIOS2_READ_SP(sp) \ + do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0) + +/* + * Macros for useful processor instructions + */ + +#define NIOS2_BREAK() \ + do { __asm volatile ("break"); } while (0) + +#define NIOS2_REPORT_STACK_OVERFLOW() \ + do { __asm volatile("break 3"); } while (0) + +/* + * Macros for accessing the control registers. + */ + +#define NIOS2_READ_STATUS(dest) \ + do { dest = __builtin_rdctl(0); } while (0) + +#define NIOS2_WRITE_STATUS(src) \ + do { __builtin_wrctl(0, src); } while (0) + +#define NIOS2_READ_ESTATUS(dest) \ + do { dest = __builtin_rdctl(1); } while (0) + +#define NIOS2_READ_BSTATUS(dest) \ + do { dest = __builtin_rdctl(2); } while (0) + +#define NIOS2_READ_IENABLE(dest) \ + do { dest = __builtin_rdctl(3); } while (0) + +#define NIOS2_WRITE_IENABLE(src) \ + do { __builtin_wrctl(3, src); } while (0) + +#define NIOS2_READ_IPENDING(dest) \ + do { dest = __builtin_rdctl(4); } while (0) + +#define NIOS2_READ_CPUID(dest) \ + do { dest = __builtin_rdctl(5); } while (0) + + +/* + * Macros for accessing extra exception registers. These + * are always enabled wit the MPU or MMU, and optionally + * with other advanced exception types/ + */ +#define NIOS2_READ_EXCEPTION(dest) \ + do { dest = __builtin_rdctl(7); } while (0) + +#define NIOS2_READ_BADADDR(dest) \ + do { dest = __builtin_rdctl(12); } while (0) + + +/* + * Macros for accessing control registers for MPU + * operation. These should not be used unless the + * MPU is enabled. + * + * The config register may be augmented for future + * enhancements. For now, only MPU support is provided. + */ +/* Config register */ +#define NIOS2_WRITE_CONFIG(src) \ + do { __builtin_wrctl(13, src); } while (0) + +#define NIOS2_READ_CONFIG(dest) \ + do { dest = __builtin_rdctl(13); } while (0) + +/* MPU Base Address Register */ +#define NIOS2_WRITE_MPUBASE(src) \ + do { __builtin_wrctl(14, src); } while (0) + +#define NIOS2_READ_MPUBASE(dest) \ + do { dest = __builtin_rdctl(14); } while (0) + +/* MPU Access Register */ +#define NIOS2_WRITE_MPUACC(src) \ + do { __builtin_wrctl(15, src); } while (0) + +#define NIOS2_READ_MPUACC(dest) \ + do { dest = __builtin_rdctl(15); } while (0) + + +/* + * Nios II control registers that are always present + */ +#define NIOS2_STATUS status +#define NIOS2_ESTATUS estatus +#define NIOS2_BSTATUS bstatus +#define NIOS2_IENABLE ienable +#define NIOS2_IPENDING ipending +#define NIOS2_CPUID cpuid + +/* + * STATUS, BSTATUS, ESTATUS, and SSTATUS fields. + * The presence of fields is a function of the Nios II configuration. + */ +#define NIOS2_STATUS_PIE_MSK (0x00000001) +#define NIOS2_STATUS_PIE_OFST (0) +#define NIOS2_STATUS_U_MSK (0x00000002) +#define NIOS2_STATUS_U_OFST (1) +#define NIOS2_STATUS_EH_MSK (0x00000004) +#define NIOS2_STATUS_EH_OFST (2) +#define NIOS2_STATUS_IH_MSK (0x00000008) +#define NIOS2_STATUS_IH_OFST (3) +#define NIOS2_STATUS_IL_MSK (0x000003f0) +#define NIOS2_STATUS_IL_OFST (4) +#define NIOS2_STATUS_CRS_MSK (0x0000fc00) +#define NIOS2_STATUS_CRS_OFST (10) +#define NIOS2_STATUS_PRS_MSK (0x003f0000) +#define NIOS2_STATUS_PRS_OFST (16) +#define NIOS2_STATUS_NMI_MSK (0x00400000) +#define NIOS2_STATUS_NMI_OFST (22) +#define NIOS2_STATUS_RSIE_MSK (0x00800000) +#define NIOS2_STATUS_RSIE_OFST (23) +#define NIOS2_STATUS_SRS_MSK (0x80000000) +#define NIOS2_STATUS_SRS_OFST (31) + +/* + * Bit masks & offsets available with extra exceptions support + */ + +/* Exception register */ +#define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c) +#define NIOS2_EXCEPTION_REG_CAUSE_OFST (2) + +/* + * Bit masks & offsets for MPU support + * + * All bit-masks are expressed relative to the position + * of the data with a register. To read data that is LSB- + * aligned, the register read data should be masked, then + * right-shifted by the designated "OFST" macro value. The + * opposite should be used for register writes when starting + * with LSB-aligned data. + */ + +/* Config register */ +#define NIOS2_CONFIG_REG_PE_MASK (0x00000001) +#define NIOS2_CONFIG_REG_PE_OFST (0) +#define NIOS2_CONFIG_REG_ANI_MASK (0x00000002) +#define NIOS2_CONFIG_REG_ANI_OFST (1) + +/* MPU Base Address Register */ +#define NIOS2_MPUBASE_D_MASK (0x00000001) +#define NIOS2_MPUBASE_D_OFST (0) +#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) +#define NIOS2_MPUBASE_INDEX_OFST (1) +#define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0) +#define NIOS2_MPUBASE_BASE_ADDR_OFST (6) + +/* MPU Access Register */ +#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) +#define NIOS2_MPUACC_LIMIT_OFST (6) +#define NIOS2_MPUACC_MASK_MASK (0xffffffc0) +#define NIOS2_MPUACC_MASK_OFST (6) +#define NIOS2_MPUACC_C_MASK (0x00000020) +#define NIOS2_MPUACC_C_OFST (5) +#define NIOS2_MPUACC_PERM_MASK (0x0000001c) +#define NIOS2_MPUACC_PERM_OFST (2) +#define NIOS2_MPUACC_RD_MASK (0x00000002) +#define NIOS2_MPUACC_RD_OFST (1) +#define NIOS2_MPUACC_WR_MASK (0x00000001) +#define NIOS2_MPUACC_WR_OFST (0) + +/* + * Number of available IRQs in internal interrupt controller. + */ +#define NIOS2_NIRQ 32 + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NIOS2_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_flag.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_flag.h new file mode 100644 index 0000000..86493c2 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_flag.h @@ -0,0 +1,98 @@ +#ifndef __ALT_FLAG_H__ +#define __ALT_FLAG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides macro definitions that can be used to create and use + * uc/OS-II style event flags. These macros can be used in both a uC/OS-II based + * environment, and a single threaded HAL based environment. + * + * The motivation for these macros is to allow code to be developed which is + * thread safe under uC/OS-II, but incurs no additional overhead when used in a + * single threaded HAL environment. + * + * In the case of a single threaded HAL environment, they compile to + * "do nothing" directives, which ensures they do not contribute to the final + * executable. + * + * The following macros are available: + * + * ALT_FLAG_GRP - Create a flag group instance. + * ALT_EXTERN_FLAG_GRP - Create a reference to an external flag group instance. + * ALT_STATIC_FLAG_GRP - Create a static flag group instance. + * ALT_FLAG_CREATE - Initialise a flag group. + * ALT_FLAG_PEND - Pend on a flag group. + * ALT_FLAG_POST - Set a flag condition. + + * + * Input arguments and return codes are all consistant with the equivalent + * uC/OS-II function. + * + * It's important to be careful in the use of the macros: ALT_FLAG_GRP, + * ALT_EXTERN_FLAG_GRP, and ALT_STATIC_FLAG_GRP. In these three cases the + * semi-colon is included in the macro definition; so, for example, you should + * use: + * + * ALT_FLAG_GRP(mygroup) + * + * not: + * + * ALT_FLAG_GRP(mygroup); + * + * The inclusion of the semi-colon has been necessary to ensure the macros can + * compile with no warnings when used in a single threaded HAL environment. + * + */ + +#include "priv/alt_no_error.h" + +#define ALT_FLAG_GRP(group) +#define ALT_EXTERN_FLAG_GRP(group) +#define ALT_STATIC_FLAG_GRP(group) + +#define ALT_FLAG_CREATE(group, flags) alt_no_error () +#define ALT_FLAG_PEND(group, flags, wait_type, timeout) alt_no_error () +#define ALT_FLAG_POST(group, flags, opt) alt_no_error () + +#ifndef ALT_SINGLE_THREADED +#define ALT_SINGLE_THREADED +#endif + +#endif /* __ALT_FLAG_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_hooks.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_hooks.h new file mode 100644 index 0000000..ba1100e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_hooks.h @@ -0,0 +1,61 @@ +#ifndef __ALT_HOOKS_H__ +#define __ALT_HOOKS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides "do-nothing" macro definitions for operating system + * hooks within the HAL. The O/S component can override these to provide it's + * own implementation. + */ + +#define ALT_OS_TIME_TICK() while(0) +#define ALT_OS_INIT() while(0) +#define ALT_OS_STOP() while(0) + +/* Call from assembly code */ +#define ALT_OS_INT_ENTER_ASM +#define ALT_OS_INT_EXIT_ASM + +/* Call from C code */ +#define ALT_OS_INT_ENTER() while(0) +#define ALT_OS_INT_EXIT() while(0) + + +#endif /* __ALT_HOOKS_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_sem.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_sem.h new file mode 100644 index 0000000..ed0f4a8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_sem.h @@ -0,0 +1,96 @@ +#ifndef __ALT_SEM_H__ +#define __ALT_SEM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides macro definitions that can be used to create and use + * semaphores. These macros can be used in both a uC/OS-II based environment, + * and a single threaded HAL based environment. + * + * The motivation for these macros is to allow code to be developed which is + * thread safe under uC/OS-II, but incurs no additional overhead when used in a + * single threaded HAL environment. + * + * In the case of a single threaded HAL environment, they compile to + * "do nothing" directives, which ensures they do not contribute to the final + * executable. + * + * The following macros are available: + * + * ALT_SEM - Create a semaphore instance. + * ALT_EXTERN_SEM - Create a reference to an external semaphore instance. + * ALT_STATIC_SEM - Create a static semaphore instance. + * ALT_SEM_CREATE - Initialise a semaphore. + * ALT_SEM_PEND - Pend on a semaphore. + * ALT_SEM_POST - Increment a semaphore. + * + * Input arguments and return codes are all consistant with the equivalent + * uC/OS-II function. + * + * It's important to be careful in the use of the macros: ALT_SEM, + * ALT_EXTERN_SEM, and ALT_STATIC_SEM. In these three cases the semi-colon is + * included in the macro definition; so, for example, you should use: + * + * ALT_SEM(mysem) + * + * not: + * + * ALT_SEM(mysem); + * + * The inclusion of the semi-colon has been necessary to ensure the macros can + * compile with no warnings when used in a single threaded HAL environment. + * + */ + +#include "priv/alt_no_error.h" + +#define ALT_SEM(sem) +#define ALT_EXTERN_SEM(sem) +#define ALT_STATIC_SEM(sem) + +#define ALT_SEM_CREATE(sem, value) alt_no_error () +#define ALT_SEM_PEND(sem, timeout) alt_no_error () +#define ALT_SEM_POST(sem) alt_no_error () + +#ifndef ALT_SINGLE_THREADED +#define ALT_SINGLE_THREADED +#endif + +#endif /* __ALT_SEM_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_syscall.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_syscall.h new file mode 100644 index 0000000..2b1165a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/os/alt_syscall.h @@ -0,0 +1,75 @@ +#ifndef __ALT_SYSCALL_H__ +#define __ALT_SYSCALL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The macros defined in this file are used to provide the function names used + * for the HAL 'UNIX style' interface, e.g. read(), write() etc. + * + * Operating systems which are ported to the HAL can provide their own + * version of this file, which will be used in preference. This allows + * the operating system to provide it's own implementation of the top level + * system calls, while retaining the HAL functions under a different name, + * for example, alt_read(), alt_write() etc. + */ + +#define ALT_CLOSE close +#define ALT_ENVIRON environ +#define ALT_EXECVE execve +#define ALT_EXIT _exit +#define ALT_FCNTL fcntl +#define ALT_FORK fork +#define ALT_FSTAT fstat +#define ALT_GETPID getpid +#define ALT_GETTIMEOFDAY gettimeofday +#define ALT_IOCTL ioctl +#define ALT_ISATTY isatty +#define ALT_KILL kill +#define ALT_LINK link +#define ALT_LSEEK lseek +#define ALT_OPEN open +#define ALT_READ read +#define ALT_RENAME _rename +#define ALT_SBRK sbrk +#define ALT_SETTIMEOFDAY settimeofday +#define ALT_STAT stat +#define ALT_UNLINK unlink +#define ALT_USLEEP usleep +#define ALT_WAIT wait +#define ALT_WRITE write +#define ALT_TIMES times + +/* + * + */ + +#endif /* __ALT_SYSCALL_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_alarm.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_alarm.h new file mode 100644 index 0000000..ae687bb --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_alarm.h @@ -0,0 +1,101 @@ +#ifndef __ALT_PRIV_ALARM_H__ +#define __ALT_PRIV_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required by the public + * interface alt_alarm.h. These variables and structures are not guaranteed to + * exist in future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm_s" is a structure type used to maintain lists of alarm callback + * functions. + */ + +struct alt_alarm_s +{ + alt_llist llist; /* linked list */ + alt_u32 time; /* time in system ticks of the callback */ + alt_u32 (*callback) (void* context); /* callback function. The return + * value is the period for the next callback; where + * zero indicates that the alarm should be removed + * from the list. + */ + alt_u8 rollover; /* set when desired alarm time + current time causes + overflow, to prevent premature alarm */ + void* context; /* Argument for the callback */ +}; + +/* + * "_alt_tick_rate" is a global variable used to store the system clock rate + * in ticks per second. This is initialised to zero, which coresponds to there + * being no system clock available. + * + * It is then set to it's final value by the system clock driver through a call + * to alt_sysclk_init(). + */ + +extern alt_u32 _alt_tick_rate; + +/* + * "_alt_nticks" is a global variable which records the elapsed number of + * system clock ticks since the last call to settimeofday() or since reset if + * settimeofday() has not been called. + */ + +extern volatile alt_u32 _alt_nticks; + +/* The list of registered alarms. */ + +extern alt_llist alt_alarm_list; + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_PRIV_ALARM_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_busy_sleep.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_busy_sleep.h new file mode 100644 index 0000000..a165e93 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_busy_sleep.h @@ -0,0 +1,35 @@ +#ifndef __ALT_BUSY_SLEEP_H +#define __ALT_BUSY_SLEEP_H + +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * The function alt_busy_sleep provides a busy loop implementation of usleep. + * This is used to provide usleep for the standalone HAL, or when the timer is + * unavailable in uC/OS-II. + */ + +extern unsigned int alt_busy_sleep (unsigned int us); + +#endif /* __ALT_BUSY_SLEEP_H */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_dev_llist.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_dev_llist.h new file mode 100644 index 0000000..0ab7a28 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_dev_llist.h @@ -0,0 +1,77 @@ +#ifndef __ALT_DEV_LLIST_H__ +#define __ALT_DEV_LLIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_llist.h" +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The alt_dev_llist is an internal structure used to form a common base + * class for all device types. The use of this structure allows common code + * to be used to manipulate the various device lists. + */ + +typedef struct { + alt_llist llist; + const char* name; +} alt_dev_llist; + +/* + * + */ + +extern int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_LLIST_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_exception_handler_registry.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_exception_handler_registry.h new file mode 100644 index 0000000..4502ea7 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_exception_handler_registry.h @@ -0,0 +1,39 @@ +#ifndef __ALT_EXCEPTION_HANDLER_REGISTRY_H__ +#define __ALT_EXCEPTION_HANDLER_REGISTRY_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "sys/alt_exceptions.h" + +/* Function pointer to exception callback routine */ +extern alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32); + +#endif /* __ALT_EXCEPTION_HANDLER_REGISTRY_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_file.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_file.h new file mode 100644 index 0000000..94007a6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_file.h @@ -0,0 +1,179 @@ +#ifndef __ALT_FILE_H__ +#define __ALT_FILE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "sys/alt_llist.h" +#include "os/alt_sem.h" + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_find_dev() is used to search the device list "list" to + * locate a device named "name". If a match is found, then a pointer to the + * device is returned, otherwise NULL is returned. + */ + +extern alt_dev* alt_find_dev (const char* name, alt_llist* list); + +/* + * alt_find_file() is used to search the list of registered file systems to + * find the filesystem that the file named "name" belongs to. If a match is + * found, then a pointer to the filesystems alt_dev structure is returned, + * otherwise NULL is returned. + * + * Note that a match does not indicate that the file exists, only that a + * filesystem exists that is registered for a partition that could contain + * the file. The filesystems open() function would need to be called in order + * to determine if the file exists. + */ + +extern alt_dev* alt_find_file (const char* name); + +/* + * alt_get_fd() is used to allocate a file descriptor for the device or + * filesystem "dev". A negative return value indicates an error, otherwise the + * return value is the index of the file descriptor within the file descriptor + * pool. + */ + +extern int alt_get_fd (alt_dev* dev); + +/* + * alt_release_fd() is called to free the file descriptor with index "fd". + */ + +extern void alt_release_fd (int fd); + +/* + * alt_fd_lock() is called by ioctl() to mark the file descriptor "fd" as + * being open for exclusive access. Subsequent calls to open() for the device + * associated with "fd" will fail. A device is unlocked by either calling + * close() for "fd", or by an alternate call to ioctl() (see ioctl.c for + * details). + */ + +extern int alt_fd_lock (alt_fd* fd); + +/* + * alt_fd_unlock() is called by ioctl() to unlock a descriptor previously + * locked by a call to alt_fd_lock(). + */ + +extern int alt_fd_unlock (alt_fd* fd); + +/* + * "alt_fd_list" is the pool of file descriptors. + */ + +extern alt_fd alt_fd_list[]; + +/* + * flags used by alt_fd. + * + * ALT_FD_EXCL is used to mark a file descriptor as locked for exclusive + * access, i.e. further calls to open() for the associated device should + * fail. + * + * ALT_FD_DEV marks a dile descriptor as belonging to a device as oposed to a + * filesystem. + */ + +#define ALT_FD_EXCL 0x80000000 +#define ALT_FD_DEV 0x40000000 + +#define ALT_FD_FLAGS_MASK (ALT_FD_EXCL | ALT_FD_DEV) + +/* + * "alt_dev_list" is the head of the linked list of registered devices. + */ + +extern alt_llist alt_dev_list; + +/* + * "alt_fs_list" is the head of the linked list of registered filesystems. + */ + +extern alt_llist alt_fs_list; + +/* + * "alt_fd_list_lock" is a semaphore used to ensure that access to the pool + * of file descriptors is thread safe. + */ + +ALT_EXTERN_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is a 'high water mark'. It indicates the highest file + * descriptor allocated. Use of this can save searching the entire pool + * for active file descriptors, which helps avoid contention on access + * to the file descriptor pool. + */ + +extern alt_32 alt_max_fd; + +/* + * alt_io_redirect() is called at startup to redirect stdout, stdin, and + * stderr to the devices named in the input arguments. By default these streams + * are directed at /dev/null, and are then redirected using this function once + * all of the devices have been registered within the system. + */ + +extern void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FILE_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_iic_isr_register.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_iic_isr_register.h new file mode 100644 index 0000000..6c53c86 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_iic_isr_register.h @@ -0,0 +1,39 @@ +#ifndef __ALT_IIC_ISR_REGISTER_H_ +#define __ALT_IIC_ISR_REGISTER_H_ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "sys/alt_irq.h" + +extern int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags); + +#endif /* __ALT_IIC_ISR_REGISTER_H_ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_irq_table.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_irq_table.h new file mode 100644 index 0000000..5b4a787 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_irq_table.h @@ -0,0 +1,59 @@ +#ifndef __ALT_IRQ_TABLE_H__ +#define __ALT_IRQ_TABLE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definition of a table describing each interrupt handler. The index into + * the array is the interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + * + * The table is physically created in alt_irq_handler.c + */ +extern struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +#endif diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_legacy_irq.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_legacy_irq.h new file mode 100644 index 0000000..0e19af2 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_legacy_irq.h @@ -0,0 +1,158 @@ +#ifndef __ALT_LEGACY_IRQ_H__ +#define __ALT_LEGACY_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides prototypes and inline implementations of certain routines + * used by the legacy interrupt API. Do not include this in your driver or + * application source files, use "sys/alt_irq.h" instead to access the proper + * public API. + */ + +#include +#include "system.h" + +#ifndef NIOS2_EIC_PRESENT + +#include "nios2.h" +#include "alt_types.h" + +#include "sys/alt_irq.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_irq_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler); + +/* + * alt_irq_disable() disables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active &= ~(1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +/* + * alt_irq_enable() enables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active |= (1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +#ifndef ALT_EXCEPTION_STACK +/* + * alt_irq_initerruptable() should only be called from within an ISR. It is used + * to allow higer priority interrupts to interrupt the current ISR. The input + * argument, "priority", is the priority, i.e. interrupt number of the current + * interrupt. + * + * If this function is called, then the ISR is required to make a call to + * alt_irq_non_interruptible() before returning. The input argument to + * alt_irq_non_interruptible() is the return value from alt_irq_interruptible(). + * + * Care should be taken when using this pair of functions, since they increasing + * the system overhead associated with interrupt handling. + * + * If you are using an exception stack then nested interrupts won't work, so + * these functions are not available in that case. + */ +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_interruptible (alt_u32 priority) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + alt_u32 old_priority; + + old_priority = alt_priority_mask; + alt_priority_mask = (1 << priority) - 1; + + NIOS2_WRITE_IENABLE (alt_irq_active & alt_priority_mask); + + NIOS2_WRITE_STATUS (1); + + return old_priority; +} + +/* + * See Comments above for alt_irq_interruptible() for an explanation of the use of this + * function. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE alt_irq_non_interruptible (alt_u32 mask) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + NIOS2_WRITE_STATUS (0); + + alt_priority_mask = mask; + + NIOS2_WRITE_IENABLE (mask & alt_irq_active); +} +#endif /* ALT_EXCEPTION_STACK */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* NIOS2_EIC_PRESENT */ + +#endif /* __ALT_LEGACY_IRQ_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_no_error.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_no_error.h new file mode 100644 index 0000000..06a036c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/alt_no_error.h @@ -0,0 +1,77 @@ +#ifndef __ALT_NO_ERROR_H__ +#define __ALT_NO_ERROR_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_no_error() is a dummy function used by alt_sem.h and alt_flag.h. It + * substitutes for functions that have a return code by creating a function + * that always returns zero. + * + * This may seem a little obscure, but what happens is that the compiler can + * then optomise away the call to this function, and any code written which + * handles the error path (i.e. non zero return values). + * + * This allows code to be written which correctly use the uC/OS-II semaphore + * and flag utilities, without the use of those utilities impacting on + * excutables built for a single threaded HAL environment. + * + * This function is considered to be part of the internal implementation of + * the HAL, and should not be called directly by application code or device + * drivers. It is not guaranteed to be preserved in future versions of the + * HAL. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void) +{ + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_NO_ERROR_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/nios2_gmon_data.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/nios2_gmon_data.h new file mode 100644 index 0000000..4bc058d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/priv/nios2_gmon_data.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#ifndef NIOS2_GMON_DATA_H +#define NIOS2_GMON_DATA_H + +#define GMON_DATA_SIG 0 +#define GMON_DATA_WORDS 1 +#define GMON_DATA_PROFILE_DATA 2 +#define GMON_DATA_PROFILE_LOWPC 3 +#define GMON_DATA_PROFILE_HIGHPC 4 +#define GMON_DATA_PROFILE_BUCKET 5 +#define GMON_DATA_PROFILE_RATE 6 +#define GMON_DATA_MCOUNT_START 7 +#define GMON_DATA_MCOUNT_LIMIT 8 + +#define GMON_DATA_SIZE 9 + +extern unsigned int alt_gmon_data[GMON_DATA_SIZE]; + +#endif diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_alarm.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_alarm.h new file mode 100644 index 0000000..9093080 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_alarm.h @@ -0,0 +1,126 @@ +#ifndef __ALT_ALARM_H__ +#define __ALT_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_llist.h" +#include "alt_types.h" + +#include "priv/alt_alarm.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm" is a structure type used by applications to register an alarm + * callback function. An instance of this type must be passed as an input + * argument to alt_alarm_start(). The user is not responsible for initialising + * the contents of the instance. This is done by alt_alarm_start(). + */ + +typedef struct alt_alarm_s alt_alarm; + +/* + * alt_alarm_start() can be called by an application/driver in order to register + * a function for periodic callback at the system clock frequency. Be aware that + * this callback is likely to occur in interrupt context. + */ + +extern int alt_alarm_start (alt_alarm* the_alarm, + alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context); + +/* + * alt_alarm_stop() is used to unregister a callback. Alternatively the callback + * can return zero to unregister. + */ + +extern void alt_alarm_stop (alt_alarm* the_alarm); + +/* + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; +} + +/* + * alt_sysclk_init() is intended to be only used by the system clock driver + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + { + _alt_tick_rate = nticks; + return 0; + } + else + { + return -1; + } +} + +/* + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; +} + +/* + * alt_tick() should only be called by the system clock driver. This is used + * to notify the system that the system timer period has expired. + */ + +extern void alt_tick (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_ALARM_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_cache.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_cache.h new file mode 100644 index 0000000..44d976c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_cache.h @@ -0,0 +1,117 @@ +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003, 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "alt_types.h" + +/* + * alt_cache.h defines the processor specific functions for manipulating the + * cache. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +extern void alt_icache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are written back to memory. + */ + +extern void alt_dcache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are NOT written back to memory. + */ + +extern void alt_dcache_flush_no_writeback (void* start, alt_u32 len); + +/* + * Flush the entire instruction cache. + */ + +extern void alt_icache_flush_all (void); + +/* + * Flush the entire data cache. + */ + +extern void alt_dcache_flush_all (void); + +/* + * Allocate a block of uncached memory. + */ + +extern volatile void* alt_uncached_malloc (size_t size); + +/* + * Free a block of uncached memory. + */ + +extern void alt_uncached_free (volatile void* ptr); + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +extern volatile void* alt_remap_uncached (void* ptr, alt_u32 len); + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +extern void* alt_remap_cached (volatile void* ptr, alt_u32 len); + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_debug.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_debug.h new file mode 100644 index 0000000..af509d8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_debug.h @@ -0,0 +1,45 @@ +#ifndef __ALT_DEBUG_H__ +#define __ALT_DEBUG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The ALT_DEVUG_ASSERT macro can be used to generate a debugger break + * from within software. The break is generated if "condition" evaluates to + * false. + */ + +#define ALT_DEBUG_ASSERT(condition) if (!condition) \ +{ \ + __asm__ volatile ("break"); \ +} + +#endif /* __ALT_DEBUG_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dev.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dev.h new file mode 100644 index 0000000..d96327e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dev.h @@ -0,0 +1,115 @@ +#ifndef __ALT_DEV_H__ +#define __ALT_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "system.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The value ALT_IRQ_NOT_CONNECTED is used to represent an unconnected + * interrupt line. It cannot evaluate to a valid interrupt number. + */ + +#define ALT_IRQ_NOT_CONNECTED (-1) + +typedef struct alt_dev_s alt_dev; + +struct stat; + +/* + * The file descriptor structure definition. + */ + +typedef struct alt_fd_s +{ + alt_dev* dev; + alt_u8* priv; + int fd_flags; +} alt_fd; + +/* + * The device structure definition. + */ + +struct alt_dev_s { + alt_llist llist; /* for internal use */ + const char* name; + int (*open) (alt_fd* fd, const char* name, int flags, int mode); + int (*close) (alt_fd* fd); + int (*read) (alt_fd* fd, char* ptr, int len); + int (*write) (alt_fd* fd, const char* ptr, int len); + int (*lseek) (alt_fd* fd, int ptr, int dir); + int (*fstat) (alt_fd* fd, struct stat* buf); + int (*ioctl) (alt_fd* fd, int req, void* arg); +}; + +/* + * Functions used to register device for access through the C standard + * library. + * + * The only difference between alt_dev_reg() and alt_fs_reg() is the + * interpretation that open() places on the device name. In the case of + * alt_dev_reg the device is assumed to be a particular character device, + * and so there must be an exact match in the name for open to succeed. + * In the case of alt_fs_reg() the name of the device is treated as the + * mount point for a directory, and so any call to open() where the name + * is the root of the device filename will succeed. + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dma.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dma.h new file mode 100644 index 0000000..88dcda0 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dma.h @@ -0,0 +1,226 @@ +#ifndef __ALT_DMA_H__ +#define __ALT_DMA_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dma_dev.h" +#include "alt_types.h" + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the application side interface for accessing DMA + * resources. See alt_dma_dev.h for the dma device driver interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * The application can supply data for transmit using an "alt_dma_txchan" + * descriptor. Alternatively an "alt_dma_rxchan" descriptor can be used to + * receive data. + */ + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_txchan alt_dma_txchan_open (const char* name); + +/* + * alt_dma_txchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA transmit channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_txchan_close (alt_dma_txchan dma) +{ + return 0; +} + +/* + * alt_dma_txchan_send() posts a transmit request to a DMA transmit channel. + * The input arguments are: + * + * dma: the channel to use. + * from: a pointer to the start of the data to send. + * length: the length of the data to send in bytes. + * done: callback function that will be called once the data has been sent. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_txchan_send (alt_dma_txchan dma, + const void* from, + alt_u32 length, + alt_txchan_done* done, + void* handle) +{ + return dma ? dma->dma_send (dma, + from, + length, + done, + handle) : -ENODEV; +} + +/* + * alt_dma_txchan_space() returns the number of tranmit requests that can be + * posted to the specified DMA transmit channel. + * + * A negative value indicates that the value could not be determined. + */ + +static ALT_INLINE int alt_dma_txchan_space (alt_dma_txchan dma) +{ + return dma ? dma->space (dma) : -ENODEV; +} + +/* + * alt_dma_txchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA transmit channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_txchan_ioctl (alt_dma_txchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_open() is used to obtain an "alt_dma_rxchan" descriptor for + * a DMA receive channel. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_rxchan alt_dma_rxchan_open (const char* dev); + +/* + * alt_dma_rxchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA receive channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_rxchan_close (alt_dma_rxchan dma) +{ + return 0; +} + +/* + * + */ + +/* + * alt_dma_rxchan_prepare() posts a receive request to a DMA receive channel. + * + * The input arguments are: + * + * dma: the channel to use. + * data: a pointer to the location that data is to be received to. + * len: the maximum length of the data to receive. + * done: callback function that will be called once the data has been + * received. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_rxchan_prepare (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle) +{ + return dma ? dma->prepare (dma, data, len, done, handle) : -ENODEV; +} + +/* + * alt_dma_rxchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA receive channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_rxchan_ioctl (alt_dma_rxchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_depth() returns the depth of the receive FIFO used to store + * receive requests. + */ + +static ALT_INLINE alt_u32 alt_dma_rxchan_depth(alt_dma_rxchan dma) +{ + return dma->depth; +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dma_dev.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dma_dev.h new file mode 100644 index 0000000..65063bd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_dma_dev.h @@ -0,0 +1,200 @@ +#ifndef __ALT_DMA_DEV_H__ +#define __ALT_DMA_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the device driver interface for accessing DMA + * resources. See alt_dma.h for the DMA application side interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * An "alt_dma_txchan_dev" is used to describe the device associated with a + * DMA transmit channel. An "alt_dma_rxchan_dev" is used to describe the + * device associated with a DMA receive channel. + */ + +/* + * List of generic ioctl requests that may be supported by a DMA device. + * + * ALT_DMA_RX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the receiver is under software control. + * The other side reads continously from a single + * location. The address to read is the argument to + * this request. + * ALT_DMA_RX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_TX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the transmitter is under software control. + * The other side writes continously to a single + * location. The address to write to is the argument to + * this request. + * ALT_DMA_TX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_SET_MODE_8: Transfer data in units of 8 bits. + * ALT_DMA_SET_MODE_16: Transfer data in units of 16 bits. + * ALT_DMA_SET_MODE_32: Transfer data in units of 32 bits. + * ALT_DMA_SET_MODE_64: Transfer data in units of 64 bits. + * ALT_DMA_SET_MODE_128: Transfer data in units of 128 bits. + * ALT_DMA_GET_MODE: Get the current transfer mode. + * + * The use of the macros: ALT_DMA_TX_STREAM_ON, ALT_DMA_TX_STREAM_OFF + * ALT_DMA_RX_STREAM_OFF and ALT_DMA_RX_STREAM_ON are depreciated. You should + * instead use the macros: ALT_DMA_RX_ONLY_ON, ALT_DMA_RX_ONLY_OFF, + * ALT_DMA_TX_ONLY_ON and ALT_DMA_TX_ONLY_OFF. + */ + +#define ALT_DMA_TX_STREAM_ON (0x1) +#define ALT_DMA_TX_STREAM_OFF (0x2) +#define ALT_DMA_RX_STREAM_ON (0x3) +#define ALT_DMA_RX_STREAM_OFF (0x4) +#define ALT_DMA_SET_MODE_8 (0x5) +#define ALT_DMA_SET_MODE_16 (0x6) +#define ALT_DMA_SET_MODE_32 (0x7) +#define ALT_DMA_SET_MODE_64 (0x8) +#define ALT_DMA_SET_MODE_128 (0x9) +#define ALT_DMA_GET_MODE (0xa) + +#define ALT_DMA_RX_ONLY_ON ALT_DMA_TX_STREAM_ON +#define ALT_DMA_RX_ONLY_OFF ALT_DMA_TX_STREAM_OFF +#define ALT_DMA_TX_ONLY_ON ALT_DMA_RX_STREAM_ON +#define ALT_DMA_TX_ONLY_OFF ALT_DMA_RX_STREAM_OFF + +/* + * + */ + +typedef struct alt_dma_txchan_dev_s alt_dma_txchan_dev; +typedef struct alt_dma_rxchan_dev_s alt_dma_rxchan_dev; + +typedef alt_dma_txchan_dev* alt_dma_txchan; +typedef alt_dma_rxchan_dev* alt_dma_rxchan; + +typedef void (alt_txchan_done)(void* handle); +typedef void (alt_rxchan_done)(void* handle, void* data); + +/* + * devices that provide a DMA transmit channel are required to provide an + * instance of the "alt_dma_txchan_dev" structure. + */ + +struct alt_dma_txchan_dev_s { + alt_llist llist; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + int (*space) (alt_dma_txchan dma); /* returns the maximum number of + * transmit requests that can be posted + */ + int (*dma_send) (alt_dma_txchan dma, + const void* from, + alt_u32 len, + alt_txchan_done* done, + void* handle); /* post a transmit request */ + int (*ioctl) (alt_dma_txchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * devices that provide a DMA receive channel are required to provide an + * instance of the "alt_dma_rxchan_dev" structure. + */ + +struct alt_dma_rxchan_dev_s { + alt_llist list; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + alt_u32 depth; /* maximum number of receive requests that + * can be posted. + */ + int (*prepare) (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle); /* post a receive request */ + int (*ioctl) (alt_dma_rxchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * Register a DMA transmit channel with the system. + */ + +static ALT_INLINE int alt_dma_txchan_reg (alt_dma_txchan_dev* dev) +{ + extern alt_llist alt_dma_txchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_txchan_list); +} + +/* + * Register a DMA receive channel with the system. + */ + +static ALT_INLINE int alt_dma_rxchan_reg (alt_dma_rxchan_dev* dev) +{ + extern alt_llist alt_dma_rxchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_rxchan_list); +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_DEV_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_driver.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_driver.h new file mode 100644 index 0000000..ca7aea1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_driver.h @@ -0,0 +1,168 @@ +#ifndef __ALT_DRIVER_H__ +#define __ALT_DRIVER_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Macros used to access a driver without HAL file descriptors. + */ + +/* + * ALT_MODULE_CLASS + * + * This macro returns the module class name for the specified module instance. + * It uses information in the system.h file. + * Neither the instance name or class name are quoted (so that they can + * be used with other pre-processor macros). + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_MODULE_CLASS(uart1) returns altera_avalon_uart. + */ + +#define ALT_MODULE_CLASS(instance) ALT_MODULE_CLASS_ ## instance + + +/* + * ALT_DRIVER_FUNC_NAME + * + * --> instance Instance name. + * --> func Function name. + * + * This macro returns the device driver function name of the specified + * module instance for the specified function name. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_FUNC_NAME(uart1, write) returns + * altera_avalon_uart_write. + */ + +#define ALT_DRIVER_FUNC_NAME(instance, func) \ + ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func) +#define ALT_DRIVER_FUNC_NAME1(module_class, func) \ + ALT_DRIVER_FUNC_NAME2(module_class, func) +#define ALT_DRIVER_FUNC_NAME2(module_class, func) \ + module_class ## _ ## func + +/* + * ALT_DRIVER_STATE_STRUCT + * + * --> instance Instance name. + * + * This macro returns the device driver state type name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE_STRUCT(uart1) returns: + * struct altera_avalon_uart_state_s + * + * Note that the ALT_DRIVER_FUNC_NAME macro is used even though "state" isn't + * really a function but it does match the required naming convention. + */ +#define ALT_DRIVER_STATE_STRUCT(instance) \ + struct ALT_DRIVER_FUNC_NAME(instance, state_s) + +/* + * ALT_DRIVER_STATE + * + * --> instance Instance name. + * + * This macro returns the device driver state name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE(uart1) returns uart1. + */ +#define ALT_DRIVER_STATE(instance) instance + +/* + * ALT_DRIVER_WRITE + * + * --> instance Instance name. + * --> buffer Write buffer. + * --> len Length of write buffer data. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "write" function of the specified driver instance. + */ + +#define ALT_DRIVER_WRITE_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, write) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_WRITE(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, write)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + + +/* + * ALT_DRIVER_READ + * + * --> instance Instance name. + * <-- buffer Read buffer. + * --> len Length of read buffer. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "read" function of the specified driver instance. + */ + +#define ALT_DRIVER_READ_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, read) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_READ(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, read)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + +/* + * ALT_DRIVER_IOCTL + * + * --> instance Instance name. + * --> req ioctl request (e.g. TIOCSTIMEOUT) + * --> arg Optional argument (void*) + * + * This macro calls the "ioctl" function of the specified driver instance + */ + +#define ALT_DRIVER_IOCTL_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, ioctl) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, int, void*); + +#define ALT_DRIVER_IOCTL(instance, req, arg) \ + ALT_DRIVER_FUNC_NAME(instance, ioctl)(&ALT_DRIVER_STATE(instance), req, arg) + +#endif /* __ALT_DRIVER_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_errno.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_errno.h new file mode 100644 index 0000000..23e3096 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_errno.h @@ -0,0 +1,87 @@ +#ifndef __ALT_ERRNO_H__ +#define __ALT_ERRNO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * errno is defined in so that it uses the thread local version + * stored in the location pointed to by "_impure_ptr". This means that the + * accesses to errno within the HAL library can cause the entirety of + * of the structure pointed to by "_impure_ptr" to be added to the + * users application. This can be undesirable in very small footprint systems. + * + * To avoid this happening, the HAL uses the macro ALT_ERRNO, defined below, + * to access errno, rather than accessing it directly. This macro will only + * use the thread local version if some other code has already caused it to be + * included into the system, otherwise it will use the global errno value. + * + * This causes a slight increases in code size where errno is accessed, but + * can lead to significant overall benefits in very small systems. The + * increase is inconsequential when compared to the size of the structure + * pointed to by _impure_ptr. + * + * Note that this macro accesses __errno() using an externally declared + * function pointer (alt_errno). This is done so that the function call uses the + * subroutine call instruction via a register rather than an immediate address. + * This is important in the case that the code has been linked for a high + * address, but __errno() is not being used. In this case the weak linkage + * would have resulted in the instruction: "call 0" which would fail to link. + */ + +extern int* (*alt_errno) (void); + +/* Must define this so that values such as EBADFD are defined in errno.h. */ +#define __LINUX_ERRNO_EXTENSIONS__ + +#include + +#include "alt_types.h" + +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + return ((alt_errno) ? alt_errno() : &errno); +} + +#define ALT_ERRNO *alt_get_errno() + +#endif /* __ALT_ERRNO_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_exceptions.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_exceptions.h new file mode 100644 index 0000000..b6b82e2 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_exceptions.h @@ -0,0 +1,127 @@ +#ifndef __ALT_EXCEPTIONS_H__ +#define __ALT_EXCEPTIONS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This file defines instruction-generated exception handling and registry + * API, exception type enumeration, and handler return value enumeration for + * Nios II. + */ + +/* + * The following enumeration describes the value in the CPU EXCEPTION + * register CAUSE bit field. Not all exception types will cause the + * processor to go to the exception vector; these are provided for + * reference. + */ +enum alt_exception_cause_e { + /* Exeption causes that will cause jump to exception vector */ + NIOS2_EXCEPTION_INTERRUPT = 2, + NIOS2_EXCEPTION_TRAP_INST = 3, + NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4, + NIOS2_EXCEPTION_ILLEGAL_INST = 5, + NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6, + NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7, + NIOS2_EXCEPTION_DIVISION_ERROR = 8, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11, + NIOS2_EXCEPTION_TLB_MISS = 12, + NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13, + NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16, + + /* Exception causes that will NOT cause a jump to exception vector */ + NIOS2_EXCEPTION_RESET = 0, + NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1, + NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14, + NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15, + NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17, + /* + * This value is passed to an exception handler's cause argument if + * "extra exceptions" information (EXECPTION) register is not + * present in the processor hardware configuration. + */ + NIOS2_EXCEPTION_CAUSE_NOT_PRESENT = -1 +}; +typedef enum alt_exception_cause_e alt_exception_cause; + +/* + * These define valid return values for a user-defined instruction-generated + * exception handler. The handler should return one of these to indicate + * whether to re-issue the instruction that triggered the exception, or to + * skip it. + */ +enum alt_exception_result_e { + NIOS2_EXCEPTION_RETURN_REISSUE_INST = 0, + NIOS2_EXCEPTION_RETURN_SKIP_INST = 1 +}; +typedef enum alt_exception_result_e alt_exception_result; + +/* + * alt_instruction_exception_register() can be used to register an exception + * handler for instruction-generated exceptions that are not handled by the + * built-in exception handler (i.e. for interrupts). + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ); +#endif /*ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * alt_exception_cause_generated_bad_addr() indicates whether a particular + * exception cause value was from an exception-type that generated a valid + * address in the BADADDR register. The contents of BADADDR is passed to + * a user-registered exception handler in all cases, whether valid or not. + * This routine should be called to validate the bad_addr argument to + * your exception handler. + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_EXCEPTIONS_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash.h new file mode 100644 index 0000000..7e903a8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash.h @@ -0,0 +1,166 @@ +#ifndef __ALT_FLASH_H__ +#define __ALT_FLASH_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.h - User interface for flash code * +* * +* Use this interface to avoid being exposed to the internals of the device * +* driver architecture. If you chose to use the flash driver internal * +* structures we don't guarantee not to change them * +* * +* Author PRR * +* * +******************************************************************************/ + + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "alt_types.h" +#include "alt_flash_types.h" +#include "alt_flash_dev.h" +#include "sys/alt_cache.h" + +alt_flash_fd* alt_flash_open_dev(const char* name); +void alt_flash_close_dev(alt_flash_fd* fd ); + +/* + * alt_write_flash + * + * Program a buffer into flash. + * + * This routine erases all the affected erase blocks (if necessary) + * and then programs the data. However it does not read the data out first + * and preserve and none overwritten data, because this would require very + * large buffers on the target. If you need + * that functionality use the functions below. + */ +static __inline__ int __attribute__ ((always_inline)) alt_write_flash( + alt_flash_fd* fd, + int offset, + const void* src_addr, + int length ) +{ + return fd->write( fd, offset, src_addr, length ); +} + +/* + * alt_read_flash + * + * Read a block of flash for most flashes this is just memcpy + * it's here for completeness in case we need it for some serial flash device + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_read_flash( + alt_flash_fd* fd, int offset, + void* dest_addr, int length ) +{ + return fd->read( fd, offset, dest_addr, length ); +} + +/* + * alt_get_flash_info + * + * Return the information on the flash sectors. + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( + alt_flash_fd* fd, flash_region** info, + int* number_of_regions) +{ + return fd->get_info( fd, info, number_of_regions); +} + +/* + * alt_erase_flash_block + * + * Erase a particular erase block, pass in the offset to the start of + * the block and it's size + */ +static __inline__ int __attribute__ ((always_inline)) alt_erase_flash_block( + alt_flash_fd* fd, int offset, int length) +{ + int ret_code; + ret_code = fd->erase_block( fd, offset ); + + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + offset, length); + + return ret_code; +} + +/* + * alt_write_flash_block + * + * Write a particular flash block, block_offset is the offset + * (from the base of flash) to start of the block + * data_offset is the offset (from the base of flash) + * where you wish to start programming + * + * NB this function DOES NOT check that you are only writing a single + * block of data as that would slow down this function. + * + * Use alt_write_flash if you want that level of error checking. + */ + +static __inline__ int __attribute__ ((always_inline)) alt_write_flash_block( + alt_flash_fd* fd, int block_offset, + int data_offset, + const void *data, int length) +{ + + int ret_code; + ret_code = fd->write_block( fd, block_offset, data_offset, data, length ); + + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + data_offset, length); + + return ret_code; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FLASH_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash_dev.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash_dev.h new file mode 100644 index 0000000..1c5692e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash_dev.h @@ -0,0 +1,98 @@ +#ifndef __ALT_FLASH_DEV_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_dev.h - Generic Flash device interfaces * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_DEV_H__ + +#include "alt_flash_types.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +typedef struct alt_flash_dev alt_flash_dev; +typedef alt_flash_dev alt_flash_fd; + +static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd) +{ + extern alt_llist alt_flash_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list); +} + +typedef alt_flash_dev* (*alt_flash_open)(alt_flash_dev* flash, + const char* name ); +typedef int (*alt_flash_close)(alt_flash_dev* flash_info); + +typedef int (*alt_flash_write)( alt_flash_dev* flash, int offset, + const void* src_addr, int length ); + +typedef int (*alt_flash_get_flash_info)( alt_flash_dev* flash, flash_region** info, + int* number_of_regions); +typedef int (*alt_flash_write_block)( alt_flash_dev* flash, int block_offset, + int data_offset, const void* data, + int length); +typedef int (*alt_flash_erase_block)( alt_flash_dev* flash, int offset); +typedef int (*alt_flash_read)(alt_flash_dev* flash, int offset, + void* dest_addr, int length ); + +struct alt_flash_dev +{ + alt_llist llist; + const char* name; + alt_flash_open open; + alt_flash_close close; + alt_flash_write write; + alt_flash_read read; + alt_flash_get_flash_info get_info; + alt_flash_erase_block erase_block; + alt_flash_write_block write_block; + void* base_addr; + int length; + int number_of_regions; + flash_region region_info[ALT_MAX_NUMBER_OF_FLASH_REGIONS]; +}; + +#endif /* __ALT_FLASH_DEV_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash_types.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash_types.h new file mode 100644 index 0000000..10f1f01 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_flash_types.h @@ -0,0 +1,64 @@ +#ifndef __ALT_FLASH_TYPES_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_types.h - Some generic types and defines used by the flash code * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_TYPES_H__ + +#ifndef ALT_MAX_NUMBER_OF_FLASH_REGIONS +#define ALT_MAX_NUMBER_OF_FLASH_REGIONS 8 +#endif /* ALT_MAX_NUMBER_OF_FLASH_REGIONS */ + +/* + * Description of a single Erase region + */ +typedef struct flash_region +{ + int offset; + int region_size; + int number_of_blocks; + int block_size; +}flash_region; + +#endif /* __ALT_FLASH_TYPES_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_irq.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_irq.h new file mode 100644 index 0000000..96c010d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_irq.h @@ -0,0 +1,245 @@ +#ifndef __ALT_IRQ_H__ +#define __ALT_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_irq.h is the Nios II specific implementation of the interrupt controller + * interface. + * + * Nios II includes optional support for an external interrupt controller. + * When an external controller is present, the "Enhanced" interrupt API + * must be used to manage individual interrupts. The enhanced API also + * supports the processor's internal interrupt controller. Certain API + * members are accessible from either the "legacy" or "enhanced" interrpt + * API. + * + * Regardless of which API is in use, this file should be included by + * application code and device drivers that register ISRs or manage interrpts. + */ +#include + +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros used by alt_irq_enabled + */ +#define ALT_IRQ_ENABLED 1 +#define ALT_IRQ_DISABLED 0 + +/* + * Number of available interrupts in internal interrupt controller. + */ +#define ALT_NIRQ NIOS2_NIRQ + +/* + * Used by alt_irq_disable_all() and alt_irq_enable_all(). + */ +typedef int alt_irq_context; + +/* ISR Prototype */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +typedef void (*alt_isr_func)(void* isr_context); +#else +typedef void (*alt_isr_func)(void* isr_context, alt_u32 id); +#endif + +/* + * The following protypes and routines are supported by both + * the enhanced and legacy interrupt APIs + */ + +/* + * alt_irq_enabled can be called to determine if the processor's global + * interrupt enable is asserted. The return value is zero if interrupts + * are disabled, and non-zero otherwise. + * + * Whether the internal or external interrupt controller is present, + * individual interrupts may still be disabled. Use the other API to query + * a specific interrupt. + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enabled (void) +{ + int status; + + NIOS2_READ_STATUS (status); + + return status & NIOS2_STATUS_PIE_MSK; +} + +/* + * alt_irq_disable_all() + * + * This routine inhibits all interrupts by negating the status register PIE + * bit. It returns the previous contents of the CPU status register (IRQ + * context) which can be used to restore the status register PIE bit to its + * state before this routine was called. + */ +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + + return context; +} + +/* + * alt_irq_enable_all() + * + * Enable all interrupts that were previously disabled by alt_irq_disable_all() + * + * This routine accepts a context to restore the CPU status register PIE bit + * to the state prior to a call to alt_irq_disable_all(). + + * In the case of nested calls to alt_irq_disable_all()/alt_irq_enable_all(), + * this means that alt_irq_enable_all() does not necessarily re-enable + * interrupts. + * + * This routine will perform a read-modify-write sequence to restore only + * status.PIE if the processor is configured with options that add additional + * writeable status register bits. These include the MMU, MPU, the enhanced + * interrupt controller port, and shadow registers. Otherwise, as a performance + * enhancement, status is overwritten with the prior context. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_enable_all (alt_irq_context context) +{ +#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || (defined NIOS2_EIC_PRESENT) || \ + (defined NIOS2_MMU_PRESENT) || (defined NIOS2_MPU_PRESENT) + alt_irq_context status; + + NIOS2_READ_STATUS (status); + + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); +#endif +} + +/* + * The function alt_irq_init() is defined within the auto-generated file + * alt_sys_init.c. This function calls the initilization macros for all + * interrupt controllers in the system at config time, before any other + * non-interrupt controller driver is initialized. + * + * The "base" parameter is ignored and only present for backwards-compatibility. + * It is recommended that NULL is passed in for the "base" parameter. + */ +extern void alt_irq_init (const void* base); + +/* + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts () +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK +#if defined(NIOS2_EIC_PRESENT) && (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) + | NIOS2_STATUS_RSIE_MSK +#endif + ); +} + + +/* + * Prototypes for the enhanced interrupt API. + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +/* + * alt_ic_isr_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_ic_isr_register(alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void *isr_context, + void *flags); + +/* + * alt_ic_irq_enable() and alt_ic_irq_disable() enable/disable a specific + * interrupt by using IRQ port and interrupt controller instance. + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq); +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq); + + /* + * alt_ic_irq_enabled() indicates whether a specific interrupt, as + * specified by IRQ port and interrupt controller instance is enabled. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq); + +#else +/* + * Prototypes for the legacy interrupt API. + */ +#include "priv/alt_legacy_irq.h" +#endif + + +/* + * alt_irq_pending() returns a bit list of the current pending interrupts. + * This is used by alt_irq_handler() to determine which registered interrupt + * handlers should be called. + * + * This routine is only available for the Nios II internal interrupt + * controller. + */ +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + + return active; +} +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_IRQ_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_irq_entry.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_irq_entry.h new file mode 100644 index 0000000..549811c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_irq_entry.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file pulls in the IRQ entry assembler and C code, which is only + * required if there are any interruptes in the system. + */ + +__asm__( "\n\t.globl alt_irq_entry" ); + +__asm__( "\n\t.globl alt_irq_handler" ); + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h new file mode 100644 index 0000000..1d1f16f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h @@ -0,0 +1,77 @@ +#ifndef __ALT_LICENSE_REMINDER_UCOSII_H__ +#define __ALT_LICENSE_REMINDER_UCOSII_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include + +#define ALT_LICENSE_REMINDER_UCOSII_STRING \ + "============== Software License Reminder ===============\n" \ + "\n" \ + "uC/OS-II is provided in source form for FREE evaluation,\n" \ + "for educational use, or for peaceful research. If you\n" \ + "plan on using uC/OS-II in a commercial product you need\n" \ + "to contact Micrium to properly license its use in your\n" \ + "product. Micrium provides ALL the source code on the\n" \ + "Altera distribution for your convenience and to help you\n" \ + "experience uC/OS-II. The fact that the source is provided\n" \ + "does NOT mean that you can use it without paying a\n" \ + "licensing fee. Please help us continue to provide the\n" \ + "Embedded community with the finest software available.\n" \ + "Your honesty is greatly appreciated.\n" \ + "\n" \ + "Please contact:\n" \ + "\n" \ + "M I C R I U M\n" \ + "949 Crestview Circle\n" \ + "Weston, FL 33327-1848\n" \ + "U.S.A.\n" \ + "\n" \ + "Phone : +1 954 217 2036\n" \ + "FAX : +1 954 217 2037\n" \ + "WEB : www.micrium.com\n" \ + "E-mail: Sales@Micrium.com\n" \ + "\n" \ + "========================================================\n" + +#define alt_license_reminder_ucosii() puts(ALT_LICENSE_REMINDER_UCOSII_STRING) + + +#endif /* __ALT_LICENSE_REMINDER_UCOSII_H__ */ + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_llist.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_llist.h new file mode 100644 index 0000000..84cb051 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_llist.h @@ -0,0 +1,123 @@ +#ifndef __ALT_LIST_H__ +#define __ALT_LIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * alt_llist.h defines structures and functions for use in manipulating linked + * lists. A list is considered to be constructed from a chain of objects of + * type alt_llist, with one object being defined to be the head element. + * + * A list is considered to be empty if it only contains the head element. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_llist is the structure used to represent an element within a linked + * list. + */ + +typedef struct alt_llist_s alt_llist; + +struct alt_llist_s { + alt_llist* next; /* Pointer to the next element in the list. */ + alt_llist* previous; /* Pointer to the previous element in the list. */ +}; + +/* + * ALT_LLIST_HEAD is a macro that can be used to create the head of a new + * linked list. This is named "head". The head element is initialised to + * represent an empty list. + */ + +#define ALT_LLIST_HEAD(head) alt_llist head = {&head, &head} + +/* + * ALT_LLIST_ENTRY is a macro used to define an uninitialised linked list + * entry. This is used to reserve space in structure initialisation for + * structures that inherit form alt_llist. + */ + +#define ALT_LLIST_ENTRY {0, 0} + +/* + * alt_llist_insert() insert adds the linked list entry "entry" as the + * first entry in the linked list "list". "list" is the list head element. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + entry->next = list->next; + + list->next->previous = entry; + list->next = entry; +} + +/* + * alt_llist_remove() is called to remove an element from a linked list. The + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + entry->previous->next = entry->next; + + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + entry->next = entry; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_LLIST_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_load.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_load.h new file mode 100644 index 0000000..e4c4c46 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_load.h @@ -0,0 +1,78 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This macro is used to load code/data from its load address to its + * execution address for a given section. The section name is the input + * argument. Note that a leading '.' is assumed in the name. For example + * to load the section .onchip_ram, use: + * + * ALT_LOAD_SECTION_BY_NAME(onchip_ram); + * + * This requires that the apropriate linker symbols have been generated + * for the section in question. This will be the case if you are using the + * default linker script. + */ + +#define ALT_LOAD_SECTION_BY_NAME(name) \ + { \ + extern void _alt_partition_##name##_start; \ + extern void _alt_partition_##name##_end; \ + extern void _alt_partition_##name##_load_addr; \ + \ + alt_load_section(&_alt_partition_##name##_load_addr, \ + &_alt_partition_##name##_start, \ + &_alt_partition_##name##_end); \ + } + +/* + * Function used to load an individual section from flash to RAM. + * + * There is an implicit assumption here that the linker script will ensure + * that all sections are word aligned. + * + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + { + *to++ = *from++; + } + } +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_log_printf.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_log_printf.h new file mode 100644 index 0000000..9890091 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_log_printf.h @@ -0,0 +1,349 @@ +/* alt_log_printf.h + * + * ALT_LOG is designed to provide extra logging/debugging messages from HAL + * through a different port than stdout. It is enabled by the ALT_LOG_ENABLE + * define, which needs to supplied at compile time. When logging is turned off, + * code size is unaffected. Thus, this should be transparent to the user + * when it is not actively turned on, and should not affect projects in any way. + * + * There are macros sprinkled within different components, such as the jtag uart + * and timer, in the HAL code. They are always named ALT_LOG_, and can be + * safely ignored if ALT_LOG is turned off. + * + * To turn on ALT_LOG, ALT_LOG_ENABLE must be defined, and ALT_LOG_PORT_TYPE and + * ALT_LOG_PORT_BASE must be set in system.h. This is done through editing + * .ptf, by editing the alt_log_port_type & alt_log_port_base settings. + * See the documentation html file for examples. + * + * When it is turned on, it will output extra HAL messages to a port specified + * in system.h. This can be a UART or JTAG UART port. By default it will + * output boot messages, detailing every step of the boot process. + * + * Extra logging is designed to be enabled by flags, which are defined in + * alt_log_printf.c. The default value is that all flags are off, so only the + * boot up logging messages show up. ALT_LOG_FLAGS can be set to enable certain + * groupings of flags, and that grouping is done in this file. Each flag can + * also be overridden with a -D at compile time. + * + * This header file includes the necessary prototypes for using the alt_log + * functions. It also contains all the macros that are used to remove the code + * from alt log is turned off. Also, the macros in other HAL files are defined + * here at the bottom. These macros all call some C function that is in + * alt_log_printf.c. + * + * The logging has functions for printing in C (ALT_LOG_PRINTF) and in assembly + * (ALT_LOG_PUTS). This was needed because the assembly printing occurs before + * the device is initialized. The assembly function corrupts register R4-R7, + * which are not used in the normal boot process. For this reason, do not call + * the assembly function in C. + * + * author: gkwan + */ + + +#ifndef __ALT_LOG_PRINTF_H__ +#define __ALT_LOG_PRINTF_H__ + +#include + +/* Global switch to turn on logging functions */ +#ifdef ALT_LOG_ENABLE + + /* ALT_LOG_PORT_TYPE values as defined in system.h. They are defined as + * numbers here first becasue the C preprocessor does not handle string + * comparisons. */ + #define ALTERA_AVALON_JTAG_UART 1 + #define ALTERA_AVALON_UART 0 + + /* If this .h file is included by an assembly file, skip over include files + * that won't compile in assembly. */ + #ifndef ALT_ASM_SRC + #include + #include "sys/alt_alarm.h" + #include "sys/alt_dev.h" + #ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #endif + #endif /* ALT_ASM_SRC */ + + /* These are included for the port register offsets and masks, needed + * to write to the port. Only include if the port type is set correctly, + * otherwise error. If alt_log is turned on and the port to output to is + * incorrect or does not exist, then should exit. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #ifdef __ALTERA_AVALON_JTAG_UART + #include + #else + #error ALT_LOG: JTAG_UART port chosen, but no JTAG_UART in system. + #endif + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #ifdef __ALTERA_AVALON_UART + #include + #else + #error ALT_LOG: UART Port chosen, but no UART in system. + #endif + #else + #error ALT_LOG: alt_log_port_type declaration invalid! + #endif + + /* ALT_LOG_ENABLE turns on the basic printing function */ + #define ALT_LOG_PRINTF(...) do {alt_log_printf_proc(__VA_ARGS__);} while (0) + + /* Assembly macro for printing in assembly, calls tx_log_str + * which is in alt_log_macro.S. + * If alt_log_boot_on_flag is 0, skips the printing */ + #define ALT_LOG_PUTS(str) movhi r4, %hiadj(alt_log_boot_on_flag) ; \ + addi r4, r4, %lo(alt_log_boot_on_flag) ; \ + ldwio r5, 0(r4) ; \ + beq r0, r5, 0f ; \ + movhi r4, %hiadj(str) ; \ + addi r4, r4, %lo(str) ; \ + call tx_log_str ; \ + 0: + + /* These defines are here to faciliate the use of one output function + * (alt_log_txchar) to print to both the JTAG UART or the UART. Depending + * on the port type, the status register, read mask, and output register + * are set to the appropriate value for the port. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_JTAG_UART_CONTROL + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_JTAG_UART_DATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_JTAG_UART_CONTROL_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_JTAG_UART_DATA_REG*0x4) + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_UART_STATUS + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_UART_STATUS_TRDY_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_UART_TXDATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_UART_STATUS_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_UART_TXDATA_REG*0x4) + #endif /* ALT_LOG_PORT */ + + /* Grouping of flags via ALT_LOG_FLAGS. Each specific flag can be set via + * -D at compile time, or else they'll be set to a default value according + * to ALT_LOG_FLAGS. ALT_LOG_FLAGS = 0 or not set is the default, where + * only the boot messages will be printed. As ALT_LOG_FLAGS increase, they + * increase in intrusiveness to the program, and will affect performance. + * + * Flag Level 1 - turns on system clock and JTAG UART startup status + * 2 - turns on write echo and JTAG_UART alarm (periodic report) + * 3 - turns on JTAG UART ISR logging - will slow performance + * significantly. + * -1 - All logging output is off, but if ALT_LOG_ENABLE is + * defined all logging function is built and code size + * remains constant + * + * Flag settings - 1 = on, 0 = off. */ + + /* This flag turns on "boot" messages for printing. This includes messages + * during crt0.S, then alt_main, and finally alt_exit. */ + #ifndef ALT_LOG_BOOT_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #endif + #endif /* ALT_LOG_BOOT_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_SYS_CLK_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_SYS_CLK_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_WRITE_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_WRITE_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_STARTUP_INFO_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING */ + +#ifndef ALT_ASM_SRC + /* Function Prototypes */ + void alt_log_txchar(int c,char *uartBase); + void alt_log_private_printf(const char *fmt,int base,va_list args); + void alt_log_repchar(char c,int r,int base); + int alt_log_printf_proc(const char *fmt, ... ); + void alt_log_system_clock(); + #ifdef __ALTERA_AVALON_JTAG_UART + alt_u32 altera_avalon_jtag_uart_report_log(void * context); + void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base); + void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, \ + int base, const char* header); + void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev); + #endif + void alt_log_write(const void *ptr, size_t len); + + /* extern all global variables */ + extern volatile alt_u32 alt_log_boot_on_flag; + extern volatile alt_u8 alt_log_write_on_flag; + extern volatile alt_u8 alt_log_sys_clk_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_alarm_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_isr_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag; + extern volatile int alt_log_sys_clk_count; + extern volatile int alt_system_clock_in_sec; + extern alt_alarm alt_log_jtag_uart_alarm_1; +#endif /* ALT_ASM_SRC */ + + + /* Below are the MACRO defines used in various HAL files. They check + * if their specific flag is turned on; if it is, then it executes its + * code. + * + * To keep this file reasonable, most of these macros calls functions, + * which are defined in alt_log_printf.c. Look there for implementation + * details. */ + + /* Boot Messages Logging */ + #define ALT_LOG_PRINT_BOOT(...) \ + do { if (alt_log_boot_on_flag==1) {ALT_LOG_PRINTF(__VA_ARGS__);} \ + } while (0) + + /* JTAG UART Logging */ + /* number of ticks before alarm runs logging function */ + #ifndef ALT_LOG_JTAG_UART_TICKS_DIVISOR + #define ALT_LOG_JTAG_UART_TICKS_DIVISOR 10 + #endif + #ifndef ALT_LOG_JTAG_UART_TICKS + #define ALT_LOG_JTAG_UART_TICKS \ + (alt_ticks_per_second()/ALT_LOG_JTAG_UART_TICKS_DIVISOR) + #endif + + /* if there's a JTAG UART defined, then enable these macros */ + #ifdef __ALTERA_AVALON_JTAG_UART + + /* Macro in altera_avalon_jtag_uart.c, to register the alarm function. + * Also, the startup register info is also printed here, as this is + * called within the device driver initialization. */ + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) \ + do { if (alt_log_jtag_uart_alarm_on_flag==1) { \ + alt_alarm_start(&alt_log_jtag_uart_alarm_1, \ + ALT_LOG_JTAG_UART_TICKS, &altera_avalon_jtag_uart_report_log,\ + dev);} \ + if (alt_log_jtag_uart_startup_info_on_flag==1) {\ + alt_log_jtag_uart_startup_info(dev, base);} \ + } while (0) + + /* JTAG UART IRQ Logging (when buffer is empty) + * Inserted in the ISR in altera_avalon_jtag_uart.c */ + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) \ + do { alt_log_jtag_uart_isr_proc(base, dev); } while (0) + /* else, define macros to nothing. Or else the jtag_uart specific types + * will throw compiler errors */ + #else + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #endif + + /* System clock logging + * How often (in seconds) the system clock logging prints. + * The default value is every 1 second */ + #ifndef ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER + #define ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER 1 + #endif + #ifndef ALT_LOG_SYS_CLK_INTERVAL + #define ALT_LOG_SYS_CLK_INTERVAL \ + (alt_ticks_per_second()*ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER) + #endif + + /* System clock logging - prints a message every interval (set above) + * to show that the system clock is alive. + * This macro is used in altera_avalon_timer_sc.c */ + #define ALT_LOG_SYS_CLK_HEARTBEAT() \ + do { alt_log_system_clock(); } while (0) + + /* alt_write_logging - echos a message every time write() is called, + * displays the first ALT_LOG_WRITE_ECHO_LEN characters. + * This macro is used in alt_write.c */ + #ifndef ALT_LOG_WRITE_ECHO_LEN + #define ALT_LOG_WRITE_ECHO_LEN 15 + #endif + + #define ALT_LOG_WRITE_FUNCTION(ptr,len) \ + do { alt_log_write(ptr,len); } while (0) + +#else /* ALT_LOG_ENABLE not defined */ + + /* logging is off, set all relevant macros to null */ + #define ALT_LOG_PRINT_BOOT(...) + #define ALT_LOG_PRINTF(...) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_SYS_CLK_HEARTBEAT() + #define ALT_LOG_PUTS(str) + #define ALT_LOG_WRITE_FUNCTION(ptr,len) + +#endif /* ALT_LOG_ENABLE */ + +#endif /* __ALT_LOG_PRINTF_H__ */ + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_set_args.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_set_args.h new file mode 100644 index 0000000..a9372c5 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_set_args.h @@ -0,0 +1,71 @@ +#ifndef __ALT_SET_ARGS_H__ +#define __ALT_SET_ARGS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_set_args() is provided in order to define the input + * arguments to main(). If this function is not called before main() then the + * argument list passed to main() will be empty. + * + * It is expected that this function will only be used by the ihost/iclient + * utility. + */ + +static inline void alt_set_args (int argc, char** argv, char** envp) +{ + extern int alt_argc; + extern char** alt_argv; + extern char** alt_envp; + + alt_argc = argc; + alt_argv = argv; + alt_envp = envp; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SET_ARGS_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sim.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sim.h new file mode 100644 index 0000000..63afad9 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sim.h @@ -0,0 +1,91 @@ +#ifndef __ALT_SIM_H__ +#define __ALT_SIM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" +#include "alt_types.h" + +/* + * Instructions that might mean something special to a simulator. + * These have no special effect on real hardware (they are just nops). + */ +#define ALT_SIM_FAIL() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc1"); } while (0) + +#define ALT_SIM_PASS() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc2"); } while (0) + +#define ALT_SIM_IN_TOP_OF_HOT_LOOP() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc3"); } while (0) + +/* + * Routine called on exit. + */ +static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + int r2 = exit_code; + +#if defined(NIOS2_HAS_DEBUG_STUB) && (defined(ALT_BREAK_ON_EXIT) || defined(ALT_PROVIDE_GMON)) + + int r3 = (1 << 2); + +#ifdef ALT_PROVIDE_GMON + extern unsigned int alt_gmon_data[]; + int r4 = (int)alt_gmon_data; + r3 |= (1 << 4); +#define ALT_GMON_DATA ,"D04"(r4) +#else +#define ALT_GMON_DATA +#endif /* ALT_PROVIDE_GMON */ + + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } + + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } +#endif /* DEBUG_STUB */ +} + +#define ALT_SIM_HALT(exit_code) \ + alt_sim_halt(exit_code) + +#endif /* __ALT_SIM_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_stack.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_stack.h new file mode 100644 index 0000000..ebcad7a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_stack.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_STACK_H__ +#define __ALT_STACK_H__ + +/* + * alt_stack.h is the nios2 specific implementation of functions used by the + * stack overflow code. + */ + +#include "nios2.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +extern char * alt_stack_limit_value; + +#ifdef ALT_EXCEPTION_STACK +extern char __alt_exception_stack_pointer[]; /* set by the linker */ +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_stack_limit can be called to determine the current value of the stack + * limit register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_limit (void) +{ + char * limit; + NIOS2_READ_ET(limit); + + return limit; +} + +/* + * alt_stack_pointer can be called to determine the current value of the stack + * pointer register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_pointer (void) +{ + char * pointer; + NIOS2_READ_SP(pointer); + + return pointer; +} + + +#ifdef ALT_EXCEPTION_STACK + +/* + * alt_exception_stack_pointer returns the normal stack pointer from + * where it is stored on the exception stack (uppermost 4 bytes). This + * is really only useful during exception processing, and is only + * available if a separate exception stack has been configured. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_exception_stack_pointer (void) +{ + return (char *) *(alt_u32 *)(__alt_exception_stack_pointer - sizeof(alt_u32)); +} + +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_set_stack_limit can be called to update the current value of the stack + * limit register. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_set_stack_limit (char * limit) +{ + alt_stack_limit_value = limit; + NIOS2_WRITE_ET(limit); +} + +/* + * alt_report_stack_overflow reports that a stack overflow happened. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_report_stack_overflow (void) +{ + NIOS2_REPORT_STACK_OVERFLOW(); +} + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_STACK_H__ */ + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_stdio.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_stdio.h new file mode 100644 index 0000000..7ae05d4 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_stdio.h @@ -0,0 +1,62 @@ +#ifndef __ALT_STDIO_H__ +#define __ALT_STDIO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definitions for ALT stdio routines. + */ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +int alt_getchar(); +int alt_putchar(int c); +int alt_putstr(const char* str); +void alt_printf(const char *fmt, ...); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_STDIO_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sys_init.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sys_init.h new file mode 100644 index 0000000..3b18059 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sys_init.h @@ -0,0 +1,62 @@ +#ifndef __ALT_SYS_INIT_H__ +#define __ALT_SYS_INIT_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_sys_init() is defined within the auto-generated file: + * alt_sys_init.c. This function calls the initilisation macros for all + * devices, file systems, and software components within the system. + * + * The list of initilisation macros to use is constructed using the PTF and + * STF files associated with the system. + */ + +extern void alt_sys_init (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SYS_INIT_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sys_wrappers.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sys_wrappers.h new file mode 100644 index 0000000..eea552d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_sys_wrappers.h @@ -0,0 +1,100 @@ +#ifndef __ALT_SYS_WRAPPERS_H__ +#define __ALT_SYS_WRAPPERS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides the prototypes for the HAL 'UNIX style functions. The + * names of these functions are defined in alt_syscall.h. THese are defined to + * be the standard names when running the standalone HAL, e.g. open(), close() + * etc., but the names may be redefined as a part of an operating system port + * in order to avoid name clashes. + */ + +#include "os/alt_syscall.h" + +#include +#include +#include +#include +#include +#include + +extern int ALT_CLOSE (int __fd); +extern int ALT_EXECVE (const char *__path, + char * const __argv[], + char * const __envp[]); +extern void ALT_EXIT (int __status); +extern int ALT_FSTAT (int file, struct stat *st); +extern int ALT_FCNTL (int file, int cmd, ...); +extern pid_t ALT_FORK (void); +extern pid_t ALT_GETPID (void); + +#if defined (__GNUC__) && __GNUC__ >= 4 +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + void *ptimezone); +#else +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + struct timezone *ptimezone); +#endif + +extern int ALT_IOCTL (int file, int req, void* arg); +extern int ALT_ISATTY (int file); +extern int ALT_KILL (int pid, int sig); +extern int ALT_LINK (const char *existing, const char *new); +extern off_t ALT_LSEEK (int file, off_t ptr, int dir); +extern int ALT_OPEN (const char* file, int flags, ...); +extern int ALT_READ (int file, void *ptr, size_t len); +extern int ALT_RENAME (char *existing, char *new); +extern void* ALT_SBRK (ptrdiff_t incr); +extern int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz); +extern int ALT_STAT (const char *file, struct stat *st); +extern clock_t ALT_TIMES (struct tms *buf); +extern int ALT_UNLINK (const char *name); + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us); +#else +unsigned int ALT_USLEEP (unsigned int us); +#endif + +extern int ALT_WAIT (int *status); +extern int ALT_WRITE (int file, const void *ptr, size_t len); + + +extern char** ALT_ENVIRON; + +/* + * + */ + +#endif /* __ALT_SYS_WRAPPERS_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_timestamp.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_timestamp.h new file mode 100644 index 0000000..ec704ba --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_timestamp.h @@ -0,0 +1,60 @@ +#ifndef __ALT_TIMESTAMP_H__ +#define __ALT_TIMESTAMP_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "altera_avalon_timer.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +extern int alt_timestamp_start (void); + +extern alt_timestamp_type alt_timestamp (void); + +extern alt_u32 alt_timestamp_freq (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_TIMESTAMP_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_warning.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_warning.h new file mode 100644 index 0000000..01318bd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/alt_warning.h @@ -0,0 +1,75 @@ +#ifndef __WARNING_H__ +#define __WARNING_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_warning.h provides macro definitions that can be used to generate link + * time warnings. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The symbol "__alt_invalid" is used to force a link error. There should be + * no corresponding implementation of this function. + */ + +extern void __alt_invalid (void); + +#define ALT_LINK_WARNING(symbol, msg) \ + __asm__(".ifndef __evoke_link_warning_" #symbol \ + "\n\t .section .gnu.warning." #symbol \ + "\n__evoke_link_warning_" #symbol ":\n\t .string \x22" msg "\x22 \n\t .previous" \ + "\n .endif"); + +/* A canned warning for sysdeps/stub functions. */ + +#define ALT_STUB_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is not implemented and will always fail") + +#define ALT_OBSOLETE_FUNCTION_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is a deprecated function") + +#define ALT_LINK_ERROR(msg) \ + ALT_LINK_WARNING (__alt_invalid, msg); \ + __alt_invalid() + +#ifdef __cplusplus +} +#endif + +#endif /* __WARNING_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/ioctl.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/ioctl.h new file mode 100644 index 0000000..453283b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/ioctl.h @@ -0,0 +1,90 @@ +#ifndef __IOCTL_H__ +#define __IOCTL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The ioctl() system call be used to initiate a variety of control operations + * on a file descriptor. For the most part this simply translates to a call to + * the ioctl() function of the associated device driver (TIOCEXCL and + * TIOCNXCL are notable exceptions - see ioctl.c for details). + * + * The interpretation of the ioctl requests are therefore device specific. + * + * This function is equivalent to the standard Posix ioctl() call. + */ + +extern int ioctl (int fd, int req, void* arg); + +/* + * list of ioctl calls handled by the system ioctl implementation. + */ + +#define TIOCEXCL 0x740d /* exclusive use of the device */ +#define TIOCNXCL 0x740e /* allow multiple use of the device */ + +/* + * ioctl calls which can be handled by device drivers. + */ + +#define TIOCOUTQ 0x7472 /* get output queue size */ +#define TIOCMGET 0x741d /* get termios flags */ +#define TIOCMSET 0x741a /* set termios flags */ + +/* + * ioctl calls specific to JTAG UART. + */ + +#define TIOCSTIMEOUT 0x6a01 /* Set Timeout before assuming no host present */ +#define TIOCGCONNECTED 0x6a02 /* Get indication of whether host is connected */ + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IOCTL_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/termios.h b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/termios.h new file mode 100644 index 0000000..d271387 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/inc/sys/termios.h @@ -0,0 +1,181 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This is the termios.h file provided with newlib. The only modification has + * been to the baud rate macro definitions, and an increase in the size of the + * termios structure to accomodate this. + */ + + +#ifndef _SYS_TERMIOS_H +# define _SYS_TERMIOS_H + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +# define _XCGETA (('x'<<8)|1) +# define _XCSETA (('x'<<8)|2) +# define _XCSETAW (('x'<<8)|3) +# define _XCSETAF (('x'<<8)|4) +# define _TCSBRK (('T'<<8)|5) +# define _TCFLSH (('T'<<8)|7) +# define _TCXONC (('T'<<8)|6) + +# define TCOOFF 0 +# define TCOON 1 +# define TCIOFF 2 +# define TCION 3 + +# define TCIFLUSH 0 +# define TCOFLUSH 1 +# define TCIOFLUSH 2 + +# define NCCS 13 + +# define TCSAFLUSH _XCSETAF +# define TCSANOW _XCSETA +# define TCSADRAIN _XCSETAW +# define TCSADFLUSH _XCSETAF + +# define IGNBRK 000001 +# define BRKINT 000002 +# define IGNPAR 000004 +# define INPCK 000020 +# define ISTRIP 000040 +# define INLCR 000100 +# define IGNCR 000200 +# define ICRNL 000400 +# define IXON 002000 +# define IXOFF 010000 + +# define OPOST 000001 +# define OCRNL 000004 +# define ONLCR 000010 +# define ONOCR 000020 +# define TAB3 014000 + +# define CLOCAL 004000 +# define CREAD 000200 +# define CSIZE 000060 +# define CS5 0 +# define CS6 020 +# define CS7 040 +# define CS8 060 +# define CSTOPB 000100 +# define HUPCL 002000 +# define PARENB 000400 +# define PAODD 001000 + +#define CCTS_OFLOW 010000 +#define CRTS_IFLOW 020000 +#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) + +# define ECHO 0000010 +# define ECHOE 0000020 +# define ECHOK 0000040 +# define ECHONL 0000100 +# define ICANON 0000002 +# define IEXTEN 0000400 /* anybody know *what* this does?! */ +# define ISIG 0000001 +# define NOFLSH 0000200 +# define TOSTOP 0001000 + +# define VEOF 4 /* also VMIN -- thanks, AT&T */ +# define VEOL 5 /* also VTIME -- thanks again */ +# define VERASE 2 +# define VINTR 0 +# define VKILL 3 +# define VMIN 4 /* also VEOF */ +# define VQUIT 1 +# define VSUSP 10 +# define VTIME 5 /* also VEOL */ +# define VSTART 11 +# define VSTOP 12 + +# define B0 0 +# define B50 50 +# define B75 75 +# define B110 110 +# define B134 134 +# define B150 150 +# define B200 200 +# define B300 300 +# define B600 600 +# define B1200 1200 +# define B1800 1800 +# define B2400 2400 +# define B4800 4800 +# define B9600 9600 +# define B19200 19200 +# define B38400 38400 +# define B57600 57600 +# define B115200 115200 + +typedef unsigned char cc_t; +typedef unsigned short tcflag_t; +typedef unsigned long speed_t; + +struct termios { + tcflag_t c_iflag; + tcflag_t c_oflag; + tcflag_t c_cflag; + tcflag_t c_lflag; + char c_line; + cc_t c_cc[NCCS]; + speed_t c_ispeed; + speed_t c_ospeed; +}; + +# ifndef _NO_MACROS + +# define cfgetospeed(tp) ((tp)->c_ospeed) +# define cfgetispeed(tp) ((tp)->c_ispeed) +# define cfsetospeed(tp,s) (((tp)->c_ospeed = (s)), 0) +# define cfsetispeed(tp,s) (((tp)->c_ispeed = (s)), 0) +# define tcdrain(fd) _ioctl (fd, _TCSBRK, 1) +# endif /* _NO_MACROS */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_TERMIOS_H */ + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_alarm_start.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_alarm_start.c new file mode 100644 index 0000000..2bd672f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_alarm_start.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_irq.h" + +/* + * alt_alarm_start is called to register an alarm with the system. The + * "alarm" structure passed as an input argument does not need to be + * initialised by the user. This is done within this function. + * + * The remaining input arguments are: + * + * nticks - The time to elapse until the alarm executes. This is specified in + * system clock ticks. + * callback - The function to run when the indicated time has elapsed. + * context - An opaque value, passed to the callback function. +* + * Care should be taken when defining the callback function since it is + * likely to execute in interrupt context. In particular, this mean that + * library calls like printf() should not be made, since they can result in + * deadlock. + * + * The interval to be used for the next callback is the return + * value from the callback function. A return value of zero indicates that the + * alarm should be unregistered. + * + * alt_alarm_start() will fail if the timer facility has not been enabled + * (i.e. there is no system clock). Failure is indicated by a negative return + * value. + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + + if (alt_ticks_per_second ()) + { + if (alarm) + { + alarm->callback = callback; + alarm->context = context; + + irq_context = alt_irq_disable_all (); + + current_nticks = alt_nticks(); + + alarm->time = nticks + current_nticks + 1; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + { + alarm->rollover = 1; + } + else + { + alarm->rollover = 0; + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + alt_irq_enable_all (irq_context); + + return 0; + } + else + { + return -EINVAL; + } + } + else + { + return -ENOTSUP; + } +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_busy_sleep.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_busy_sleep.c new file mode 100644 index 0000000..1b910a5 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_busy_sleep.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + * + * alt_busy_sleep.c - Microsecond delay routine which uses a calibrated busy + * loop to perform the delay. This is used to implement + * usleep for both uC/OS-II and the standalone HAL. + * + * Author PRR + * + * Calibrated delay with no timer required + * + * The ASM instructions in the routine are equivalent to + * + * for (i=0;i +#include + +#include "system.h" +#include "alt_types.h" + +#include "priv/alt_busy_sleep.h" + +unsigned int alt_busy_sleep (unsigned int us) +{ +/* + * Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software + * is built targetting ModelSim RTL simulation, the delay will be + * skipped to speed up simulation. + */ +#ifndef ALT_SIM_OPTIMIZE + int i; + int big_loops; + alt_u32 cycles_per_loop; + + if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny")) + { + cycles_per_loop = 9; + } + else + { + cycles_per_loop = 3; + } + + + big_loops = us / (INT_MAX/ + (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); + + if (big_loops) + { + for(i=0;i + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_CLOSE (int fildes) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(close); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * close() is called by an application to release a file descriptor. If the + * associated file system/device has a close() callback function registered + * then this called. The file descriptor is then marked as free. + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + + if (fd) + { + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + if (rval < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return 0; + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush.c new file mode 100644 index 0000000..8afe062 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush.c @@ -0,0 +1,97 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * Nios II version 1.2 and newer supports the "flush by address" instruction, in + * addition to the "flush by line" instruction provided by older versions of + * the core. This newer instruction is used by preference when it is + * available. + */ + +#ifdef NIOS2_FLUSHDA_SUPPORTED +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushda (%0)" :: "r" (i)); +#else +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushd (%0)" :: "r" (i)); +#endif /* NIOS2_FLUSHDA_SUPPORTED */ + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are written back to memory. + */ + +void alt_dcache_flush (void* start, alt_u32 len) +{ +#if NIOS2_DCACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + * + * SPR 196942, 2006.01.13: The cache flush loop below will use the + * 'flushda' instruction if its available; in that case each line + * must be flushed individually, and thus 'len' cannot be trimmed. + */ + #ifndef NIOS2_FLUSHDA_SUPPORTED + if (len > NIOS2_DCACHE_SIZE) + { + len = NIOS2_DCACHE_SIZE; + } + #endif + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA(i); + } + +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush_all.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush_all.c new file mode 100644 index 0000000..80735b7 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush_all.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush_no_writeback.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush_no_writeback.c new file mode 100644 index 0000000..3b277d2 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dcache_flush_no_writeback.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * The INITDA instruction was added to Nios II in the 8.0 release. + * + * The INITDA instruction has one of the following possible behaviors + * depending on the processor configuration: + * 1) Flushes a line by address but does NOT write back dirty data. + * Occurs when a data cache is present that supports INITDA. + * The macro NIOS2_INITDA_SUPPORTED is defined in system.h. + * 2) Takes an unimplemented instruction exception. + * Occurs when a data cache is present that doesn't support INITDA. + * 3) Performs no operation + * Occurs when there is no data cache present. + * The macro NIOS2_DCACHE_SIZE is 0 in system.h. + */ + +#define ALT_FLUSH_DATA_NO_WRITEBACK(i) \ + __asm__ volatile ("initda (%0)" :: "r" (i)); + +/* + * alt_dcache_flush_no_writeback() is called to flush the data cache for a + * memory region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are NOT written back to memory. + * Make sure you really want this behavior. If you aren't 100% sure, + * use the alt_dcache_flush() routine instead. + */ + +void alt_dcache_flush_no_writeback (void* start, alt_u32 len) +{ +#if defined(NIOS2_INITDA_SUPPORTED) + + char* i; + char* end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + +#endif /* NIOS2_INITDA_SUPPORTED */ +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dev.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dev.c new file mode 100644 index 0000000..92f3f2a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dev.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * This file contains the data constructs used to control access to device and + * filesytems. + */ + +/* + * "alt_fs_list" is the head of a linked list of registered filesystems. It is + * initialised as an empty list. New entries can be added using the + * alt_fs_reg() function. + */ + +ALT_LLIST_HEAD(alt_fs_list); + + +/* + * "alt_dev_list" is the head of a linked list of registered devices. It is + * configured at startup to include a single device, "alt_dev_null". This + * device is discussed below. + */ + +extern alt_dev alt_dev_null; /* forward declaration */ + +alt_llist alt_dev_list = {&alt_dev_null.llist, &alt_dev_null.llist}; + +/* + * alt_dev_null_write() is the implementation of the write() function used + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + return len; +} + +/* + * "alt_dev_null" is used to allow output to be redirected to nowhere. It is + * the only device registered before the call to alt_sys_init(). At startup + * stin, stdout & stderr are all directed towards this device so that library + * calls like printf() will be safe but inefectual. + */ + +alt_dev alt_dev_null = { + { + &alt_dev_list, + &alt_dev_list + }, + "/dev/null", + NULL, /* open */ + NULL, /* close */ + NULL, /* write */ + alt_dev_null_write, /* write */ + NULL, /* lseek */ + NULL, /* fstat */ + NULL /* ioctl */ + }; + +/* + * "alt_fd_list_lock" is a semaphore used to control access to the file + * descriptor list. This is used to ensure that access to the list is thread + * safe. + */ + +ALT_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is used to make access to the file descriptor list more + * efficent. It is set to be the value of the highest allocated file + * descriptor. This saves having to search the entire pool of unallocated + * file descriptors when looking for a match. + */ + +alt_32 alt_max_fd = -1; + +/* + * "alt_fd_list" is the file descriptor pool. The first three entries in the + * array are configured as standard in, standard out, and standard error. These + * are all initialised so that accesses are directed to the alt_dev_null + * device. The remaining file descriptors are initialised as unallocated. + * + * The maximum number of file descriptors within the system is specified by the + * user defined macro "ALT_MAX_FD". This is defined in "system.h", which is + * auto-genereated using the projects PTF and STF files. + */ + +alt_fd alt_fd_list[ALT_MAX_FD] = + { + { + &alt_dev_null, /* standard in */ + 0, + 0 + }, + { + &alt_dev_null, /* standard out */ + 0, + 0 + }, + { + &alt_dev_null, /* standard error */ + 0, + 0 + } + /* all other elements are set to zero */ + }; diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dev_llist_insert.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dev_llist_insert.c new file mode 100644 index 0000000..5e8a952 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dev_llist_insert.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" +#include "sys/alt_errno.h" + +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + { + ALT_ERRNO = EINVAL; + return -EINVAL; + } + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + + return 0; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dma_rxchan_open.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dma_rxchan_open.c new file mode 100644 index 0000000..5d461d9 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dma_rxchan_open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered DMA receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_rxchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_rxchan alt_dma_rxchan_open (const char* name) +{ + alt_dma_rxchan dev; + + dev = (alt_dma_rxchan) alt_find_dev (name, &alt_dma_rxchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dma_txchan_open.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dma_txchan_open.c new file mode 100644 index 0000000..99f9181 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_dma_txchan_open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_txchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_txchan alt_dma_txchan_open (const char* name) +{ + alt_dma_txchan dev; + + dev = (alt_dma_txchan) alt_find_dev (name, &alt_dma_txchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_do_ctors.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_do_ctors.c new file mode 100644 index 0000000..be1c134 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_do_ctors.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*constructor) (void); +extern constructor __CTOR_LIST__[]; +extern constructor __CTOR_END__[]; + +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + (*ctor) (); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_do_dtors.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_do_dtors.c new file mode 100644 index 0000000..b61166a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_do_dtors.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*destructor) (void); +extern destructor __DTOR_LIST__[]; +extern destructor __DTOR_END__[]; + +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + (*dtor) (); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_env_lock.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_env_lock.c new file mode 100644 index 0000000..0c5d522 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_env_lock.c @@ -0,0 +1,53 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +/* + * These are the empty env lock/unlock stubs required by newlib. These are + * used to make accesses to environment variables thread safe. The default HAL + * configuration is single threaded, so there is nothing to do here. Note that + * this requires that environment variables are never manipulated by an interrupt + * service routine. + */ + +void __env_lock ( struct _reent *_r ) +{ +} + +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_environ.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_environ.c new file mode 100644 index 0000000..780635a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_environ.c @@ -0,0 +1,42 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * These are the environment variables passed to the C code. By default there + * are no variables registered. An application can manipulate this list using + * getenv() and setenv(). + */ + +char *__env[1] = { 0 }; +char **ALT_ENVIRON = __env; diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_errno.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_errno.c new file mode 100644 index 0000000..4c5ca3e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_errno.c @@ -0,0 +1,44 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file defines the alt_errno global variable. See comments in + * alt_errno.h for the use of this variable. + */ + + +#include "sys/alt_errno.h" +#include "alt_types.h" + +extern int ALT_WEAK *__errno (void); + +int* (*alt_errno) (void) = __errno; diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_entry.S b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_entry.S new file mode 100644 index 0000000..486465b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_entry.S @@ -0,0 +1,360 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the exception entry point code, which saves all the caller saved + * registers and then handles the appropriate exception. It should be pulled + * in using a .globl from all the exception handler routines. This scheme is + * used so that if an interrupt is never registered, then this code will not + * appear in the generated executable, thereby improving code footprint. + * + * If an external interrpt controller (EIC) is present, it will supply an + * interrupt vector address to the processor when an interrupt occurs. For + * The Altera Vectored Interrupt Controller (VIC) driver will establish a + * vector table and the processor will jump directly to the appropriate + * table entry, funnel routine, and then user ISR. This will bypass this code + * in entirety. This code might still be linked into a system with an EIC, + * but would then be used only for non-interrupt exceptions. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + + /* + * The top and bottom of the exception stack + */ +#ifdef ALT_EXCEPTION_STACK + + .globl __alt_exception_stack_pointer + +#ifdef ALT_STACK_CHECK + + .globl __alt_exception_stack_limit + + /* + * We need to store the value of the stack limit after interrupt somewhere. + */ + .globl alt_exception_old_stack_limit + +#endif +#endif + + .section .exceptions.entry.label, "xa" + + .globl alt_exception + .type alt_exception, @function +alt_exception: + + .section .exceptions.entry, "xa" + +#ifdef ALT_EXCEPTION_STACK + +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + movhi et, %hiadj(__alt_exception_stack_pointer - 80) + addi et, et, %lo(__alt_exception_stack_pointer - 80) + stw sp, 76(et) + mov sp, et + +#ifdef ALT_STACK_CHECK + movhi et, %hiadj(__alt_exception_stack_limit) + addi et, et, %lo(__alt_exception_stack_limit) + stw et, %gprel(alt_stack_limit_value)(gp) +#endif + +#else + /* + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios2 ABI + * documentation for details). + */ + + addi sp, sp, -76 + +#ifdef ALT_STACK_CHECK + + bltu sp, et, .Lstack_overflow + +#endif + +#endif + + stw ra, 0(sp) + + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + stw r1, 8(sp) + stw r2, 12(sp) + stw r3, 16(sp) + stw r4, 20(sp) + stw r5, 24(sp) + stw r6, 28(sp) + stw r7, 32(sp) + + rdctl r5, estatus + + stw r8, 36(sp) + stw r9, 40(sp) + stw r10, 44(sp) + stw r11, 48(sp) + stw r12, 52(sp) + stw r13, 56(sp) + stw r14, 60(sp) + stw r15, 64(sp) + + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + + /* + * The interrupt testing code (.exceptions.irqtest) will be + * linked here. If the Internal Interrupt Controller (IIC) is + * present (an EIC is not present), the presense of an interrupt + * is determined by examining CPU control registers or an interrupt + * custom instruction, if present. + * + * If the IIC is used and an interrupt is active, the code linked + * here will call the HAL IRQ handler (alt_irq_handler()) which + * successively calls registered interrupt handler(s) until no + * interrupts remain pending. It then jumps to .exceptions.exit. If + * there is no interrupt then it continues to .exception.notirq, below. + */ + + .section .exceptions.notirq, "xa" + + /* + * Prepare to service unimplemtned instructions or traps, + * each of which is optionally inked into section .exceptions.soft, + * which will preceed .exceptions.unknown below. + * + * Unlike interrupts, we want to skip the exception-causing instructon + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* Don't re-issue */ + ldw r2, -4(ea) /* Instruction that caused exception */ + + /* + * Other exception handling code, if enabled, will be linked here. + * This includes unimplemted (multiply/divide) instruction support + * (a BSP generaton option), and a trap handler (that would typically + * be augmented with user-specific code). These are not linked in by + * default. + */ + + /* + * In the context of linker sections, "unknown" are all exceptions + * not handled by the built-in handlers above (interupt, and trap or + * unimplemented instruction decoding, if enabled). + * + * Advanced exception types can be serviced by registering a handler. + * To do so, enable the "Enable Instruction-related Exception API" HAL + * BSP setting. If this setting is disabled, this handler code will + * either break (if the debug core is present) or enter an infinite + * loop because we don't how how to handle the exception. + */ + .section .exceptions.unknown +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + /* + * The C-based HAL routine alt_instruction_exception_entry() will + * attempt to service the exception by calling a user-registered + * exception handler using alt_instruction_exception_register(). + * If no handler was registered it will either break (if the + * debugger is present) or go into an infinite loop since the + * handling behavior is undefined; in that case we will not return here. + */ + + /* Load exception-causing address as first argument (r4) */ + addi r4, ea, -4 + + /* Call the instruction-exception entry */ + call alt_instruction_exception_entry + + /* + * If alt_instruction_exception_entry() returned, the exception was + * serviced by a user-registered routine. Its return code (now in r2) + * indicates whether to re-issue or skip the exception-causing + * instruction + * + * Return code was 0: Skip. The instruction after the exception is + * already stored in 72(sp). + */ + bne r2, r0, .Lexception_exit + + /* + * Otherwise, modify 72(sp) to re-issue the instruction that caused the + * exception. + */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + +#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */ + + /* + * We got here because an instruction-related exception occured, but the + * handler API was not compiled in. We do not presume to know how to + * handle it. If the debugger is present, break, otherwise hang. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious + * interrupts) + */ +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break +#else + /* + * If there is no debug stub then a BREAK will probably cause a reboot. + * An infinate loop will probably be more useful. + */ +0: + br 0b +#endif /* NIOS2_HAS_DEBUG_STUB */ + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + + .section .exceptions.exit.label +.Lexception_exit: + + .section .exceptions.exit, "xa" + + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + ldw ra, 0(sp) + + wrctl estatus, r5 + + ldw r1, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + +#ifdef ALT_EXCEPTION_STACK +#ifdef ALT_STACK_CHECK + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif +#endif + + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + +#ifdef ALT_EXCEPTION_STACK + +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_stack_limit_value)(gp) + stw zero, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + ldw sp, 76(sp) + +#else + addi sp, sp, 76 + +#endif + + /* + * Return to the interrupted instruction. + */ + + eret + +#ifdef ALT_STACK_CHECK + +.Lstack_overflow: + break 3 + +#endif + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_muldiv.S b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_muldiv.S new file mode 100644 index 0000000..6a794a3 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_muldiv.S @@ -0,0 +1,583 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the software multiply/divide handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_muldiv +alt_exception_muldiv: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + + .section .exceptions.soft, "xa" + + + /* INSTRUCTION EMULATION + * --------------------- + * + * Nios II processors generate exceptions for unimplemented instructions. + * The routines below emulate these instructions. Depending on the + * processor core, the only instructions that might need to be emulated + * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu. + * + * The emulations match the instructions, except for the following + * limitations: + * + * 1) The emulation routines do not emulate the use of the exception + * temporary register (et) as a source operand because the exception + * handler already has modified it. + * + * 2) The routines do not emulate the use of the stack pointer (sp) or the + * exception return address register (ea) as a destination because + * modifying these registers crashes the exception handler or the + * interrupted routine. + * + * 3) To save code size, the routines do not emulate the use of the + * breakpoint registers (ba and bt) as operands. + * + * Detailed Design + * --------------- + * + * The emulation routines expect the contents of integer registers r0-r31 + * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The + * routines retrieve source operands from the stack and modify the + * destination register's value on the stack prior to the end of the + * exception handler. Then all registers except the destination register + * are restored to their previous values. + * + * The instruction that causes the exception is found at address -4(ea). + * The instruction's OP and OPX fields identify the operation to be + * performed. + * + * One instruction, muli, is an I-type instruction that is identified by + * an OP field of 0x24. + * + * muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24- + * 27 22 6 0 <-- LSB of field + * + * The remaining emulated instructions are R-type and have an OP field + * of 0x3a. Their OPX fields identify them. + * + * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a- + * 27 22 17 11 6 0 <-- LSB of field + * + * + */ + + + /* + * Split the instruction into its fields. We need 4*A, 4*B, and 4*C as + * offsets to the stack pointer for access to the stored register values. + */ + /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */ + roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */ + roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */ + roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */ + srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */ + xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */ + roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */ + andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */ + xori r3, r3, 0x40 + andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */ + andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */ + andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */ + + /* Now either + * r5 = OP + * r3 = 4*(A^16) + * r4 = IMM16 (sign extended) + * r6 = 4*(B^16) + * r7 = 4*(C^16) + * or + * r5 = OP + */ + + + /* + * Save everything on the stack to make it easy for the emulation routines + * to retrieve the source register operands. The exception entry code has + * already saved some of this so we don't need to do it all again. + */ + + addi sp, sp, -60 + stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */ + /* Register at and r2-r15 have already been saved. */ + + stw r16, 0(sp) + stw r17, 4(sp) + stw r18, 8(sp) + stw r19, 12(sp) + stw r20, 16(sp) + stw r21, 20(sp) + stw r22, 24(sp) + stw r23, 28(sp) + /* et @ 32 - Has already been changed.*/ + /* bt @ 36 - Usually isn't an operand. */ + stw gp, 40(sp) + stw sp, 44(sp) + stw fp, 48(sp) + /* ea @ 52 - Don't bother to save - it's already been changed */ + /* ba @ 56 - Breakpoint register usually isn't an operand */ + /* ra @ 60 - Has already been saved */ + + + /* + * Prepare for either multiplication or division loop. + * They both loop 32 times. + */ + movi r14, 32 + + + /* + * Get the operands. + * + * It is necessary to check for muli because it uses an I-type instruction + * format, while the other instructions are have an R-type format. + */ + add r3, r3, sp /* r3 = address of A-operand. */ + ldw r3, 0(r3) /* r3 = A-operand. */ + movi r15, 0x24 /* muli opcode (I-type instruction format) */ + beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */ + + add r6, r6, sp /* r6 = address of B-operand. */ + ldw r6, 0(r6) /* r6 = B-operand. */ + /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */ + /* IMM16 not needed, align OPX portion */ + /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */ + srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */ + andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */ + + /* Now + * r5 = OP + * r3 = src1 + * r6 = src2 + * r4 = OPX (no longer can be muli) + * r7 = 4*(C^16) + * r14 = loop counter + */ + + /* ILLEGAL-INSTRUCTION EXCEPTION + * ----------------------------- + * + * This code is for Nios II cores that generate exceptions when attempting + * to execute illegal instructions. Nios II cores that support an + * illegal-instruction exception are identified by the presence of the + * macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h . + * + * Remember that illegal instructions are different than unimplemented + * instructions. Illegal instructions are instruction encodings that + * have not been defined by the Nios II ISA. Unimplemented instructions + * are legal instructions that must be emulated by some Nios II cores. + * + * If we get here, all instructions except multiplies and divides + * are illegal. + * + * This code assumes that OP is not muli (because muli was tested above). + * All other multiplies and divides are legal. Anything else is illegal. + */ + + movi r8, 0x3a /* OP for R-type mul* and div* */ + bne r5, r8, .Lnot_muldiv + + /* r15 already is 0x24 */ /* OPX of divu */ + beq r4, r15, .Ldivide + + movi r15,0x27 /* OPX of mul */ + beq r4, r15, .Lmultiply + + movi r15,0x07 /* OPX of mulxuu */ + beq r4, r15, .Lmultiply + + movi r15,0x17 /* OPX of mulxsu */ + beq r4, r15, .Lmultiply + + movi r15,0x1f /* OPX of mulxss */ + beq r4, r15, .Lmultiply + + movi r15,0x25 /* OPX of div */ + bne r4, r15, .Lnot_muldiv + + + /* DIVISION + * + * Divide an unsigned dividend by an unsigned divisor using + * a shift-and-subtract algorithm. The example below shows + * 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a + * single register to store both the dividend and the quotient, + * allowing both values to be shifted with a single instruction. + * + * remainder dividend:quotient + * --------- ----------------- + * initialize 00000000 00101011: + * shift 00000000 0101011:_ + * remainder >= divisor? no 00000000 0101011:0 + * shift 00000000 101011:0_ + * remainder >= divisor? no 00000000 101011:00 + * shift 00000001 01011:00_ + * remainder >= divisor? no 00000001 01011:000 + * shift 00000010 1011:000_ + * remainder >= divisor? no 00000010 1011:0000 + * shift 00000101 011:0000_ + * remainder >= divisor? no 00000101 011:00000 + * shift 00001010 11:00000_ + * remainder >= divisor? yes 00001010 11:000001 + * remainder -= divisor - 00000111 + * ---------- + * 00000011 11:000001 + * shift 00000111 1:000001_ + * remainder >= divisor? yes 00000111 1:0000011 + * remainder -= divisor - 00000111 + * ---------- + * 00000000 1:0000011 + * shift 00000001 :0000011_ + * remainder >= divisor? no 00000001 :00000110 + * + * The quotient is 00000110. + */ + +.Ldivide: + /* + * Prepare for division by assuming the result + * is unsigned, and storing its "sign" as 0. + */ + movi r17, 0 + + + /* Which division opcode? */ + xori r15, r4, 0x25 /* OPX of div */ + bne r15, zero, .Lunsigned_division + + + /* + * OPX is div. Determine and store the sign of the quotient. + * Then take the absolute value of both operands. + */ + xor r17, r3, r6 /* MSB contains sign of quotient */ + bge r3, zero, 0f + sub r3, zero, r3 /* -r3 */ +0: + bge r6, zero, 0f + sub r6, zero, r6 /* -r6 */ +0: + + +.Lunsigned_division: + /* Initialize the unsigned-division loop. */ + movi r13, 0 /* remainder = 0 */ + + /* Now + * r3 = dividend : quotient + * r4 = 0x25 for div, 0x24 for divu + * r6 = divisor + * r13 = remainder + * r14 = loop counter (already initialized to 32) + * r17 = MSB contains sign of quotient + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Ldivide_loop: + + /* + * Division: + * + * (remainder:dividend:quotient) <<= 1; + */ + slli r13, r13, 1 + cmplt r15, r3, zero /* r15 = MSB of r3 */ + or r13, r13, r15 + slli r3, r3, 1 + + + /* + * if (remainder >= divisor) + * { + * set LSB of quotient + * remainder -= divisor; + * } + */ + bltu r13, r6, .Ldiv_skip + ori r3, r3, 1 + sub r13, r13, r6 +.Ldiv_skip: + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Ldivide_loop + + mov r9, r3 + + + /* Now + * r9 = quotient + * r4 = 0x25 for div, 0x24 for divu + * r7 = 4*(C^16) + * r17 = MSB contains sign of quotient + */ + + + /* + * Conditionally negate signed quotient. If quotient is unsigned, + * the sign already is initialized to 0. + */ + bge r17, zero, .Lstore_result + sub r9, zero, r9 /* -r9 */ + + br .Lstore_result + + + + + /* MULTIPLICATION + * + * A "product" is the number that one gets by summing a "multiplicand" + * several times. The "multiplier" specifies the number of copies of the + * multiplicand that are summed. + * + * Actual multiplication algorithms don't use repeated addition, however. + * Shift-and-add algorithms get the same answer as repeated addition, and + * they are faster. To compute the lower half of a product (pppp below) + * one shifts the product left before adding in each of the partial products + * (a * mmmm) through (d * mmmm). + * + * To compute the upper half of a product (PPPP below), one adds in the + * partial products (d * mmmm) through (a * mmmm), each time following the + * add by a right shift of the product. + * + * mmmm + * * abcd + * ------ + * #### = d * mmmm + * #### = c * mmmm + * #### = b * mmmm + * #### = a * mmmm + * -------- + * PPPPpppp + * + * The example above shows 4 partial products. Computing actual Nios II + * products requires 32 partials. + * + * It is possible to compute the result of mulxsu from the result of mulxuu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rA. + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + * + * It is possible to compute the result of mulxss from the result of mulxsu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rB. + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + * + */ + +.Lmul_immed: + /* Opcode is muli. Change it into mul for remainder of algorithm. */ + mov r7, r6 /* Field B is dest register, not field C. */ + mov r6, r4 /* Field IMM16 is src2, not field B. */ + movi r4, 0x27 /* OPX of mul is 0x27 */ + +.Lmultiply: + /* Initialize the multiplication loop. */ + movi r9, 0 /* mul_product = 0 */ + movi r10, 0 /* mulxuu_product = 0 */ + mov r11, r6 /* save original multiplier for mulxsu and mulxss */ + mov r12, r6 /* mulxuu_multiplier (will be shifted) */ + movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */ + + /* Now + * r3 = multiplicand + * r6 = mul_multiplier + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r12 = mulxuu_multiplier + * r14 = loop counter (already initialized) + * r15 = temp + * r16 = 1 + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Lmultiply_loop: + + /* + * mul_product <<= 1; + * lsb = multiplier & 1; + */ + slli r9, r9, 1 + andi r15, r12, 1 + + /* + * if (lsb == 1) + * { + * mulxuu_product += multiplicand; + * } + */ + beq r15, zero, .Lmulx_skip + add r10, r10, r3 + cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */ + ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */ +.Lmulx_skip: + + /* + * if (MSB of mul_multiplier == 1) + * { + * mul_product += multiplicand; + * } + */ + bge r6, zero, .Lmul_skip + add r9, r9, r3 +.Lmul_skip: + + /* + * mulxuu_product >>= 1; logical shift + * mul_multiplier <<= 1; done with MSB + * mulx_multiplier >>= 1; done with LSB + */ + srli r10, r10, 1 + or r10, r10, r15 /* OR in the saved carry bit. */ + slli r6, r6, 1 + srli r12, r12, 1 + + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Lmultiply_loop + + + /* + * Multiply emulation loop done. + */ + + /* Now + * r3 = multiplicand + * r4 = OPX + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r15 = temp + */ + + + /* + * Select/compute the result based on OPX. + */ + + + /* OPX == mul? Then store. */ + xori r15, r4, 0x27 + beq r15, zero, .Lstore_result + + /* It's one of the mulx.. opcodes. Move over the result. */ + mov r9, r10 + + /* OPX == mulxuu? Then store. */ + xori r15, r4, 0x07 + beq r15, zero, .Lstore_result + + /* Compute mulxsu + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + */ + bge r3, zero, .Lmulxsu_skip + sub r9, r9, r11 +.Lmulxsu_skip: + + /* OPX == mulxsu? Then store. */ + xori r15, r4, 0x17 + beq r15, zero, .Lstore_result + + /* Compute mulxss + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + */ + bge r11, zero, .Lmulxss_skip + sub r9, r9, r3 +.Lmulxss_skip: + /* At this point, assume that OPX is mulxss, so store */ + + +.Lstore_result: + add r7, r7, sp + stw r9, 0(r7) + + ldw r16, 0(sp) + ldw r17, 4(sp) + ldw r18, 8(sp) + ldw r19, 12(sp) + ldw r20, 16(sp) + ldw r21, 20(sp) + ldw r22, 24(sp) + ldw r23, 28(sp) + + /* bt @ 32 - Breakpoint register usually isn't an operand. */ + /* et @ 36 - Don't corrupt et. */ + /* gp @ 40 - Don't corrupt gp. */ + /* sp @ 44 - Don't corrupt sp. */ + ldw fp, 48(sp) + /* ea @ 52 - Don't corrupt ea. */ + /* ba @ 56 - Breakpoint register usually isn't an operand. */ + + addi sp, sp, 60 + + br .Lexception_exit + + +.Lnot_muldiv: + + addi sp, sp, 60 + + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_trap.S b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_trap.S new file mode 100644 index 0000000..bd9a9f5 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exception_trap.S @@ -0,0 +1,81 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the trap exception handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_trap +alt_exception_trap: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + .section .exceptions.soft, "xa" + +.Ltrap_handler: + + /* + * Did a trap instruction cause the exception? + * + * The instruction which the exception occurred on has been loaded + * into r2 by code in alt_exception_entry.S + * + */ + + movhi r3,0x003b /* upper half of trap opcode */ + ori r3,r3,0x683a /* lower half of trap opcode */ + bne r2,r3,.Lnot_trap + + /* + * There is no trap handler defined here, and so executing a trap + * instruction causes a software break. If you provide a trap handler, + * then you must replace the break instruction below with your handler. + * Your handler must preserve ea and the usual callee saved registers. + */ + + break + + br .Lexception_exit + +.Lnot_trap: + + + .section .exceptions.exit.label +.Lexception_exit: + + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_execve.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_execve.c new file mode 100644 index 0000000..51bfcc4 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_execve.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * execve() is used by newlib to launch new processes. This is unsupported in + * the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_EXECVE is mapped onto the execve() system call in alt_syscall.h + */ + +int ALT_EXECVE (char *name, char ** argv, char** env) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(execve); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exit.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exit.c new file mode 100644 index 0000000..46cbe18 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_exit.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_sim.h" +#include "os/alt_hooks.h" +#include "os/alt_syscall.h" + +#include "alt_types.h" +#include "sys/alt_log_printf.h" +/* + * _exit() is called by exit() in order to terminate the current process. + * Typically this is called when main() completes. It should never return. + * Since there is nowhere to go once this process completes, this + * implementation simply blocks forever. + * + * Note that interrupts are not disabled so that execution outside of this + * thread is allowed to continue. + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + /* ALT_LOG - please see HAL/inc/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fcntl.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fcntl.c new file mode 100644 index 0000000..382fa43 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fcntl.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include +#include + +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#define ALT_FCNTL_FLAGS_MASK ((alt_u32) (O_APPEND | O_NONBLOCK)) + +/* + * fcntl() is a limited implementation of the standard fcntl() system call. + * It can be used to change the state of the flags associated with an open + * file descriptor. Normally these flags are set during the call to + * open(). It is anticipated that the main use of this function will be to + * change the state of a device from blocking to non-blocking (where this is + * supported). + * + * The input argument "fd" is the file descriptor to be manipulated. "cmd" + * is the command to execute. This can be either F_GETFL (return the + * current value of the flags) or F_SETFL (set the value of the flags). + * + * If "cmd" is F_SETFL then the argument "arg" is the new value of flags, + * otherwise "arg" is ignored. Only the flags: O_APPEND and O_NONBLOCK + * can be updated by a call to fcntl(). All other flags remain + * unchanged. + * + * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h + */ + +int ALT_FCNTL (int file, int cmd, ...) +{ + alt_fd* fd; + long flags; + va_list argp; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + switch (cmd) + { + case F_GETFL: + return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK); + case F_SETFL: + va_start(argp, cmd); + flags = va_arg(argp, long); + fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK; + fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK); + va_end(argp); + return 0; + default: + ALT_ERRNO = EINVAL; + return -1; + } + } + + ALT_ERRNO = EBADFD; + return -1; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fd_lock.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fd_lock.c new file mode 100644 index 0000000..162295a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fd_lock.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_lock() is called as a consequence of an ioctl call to gain exclusive + * access to a device, i.e.: + * + * ioctl (fd, TIOCEXCL, NULL); + * + * If there are no other open file descriptors which reference the same + * device, then alt_fd_lock() will grant the lock. Further calls to open() + * for this device will fail until the lock is released. + * + * This is done by calling close() for this file descriptor, or by calling: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * The return value is zero for success, or negative in the case of failure. + */ + +int alt_fd_lock (alt_fd* fd) +{ + int i; + int rc = 0; + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + for (i = 0; i < alt_max_fd; i++) + { + if ((&alt_fd_list[i] != fd) && (alt_fd_list[i].dev == fd->dev)) + { + rc = -EACCES; + goto alt_fd_lock_exit; + } + } + fd->fd_flags |= ALT_FD_EXCL; + + alt_fd_lock_exit: + + ALT_SEM_POST(alt_fd_list_lock); + return rc; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fd_unlock.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fd_unlock.c new file mode 100644 index 0000000..5f50386 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fd_unlock.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_unlock() is the inverse of alt_fd_lock(). It is called as a + * consequence of a TIOCNXCL ioctl request, e.g: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * It enables multiple file descriptors to exist for the same device. This + * is normally the case, but it may have been disabled by a previous call to + * alt_fd_lock(). + * + * Return zero on sucess, and a negative value on failure. + * + * The current implementation always succeeds. + */ + +int alt_fd_unlock (alt_fd* fd) +{ + fd->fd_flags &= ~ALT_FD_EXCL; + return 0; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_find_dev.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_find_dev.c new file mode 100644 index 0000000..964f63f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_find_dev.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_dev() is used by open() in order to locate a previously registered + * device with the name "name". The input argument "llist" is a pointer to the + * head of the device list to search. + * + * The return value is a pointer to the matching device, or NULL if there is + * no match. + * + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + alt_dev* next = (alt_dev*) llist->next; + alt_32 len; + + len = strlen(name) + 1; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + { + + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_find_file.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_find_file.c new file mode 100644 index 0000000..ae30e93 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_find_file.c @@ -0,0 +1,89 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_file() is used by open() in order to locate a previously registered + * filesystem that owns that mount point that contains the file named "name". + * + * The return value is a pointer to the matching filesystem, or NULL if there is + * no match. + * + * A match is considered to have been found if the filesystem name followed by + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + alt_dev* next = (alt_dev*) alt_fs_list.next; + + alt_32 len; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + { + len = strlen(next->name); + + if (next->name[len-1] == '/') + { + len -= 1; + } + + if (((name[len] == '/') || (name[len] == '\0')) && + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_flash_dev.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_flash_dev.c new file mode 100644 index 0000000..0acffc7 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_flash_dev.c @@ -0,0 +1,69 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.c - Functions to register a flash device to the "generic" flash * +* interface * +* * +* Author PRR * +* * +******************************************************************************/ + +#include +#include "sys/alt_llist.h" +#include "sys/alt_flash_dev.h" +#include "priv/alt_file.h" + +ALT_LLIST_HEAD(alt_flash_dev_list); + +alt_flash_fd* alt_flash_open_dev(const char* name) +{ + alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list); + + if ((dev) && dev->open) + { + return dev->open(dev, name); + } + + return dev; +} + +void alt_flash_close_dev(alt_flash_fd* fd) +{ + if (fd && fd->close) + { + fd->close(fd); + } + return; +} + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fork.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fork.c new file mode 100644 index 0000000..b6edbb5 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fork.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * The fork() system call is used by newlib to create a duplicate copy of the + * curent process. This is unsupported in the HAL environment. However a + * "do-nothing" implementation is still provied for newlib compatability. + * + * ALT_FORK is mapped onto the fork() system call in alt_syscall.h + */ + +int ALT_FORK (void) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(fork); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fs_reg.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fs_reg.c new file mode 100644 index 0000000..e88a340 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fs_reg.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * The alt_fs_reg() function is used to register a file system. Once registered + * a device can be accessed using the standard posix calls: open(), read(), + * write() etc. + * + * System behaviour is undefined in the event that a file system is registered + * with a name that conflicts with an existing device or file system. + * + * alt_fs_reg() is not thread safe in the sense that there should be no other + * thread using the file system list at the time that alt_dev_reg() is called. In + * practice this means that alt_fs_reg() should only be called while operating + * in a single threaded mode. The expectation is that it will only be called + * by the file system initilisation functions invoked by alt_sys_init(), which in + * turn should only be called by the single threaded C startup code. + * + * A return value of zero indicates success. A negative return value indicates + * failure. + */ + +int alt_fs_reg (alt_dev* dev) +{ + /* + * check that the device has a name. + */ + + if (!dev->name) + { + return -ENODEV; + } + + /* + * register the file system. + */ + + alt_llist_insert(&alt_fs_list, &dev->llist); + + return 0; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fstat.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fstat.c new file mode 100644 index 0000000..3248764 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_fstat.c @@ -0,0 +1,128 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The fstat() system call is used to obtain information about the capabilities + * of an open file descriptor. By default file descriptors are marked as + * being character devices. If a device or file system wishes to advertise + * alternative capabilities then they can register an fstat() function within + * their associated alt_dev structure. This will be called to fill in the + * entries in the imput "st" structure. + * + * This function is provided for compatability with newlib. + * + * ALT_FSTAT is mapped onto the fstat() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as character devices for provided stdio devices. + */ +int ALT_FSTAT (int file, struct stat *st) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + st->st_mode = _IFCHR; + return 0; + default: + return -1; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(fstat); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + alt_fd* fd; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + { + return fd->dev->fstat(fd, st); + } + + /* + * If no function is provided, mark the fd as belonging to a character + * device. + */ + + else + { + st->st_mode = _IFCHR; + return 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_get_fd.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_get_fd.c new file mode 100644 index 0000000..f42944b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_get_fd.c @@ -0,0 +1,105 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * alt_get_fd() is called to allocate a new file descriptor from the file + * descriptor pool. If a file descriptor is succesfully allocated, it is + * configured to refer to device "dev". + * + * The return value is the index of the file descriptor structure (i.e. + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + alt_32 i; + int rc = -EMFILE; + + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + /* + * Search through the list of file descriptors, and allocate the first + * free descriptor that's found. + * + * If a free descriptor is found, then the value of "alt_max_fd" is + * updated accordingly. "alt_max_fd" is a 'highwater mark' which + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + { + if (!alt_fd_list[i].dev) + { + alt_fd_list[i].dev = dev; + if (i > alt_max_fd) + { + alt_max_fd = i; + } + rc = i; + goto alt_get_fd_exit; + } + } + + alt_get_fd_exit: + + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + + return rc; +} + + + + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_getchar.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_getchar.c new file mode 100644 index 0000000..3e7df79 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_getchar.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#include "priv/alt_file.h" +#include "unistd.h" +#endif + +/* + * Uses the ALT_DRIVER_READ() macro to call directly to driver if available. + * Otherwise, uses newlib provided getchar() routine. + */ +int +alt_getchar(void) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); + char c; + + if (ALT_DRIVER_READ(ALT_STDIN_DEV, &c, 1, alt_fd_list[STDIN_FILENO].fd_flags) <= 0) { + return -1; + } + return c; +#else + return getchar(); +#endif +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_getpid.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_getpid.c new file mode 100644 index 0000000..b63ec33 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_getpid.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * The getpid() system call is used by newlib to obtain the current process + * id. Since there is only ever a single process in the HAL environment, + * this just returns a constant. + * + * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h + */ + +int ALT_GETPID (void) +{ + return 0; +} + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_gettod.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_gettod.c new file mode 100644 index 0000000..46b12c2 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_gettod.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_alarm.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +struct timezone alt_timezone = {0, 0}; +struct timeval alt_resettime = {0, 0}; + +/* + * gettimeofday() can be called to obtain a time structure which indicates the + * current "wall clock" time. This is calculated using the elapsed number of + * system clock ticks, and the value of "alt_resettime" and "alt_timezone" set + * through the last call to settimeofday(). + * + * Warning: if this function is called concurrently with a call to + * settimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_GETTIMEOFDAY is mapped onto the gettimeofday() system call in + * alt_syscall.h + */ + + +#if defined (__GNUC__) && (__GNUC__ >= 4) +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, void *ptimezone_vptr) +{ + struct timezone *ptimezone = (struct timezone*)ptimezone_vptr; +#else +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, struct timezone *ptimezone) +{ +#endif + + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* + * Check to see if the system clock is running. This is indicated by a + * non-zero system clock rate. If the system clock is not running, an error + * is generated and the contents of "ptimeval" and "ptimezone" are not + * updated. + */ + + if (tick_rate) + { + ptimeval->tv_sec = alt_resettime.tv_sec + nticks/tick_rate; + ptimeval->tv_usec = alt_resettime.tv_usec + + (alt_u32)(((alt_u64)nticks*(ALT_US/tick_rate))%ALT_US); + + while(ptimeval->tv_usec < 0) { + if (ptimeval->tv_sec <= 0) + { + ptimeval->tv_sec = 0; + ptimeval->tv_usec = 0; + break; + } + else + { + ptimeval->tv_sec--; + ptimeval->tv_usec += ALT_US; + } + } + + while(ptimeval->tv_usec >= ALT_US) { + ptimeval->tv_sec++; + ptimeval->tv_usec -= ALT_US; + } + + if (ptimezone) + { + ptimezone->tz_minuteswest = alt_timezone.tz_minuteswest; + ptimezone->tz_dsttime = alt_timezone.tz_dsttime; + } + + return 0; + } + + return -ENOTSUP; +} + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_gmon.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_gmon.c new file mode 100644 index 0000000..fce7587 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_gmon.c @@ -0,0 +1,272 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include + +#include "priv/nios2_gmon_data.h" + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" + + +/* Macros */ + +/* How large should the bins be which we use to generate the histogram */ +#define PCSAMPLE_BYTES_PER_BUCKET 32 + +#define NIOS2_READ_EA(dest) __asm__ ("mov %0, ea" : "=r" (dest)) + +/* The compiler inserts calls to mcount() at the start of + * every function call. The structure mcount_fn_arc records t + * he return address of the function called (in from_pc) + * and the return address of the mcount function + * (in self_pc). The number of times this arc is executed is + * recorded in the field count. + */ +struct mcount_fn_arc +{ + struct mcount_fn_arc * next; + void * from_pc; + unsigned int count; +}; + +/* We need to maintain a list of pointers to the heads of each adjacency + * list so that we can find them when writing out the gmon.out file. Since + * we don't know at the start of program execution how many functions will + * be called we use a list structure to do this. + */ +struct mcount_fn_entry +{ + struct mcount_fn_entry * next; + void * self_pc; + struct mcount_fn_arc * arc_head; +}; + +/* function prototypes */ + +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) __attribute__ ((no_instrument_function)); + +static __inline__ void * mcount_allocate(unsigned int size) __attribute__ ((no_instrument_function)); +static int nios2_pcsample_init(void) __attribute__ ((no_instrument_function)); +static alt_u32 nios2_pcsample(void* alarm) __attribute__ ((no_instrument_function)); + +/* global variables */ + +/* stext and etext are defined in the linker script */ +extern char stext[]; +extern char etext[]; + +/* Is the PC sampling stuff enabled yet? */ +static int pcsample_need_init = 1; + +#define HASH_BUCKETS 64 /* Must be a power of 2 */ + +/* This points to the list of adjacency list pointers. */ +struct mcount_fn_entry * __mcount_fn_head[HASH_BUCKETS]; + +/* pointer to the in-memory buffer containing the histogram */ +static unsigned short* s_pcsamples = 0; + +/* the address of the start and end of text section */ +static const unsigned int s_low_pc = (unsigned int)stext; +static const unsigned int s_high_pc = (unsigned int)etext; + +/* the alarm structure to register for pc sampling */ +static alt_alarm s_nios2_pcsample_alarm; + +unsigned int alt_gmon_data[GMON_DATA_SIZE] = +{ + 0x6e6f6d67, /* "gmon" */ + GMON_DATA_SIZE, + 0, + (unsigned int)stext, + (unsigned int)etext, + PCSAMPLE_BYTES_PER_BUCKET, + 0, + (unsigned int)__mcount_fn_head, + (unsigned int)(__mcount_fn_head + HASH_BUCKETS) +}; + +/* This holds the current slab of memory we're allocating out of */ +static char * mcount_slab_ptr = 0; +static int mcount_slab_size = 0; + +#define MCOUNT_SLAB_INCREMENT 1020 + + +/* + * We can't use malloc to allocate memory because that's too complicated, and + * can't be called at interrupt time. Use the lower level allocator instead + * because that's interrupt safe (and because we never free anything). + * + * For speed, we allocate a block of data at once. + */ +static __inline__ void * mcount_allocate(unsigned int size) +{ + void * data; + + if (size > mcount_slab_size) + { + mcount_slab_ptr = sbrk(MCOUNT_SLAB_INCREMENT); + mcount_slab_size = MCOUNT_SLAB_INCREMENT; + } + + data = mcount_slab_ptr; + mcount_slab_ptr += size; + mcount_slab_size -= size; + + return data; +} + + +/* + * Add the arc with the values of frompc and topc given to the graph. + * This function might be called at interrupt time so must be able to + * cope with reentrancy. + * + * The fast case, where we have already allocated a function arc, has been + * handled by the assmebler code. + */ +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) +{ + alt_irq_context context; + struct mcount_fn_arc * arc_entry; + + /* Keep trying to start up the PC sampler until it is running. + * (It can't start until the timer is going). + */ + if (pcsample_need_init) + { + pcsample_need_init = 0; + pcsample_need_init = nios2_pcsample_init(); + } + + /* + * We must disable interrupts around the allocation and the list update to + * prevent corruption if the instrumented function is re-entrant. + * + * It's safe for the code above to be stepping through the chain and be + * interrupted by this code modifying it - there is an edge case which will + * leave two copies of the same arc on the list (both with count=1), but + * this is dealt with on the host. + */ + context = alt_irq_disable_all(); + + if (fn_entry == NULL) + { + /* Add it to the list of functions we must output later. */ + fn_entry = (struct mcount_fn_entry *)mcount_allocate(sizeof(struct mcount_fn_entry)); + + fn_entry->self_pc = self_pc; + fn_entry->arc_head = NULL; + + fn_entry->next = *fn_head; + *fn_head = fn_entry; + } + + /* We will need a new list entry - if there was a list entry before + * then the assembler code would have handled it. */ + arc_entry = (struct mcount_fn_arc *)mcount_allocate(sizeof(struct mcount_fn_arc)); + + arc_entry->from_pc = from_pc; + arc_entry->count = 1; + + arc_entry->next = fn_entry->arc_head; + fn_entry->arc_head = arc_entry; + + alt_irq_enable_all(context); +} + + +/* + * nios2_pcsample_init starts profiling. + * It is called the first time mcount is called, and on subsequent calls to + * mcount until it returns zero. It initializes the pc histogram and turns on + * timer driven pc sampling. + */ +static int nios2_pcsample_init(void) +{ + unsigned int pcsamples_size; + + /* We sample the PC every tick */ + unsigned int prof_rate = alt_ticks_per_second(); + if (prof_rate == 0) + return 1; + + /* allocate the histogram buffer s_pcsamples */ + pcsamples_size = (s_high_pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples = (unsigned short*)sbrk(pcsamples_size * sizeof(unsigned short)); + + if (s_pcsamples != 0) + { + /* initialize the buffer to zero */ + memset(s_pcsamples, 0, pcsamples_size * sizeof(unsigned short)); + + alt_gmon_data[GMON_DATA_PROFILE_DATA] = (int)s_pcsamples; + alt_gmon_data[GMON_DATA_PROFILE_RATE] = prof_rate; + + /* Sample every tick (it's cheap) */ + alt_alarm_start(&s_nios2_pcsample_alarm, 1, nios2_pcsample, 0); + } + + return 0; +} + + +/* + * Sample the PC value and store it in the histogram + */ +static alt_u32 nios2_pcsample(void* context) +{ + unsigned int pc; + unsigned int bucket; + + /* read the exception return address - this will be + * inaccurate if there are nested interrupts but we + * assume that this is rare and the inaccuracy will + * not be great */ + NIOS2_READ_EA(pc); + + /* + * If we're within the profilable range then increment the relevant + * bucket in the histogram + */ + if (pc >= s_low_pc && pc < s_high_pc && s_pcsamples != 0) + { + bucket = (pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples[bucket]++; + } + + /* Sample every tick */ + return 1; +} + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_icache_flush.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_icache_flush.c new file mode 100644 index 0000000..1662991 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_icache_flush.c @@ -0,0 +1,84 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +void alt_icache_flush (void* start, alt_u32 len) +{ +#if NIOS2_ICACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + */ + + if (len > NIOS2_ICACHE_SIZE) + { + len = NIOS2_ICACHE_SIZE; + } + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * Having flushed the cache, flush any stale instructions in the + * pipeline + */ + + __asm__ volatile ("flushp"); + +#endif /* NIOS2_ICACHE_SIZE > 0 */ +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_icache_flush_all.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_icache_flush_all.c new file mode 100644 index 0000000..dc40ea8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_icache_flush_all.c @@ -0,0 +1,46 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); +#endif +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_iic.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_iic.c new file mode 100644 index 0000000..4821f25 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_iic.c @@ -0,0 +1,106 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" + +/* + * This file implements the HAL Enhanced interrupt API for Nios II processors + * with an internal interrupt controller (IIC). For most routines, this serves + * as a wrapper layer over the legacy interrupt API (which must be used with + * the IIC only). + * + * Use of the enhanced API is recommended so that application and device + * drivers are compatible with a Nios II system configured with an external + * interrupt controller (EIC), or IIC. This will afford maximum portability. + * + * If an EIC is present, the EIC device driver must provide these routines, + * because their operation will be specific to that EIC type. + */ +#ifndef NIOS2_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" +#include "priv/alt_legacy_irq.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); +} + +/** @Function Description: This function enables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_enable(irq); +} + +/** @Function Description: This function disables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_disable(irq); +} + +/** @Function Description: This function to determine if corresponding + * interrupt is enabled. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return Zero if corresponding interrupt is disabled and + * non-zero otherwise. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) +{ + alt_u32 irq_enabled; + + NIOS2_READ_IENABLE(irq_enabled); + + return (irq_enabled & (1 << irq)) ? 1: 0; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* NIOS2_EIC_PRESENT */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_iic_isr_register.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_iic_isr_register.c new file mode 100644 index 0000000..2e6bf5b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_iic_isr_register.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * Provides an interrupt registry mechanism for the any CPUs internal interrupt + * controller (IIC) when the enhanced interrupt API is active. + */ +#ifndef ALT_CPU_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "alt_types.h" +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled + * upon return. Registering a NULL handler will disable the interrupt. + * + * @API Type: External + * @param ic_id Interrupt controller ID + * @param irq IRQ ID number + * @param isr Pointer to interrupt service routine + * @param isr_context Opaque pointer passed to ISR + * @param flags + * @return 0 if successful, else error (-1) + */ +int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + int rc = -EINVAL; + int id = irq; /* IRQ interpreted as the interrupt ID. */ + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all(); + + alt_irq[id].handler = isr; + alt_irq[id].context = isr_context; + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + + alt_irq_enable_all(status); + } + + return rc; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_instruction_exception_entry.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_instruction_exception_entry.c new file mode 100644 index 0000000..5cc8767 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_instruction_exception_entry.c @@ -0,0 +1,203 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. This handler could also be reached + * in the event of a spurious interrupt. + * + * The handler code is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* Function pointer to exception callback routine */ +alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32) = 0x0; + +/* Link entry routine to .exceptions section */ +int alt_instruction_exception_entry (alt_u32 exception_pc) + __attribute__ ((section (".exceptions"))); + +/* + * This is the entry point for instruction-generated exceptions handling. + * This routine will be called by alt_exceptions_entry.S, after it determines + * that an exception could not be handled by handlers that preceed that + * of instruction-generated exceptions (such as interrupts). + * + * For this to function properly, you must register an exception handler + * using alt_instruction_exception_register(). This routine will call + * that handler if it has been registered. Absent a handler, it will + * break break or hang as discussed below. + */ +int alt_instruction_exception_entry (alt_u32 exception_pc) +{ + alt_u32 cause, badaddr; + +/* + * If the processor hardware has the optional EXCEPTIONS & BADADDR registers, + * read them and pass their content to the user handler. These are always + * present if the MMU or MPU is enabled, and optionally for other advanced + * exception types via the "Extra exceptions information" setting in the + * processor (hardware) configuration. + * + * If these registers are not present, the cause field will be set to + * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should + * check the validity of the cause argument before proceeding. + */ +#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO + /* Get exception cause & "badaddr" */ + NIOS2_READ_EXCEPTION(cause); + cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >> + NIOS2_EXCEPTION_REG_CAUSE_OFST ); + + NIOS2_READ_BADADDR(badaddr); +#else + cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT; + badaddr = 0; +#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */ + + if(alt_instruction_exception_handler) { + /* + * Call handler. Its return value indicates whether the exception-causing + * instruction should be re-issued. The code that called us, + * alt_eceptions_entry.S, will look at this value and adjust the ea + * register as necessary + */ + return alt_instruction_exception_handler(cause, exception_pc, badaddr); + } + /* + * We got here because an instruction-generated exception occured, but no + * handler is present. We do not presume to know how to handle it. If the + * debugger is present, break, otherwise hang. + * + * If you've reached here in the debugger, consider examining the + * EXCEPTIONS register cause bit-field, which was read into the 'cause' + * variable above, and compare it against the exceptions-type enumeration + * in alt_exceptions.h. This register is availabe if the MMU or MPU is + * present, or if the "Extra exceptions information" hardware option is + * selected. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious interrupts) + */ + else { +#ifdef NIOS2_HAS_DEBUG_STUB + NIOS2_BREAK(); +#else + while(1) + ; +#endif /* NIOS2_HAS_DEBUG_STUB */ + } + + /* // We should not get here. Remove compiler warning. */ + return NIOS2_EXCEPTION_RETURN_REISSUE_INST; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * This routine indicates whether a particular exception cause will have + * set a valid address into the BADADDR register, which is included + * in the arguments to a user-registered instruction-generated exception + * handler. Many exception types do not set valid contents in BADADDR; + * this is a convenience routine to easily test the validity of that + * argument in your handler. + * + * Note that this routine will return false (0) for cause '12', + * TLB miss. This is because there are four exception types that + * share that cause, two of which do not have a valid BADADDR. You + * must determine BADADDR's validity for these. + * + * Arguments: + * cause: The 5-bit exception cause field of the EXCEPTIONS register, + * shifted to the LSB position. You may pass the 'cause' argument + * in a handler you registered directy to this routine. + * + * Return: 1: BADADDR (bad_addr argument to handler) is valid + * 0: BADADDR is not valid + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause) +{ + switch (cause) { + case NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR: + return 1; + case NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR: + return 1; + case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC: + return 1; + case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION: + return 1; + case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION: + return 1; + case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION: + return 1; + default: + return 0; + } +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_instruction_exception_register.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_instruction_exception_register.c new file mode 100644 index 0000000..395c644 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_instruction_exception_register.c @@ -0,0 +1,82 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* + * The header, alt_exception_handler_registry.h contains a struct describing + * the registered exception handler + */ +#include "priv/alt_exception_handler_registry.h" + +/* + * Pull in the exception entry assembly code. This will not be linked in + * unless this object is linked into the executable (i.e. only if + * alt_instruction_exception_register() is called). + */ +__asm__( "\n\t.globl alt_exception" ); + +/* + * alt_instruction_exception_register() is called to register a handler to + * service instruction-generated exceptions that are not handled by the + * default exception handler code (interrupts, and optionally unimplemented + * instructions and traps). + * + * Passing null (0x0) in the handler argument will disable a previously- + * registered handler. + * + * Note that if no handler is registered, exceptions that are not processed + * using the built-in handler (interrupts, and optionally unimplemented + * instructions and traps) are treated as unknown exceptions, resulting + * in either a break or an infinite loop. + */ +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ) +{ + alt_instruction_exception_handler = exception_handler; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_io_redirect.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_io_redirect.c new file mode 100644 index 0000000..049ed62 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_io_redirect.c @@ -0,0 +1,98 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + + +/* + * alt_open_fd() is similar to open() in that it is used to obtain a file + * descriptor for the file named "name". The "flags" and "mode" arguments are + * identical to the "flags" and "mode" arguments of open(). + * + * The distinction between the two functions is that the file descriptor + * structure to use is passed in as an argument, rather than allocated from the + * list of free file descriptors. + * + * This is used by alt_io_redirect() to redirect the stdin, stdout and stderr + * file descriptors to point to new devices. + * + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + int old; + + old = open (name, flags, mode); + + if (old >= 0) + { + fd->dev = alt_fd_list[old].dev; + fd->priv = alt_fd_list[old].priv; + fd->fd_flags = alt_fd_list[old].fd_flags; + + alt_release_fd (old); + } +} + +/* + * alt_io_redirect() is called once the device/filesystem lists have been + * initialised, but before main(). Its function is to redirect standard in, + * standard out and standard error so that they point to the devices selected by + * the user (as defined in system.h). + * + * Prior to the call to this function, io is directed towards /dev/null. If + * i/o can not be redirected to the requested device, for example if the device + * does not exist, then it remains directed at /dev/null. + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); +} + + + + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_ioctl.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_ioctl.c new file mode 100644 index 0000000..510b40d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_ioctl.c @@ -0,0 +1,170 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/ioctl.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The ioctl() system call is provided so that application code can manipulate + * the i/o capabilities of a device in device specific ways. This is identical + * to the standard posix ioctl() function. + * + * In general this implementation simply vectors ioctl requests to the + * apropriate drivers ioctl function (as registered in the drivers alt_dev + * structure). + * + * However in the case of devices (as oposed to filesystem), the TIOCEXCL and + * TIOCNXCL requests are handled without reference to the driver. These + * requests are used to lock/release a device for exclusive access. + * + * Handling these requests centrally eases the task of device driver + * development. + * + * ALT_IOCTL is mapped onto the ioctl() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that calls ioctl routine of provided stdio devices. + */ +int ALT_IOCTL (int file, int req, void* arg) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDIN_DEV); +#endif +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(ioctl); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDIN_DEV, req, arg); +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDOUT_DEV, req, arg); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDERR_DEV, req, arg); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_IOCTL (int file, int req, void* arg) +{ + alt_fd* fd; + int rc; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + + /* + * In the case of device drivers (not file systems) handle the TIOCEXCL + * and TIOCNXCL requests as special cases. + */ + + if (fd->fd_flags & ALT_FD_DEV) + { + if (req == TIOCEXCL) + { + rc = alt_fd_lock (fd); + goto ioctl_done; + } + else if (req == TIOCNXCL) + { + rc = alt_fd_unlock (fd); + goto ioctl_done; + } + } + + /* + * If the driver provides an ioctl() function, call that to handle the + * request, otherwise set the return code to indicate that the request + * could not be processed. + */ + + if (fd->dev->ioctl) + { + rc = fd->dev->ioctl(fd, req, arg); + } + else + { + rc = -ENOTTY; + } + } + else + { + rc = -EBADFD; + } + +ioctl_done: + + if (rc < 0) + { + ALT_ERRNO = -rc; + } + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_entry.S b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_entry.S new file mode 100644 index 0000000..8ee89e1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_entry.S @@ -0,0 +1,108 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the interrupt exception entry point code, which saves all the + * registers and calls the interrupt handler. It should be pulled in using + * a .globl from alt_irq_register.c. This scheme is used so that if an + * interrupt is never registered, then this code will not appear in the + * generated executable, thereby improving code footprint. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the compiler. + */ + .set noat + + /* + * Pull in the exception handler register save code. + */ + .globl alt_exception + + .globl alt_irq_entry + .section .exceptions.entry.label, "xa" +alt_irq_entry: + + /* + * Section .exceptions.entry is in alt_exception_entry.S + * This saves all the caller saved registers and reads estatus into r5 + */ + + .section .exceptions.irqtest, "xa" + +#ifdef ALT_CI_INTERRUPT_VECTOR_N + /* + * Use the interrupt vector custom instruction if present to accelerate + * this code. + * If the interrupt vector custom instruction returns a negative + * value, there are no interrupts active (estatus.pie is 0 + * or ipending is 0) so assume it is a software exception. + */ + custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0 + blt r4, r0, .Lnot_irq +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + andi r2, r5, 1 + beq r2, zero, .Lnot_irq + beq r4, zero, .Lnot_irq +#endif /* ALT_CI_INTERRUPT_VECTOR_N */ + + .section .exceptions.irqhandler, "xa" + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + + .section .exceptions.notirq.label, "xa" + +.Lnot_irq: + + /* + * Section .exceptions.exit is in alt_exception_entry.S + * This restores all the caller saved registers + */ + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_handler.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_handler.c new file mode 100644 index 0000000..bb52fc8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_handler.c @@ -0,0 +1,169 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include "system.h" + +/* + * This interrupt handler only works with an internal interrupt controller + * (IIC). Processors with an external interrupt controller (EIC) use an + * implementation provided by an EIC driver. + */ +#ifndef ALT_CPU_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * A table describing each interrupt handler. The index into the array is the + * interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + */ +struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +/* + * alt_irq_handler() is called by the interrupt exception handler in order to + * process any outstanding interrupts. + * + * It is defined here since it is linked in using weak linkage. + * This means that if there is never a call to alt_irq_register() (above) then + * this function will not get linked in to the executable. This is acceptable + * since if no handler is ever registered, then an interrupt can never occur. + * + * If Nios II interrupt vector custom instruction exists, use it to accelerate + * the dispatch of interrupt handlers. The Nios II interrupt vector custom + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ +#ifdef ALT_CI_INTERRUPT_VECTOR + alt_32 offset; + char* alt_irq_base = (char*)alt_irq; +#else + alt_u32 active; + alt_u32 mask; + alt_u32 i; +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + +#ifdef ALT_CI_INTERRUPT_VECTOR + /* + * Call the interrupt vector custom instruction using the + * ALT_CI_INTERRUPT_VECTOR macro. + * It returns the offset into the vector table of the lowest-valued pending + * interrupt (corresponds to highest priority) or a negative value if none. + * The custom instruction assumes that each table entry is eight bytes. + */ + while ((offset = ALT_CI_INTERRUPT_VECTOR) >= 0) { + struct ALT_IRQ_HANDLER* handler_entry = + (struct ALT_IRQ_HANDLER*)(alt_irq_base + offset); +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + handler_entry->handler(handler_entry->context); +#else + handler_entry->handler(handler_entry->context, offset >> 3); +#endif + } +#else /* ALT_CI_INTERRUPT_VECTOR */ + /* + * Obtain from the interrupt controller a bit list of pending interrupts, + * and then process the highest priority interrupt. This process loops, + * loading the active interrupt list on each pass until alt_irq_pending() + * return zero. + * + * The maximum interrupt latency for the highest priority interrupt is + * reduced by finding out which interrupts are pending as late as possible. + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + + do + { + i = 0; + mask = 1; + + /* + * Test each bit in turn looking for an active interrupt. Once one is + * found, the interrupt handler asigned by a call to alt_irq_register() is + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + + } while (active); +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); +} + +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_register.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_register.c new file mode 100644 index 0000000..cf7261e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_register.c @@ -0,0 +1,102 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * This interrupt registry mechanism works with the Nios II internal interrupt + * controller (IIC) only. Systems with an external interrupt controller (EIC), + * or those with the IIC who are using the enhanced interrupt API will + * utilize the alt_ic_isr_register() routine to register an interrupt. + */ +#ifndef NIOS2_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_legacy_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/* + * alt_irq_handler() is called to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * + * The return value is 0 if the interrupt handler was registered and the + * interrupt was enabled, otherwise it is negative. + */ + +int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler) +{ + int rc = -EINVAL; + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + + alt_irq[id].handler = handler; + alt_irq[id].context = context; + + rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); + + alt_irq_enable_all(status); + } + return rc; +} +#endif /* NIOS2_EIC_PRESENT */ + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_vars.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_vars.c new file mode 100644 index 0000000..4f4d140 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_irq_vars.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#include "system.h" + +/* + * These global variables are used to save the current list of enabled + * interrupts. See alt_irq.h for further details. + */ + +volatile alt_u32 alt_irq_active = 0; + +#ifndef ALT_EXCEPTION_STACK + +volatile alt_u32 alt_priority_mask = (alt_u32) -1; + +#endif + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_isatty.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_isatty.c new file mode 100644 index 0000000..73677dd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_isatty.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as tty devices for provided stdio devices. + */ +int ALT_ISATTY (int file) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + return 1; + default: + return 0; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(isatty); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ +/* + * isatty() can be used to determine whether the input file descriptor "file" + * refers to a terminal device or not. If it is a terminal device then the + * return value is one, otherwise it is zero. + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + alt_fd* fd; + struct stat stat; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + { + return 1; + } + + /* + * If a driver does provide an implementation of the fstat() function, then + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + return (stat.st_mode == _IFCHR) ? 1 : 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return 0; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_kill.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_kill.c new file mode 100644 index 0000000..58097d1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_kill.c @@ -0,0 +1,121 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + + +/* + * kill() is used by newlib in order to send signals to processes. Since there + * is only a single process in the HAL, the only valid values for pid are + * either the current process id, or the broadcast values, i.e. pid must be + * less than or equal to zero. + * + * ALT_KILL is mapped onto the kill() system call in alt_syscall.h + */ + +int ALT_KILL (int pid, int sig) +{ + int status = 0; + + if (pid <= 0) + { + switch (sig) + { + case 0: + + /* The null signal is used to check that a pid is valid. */ + + break; + + case SIGABRT: + case SIGALRM: + case SIGFPE: + case SIGILL: + case SIGKILL: + case SIGPIPE: + case SIGQUIT: + case SIGSEGV: + case SIGTERM: + case SIGUSR1: + case SIGUSR2: + case SIGBUS: + case SIGPOLL: + case SIGPROF: + case SIGSYS: + case SIGTRAP: + case SIGVTALRM: + case SIGXCPU: + case SIGXFSZ: + + /* + * The Posix standard defines the default behaviour for all these signals + * as being eqivalent to a call to _exit(). No mechanism is provided to + * change this behaviour. + */ + + _exit(0); + case SIGCHLD: + case SIGURG: + + /* + * The Posix standard defines these signals to be ignored by default. No + * mechanism is provided to change this behaviour. + */ + + break; + default: + + /* Tried to send an unsupported signal */ + + status = EINVAL; + } + } + + else if (pid > 0) + { + /* Attempted to signal a non-existant process */ + + status = ESRCH; + } + + if (status) + { + ALT_ERRNO = status; + return -1; + } + + return 0; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_link.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_link.c new file mode 100644 index 0000000..a57a5c4 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_link.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * link() is used by newlib to create a new link to an existing file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_LINK is mapped onto the link() system call in alt_syscall.h + */ + +int ALT_LINK ( char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(link); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_load.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_load.c new file mode 100644 index 0000000..27d492b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_load.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_load.h" +#include "sys/alt_cache.h" + +/* + * Linker defined symbols. + */ + +extern void __flash_rwdata_start; +extern void __ram_rwdata_start; +extern void __ram_rwdata_end; +extern void __flash_rodata_start; +extern void __ram_rodata_start; +extern void __ram_rodata_end; +extern void __flash_exceptions_start; +extern void __ram_exceptions_start; +extern void __ram_exceptions_end; + +/* + * alt_load() is called when the code is executing from flash. In this case + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + &__ram_rwdata_start, + &__ram_rwdata_end); + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + &__ram_exceptions_start, + &__ram_exceptions_end); + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + &__ram_rodata_start, + &__ram_rodata_end); + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + alt_icache_flush_all(); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_log_macro.S b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_log_macro.S new file mode 100644 index 0000000..2e3cc26 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_log_macro.S @@ -0,0 +1,56 @@ +/* alt_log_macro.S + * + * Implements the function tx_log_str, called by the assembly macro + * ALT_LOG_PUTS(). The macro will be empty when logging is turned off, + * and this function will not be compiled. When logging is on, + * this function is used to print out the strings defined in the beginning + * of alt_log_printf.c, using port information taken from system.h and + * alt_log_printf.h. + * + * This routine only handles strings, and sends a character into the defined + * output device's output buffer when the device is ready. It's intended for + * debugging purposes, where messages can be set to print out at certain + * points in the boot code to indicate the progress of the program. + * + */ + +#ifndef __ALT_LOG_MACROS__ +#define __ALT_LOG_MACROS__ + +/* define this flag to skip assembly-incompatible parts + * of various include files. */ +#define ALT_ASM_SRC + +#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. + + #include "system.h" + #include "sys/alt_log_printf.h" + + .global tx_log_str +tx_log_str: + /* load base uart / jtag uart address into r6 */ + movhi r6, %hiadj(ALT_LOG_PORT_BASE) + addi r6, r6, %lo(ALT_LOG_PORT_BASE) +tx_next_char: + /* if pointer points to null, return + * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */ + ldb r7, (r4) + beq r0, r7, end_tx + + /* check device transmit ready */ +wait_tx_ready_loop: + ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6) + andi r5, r5, ALT_LOG_PRINT_MSK + beq r5, r0, wait_tx_ready_loop + /* write char */ + stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6) + /* advance string pointer */ + addi r4, r4, 1 + br tx_next_char +end_tx: + ret + +#endif + +#endif /* __ALT_LOG_MACROS__ */ + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_log_printf.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_log_printf.c new file mode 100644 index 0000000..af0116f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_log_printf.c @@ -0,0 +1,479 @@ + +/* alt_log_printf.c + * + * This file implements the various C functions used for the + * alt_log logging/debugging print functions. The functions + * sit as is here - the job of hiding them from the compiler + * if logging is disabled is accomplished in the .h file. + * + * All the global variables for alt_log are defined here. + * These include the various flags that turn on additional + * logging options; the strings for assembly printing; and + * other globals needed by different logging options. + * + * There are 4 functions that handle the actual printing: + * alt_log_txchar: Actual function that puts 1 char to UART/JTAG UART. + * alt_log_repchar: Calls alt_log_txchar 'n' times - used by + * alt_log_private_printf for formatting. + * alt_log_private_printf: + * Stripped down implementation of printf - no floats. + * alt_log_printf_proc: + * Wrapper function for private_printf. + * + * The rest of the functions are called by the macros which + * were called by code in the other components. Each function + * is preceded by a comment, about which file it gets called + * in, and what its purpose is. + * + * author: gkwan + */ + +/* skip all code if enable is off */ +#ifdef ALT_LOG_ENABLE + +#include +#include +#include +#ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #include +#endif +#include "sys/alt_log_printf.h" + +/* strings for assembly puts */ +char alt_log_msg_bss[] = "[crt0.S] Clearing BSS \r\n";; +char alt_log_msg_alt_main[] = "[crt0.S] Calling alt_main.\r\n"; +char alt_log_msg_stackpointer[] \ + = "[crt0.S] Setting up stack and global pointers.\r\n"; +char alt_log_msg_cache[] = "[crt0.S] Inst & Data Cache Initialized.\r\n"; +/* char array allocation for alt_write */ +char alt_log_write_buf[ALT_LOG_WRITE_ECHO_LEN+2]; + +/* global variables for all 'on' flags */ + +/* + * The boot message flag is linked into the data (rwdata) section + * because if it is zero, it would otherwise be placed in the bss section. + * alt_log examines this variable before the BSS is cleared in the boot-up + * process. + */ +volatile alt_u32 alt_log_boot_on_flag \ + __attribute__ ((section (".data"))) = ALT_LOG_BOOT_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_write_on_flag = ALT_LOG_WRITE_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_sys_clk_on_flag = ALT_LOG_SYS_CLK_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_alarm_on_flag = \ + ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_isr_on_flag = \ + ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag = \ + ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING; + +/* Global alarm object for recurrent JTAG UART status printing */ +alt_alarm alt_log_jtag_uart_alarm_1; + +/* Global ints for system clock printing and count */ +volatile int alt_log_sys_clk_count; +volatile int alt_system_clock_in_sec; + +/* enum used by alt_log_private_printf */ +enum +{ + pfState_chars, + pfState_firstFmtChar, + pfState_otherFmtChar +}; + + + + +/* Function to put one char onto the UART/JTAG UART txdata register. */ +void alt_log_txchar(int c,char *base) +{ + /* Wait until the device is ready for a character */ + while((ALT_LOG_PRINT_REG_RD(base) & ALT_LOG_PRINT_MSK) == 0) + ; + /* And pop the character into the register */ + ALT_LOG_PRINT_TXDATA_WR(base,c); +} + + +/* Called by alt_log_private_printf to print out characters repeatedly */ +void alt_log_repchar(char c,int r,int base) +{ + while(r-- > 0) + alt_log_txchar(c,(char*) base); +} + + +/* Stripped down printf function */ +void alt_log_private_printf(const char *fmt,int base,va_list args) + { + const char *w; + char c; + int state; + int fmtLeadingZero = 0; /* init these all to 0 for -W warnings. */ + int fmtLong = 0; + int fmtBeforeDecimal = 0; + int fmtAfterDecimal = 0; + int fmtBase = 0; + int fmtSigned = 0; + int fmtCase = 0; /* For hex format, if 1, A-F, else a-f. */ + + w = fmt; + state = pfState_chars; + + while(0 != (c = *w++)) + { + switch(state) + { + case pfState_chars: + if(c == '%') + { + fmtLeadingZero = 0; + fmtLong = 0; + fmtBase = 10; + fmtSigned = 1; + fmtCase = 0; /* Only %X sets this. */ + fmtBeforeDecimal = -1; + fmtAfterDecimal = -1; + state = pfState_firstFmtChar; + } + else + { + alt_log_txchar(c,(char*)base); + } + break; + + case pfState_firstFmtChar: + if(c == '0') + { + fmtLeadingZero = 1; + state = pfState_otherFmtChar; + } + else if(c == '%') + { + alt_log_txchar(c,(char*)base); + state = pfState_chars; + } + else + { + state = pfState_otherFmtChar; + goto otherFmtChar; + } + break; + + case pfState_otherFmtChar: +otherFmtChar: + if(c == '.') + { + fmtAfterDecimal = 0; + } + else if('0' <= c && c <= '9') + { + c -= '0'; + if(fmtAfterDecimal < 0) /* still before decimal */ + { + if(fmtBeforeDecimal < 0) + { + fmtBeforeDecimal = 0; + } + else + { + fmtBeforeDecimal *= 10; + } + fmtBeforeDecimal += c; + } + else + { + fmtAfterDecimal = (fmtAfterDecimal * 10) + c; + } + } + else if(c == 'l') + { + fmtLong = 1; + } + else /* we're up to the letter which determines type */ + { + switch(c) + { + case 'd': + case 'i': +doIntegerPrint: + { + unsigned long v; + unsigned long p; /* biggest power of fmtBase */ + unsigned long vShrink; /* used to count digits */ + int sign; + int digitCount; + + /* Get the value */ + if(fmtLong) + { + if (fmtSigned) + { + v = va_arg(args,long); + } + else + { + v = va_arg(args,unsigned long); + } + } + else + { + if (fmtSigned) + { + v = va_arg(args,int); + } + else + { + v = va_arg(args,unsigned int); + } + } + + /* Strip sign */ + sign = 0; + /* (assumes sign bit is #31) */ + if( fmtSigned && (v & (0x80000000)) ) + { + v = ~v + 1; + sign = 1; + } + + /* Count digits, and get largest place value */ + vShrink = v; + p = 1; + digitCount = 1; + while( (vShrink = vShrink / fmtBase) > 0 ) + { + digitCount++; + p *= fmtBase; + } + + /* Print leading characters & sign */ + fmtBeforeDecimal -= digitCount; + if(fmtLeadingZero) + { + if(sign) + { + alt_log_txchar('-',(char*)base); + fmtBeforeDecimal--; + } + alt_log_repchar('0',fmtBeforeDecimal,base); + } + else + { + if(sign) + { + fmtBeforeDecimal--; + } + alt_log_repchar(' ',fmtBeforeDecimal,base); + if(sign) + { + alt_log_txchar('-',(char*)base); + } + } + + /* Print numbery parts */ + while(p) + { + unsigned char d; + + d = v / p; + d += '0'; + if(d > '9') + { + d += (fmtCase ? 'A' : 'a') - '0' - 10; + } + alt_log_txchar(d,(char*)base); + + v = v % p; + p = p / fmtBase; + } + } + + state = pfState_chars; + break; + + case 'u': + fmtSigned = 0; + goto doIntegerPrint; + case 'o': + fmtSigned = 0; + fmtBase = 8; + goto doIntegerPrint; + case 'x': + fmtSigned = 0; + fmtBase = 16; + goto doIntegerPrint; + case 'X': + fmtSigned = 0; + fmtBase = 16; + fmtCase = 1; + goto doIntegerPrint; + + case 'c': + alt_log_repchar(' ',fmtBeforeDecimal-1,base); + alt_log_txchar(va_arg(args,int),(char*)base); + break; + + case 's': + { + char *s; + + s = va_arg(args,char *); + alt_log_repchar(' ',fmtBeforeDecimal-strlen(s),base); + + while(*s) + alt_log_txchar(*s++,(char*)base); + } + break; + } /* switch last letter of fmt */ + state=pfState_chars; + } + break; + } /* switch */ + } /* while chars left */ + } /* printf */ + +/* Main logging printf function */ +int alt_log_printf_proc(const char *fmt, ... ) +{ + va_list args; + + va_start (args, fmt); + alt_log_private_printf(fmt,ALT_LOG_PORT_BASE,args); + return (0); +} + +/* Below are the functions called by different macros in various components. */ + +/* If the system has a JTAG_UART, include JTAG_UART debugging functions */ +#ifdef __ALTERA_AVALON_JTAG_UART + +/* The alarm function in altera_avalon_jtag_uart.c. + * This function, when turned on, prints out the status + * of the JTAG UART Control register, every ALT_LOG_JTAG_UART_TICKS. + * If the flag is off, the alarm should never be registered, and this + * function should never run */ +alt_u32 altera_avalon_jtag_uart_report_log(void * context) +{ + if (alt_log_jtag_uart_alarm_on_flag) { + altera_avalon_jtag_uart_state* dev = (altera_avalon_jtag_uart_state*) context; + const char* header="JTAG Alarm:"; + alt_log_jtag_uart_print_control_reg(dev, dev->base, header); + return ALT_LOG_JTAG_UART_TICKS; + } + else + { + /* If flag is not on, return 0 to disable future alarms. + * Should never be here, alarm should not be enabled at all. */ + return 0; + } +} + +void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, int base, const char* header) +{ + unsigned int control, space, ac, wi, ri, we, re; + control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + we= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST; + re= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST; + ri= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST; + wi= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST; + ac= (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST; + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + ALT_LOG_PRINTF( + "%s HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,space,ac,wi,ri,we,re); +#else + ALT_LOG_PRINTF( + "%s SW CirBuf = %d, HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,(dev->tx_out-dev->tx_in),space,ac,wi,ri,we,re); +#endif + + return; + +} + +/* In altera_avalon_jtag_uart.c + * Same output as the alarm function above, but this is called in the driver + * init function. Hence, it gives the status of the JTAG UART control register + * right at the initialization of the driver */ +void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base) +{ + const char* header="JTAG Startup Info:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + return; +} + +/* In altera_avalon_jtag_uart.c + * When turned on, this function will print out the status of the jtag uart + * control register every time there is a jtag uart "almost-empty" interrupt. */ +void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev) +{ + if (alt_log_jtag_uart_isr_on_flag) { + const char* header="JTAG IRQ:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + } + return; +} + +#endif /* __ALTERA_AVALON_JTAG_UART */ + +/* In alt_write.c + * When the alt_log_write_on_flag is turned on, this function gets called + * every time alt_write gets called. The first + * ALT_LOG_WRITE_ECHO_LEN characters of every printf command (or any command + * that eventually calls write()) gets echoed to the alt_log output. */ +void alt_log_write(const void *ptr, size_t len) +{ + if (alt_log_write_on_flag) { + int temp_cnt; + int length=(ALT_LOG_WRITE_ECHO_LEN>len) ? len : ALT_LOG_WRITE_ECHO_LEN; + + if (length < 2) return; + + strncpy (alt_log_write_buf,ptr,length); + alt_log_write_buf[length-1]='\n'; + alt_log_write_buf[length]='\r'; + alt_log_write_buf[length+1]='\0'; + + /* Escape Ctrl-D's. If the Ctrl-D gets sent it might kill the terminal + * connection of alt_log. It will get replaced by 'D'. */ + for (temp_cnt=0;temp_cnt < length; temp_cnt++) { + if (alt_log_write_buf[temp_cnt]== 0x4) { + alt_log_write_buf[temp_cnt]='D'; + } + } + ALT_LOG_PRINTF("Write Echo: %s",alt_log_write_buf); + } +} + +/* In altera_avalon_timer_sc + * This function prints out a system clock is alive message + * every ALT_LOG_SYS_CLK_INTERVAL (in ticks). */ +void alt_log_system_clock() +{ + if (alt_log_sys_clk_on_flag) { + alt_log_sys_clk_count++; + if (alt_log_sys_clk_count > ALT_LOG_SYS_CLK_INTERVAL) { + alt_log_sys_clk_count = 0; + ALT_LOG_PRINTF("System Clock On %u\r\n",alt_system_clock_in_sec++); + } + } +} + + +#endif diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_lseek.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_lseek.c new file mode 100644 index 0000000..a56dbfb --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_lseek.c @@ -0,0 +1,117 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(lseek); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * lseek() can be called to move the read/write pointer associated with the + * file descriptor "file". This function simply vectors the call to the lseek() + * function provided by the driver associated with the file descriptor. + * + * If the driver does not provide an implementation of lseek() an error is + * indicated. + * + * lseek() corresponds to the standard lseek() function. + * + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + alt_fd* fd; + off_t rc = 0; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + { + rc = fd->dev->lseek(fd, ptr, dir); + } + /* + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + } + } + else + { + rc = -EBADFD; + } + + if (rc < 0) + { + ALT_ERRNO = -rc; + rc = -1; + } + + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_main.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_main.c new file mode 100644 index 0000000..33e3463 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_main.c @@ -0,0 +1,161 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_sys_init.h" +#include "sys/alt_irq.h" +#include "sys/alt_dev.h" + +#include "os/alt_hooks.h" + +#include "priv/alt_file.h" +#include "alt_types.h" + +#include "system.h" + +#include "sys/alt_log_printf.h" + +extern void _do_ctors(void); +extern void _do_dtors(void); + +/* + * Standard arguments for main. By default, no arguments are passed to main. + * However a device driver may choose to configure these arguments by calling + * alt_set_args(). The expectation is that this facility will only be used by + * the iclient/ihost utility. + */ + +int alt_argc = 0; +char** alt_argv = {NULL}; +char** alt_envp = {NULL}; + +/* + * Prototype for the entry point to the users application. + */ + +extern int main (int, char **, char **); + +/* + * alt_main is the C entry point for the HAL. It is called by the assembler + * startup code in the processor specific crt0.S. It is responsible for: + * completing the C runtime configuration; configuring all the + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ +#ifndef ALT_NO_EXIT + int result; +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + + /* + * Initialize the semaphore used to control access to the file descriptor + * list. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_sys_init.\r\n"); + +#if !defined(ALT_USE_DIRECT_DRIVERS) && (defined(ALT_STDIN_PRESENT) || defined(ALT_STDOUT_PRESENT) || defined(ALT_STDERR_PRESENT)) + + /* + * Redirect stdio to the apropriate devices now that the devices have + * been initialized. This is only done if the user has requested these + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); +#endif + +#ifndef ALT_NO_C_PLUS_PLUS + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); +#endif /* ALT_NO_C_PLUS_PLUS */ + +#if !defined(ALT_NO_C_PLUS_PLUS) && !defined(ALT_NO_CLEAN_EXIT) && !defined(ALT_NO_EXIT) + /* + * Set the C++ destructors to be called at system shutdown. This is only done + * if a clean exit has been requested (i.e. the exit() function has not been + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); +#endif + + /* + * Finally, call main(). The return code is then passed to a subsequent + * call to exit() unless the application is never supposed to exit. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + close(STDOUT_FILENO); + exit (result); +#endif + + ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n"); +} + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_malloc_lock.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_malloc_lock.c new file mode 100644 index 0000000..89c2dd4 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_malloc_lock.c @@ -0,0 +1,52 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +/* + * These are the empty malloc lock/unlock stubs required by newlib. These are + * used to make newlib's malloc() function thread safe. The default HAL + * configuration is single threaded, so there is nothing to do here. Note that + * this requires that malloc is never called by an interrupt service routine. + */ + +void __malloc_lock ( struct _reent *_r ) +{ +} + +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_mcount.S b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_mcount.S new file mode 100644 index 0000000..cf510da --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_mcount.S @@ -0,0 +1,198 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* mcount or _mcount is inserted by GCC before the function prologue of every + * function when a program is compiled for profiling. At the start of mcount, + * we guarantee that: + * ra = self_pc (an address in the function which called mcount) + * r8 = from_pc (an address in the function which called mcount's caller) + * + * Because this is always called at the start of a function we can corrupt + * r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain + * function arguments for the instrumented function) or r8 (which holds ra + * for the instrumented function). + */ + + .global __mcount_fn_head + + .global mcount + + /* _mcount is used by gcc4 */ + .global _mcount + +_mcount: +mcount: + /* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose + * the bucket because bits 1:0 will always be 0, and because the distribution + * of values for bits 4:2 won't be even (aligning on cache line boundaries + * will skew it). Higher bits should be fairly random. + */ + /* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */ + + srli r2, ra, 3 + movhi r3, %hiadj(__mcount_fn_head) + addi r3, r3, %lo(__mcount_fn_head) + andi r2, r2, 0xFC + add r11, r2, r3 + + /* The fast case is where we have already allocated a function arc, and so + * also a function pointer. + */ + + /* First find the function being called (using self_pc) */ + mov r10, r11 +0: + ldw r10, 0(r10) + beq r10, zero, .Lnew_arc + ldw r2, 4(r10) + bne r2, ra, 0b + + /* Found a function entry for this PC. Now look for an arc with a matching + * from_pc value. There will always be at least one arc. */ + ldw r3, 8(r10) +0: + ldw r2, 4(r3) + beq r2, r8, .Lfound_arc + ldw r3, 0(r3) + bne r3, zero, 0b + +.Lnew_arc: + addi sp, sp, -24 + +.LCFI0: + stw ra, 0(sp) + stw r4, 4(sp) + stw r5, 8(sp) + stw r6, 12(sp) + stw r7, 16(sp) + stw r8, 20(sp) + +.LCFI1: + /* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */ + mov r4, ra + mov r5, r8 + mov r6, r10 + mov r7, r11 + call __mcount_record + + /* restore registers from the stack */ + ldw ra, 0(sp) + ldw r4, 4(sp) + ldw r5, 8(sp) + ldw r6, 12(sp) + ldw r7, 16(sp) + ldw r8, 20(sp) + + addi sp, sp, 24 + +.LCFI2: + ret + +.Lfound_arc: + /* We've found the correct arc record. Increment the count and return */ + ldw r2, 8(r3) + addi r2, r2, 1 + stw r2, 8(r3) + ret + +.Lmcount_end: + + + +/* + * Dwarf2 debug information for the function. This provides GDB with the + * information it needs to backtrace out of this function. + */ + + .section .debug_frame,"",@progbits +.LCIE: + .4byte 2f - 1f /* Length */ +1: + .4byte 0xffffffff /* CIE id */ + .byte 0x1 /* Version */ + .string "" /* Augmentation */ + .uleb128 0x1 /* Code alignment factor */ + .sleb128 -4 /* Data alignment factor */ + .byte 0x1f /* Return address register */ + + .byte 0xc /* Define CFA */ + .uleb128 0x1b /* Register 27 (sp) */ + .uleb128 0x0 /* Offset 0 */ + + .align 2 /* Padding */ +2: + +.LFDE_mcount: + .4byte 2f - 1f /* Length */ +1: + .4byte .LCIE /* Pointer to CIE */ + .4byte mcount /* Start of table entry */ + .4byte .Lmcount_end - mcount /* Size of table entry */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI0 - mcount /* to .LCFI0 */ + .byte 0xe /* Define CFA offset */ + .uleb128 24 /* to 24 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI1 - .LCFI0 /* to .LCFI1 */ + .byte 0x9f /* Store ra */ + .uleb128 0x6 /* at CFA-24 */ + .byte 0x84 /* Store r4 */ + .uleb128 0x5 /* at CFA-20 */ + .byte 0x85 /* Store r5 */ + .uleb128 0x4 /* at CFA-16 */ + .byte 0x86 /* Store r6 */ + .uleb128 0x3 /* at CFA-12 */ + .byte 0x87 /* Store r7 */ + .uleb128 0x2 /* at CFA-8 */ + .byte 0x88 /* Store r8 */ + .uleb128 0x1 /* at CFA-4 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI2 - .LCFI1 /* to .LCFI2 */ + .byte 0xe /* Define CFA offset */ + .uleb128 0 /* to 0 */ + .byte 0x8 /* Same value */ + .uleb128 31 /* for ra */ + .byte 0x8 /* Same value */ + .uleb128 4 /* for r4 */ + .byte 0x8 /* Same value */ + .uleb128 5 /* for r5 */ + .byte 0x8 /* Same value */ + .uleb128 6 /* for r6 */ + .byte 0x8 /* Same value */ + .uleb128 7 /* for r7 */ + .byte 0x8 /* Same value */ + .uleb128 8 /* for r8 */ + + .align 2 +2: + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_open.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_open.c new file mode 100644 index 0000000..d7040bc --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_open.c @@ -0,0 +1,173 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_OPEN (const char* file, int flags, int mode) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(open); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +extern alt_llist alt_dev_list; + +/* + * alt_file_locked() is used by open() to ensure that a device has not been + * previously locked for exclusive access using ioctl(). This test is only + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + alt_u32 i; + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + { + if ((alt_fd_list[i].dev == fd->dev) && + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + } + } + + /* The device is not locked */ + + return 0; +} + +/* + * open() is called in order to get a file descriptor that reference the file + * or device named "name". This descriptor can then be used to manipulate the + * file/device using the standard system calls, e.g. write(), read(), ioctl() + * etc. + * + * This is equivalent to the standard open() system call. + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + alt_dev* dev; + alt_fd* fd; + int index = -1; + int status = -ENODEV; + int isafs = 0; + + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + isafs = 1; + } + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + { + if ((index = alt_get_fd (dev)) < 0) + { + status = index; + } + else + { + fd = &alt_fd_list[index]; + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + { + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + } + } + } + else + { + status = -ENODEV; + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + { + alt_release_fd (index); + ALT_ERRNO = -status; + return -1; + } + + /* return the reference upon success */ + + return index; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_printf.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_printf.c new file mode 100644 index 0000000..fe5bcd3 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_printf.c @@ -0,0 +1,127 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file provides a very minimal printf implementation for use with very + * small applications. Only the following format strings are supported: + * %x + * %s + * %c + * %% + */ + +#include +#include "sys/alt_stdio.h" + +/* + * ALT printf function + */ +void +alt_printf(const char* fmt, ... ) +{ + va_list args; + va_start(args, fmt); + const char *w; + char c; + + /* Process format string. */ + w = fmt; + while ((c = *w++) != 0) + { + /* If not a format escape character, just print */ + /* character. Otherwise, process format string. */ + if (c != '%') + { + alt_putchar(c); + } + else + { + /* Get format character. If none */ + /* available, processing is complete. */ + if ((c = *w++) != 0) + { + if (c == '%') + { + /* Process "%" escape sequence. */ + alt_putchar(c); + } + else if (c == 'c') + { + int v = va_arg(args, int); + alt_putchar(v); + } + else if (c == 'x') + { + /* Process hexadecimal number format. */ + unsigned long v = va_arg(args, unsigned long); + unsigned long digit; + int digit_shift; + + /* If the number value is zero, just print and continue. */ + if (v == 0) + { + alt_putchar('0'); + continue; + } + + /* Find first non-zero digit. */ + digit_shift = 28; + while (!(v & (0xF << digit_shift))) + digit_shift -= 4; + + /* Print digits. */ + for (; digit_shift >= 0; digit_shift -= 4) + { + digit = (v & (0xF << digit_shift)) >> digit_shift; + if (digit <= 9) + c = '0' + digit; + else + c = 'a' + digit - 10; + alt_putchar(c); + } + } + else if (c == 's') + { + /* Process string format. */ + char *s = va_arg(args, char *); + + while(*s) + alt_putchar(*s++); + } + } + else + { + break; + } + } + } +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_putchar.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_putchar.c new file mode 100644 index 0000000..900bb9f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_putchar.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided putchar() routine. + */ +int +alt_putchar(int c) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + char c1 = (char)(c & 0xff); + + if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) { + return -1; + } + return c; +#else + return putchar(c); +#endif +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_putstr.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_putstr.c new file mode 100644 index 0000000..131ba19 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_putstr.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided fputs() routine. + */ +int +alt_putstr(const char* str) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, str, strlen(str), 0); +#else + return fputs(str, stdout); +#endif +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_read.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_read.c new file mode 100644 index 0000000..920ab13 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_read.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The read() system call is used to read a block of data from a file or device. + * This function simply vectors the request to the device driver associated + * with the input file descriptor "file". + * + * ALT_READ is mapped onto the read() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just reads from the stdin device when provided. + */ + +int ALT_READ (int file, void *ptr, size_t len) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(read); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_READ(ALT_STDIN_DEV, ptr, len, 0); +#endif /* ALT_STDIN_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_release_fd.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_release_fd.c new file mode 100644 index 0000000..c22a97f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_release_fd.c @@ -0,0 +1,54 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * alt_release_fd() is called to free an allocated file descriptor. This is + * done by setting the device pointer in the file descriptor structure to zero. + * + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + if (fd > 2) + { + alt_fd_list[fd].fd_flags = 0; + alt_fd_list[fd].dev = 0; + } +} + + + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_remap_cached.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_remap_cached.c new file mode 100644 index 0000000..6afc465 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_remap_cached.c @@ -0,0 +1,50 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +void* alt_remap_cached (volatile void* ptr, alt_u32 len) +{ + return (void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_remap_uncached.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_remap_uncached.c new file mode 100644 index 0000000..e533f94 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_remap_uncached.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +volatile void* alt_remap_uncached (void* ptr, alt_u32 len) +{ + alt_dcache_flush (ptr, len); + return (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_rename.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_rename.c new file mode 100644 index 0000000..26db44d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_rename.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * _rename() is used by newlib to rename an existing file. This is unsupported + * in the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_RENAME is mapped onto the _rename() system call in alt_syscall.h + */ + +int ALT_RENAME (char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(_rename); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_sbrk.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_sbrk.c new file mode 100644 index 0000000..7ab3367 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_sbrk.c @@ -0,0 +1,136 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "os/alt_syscall.h" + +#include "sys/alt_irq.h" +#include "sys/alt_stack.h" + +#include "system.h" + +/* + * sbrk() is called to dynamically extend the data segment for the application. + * Thie input argument "incr" is the size of the block to allocate. + * + * This simple implementation does not perform any bounds checking. Memory will + * be allocated, even if the request region colides with the stack or overflows + * the available physical memory. + * + * ALT_SBRK is mapped onto the sbrk() system call in alt_syscall.h + * + * This function is called by the profiling code to allocate memory so must be + * safe if called from an interrupt context. It must also not be instrumented + * because that would lead to an infinate loop. + */ + +extern char __alt_heap_start[]; /* set by linker */ +extern char __alt_heap_limit[]; /* set by linker */ + +static char *heap_end = __alt_heap_start; + +#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) +char * alt_exception_old_stack_limit = NULL; +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + +#ifdef ALT_MAX_HEAP_BYTES + /* + * User specified a maximum heap size. Return -1 if it would + * be exceeded by this sbrk call. + */ + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#endif + + prev_heap_end = heap_end; + heap_end += incr; + +#ifdef ALT_STACK_CHECK + /* + * If the stack and heap are contiguous then extending the heap reduces the + * space available for the stack. If we are still using the default stack + * then adjust the stack limit to note this, while checking for stack + * pointer overflow. + * If the stack limit isn't pointing at the top of the heap then the code + * is using a different stack so none of this needs to be done. + */ + + if (alt_stack_limit() == prev_heap_end) + { + if (alt_stack_pointer() <= heap_end) + alt_report_stack_overflow(); + + alt_set_stack_limit(heap_end); + } + +#ifdef ALT_EXCEPTION_STACK + /* + * If we are executing from the exception stack then compare against the + * stack we switched away from as well. The exception stack is a fixed + * size so doesn't need to be checked. + */ + + if (alt_exception_old_stack_limit == prev_heap_end) + { + if (alt_exception_old_stack_limit <= heap_end) + alt_report_stack_overflow(); + + alt_exception_old_stack_limit = heap_end; + } +#endif + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_settod.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_settod.c new file mode 100644 index 0000000..13349b8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_settod.c @@ -0,0 +1,96 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +extern struct timezone alt_timezone; +extern struct timeval alt_resettime; + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + + +/* + * settimeofday() can be called to calibrate the system clock, so that + * subsequent calls to gettimeofday() will return the elapsed "wall clock" + * time. + * + * This is done by updating the global structures "alt_resettime" and + * "alt_timezone" so that an immediate call to gettimeofday() would return + * the value specified by "t" and "tz". + * + * Warning: if this function is called concurrently with a call to + * gettimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_SETTIMEOFDAY is mapped onto the settimeofday() system call in + * alt_syscall.h + */ + +int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz) +{ + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* If there is a system clock available, update the current time */ + + if (tick_rate) + { + alt_resettime.tv_sec = t->tv_sec - nticks/tick_rate; + alt_resettime.tv_usec = t->tv_usec - + ((nticks*(ALT_US/tick_rate))%ALT_US); + + alt_timezone.tz_minuteswest = tz->tz_minuteswest; + alt_timezone.tz_dsttime = tz->tz_dsttime; + + return 0; + } + + /* There's no system clock available */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_software_exception.S b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_software_exception.S new file mode 100644 index 0000000..0a9381e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_software_exception.S @@ -0,0 +1,53 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This file provides the global symbol: software_exception. It is provided to + * support legacy code, and should not be used by new software. + * + * It is used by legacy code to invoke the software exception handler as + * defined by version 1.0 of the Nios II kit. It should only be used when you + * are providing your own interrupt entry point, i.e. you are not using + * alt_irq_entry. + */ + +#include "system.h" + + /* + * Pull in the exception handler. + */ + + .globl alt_exception + + .section .exceptions.entry.label, "xa" + + .globl software_exception + .type software_exception, @function +software_exception: diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_stat.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_stat.c new file mode 100644 index 0000000..c196d0c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_stat.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "os/alt_syscall.h" + +/* + * The stat() function is similar to the fstat() function in that it is used to + * obtain status information about a file. Instead of using an open file + * descriptor (like fstat()), stat() takes the name of a file as an input + * argument. + * + * ALT_STAT is mapped onto the stat() system call in alt_syscall.h + */ + +int ALT_STAT (const char *file, struct stat *st) +{ + int fd; + int rc; + + fd = open (file, 0); + rc = fstat (fd, st); + close (fd); + + return rc; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_tick.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_tick.c new file mode 100644 index 0000000..23719b1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_tick.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "os/alt_hooks.h" +#include "alt_types.h" + +/* + * "_alt_tick_rate" is used to store the value of the system clock frequency + * in ticks per second. It is initialised to zero, which corresponds to there + * being no system clock facility available. + */ + +alt_u32 _alt_tick_rate = 0; + +/* + * "_alt_nticks" is the number of system clock ticks that have elapsed since + * reset. + */ + +volatile alt_u32 _alt_nticks = 0; + +/* + * "alt_alarm_list" is the head of a linked list of registered alarms. This is + * initialised to be an empty list. + */ + +ALT_LLIST_HEAD(alt_alarm_list); + +/* + * alt_alarm_stop() is called to remove an alarm from the list of registered + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + alt_llist_remove (&alarm->llist); + alt_irq_enable_all (irq_context); +} + +/* + * alt_tick() is periodically called by the system clock driver in order to + * process the registered list of alarms. Each alarm is registed with a + * callback interval, and a callback function, "callback". + * + * The return value of the callback function indicates how many ticks are to + * elapse until the next callback. A return value of zero indicates that the + * alarm should be deactivated. + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + { + next = (alt_alarm*) alarm->llist.next; + + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + { + alarm->rollover = 0; + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + { + next_callback = alarm->callback (alarm->context); + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + { + alt_alarm_stop (alarm); + } + else + { + alarm->time += next_callback; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + { + alarm->rollover = 1; + } + } + } + alarm = next; + } + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); +} + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_times.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_times.c new file mode 100644 index 0000000..6543164 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_times.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * The times() function is used by newlib to obtain elapsed time information. + * The return value is the elapsed time since reset in system clock ticks. Note + * that this is distinct from the strict Posix version of times(), which should + * return the time since: 0 hours, 0 minutes, 0 seconds, January 1, 1970, GMT. + * + * The input structure is filled in with time accounting information. This + * implementation attributes all cpu time to the system. + * + * ALT_TIMES is mapped onto the times() system call in alt_syscall.h + */ + +clock_t ALT_TIMES (struct tms *buf) +{ + clock_t ticks = alt_nticks(); + + /* If there is no system clock present, generate an error */ + + if (!alt_ticks_per_second()) + { + ALT_ERRNO = ENOSYS; + return 0; + } + + /* Otherwise return the elapsed time */ + + buf->tms_utime = 0; + buf->tms_stime = ticks; + buf->tms_cutime = 0; + buf->tms_cstime = 0; + + return ticks; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_uncached_free.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_uncached_free.c new file mode 100644 index 0000000..37f4ac1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_uncached_free.c @@ -0,0 +1,49 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Free a block of uncached memory. + */ + +void alt_uncached_free (volatile void* ptr) +{ + free ((void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK)); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_uncached_malloc.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_uncached_malloc.c new file mode 100644 index 0000000..325132e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_uncached_malloc.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Allocate a block of uncached memory. + */ + +volatile void* alt_uncached_malloc (size_t size) +{ + void* ptr; + + ptr = malloc (size); + + alt_dcache_flush (ptr, size); + + return ptr ? (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK) : NULL; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_unlink.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_unlink.c new file mode 100644 index 0000000..606f019 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_unlink.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * unlink() is used by newlib to delete an existing link to a file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_UNLINK is mapped onto the unlink() system call in alt_syscall.h + */ + +int ALT_UNLINK (char *name) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(unlink); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_usleep.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_usleep.c new file mode 100644 index 0000000..eea89cd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_usleep.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + * + * usleep.c - Microsecond delay routine + */ + +#include + +#include "priv/alt_busy_sleep.h" +#include "os/alt_syscall.h" + +/* + * This function simply calls alt_busy_sleep() to perform the delay. This + * function implements the delay as a calibrated "busy loop". + * + * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h + */ + + + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us) +#else +unsigned int ALT_USLEEP (unsigned int us) +#endif +{ + return alt_busy_sleep(us); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_wait.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_wait.c new file mode 100644 index 0000000..dd768ad --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_wait.c @@ -0,0 +1,52 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * wait() is used by newlib to wait for all child processes to exit. Since the + * HAL does not support spawning child processes, this returns immediately as + * there can't be anythign to wait for. + * + * ALT_WAIT is mapped onto the wait() system call in alt_syscall.h + */ + +int ALT_WAIT (int *status) +{ + *status = 0; + + ALT_ERRNO = ECHILD; + + return -1; +} + diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/alt_write.c b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_write.c new file mode 100644 index 0000000..d161cdf --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/alt_write.c @@ -0,0 +1,138 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#include "sys/alt_log_printf.h" + +/* + * The write() system call is used to write a block of data to a file or + * device. This function simply vectors the request to the device driver + * associated with the input file descriptor "file". + * + * ALT_WRITE is mapped onto the write() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just writes to the stdout/stderr devices + * when provided. + */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(write); +#endif + + switch (file) { +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, ptr, len, 0); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDERR_DEV, ptr, len, 0); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/altera_nios2_qsys_irq.c b/software/DE2_115_ASM3_release_bsp/HAL/src/altera_nios2_qsys_irq.c new file mode 100644 index 0000000..c719dbc --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/altera_nios2_qsys_irq.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2009 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * altera_nios2_irq.c - Support for Nios II internal interrupt controller. + * + */ + +#include "sys/alt_irq.h" +#include "altera_nios2_qsys_irq.h" + +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_qsys_irq_init(void) +{ + NIOS2_WRITE_IENABLE(0); +} diff --git a/software/DE2_115_ASM3_release_bsp/HAL/src/crt0.S b/software/DE2_115_ASM3_release_bsp/HAL/src/crt0.S new file mode 100644 index 0000000..739e45e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/HAL/src/crt0.S @@ -0,0 +1,456 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" +#include "nios2.h" + +/* Setup header files to work with assembler code. */ +#define ALT_ASM_SRC + +/* Debug logging facility */ +#include "sys/alt_log_printf.h" + +/*************************************************************************\ +| MACROS | +\*************************************************************************/ + +/* + * The new build tools explicitly define macros when alt_load() + * must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that + * those macros are controlling if alt_load() needs to be called. + */ +#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED + +/* Need to call alt_load() if any of these sections are being copied. */ +#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS) +#define CALL_ALT_LOAD +#endif + +#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * The legacy build tools use the following macros to detect when alt_load() + * needs to be called. + */ + +#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + ((res##_BASE != rodata##_BASE) || \ + (res##_BASE != rwdata##_BASE) || \ + (res##_BASE != exc##_BASE)) + +#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + __ALT_LOAD_SECTIONS(res, text, rodata, exc) + +#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \ + ALT_RODATA_DEVICE, \ + ALT_RWDATA_DEVICE, \ + ALT_EXCEPTIONS_DEVICE) + +/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */ +#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS +#define CALL_ALT_LOAD +#endif + +#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * When the legacy build tools define a macro called ALT_NO_BOOTLOADER, + * it indicates that initialization code is allowed at the reset address. + * The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for + * the same purpose. + */ +#ifdef ALT_NO_BOOTLOADER +#define ALT_ALLOW_CODE_AT_RESET +#endif + +/*************************************************************************\ +| EXTERNAL REFERENCES | +\*************************************************************************/ + +/* + * The entry point for user code is either "main" in hosted mode, or + * "alt_main" in standalone mode. These are explicitly referenced here, + * to ensure they are built into the executable. This allows the user + * to build them into libraries, rather than supplying them in object + * files at link time. + */ + .globl main + .globl alt_main + +/* + * Create a reference to the software multiply/divide and trap handers, + * so that if they are provided, they will appear in the executable. + */ +#ifndef ALT_NO_INSTRUCTION_EMULATION + .globl alt_exception_muldiv +#endif +#ifdef ALT_TRAP_HANDLER + .globl alt_exception_trap +#endif + +/* + * Linker defined symbols used to initialize bss. + */ +.globl __bss_start +.globl __bss_end + +/*************************************************************************\ +| RESET SECTION (.entry) | +\*************************************************************************/ + +/* + * This is the reset entry point for Nios II. + * + * At reset, only the cache line which contain the reset vector is + * initialized by the hardware. The code within the first cache line + * initializes the remainder of the instruction cache. + */ + + .section .entry, "xa" + .align 5 + +/* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + +/* + * Some tools want to know where the reset vector is. + * Code isn't always provided at the reset vector but at least the + * __reset label always contains the reset vector address because + * it is defined at the start of the .entry section. + */ + + .globl __reset + .type __reset, @function +__reset: + +/* + * Initialize the instruction cache if present (i.e. size > 0) and + * reset code is allowed unless optimizing for RTL simulation. + * RTL simulations can ensure the instruction cache is already initialized + * so skipping this loop speeds up RTL simulation. + */ + +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE +#endif + +0: + initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 1, 1, 0b, 1b + .popsection +#endif /* Initialize Instruction Cache */ + +/* + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + ori r1, r1, %lo(_start) + jmp r1 + + .size __reset, . - __reset +#endif /* Jump to _start */ + +/* + * When not using exit, provide an _exit symbol to prevent unresolved + * references to _exit from the linker script. + */ +#ifdef ALT_NO_EXIT + .globl _exit +_exit: +#endif + +/*************************************************************************\ +| TEXT SECTION (.text) | +\*************************************************************************/ + +/* + * Start of the .text section, and also the code entry point when + * the code is executed by a bootloader rather than directly from reset. + */ + .section .text + .align 2 + + .globl _start + .type _start, @function +_start: + +/* + * Initialize the data cache if present (i.e. size > 0) and not + * optimizing for RTL simulation. + * RTL simulations can ensure the data cache is already initialized + * so skipping this loop speeds up RTL simulation. + */ + +#if NIOS2_DCACHE_SIZE > 0 && !defined(ALT_SIM_OPTIMIZE) + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE +#endif + +0: + initd 0(r2) + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 2, 1, 0b, 1b + .popsection + +#endif /* Initialize Data Cache */ + + /* Log that caches have been initialized. */ + ALT_LOG_PUTS(alt_log_msg_cache) + + /* Log that the stack pointer is about to be setup. */ + ALT_LOG_PUTS(alt_log_msg_stackpointer) + +#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) + /* + * Now that the caches are initialized, set up the stack pointer. + * The value provided by the linker is assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + + /* Set up the global pointer. */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +#else /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */ + + /* + * Set up the GP and SP in all shadow register sets. + */ + + /* + * Check current register set number, if CPU resets into a shadow register + * set, switch register set to 0 by writing zero to SSTATUS register and + * execute an ERET instruction that just jumps to the next PC address + * (use the NEXTPC instruction to get this). + */ + + rdctl r2, status + + /* Get the current register set number (STATUS.CRS). */ + andi r3, r2, NIOS2_STATUS_CRS_MSK + + /* Skip switch register set if STATUS.CRS is 0. */ + beq r3, zero, .Lskip_switch_reg_set + + .set nobreak + + /* Current register set is non-zero, set SSTATUS to 0. */ + mov sstatus, zero + + /* Get next pc and store in ea. */ + nextpc ea + + /* Point to instruction after eret. */ + addi ea, ea, 8 + + /* + * Execute ERET instruction that just jumps to the next PC address + */ + eret + +.Lskip_switch_reg_set: + mov r2, zero + + /* Reset STATUS register */ + wrctl status, r2 + + movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS + + /* Set up the stack pointer in register set 0. */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + + /* Set up the global pointer in register set 0. */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +.Lsetup_sp_and_gp_loop: + /* + * Setup GP and SP for shadow register set + * from NIOS2_NUM_OF_SHADOW_REG_SETS to 0 + */ + + /* Skip if number of register sets is 0. */ + beq r3, zero, .Lno_shadow_register_set + + + /* Add previous register set STATUS.PRS by 1 */ + movhi r4, 1 + add r2, r2, r4 + + /* Write STATUS */ + wrctl status, r2 + + /* Clear r0 in the shadow register set (not done by hardware) */ + wrprs r0, r0 + + /* Write the GP in previous register set */ + wrprs gp, gp + + /* Only write the SP in previous register set + * if using the seperate exception stack. For normal case (single stack), + * funnel code would read the SP from previous register set. + */ +#ifdef ALT_INTERRUPT_STACK + + movhi et, %hiadj(__alt_interrupt_stack_pointer) + addi et, et, %lo(__alt_interrupt_stack_pointer) + wrprs sp, et + +#endif /* ALT_INTERRUPT_STACK */ + + /* Decrease number of register set counter by 1 */ + addi r3, r3, -1 + + br .Lsetup_sp_and_gp_loop +.Lno_shadow_register_set: + +#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS */ +/* + * Clear the BSS if not optimizing for RTL simulation. + * + * This uses the symbols: __bss_start and __bss_end, which are defined + * by the linker script. They mark the begining and the end of the bss + * region. The linker script guarantees that these values are word aligned. + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + ori r2, r2, %lo(__bss_start) + + movhi r3, %hi(__bss_end) + ori r3, r3, %lo(__bss_end) + + beq r2, r3, 1f + +0: + stw zero, (r2) + addi r2, r2, 4 + bltu r2, r3, 0b + +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 3, 1, 0b, 1b + .popsection +#endif /* ALT_SIM_OPTIMIZE */ + +/* + * The alt_load() facility is normally used when there is no bootloader. + * It copies some sections into RAM so it acts like a mini-bootloader. + */ +#ifdef CALL_ALT_LOAD + +#ifdef ALT_STACK_CHECK + /* + * If the user has selected stack checking then we need to set up a safe + * value in the stack limit register so that the relocation functions + * don't think the stack has overflowed (the contents of the rwdata + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + +#endif /* CALL_ALT_LOAD */ + +#ifdef ALT_STACK_CHECK + /* + * Set up the stack limit (if required). The linker has set up the + * copy of the variable which is in memory. + */ + + ldw et, %gprel(alt_stack_limit_value)(gp) +#endif + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + + .size _start, . - _start + +/* + * Add information about the stack base if stack overflow checking is enabled. + */ +#ifdef ALT_STACK_CHECK + .globl alt_stack_limit_value + .section .sdata,"aws",@progbits + .align 2 + .type alt_stack_limit_value, @object + .size alt_stack_limit_value, 4 +alt_stack_limit_value: + .long __alt_stack_limit +#endif diff --git a/software/DE2_115_ASM3_release_bsp/Makefile b/software/DE2_115_ASM3_release_bsp/Makefile new file mode 100644 index 0000000..0e63d38 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/Makefile @@ -0,0 +1,775 @@ +#------------------------------------------------------------------------------ +# BSP MAKEFILE +# +# This makefile was automatically generated by the nios2-bsp-generate-files +# command. Its purpose is to build a custom Board Support Package (BSP) +# targeting a specific Nios II processor in an SOPC Builder-based design. +# +# To create an application or library Makefile which uses this BSP, try the +# nios2-app-generate-makefile or nios2-lib-generate-makefile commands. +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +MKDIR := mkdir -p +ECHO := echo +SPACE := $(empty) $(empty) + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC is defined, Make is launched from Windows through +# Cygwin. This adjust-path macro will call 'cygpath -u' on all +# paths to ensure they are readable by Make. +# +# If COMSPEC is not defined, Make is launched from *nix, and no adjustment +# is necessary +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # !COMSPEC + +ifdef COMSPEC + adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1")) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1")) +else + adjust-path = $(subst $(SPACE),\$(SPACE),$1) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1) +endif + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +# +# The default target, "all", must appear before any other target in the +# Makefile. Note that extra prerequisites are added to the "all" rule later. +#------------------------------------------------------------------------------ +.PHONY: all +all: + @$(ECHO) [BSP build complete] + + +#------------------------------------------------------------------------------ +# PATHS & DIRECTORY NAMES +# +# Explicitly locate absolute path of the BSP root +#------------------------------------------------------------------------------ + +BSP_ROOT_DIR := . + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd)) + +# Stash all BSP object files here +OBJ_DIR := ./obj + +NEWLIB_DIR = $(BSP_ROOT_DIR)/newlib + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +# +# Note that most variable assignments in this section have a corresponding BSP +# setting that can be changed by using the nios2-bsp-create-settings or +# nios2-bsp-update-settings command before nios2-bsp-generate-files; if you +# want any variable set to a specific value when this Makefile is re-generated +# (to prevent hand-edits from being over-written), use the BSP settings +# facilities above. +#------------------------------------------------------------------------------ + +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PRIVATE_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +SETTINGS_FILE := settings.bsp +SOPC_FILE := C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + +#------------------------------------------------------------------------------- +# TOOL & COMMAND DEFINITIONS +# +# The base command for each build operation are expressed here. Additional +# switches may be expressed here. They will run for all instances of the +# utility. +#------------------------------------------------------------------------------- + +# Archiver command. Creates library files. +AR = nios2-elf-ar + +# Assembler command. Note that CC is used for .S files. +AS = nios2-elf-gcc + +# Custom flags only passed to the archiver. This content of this variable is +# directly passed to the archiver rather than the more standard "ARFLAGS". The +# reason for this is that GNU Make assumes some default content in ARFLAGS. +# This setting defines the value of BSP_ARFLAGS in Makefile. +BSP_ARFLAGS = -src + +# Custom flags only passed to the assembler. This setting defines the value of +# BSP_ASFLAGS in Makefile. +BSP_ASFLAGS = -Wa,-gdwarf2 + +# C/C++ compiler debug level. '-g' provides the default set of debug symbols +# typically required to debug a typical application. Omitting '-g' removes +# debug symbols from the ELF. This setting defines the value of +# BSP_CFLAGS_DEBUG in Makefile. +BSP_CFLAGS_DEBUG = -g + +# C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" +# optimization, etc. "-O0" is recommended for code that you want to debug since +# compiler optimization can remove variables and produce non-sequential +# execution of code while debugging. This setting defines the value of +# BSP_CFLAGS_OPTIMIZATION in Makefile. +BSP_CFLAGS_OPTIMIZATION = -O0 + +# C/C++ compiler warning level. "-Wall" is commonly used.This setting defines +# the value of BSP_CFLAGS_WARNINGS in Makefile. +BSP_CFLAGS_WARNINGS = -Wall + +# C compiler command. +CC = nios2-elf-gcc -xc + +# C++ compiler command. +CXX = nios2-elf-gcc -xc++ + +# Command used to remove files during 'clean' target. +RM = rm -f + + +#------------------------------------------------------------------------------- +# BUILD PRE & POST PROCESS COMMANDS +# +# The following variables are treated as shell commands in the rule +# definitions for each file-type associated with the BSP build, as well as +# commands run at the beginning and end of the entire BSP build operation. +# Pre-process commands are executed before the relevant command (for example, +# a command defined in the "CC_PRE_PROCESS" variable executes before the C +# compiler for building .c files), while post-process commands are executed +# immediately afterwards. +# +# You can view each pre/post-process command in the "Build Rules: All & +# Clean", "Pattern Rules to Build Objects", and "Library Rules" sections of +# this Makefile. +#------------------------------------------------------------------------------- + + +#------------------------------------------------------------------------------- +# BSP SOURCE BUILD SETTINGS (FLAG GENERATION) +# +# Software build settings such as compiler optimization, debug level, warning +# flags, etc., may be defined in the following variables. The variables below +# are concatenated together in the 'Flags' section of this Makefile to form +# final variables of flags passed to the build tools. +# +# These settings are considered private to the BSP and apply to all library & +# driver files in it; they do NOT automatically propagate to, for example, the +# build settings for an application. +# # For additional detail and syntax requirements, please refer to GCC help +# (example: "nios2-elf-gcc --help --verbose"). +# +# Unless indicated otherwise, multiple entries in each variable should be +# space-separated. +#------------------------------------------------------------------------------- + +# Altera HAL alt_sys_init.c generated source file +GENERATED_C_FILES := $(ABS_BSP_ROOT)/alt_sys_init.c +GENERATED_C_LIB_SRCS += alt_sys_init.c + + +#------------------------------------------------------------------------------- +# BSP SOURCE FILE LISTING +# +# All source files that comprise the BSP are listed here, along with path +# information to each file expressed relative to the BSP root. The precise +# list and location of each file is derived from the driver, operating system, +# or software package source file declarations. +# +# Following specification of the source files for each component, driver, etc., +# each source file type (C, assembly, etc.) is concatenated together and used +# to construct a list of objects. Pattern rules to build each object are then +# used to build each file. +#------------------------------------------------------------------------------- + +# altera_avalon_jtag_uart_driver sources root +altera_avalon_jtag_uart_driver_SRCS_ROOT := drivers + +# altera_avalon_jtag_uart_driver sources +altera_avalon_jtag_uart_driver_C_LIB_SRCS := \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_init.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_read.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_write.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_ioctl.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_fd.c + +# altera_avalon_lcd_16207_driver sources root +altera_avalon_lcd_16207_driver_SRCS_ROOT := drivers + +# altera_avalon_lcd_16207_driver sources +altera_avalon_lcd_16207_driver_C_LIB_SRCS := \ + $(altera_avalon_lcd_16207_driver_SRCS_ROOT)/src/altera_avalon_lcd_16207.c \ + $(altera_avalon_lcd_16207_driver_SRCS_ROOT)/src/altera_avalon_lcd_16207_fd.c + +# altera_avalon_pio_driver sources root +altera_avalon_pio_driver_SRCS_ROOT := drivers + +# altera_avalon_pio_driver sources +# altera_nios2_qsys_hal_driver sources root +altera_nios2_qsys_hal_driver_SRCS_ROOT := HAL + +# altera_nios2_qsys_hal_driver sources +altera_nios2_qsys_hal_driver_C_LIB_SRCS := \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/altera_nios2_qsys_irq.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_usleep.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_busy_sleep.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_vars.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_icache_flush.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_icache_flush_all.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush_all.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush_no_writeback.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_instruction_exception_entry.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_register.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_iic.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_remap_cached.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_remap_uncached.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_uncached_free.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_uncached_malloc.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_do_ctors.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_do_dtors.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_gmon.c + +altera_nios2_qsys_hal_driver_ASM_LIB_SRCS := \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_entry.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_trap.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_muldiv.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_entry.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_software_exception.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_mcount.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_log_macro.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/crt0.S + +# hal sources root +hal_SRCS_ROOT := HAL + +# hal sources +hal_C_LIB_SRCS := \ + $(hal_SRCS_ROOT)/src/alt_alarm_start.c \ + $(hal_SRCS_ROOT)/src/alt_close.c \ + $(hal_SRCS_ROOT)/src/alt_dev.c \ + $(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \ + $(hal_SRCS_ROOT)/src/alt_dma_rxchan_open.c \ + $(hal_SRCS_ROOT)/src/alt_dma_txchan_open.c \ + $(hal_SRCS_ROOT)/src/alt_environ.c \ + $(hal_SRCS_ROOT)/src/alt_env_lock.c \ + $(hal_SRCS_ROOT)/src/alt_errno.c \ + $(hal_SRCS_ROOT)/src/alt_execve.c \ + $(hal_SRCS_ROOT)/src/alt_exit.c \ + $(hal_SRCS_ROOT)/src/alt_fcntl.c \ + $(hal_SRCS_ROOT)/src/alt_fd_lock.c \ + $(hal_SRCS_ROOT)/src/alt_fd_unlock.c \ + $(hal_SRCS_ROOT)/src/alt_find_dev.c \ + $(hal_SRCS_ROOT)/src/alt_find_file.c \ + $(hal_SRCS_ROOT)/src/alt_flash_dev.c \ + $(hal_SRCS_ROOT)/src/alt_fork.c \ + $(hal_SRCS_ROOT)/src/alt_fs_reg.c \ + $(hal_SRCS_ROOT)/src/alt_fstat.c \ + $(hal_SRCS_ROOT)/src/alt_get_fd.c \ + $(hal_SRCS_ROOT)/src/alt_getchar.c \ + $(hal_SRCS_ROOT)/src/alt_getpid.c \ + $(hal_SRCS_ROOT)/src/alt_gettod.c \ + $(hal_SRCS_ROOT)/src/alt_iic_isr_register.c \ + $(hal_SRCS_ROOT)/src/alt_instruction_exception_register.c \ + $(hal_SRCS_ROOT)/src/alt_ioctl.c \ + $(hal_SRCS_ROOT)/src/alt_io_redirect.c \ + $(hal_SRCS_ROOT)/src/alt_irq_handler.c \ + $(hal_SRCS_ROOT)/src/alt_isatty.c \ + $(hal_SRCS_ROOT)/src/alt_kill.c \ + $(hal_SRCS_ROOT)/src/alt_link.c \ + $(hal_SRCS_ROOT)/src/alt_load.c \ + $(hal_SRCS_ROOT)/src/alt_log_printf.c \ + $(hal_SRCS_ROOT)/src/alt_lseek.c \ + $(hal_SRCS_ROOT)/src/alt_main.c \ + $(hal_SRCS_ROOT)/src/alt_malloc_lock.c \ + $(hal_SRCS_ROOT)/src/alt_open.c \ + $(hal_SRCS_ROOT)/src/alt_printf.c \ + $(hal_SRCS_ROOT)/src/alt_putchar.c \ + $(hal_SRCS_ROOT)/src/alt_putstr.c \ + $(hal_SRCS_ROOT)/src/alt_read.c \ + $(hal_SRCS_ROOT)/src/alt_release_fd.c \ + $(hal_SRCS_ROOT)/src/alt_rename.c \ + $(hal_SRCS_ROOT)/src/alt_sbrk.c \ + $(hal_SRCS_ROOT)/src/alt_settod.c \ + $(hal_SRCS_ROOT)/src/alt_stat.c \ + $(hal_SRCS_ROOT)/src/alt_tick.c \ + $(hal_SRCS_ROOT)/src/alt_times.c \ + $(hal_SRCS_ROOT)/src/alt_unlink.c \ + $(hal_SRCS_ROOT)/src/alt_wait.c \ + $(hal_SRCS_ROOT)/src/alt_write.c + + +# Assemble all component C source files +COMPONENT_C_LIB_SRCS += \ + $(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \ + $(altera_avalon_lcd_16207_driver_C_LIB_SRCS) \ + $(altera_nios2_qsys_hal_driver_C_LIB_SRCS) \ + $(hal_C_LIB_SRCS) + +# Assemble all component assembly source files +COMPONENT_ASM_LIB_SRCS += \ + $(altera_nios2_qsys_hal_driver_ASM_LIB_SRCS) + +# Assemble all component C++ source files +COMPONENT_CPP_LIB_SRCS += \ + +#END MANAGED + +#------------------------------------------------------------------------------ +# PUBLIC.MK +# +# The generated public.mk file contains BSP information that is shared with +# other external makefiles, such as a Nios II application makefile. System- +# dependent information such as hardware-specific compiler flags and +# simulation file generation are stored here. +# +# In addition, public.mk contains include paths that various software, +# such as a device driver, may need for the C compiler. These paths are +# written to public.mk with respect to the BSP root. In public.mk, each +# path is prefixed with a special variable, $(ALT_LIBRARY_ROOT_DIR). The +# purpose of this variable is to allow an external Makefile to append on +# path information to precisely locate paths expressed in public.mk +# Since this is the BSP Makefile, we set ALT_LIBRARY_ROOT_DIR to point right +# here ("."), at the BSP root. +# +# ALT_LIBRARY_ROOT_DIR must always be set before public.mk is included. +#------------------------------------------------------------------------------ +ALT_LIBRARY_ROOT_DIR := . +include public.mk + + +#------------------------------------------------------------------------------ +# FLAGS +# +# Include paths for BSP files are written into the public.mk file and must +# be added to the existing list of pre-processor flags. In addition, "hooks" +# for standard flags left intentionally empty (CFLAGS, CPPFLAGS, ASFLAGS, +# and CXXFLAGS) are provided for conveniently adding to the relevant flags +# on the command-line or via script that calls make. +#------------------------------------------------------------------------------ +# Assemble final list of compiler flags from generated content +BSP_CFLAGS += \ + $(BSP_CFLAGS_DEFINED_SYMBOLS) \ + $(BSP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(BSP_CFLAGS_OPTIMIZATION) \ + $(BSP_CFLAGS_DEBUG) \ + $(BSP_CFLAGS_WARNINGS) \ + $(BSP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Make ready the final list of include directories and other C pre-processor +# flags. Each include path is made ready by prefixing it with "-I". +BSP_CPPFLAGS += \ + $(addprefix -I, $(BSP_INC_DIRS)) \ + $(addprefix -I, $(ALT_INCLUDE_DIRS)) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Finish off assembler flags with any user-provided flags +BSP_ASFLAGS += $(ASFLAGS) + +# Finish off C++ flags with any user-provided flags +BSP_CXXFLAGS += $(CXXFLAGS) + +# And finally, the ordered list +C_SRCS += $(GENERATED_C_LIB_SRCS) \ + $(COMPONENT_C_LIB_SRCS) + +CXX_SRCS += $(GENERATED_CPP_LIB_SRCS) \ + $(COMPONENT_CPP_LIB_SRCS) + +ASM_SRCS += $(GENERATED_ASM_LIB_SRCS) \ + $(COMPONENT_ASM_LIB_SRCS) + + +#------------------------------------------------------------------------------ +# LIST OF GENERATED FILES +# +# A Nios II BSP relies on the generation of several source files used +# by both the BSP and any applications referencing the BSP. +#------------------------------------------------------------------------------ + + +GENERATED_H_FILES := $(ABS_BSP_ROOT)/system.h + +GENERATED_LINKER_SCRIPT := $(ABS_BSP_ROOT)/linker.x + +GENERATED_FILES += $(GENERATED_H_FILES) \ + $(GENERATED_LINKER_SCRIPT) + + +#------------------------------------------------------------------------------ +# SETUP TO BUILD OBJECTS +# +# List of object files which are to be built. This is constructed from the input +# list of C source files (C_SRCS), C++ source files (CXX_SRCS), and assembler +# source file (ASM_SRCS). The permitted file extensions are: +# +# .c .C - for C files +# .cxx .cc .cpp .CXX .CC .CPP - for C++ files +# .S .s - for assembly files +# +# Extended description: The list of objects is a sorted list (duplicates +# removed) of all possible objects, placed beneath the ./obj directory, +# including any path information stored in the "*_SRCS" variable. The +# "patsubst" commands are used to concatenate together multiple file suffix +# types for common files (i.e. c++ as .cxx, .cc, .cpp). +# +# File extensions are case-insensitive in build rules with the exception of +# assembly sources. Nios II assembly sources with the ".S" extension are first +# run through the C preprocessor. Sources with the ".s" extension are not. +#------------------------------------------------------------------------------ +OBJS = $(sort $(addprefix $(OBJ_DIR)/, \ + $(patsubst %.c, %.o, $(patsubst %.C, %.o, $(C_SRCS))) \ + $(patsubst %.cxx, %.o, $(patsubst %.CXX, %.o, \ + $(patsubst %.cc, %.o, $(patsubst %.CC, %.o, \ + $(patsubst %.cpp, %.o, $(patsubst %.CPP, %.o, \ + $(CXX_SRCS) )))))) \ + $(patsubst %.S, %.o, $(patsubst %.s, %.o, $(ASM_SRCS))) )) + +# List of dependancy files for each object file. +DEPS = $(OBJS:.o=.d) + + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(FORCE_RELINK_DEP) $(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP)) + + +#------------------------------------------------------------------------------ +# BUILD RULES: ALL & CLEAN +#------------------------------------------------------------------------------ +.DELETE_ON_ERROR: + +.PHONY: all +all: build_pre_process +all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR) +all: build_post_process + + +# clean: remove .o/.a/.d +.PHONY: clean +clean: + @$(RM) -r $(BSP_LIB) $(OBJ_DIR) $(FORCE_REBUILD_DEP_LIST) +ifneq ($(wildcard $(NEWLIB_DIR)),) + @$(RM) -r $(NEWLIB_DIR) +endif + @$(ECHO) [BSP clean complete] + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + + +#------------------------------------------------------------------------------ +# MAKEFILE UP TO DATE? +# +# Is this very Makefile up to date? Someone may have changed the BSP settings +# file or the associated target hardware. +#------------------------------------------------------------------------------ +# Skip this check when clean is the only target +ifneq ($(MAKECMDGOALS),clean) + +ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE)) +$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.) +endif + +Makefile: $(wildcard $(SETTINGS_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE)) +$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) +endif + +public.mk: $(wildcard $(SOPC_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +endif # $(MAKECMDGOALS) != clean + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ +$(OBJ_DIR)/%.o: %.c + @$(ECHO) Compiling $( + +/* + * Device headers + */ + +#include "altera_nios2_qsys_irq.h" +#include "altera_avalon_jtag_uart.h" +#include "altera_avalon_lcd_16207.h" + +/* + * Allocate the device storage + */ + +ALTERA_NIOS2_QSYS_IRQ_INSTANCE ( NIOS2_PROCESSOR, nios2_processor); +ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART, jtag_uart); +ALTERA_AVALON_LCD_16207_INSTANCE ( LCD_16207_0, lcd_16207_0); + +/* + * Initialize the interrupt controller devices + * and then enable interrupts in the CPU. + * Called before alt_sys_init(). + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + ALTERA_NIOS2_QSYS_IRQ_INIT ( NIOS2_PROCESSOR, nios2_processor); + alt_irq_cpu_enable_interrupts(); +} + +/* + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart); + ALTERA_AVALON_LCD_16207_INIT ( LCD_16207_0, lcd_16207_0); +} diff --git a/software/DE2_115_ASM3_release_bsp/create-this-bsp b/software/DE2_115_ASM3_release_bsp/create-this-bsp new file mode 100644 index 0000000..1228b16 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/create-this-bsp @@ -0,0 +1,49 @@ +#!/bin/bash +# +# This script creates the ucosii_net_zipfs Board Support Package (BSP). + +BSP_TYPE=hal +BSP_DIR=. +SOPC_DIR=../../ +SOPC_FILE=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo +NIOS2_BSP_ARGS="" +CPU_NAME= + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + *) + NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1" + ;; + esac + shift +done + + +# Run nios2-bsp utility to create a hal BSP in this directory +# for the system with a .sopc file in $SOPC_FILE. +# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist. + +if [ -z "$SOPC_FILE" ]; then + echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path." + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS $CPU_NAME" +else + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS $CPU_NAME" +fi + + +echo "create-this-bsp: Running \"$cmd\"" +$cmd || { + echo "$cmd failed" + exit 1 +} +if [ -z "$SKIP_MAKE" ]; then + echo "create-this-bsp: Running make" + make +fi diff --git a/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart.h b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart.h new file mode 100644 index 0000000..3168183 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart.h @@ -0,0 +1,198 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_JTAG_UART_H__ +#define __ALT_AVALON_JTAG_UART_H__ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_warning.h" + +#include "os/alt_sem.h" +#include "os/alt_flag.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * If the user wants all drivers to be small rather than fast then make sure + * this one is marked as needing to be small. + */ +#if defined ALT_USE_SMALL_DRIVERS && !defined ALTERA_AVALON_JTAG_UART_SMALL +#define ALTERA_AVALON_JTAG_UART_SMALL +#endif + +/* + * If the user wants to ignore FIFO full error after timeout + */ +#if defined ALT_JTAG_UART_IGNORE_FIFO_FULL_ERROR && !defined ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR +#define ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR +#endif + +/* + * Constants that can be overriden. + */ +#ifndef ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT +#define ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT 10 +#endif + +#ifndef ALTERA_AVALON_JTAG_UART_BUF_LEN +#define ALTERA_AVALON_JTAG_UART_BUF_LEN 2048 +#endif + +/* + * ALT_JTAG_UART_READ_RDY and ALT_JTAG_UART_WRITE_RDY are the bitmasks + * that define uC/OS-II event flags that are releated to this device. + * + * ALT_JTAG_UART_READ_RDY indicates that there is read data in the buffer + * ready to be processed. ALT_JTAG_UART_WRITE_RDY indicates that the transmitter is + * ready for more data. + */ +#define ALT_JTAG_UART_READ_RDY 0x1 +#define ALT_JTAG_UART_WRITE_RDY 0x2 +#define ALT_JTAG_UART_TIMEOUT 0x4 + +/* + * State structure definition. Each instance of the driver uses one + * of these structures to hold its associated state. + */ + +typedef struct altera_avalon_jtag_uart_state_s +{ + unsigned int base; + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + + unsigned int timeout; /* Timeout until host is assumed inactive */ + alt_alarm alarm; + unsigned int irq_enable; + unsigned int host_inactive; + + ALT_SEM (read_lock) + ALT_SEM (write_lock) + ALT_FLAG_GRP (events) + + /* The variables below are volatile because they are modified by the + * interrupt routine. Making them volatile and reading them atomically + * means that we don't need any large critical sections. + */ + volatile unsigned int rx_in; + unsigned int rx_out; + unsigned int tx_in; + volatile unsigned int tx_out; + char rx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; + char tx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +} altera_avalon_jtag_uart_state; + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility isn't used. + */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ + altera_avalon_jtag_uart_state state = \ + { \ + name##_BASE, \ + } + +#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ + altera_avalon_jtag_uart_state state = \ + { \ + name##_BASE, \ + ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ + } + +/* + * Externally referenced routines + */ +extern void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq); + +#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) \ + { \ + if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ + { \ + ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". " \ + "You have selected the interrupt driven version of " \ + "the ALTERA Avalon JTAG UART driver, but the " \ + "interrupt is not connected for this device. You can " \ + "select a polled mode driver by checking the 'small " \ + "driver' option in the HAL configuration window, or " \ + "by using the -DALTERA_AVALON_JTAG_UART_SMALL " \ + "preprocessor flag."); \ + } \ + else \ + altera_avalon_jtag_uart_init(&state, \ + name##_IRQ_INTERRUPT_CONTROLLER_ID, \ + name##_IRQ); \ + } + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_jtag_uart_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, state) \ + ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_JTAG_UART_INIT(name, state) \ + ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, dev) \ + ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_JTAG_UART_INIT(name, dev) \ + ALTERA_AVALON_JTAG_UART_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_JTAG_UART_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h new file mode 100644 index 0000000..183bd3f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_JTAG_UART_FD_H__ +#define __ALT_AVALON_JTAG_UART_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_jtag_uart_read_fd (alt_fd* fd, char* ptr, int len); +extern int altera_avalon_jtag_uart_write_fd (alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ + +typedef struct altera_avalon_jtag_uart_dev_s +{ + alt_dev dev; + altera_avalon_jtag_uart_state state; +} altera_avalon_jtag_uart_dev; + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_jtag_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + altera_avalon_jtag_uart_read_fd, \ + altera_avalon_jtag_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE, \ + } \ + } + +#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev) + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +extern int altera_avalon_jtag_uart_close_fd(alt_fd* fd); +extern int altera_avalon_jtag_uart_ioctl_fd (alt_fd* fd, int req, void* arg); + +#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_jtag_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + altera_avalon_jtag_uart_close_fd, \ + altera_avalon_jtag_uart_read_fd, \ + altera_avalon_jtag_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + altera_avalon_jtag_uart_ioctl_fd, \ + }, \ + { \ + name##_BASE, \ + ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ + } \ + } + +#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_JTAG_UART_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_JTAG_UART_FD_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h new file mode 100644 index 0000000..8fe6b80 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h @@ -0,0 +1,73 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_JTAG_UART_REGS_H__ +#define __ALTERA_AVALON_JTAG_UART_REGS_H__ + +#include + +#define ALTERA_AVALON_JTAG_UART_DATA_REG 0 +#define IOADDR_ALTERA_AVALON_JTAG_UART_DATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_DATA_REG) +#define IORD_ALTERA_AVALON_JTAG_UART_DATA(base) \ + IORD(base, ALTERA_AVALON_JTAG_UART_DATA_REG) +#define IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, data) \ + IOWR(base, ALTERA_AVALON_JTAG_UART_DATA_REG, data) + +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FF) +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16) + + +#define ALTERA_AVALON_JTAG_UART_CONTROL_REG 1 +#define IOADDR_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) +#define IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ + IORD(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) +#define IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, data) \ + IOWR(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG, data) + +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16) + +#endif /* __ALTERA_AVALON_JTAG_UART_REGS_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207.h b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207.h new file mode 100644 index 0000000..526ef17 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_H__ +#define __ALTERA_AVALON_LCD_16207_H__ + +#include + +#include "sys/alt_alarm.h" +#include "os/alt_sem.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The altera_avalon_lcd_16207_dev structure is used to hold device specific + * data. This includes the transmit and receive buffers. + * + * An instance of this structure is created in the auto-generated + * alt_sys_init.c file for each UART listed in the systems PTF file. This is + * done using the ALTERA_AVALON_LCD_16207_STATE_INSTANCE macro given below. + */ + +#define ALT_LCD_HEIGHT 2 +#define ALT_LCD_WIDTH 16 +#define ALT_LCD_VIRTUAL_WIDTH 80 + +typedef struct altera_avalon_lcd_16207_state_s +{ + int base; + + alt_alarm alarm; + int period; + + char broken; + + unsigned char x; + unsigned char y; + char address; + char esccount; + + char scrollpos; + char scrollmax; + char active; /* If non-zero then the foreground routines are + * active so the timer call must not update the + * display. */ + + char escape[8]; + + struct + { + char visible[ALT_LCD_WIDTH]; + char data[ALT_LCD_VIRTUAL_WIDTH+1]; + char width; + unsigned char speed; + + } line[ALT_LCD_HEIGHT]; + + ALT_SEM (write_lock)/* Semaphore used to control access to the + * write buffer in multi-threaded mode */ +} altera_avalon_lcd_16207_state; + +/* + * Called by alt_sys_init.c to initialize the driver. + */ +extern void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp); + +/* + * The LCD panel driver is not trivial, so leave it out in the small + * drivers case. Also leave it out in simulation because there is no + * simulated hardware for the LCD panel. These two can be overridden + * by defining ALT_USE_LCE_16207 if you really want it. + */ + +#if (!defined(ALT_USE_SMALL_DRIVERS) && !defined(ALT_SIM_OPTIMIZE)) || defined ALT_USE_LCD_16207 + +/* + * Used by the auto-generated file + * alt_sys_init.c to create an instance of this device driver. + */ +#define ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) \ + altera_avalon_lcd_16207_state state = \ + { \ + name##_BASE \ + } + +/* + * The macro ALTERA_AVALON_LCD_16207_INIT is used by the auto-generated file + * alt_sys_init.c to initialize an instance of the device driver. + */ +#define ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) \ + altera_avalon_lcd_16207_init(&state) + +#else /* exclude driver */ + +#define ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) extern int alt_no_storage +#define ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) while (0) + +#endif /* exclude driver */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_lcd_16207_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_LCD_16207_INSTANCE(name, state) \ + ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_LCD_16207_INIT(name, state) \ + ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_LCD_16207_INSTANCE(name, dev) \ + ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_LCD_16207_INIT(name, dev) \ + ALTERA_AVALON_LCD_16207_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_AVALON_LCD_16207_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h new file mode 100644 index 0000000..88436c0 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_FD_H__ +#define __ALTERA_AVALON_LCD_16207_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ + +typedef struct altera_avalon_lcd_16207_dev_s +{ + alt_dev dev; + altera_avalon_lcd_16207_state state; +} altera_avalon_lcd_16207_dev; + +/* + * The LCD panel driver is not trivial, so leave it out in the small + * drivers case. Also leave it out in simulation because there is no + * simulated hardware for the LCD panel. These two can be overridden + * by defining ALT_USE_LCE_16207 if you really want it. + */ + +#if (!defined(ALT_USE_SMALL_DRIVERS) && !defined(ALT_SIM_OPTIMIZE)) || defined ALT_USE_LCD_16207 + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ +#define ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, d) \ + static altera_avalon_lcd_16207_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + NULL, /* read */ \ + altera_avalon_lcd_16207_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE \ + }, \ + } + +#define ALTERA_AVALON_LCD_16207_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_LCD_16207_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#else /* exclude driver */ + +#define ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, d) extern int alt_no_storage +#define ALTERA_AVALON_LCD_16207_DEV_INIT(name, d) while (0) + +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_AVALON_LCD_16207_FD_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h new file mode 100644 index 0000000..bc35f1a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h @@ -0,0 +1,83 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_REGS_H__ +#define __ALTERA_AVALON_LCD_16207_REGS_H__ + +/* +/////////////////////////////////////////////////////////////////////////// +// +// ALTERA_AVALON_LCD_16207 PERIPHERAL +// +// Provides a hardware interface that allows software to +// access the two (2) internal 8-bit registers in an Optrex +// model 16207 (or equivalent) character LCD display (the kind +// shipped with the Nios Development Kit, 2 rows x 16 columns). +// +// Because the interface to the LCD module is "not quite Avalon," +// the hardware in this module ends-up mapping the module's +// two physical read-write registers into four Avalon-visible +// registers: Two read-only registers and two write-only registers. +// A picture is worth a thousand words: +// +// THE REGISTER MAP +// +// 7 6 5 4 3 2 1 0 Offset +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 0 | Command Register (WRITE-Only) | 0 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 0 | Status Register (READ -Only) | 1 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 1 | Data Register (WRITE-Only) | 2 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 1 | Data Register (READ -Only) | 3 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// +/////////////////////////////////////////////////////////////////////////// +*/ + +#include + +#define IOADDR_ALTERA_AVALON_LCD_16207_COMMAND(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, data) IOWR(base, 0, data) + +#define IOADDR_ALTERA_AVALON_LCD_16207_STATUS(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_LCD_16207_STATUS(base) IORD(base, 1) + +#define ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK (0x00000080u) +#define ALTERA_AVALON_LCD_16207_STATUS_BUSY_OFST (7) + +#define IOADDR_ALTERA_AVALON_LCD_16207_DATA_WR(base) __IO_CALC_ADDRESS_NATIVE(base, 2) +#define IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data) IOWR(base, 2, data) + +#define IOADDR_ALTERA_AVALON_LCD_16207_DATA_RD(base) __IO_CALC_ADDRESS_NATIVE(base, 3) +#define IORD_ALTERA_AVALON_LCD_16207_DATA(base) IORD(base, 3) + +#endif diff --git a/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_pio_regs.h b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_pio_regs.h new file mode 100644 index 0000000..a829ddd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/inc/altera_avalon_pio_regs.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_PIO_REGS_H__ +#define __ALTERA_AVALON_PIO_REGS_H__ + +#include + +#define IOADDR_ALTERA_AVALON_PIO_DATA(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IORD_ALTERA_AVALON_PIO_DATA(base) IORD(base, 0) +#define IOWR_ALTERA_AVALON_PIO_DATA(base, data) IOWR(base, 0, data) + +#define IOADDR_ALTERA_AVALON_PIO_DIRECTION(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_PIO_DIRECTION(base) IORD(base, 1) +#define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data) IOWR(base, 1, data) + +#define IOADDR_ALTERA_AVALON_PIO_IRQ_MASK(base) __IO_CALC_ADDRESS_NATIVE(base, 2) +#define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base) IORD(base, 2) +#define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data) + +#define IOADDR_ALTERA_AVALON_PIO_EDGE_CAP(base) __IO_CALC_ADDRESS_NATIVE(base, 3) +#define IORD_ALTERA_AVALON_PIO_EDGE_CAP(base) IORD(base, 3) +#define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data) IOWR(base, 3, data) + + +#define IOADDR_ALTERA_AVALON_PIO_SET_BIT(base) __IO_CALC_ADDRESS_NATIVE(base, 4) +#define IORD_ALTERA_AVALON_PIO_SET_BITS(base) IORD(base, 4) +#define IOWR_ALTERA_AVALON_PIO_SET_BITS(base, data) IOWR(base, 4, data) + +#define IOADDR_ALTERA_AVALON_PIO_CLEAR_BITS(base) __IO_CALC_ADDRESS_NATIVE(base, 5) +#define IORD_ALTERA_AVALON_PIO_CLEAR_BITS(base) IORD(base, 5) +#define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(base, data) IOWR(base, 5, data) + + + +/* Defintions for direction-register operation with bi-directional PIOs */ +#define ALTERA_AVALON_PIO_DIRECTION_INPUT 0 +#define ALTERA_AVALON_PIO_DIRECTION_OUTPUT 1 + +#endif /* __ALTERA_AVALON_PIO_REGS_H__ */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_fd.c b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_fd.c new file mode 100644 index 0000000..c2a882a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_fd.c @@ -0,0 +1,86 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_jtag_uart.h" + +extern int altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char* buffer, int space, int flags); +extern int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char* ptr, int count, int flags); +extern int altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, + int req, void* arg); +extern int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, + int flags); + +/* ----------------------------------------------------------------------- */ +/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */ +/* + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + fd->fd_flags); +} + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + fd->fd_flags); +} + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); +} + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_init.c b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_init.c new file mode 100644 index 0000000..16376e3 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_init.c @@ -0,0 +1,256 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context); +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id); +#endif +static alt_u32 altera_avalon_jtag_uart_timeout(void* context); + +/* + * Driver initialization code. Register interrupts and start a timer + * which we can use to check whether the host is there. + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + ALT_FLAG_CREATE(&sp->events, 0); + ALT_SEM_CREATE(&sp->read_lock, 1); + ALT_SEM_CREATE(&sp->write_lock, 1); + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + sp, NULL); +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + +/* + * Interrupt routine + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + unsigned int base = sp->base; + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + if (next == sp->rx_out) + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + } + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + } +} + +/* + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + sp->host_inactive = 0; + } + else if (sp->host_inactive < INT_MAX - 2) { + sp->host_inactive++; + + if (sp->host_inactive >= sp->timeout) { + /* Post an event to indicate host is inactive (for jtag_uart_read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + } + } + + return alt_ticks_per_second(); +} + +/* + * The close() routine is implemented to drain the JTAG UART transmit buffer + * when not in "small" mode. This routine will wait for transimt data to be + * emptied unless a timeout from host-activity occurs. If the driver flags + * have been set to non-blocking mode, this routine will exit immediately if + * any data remains. This routine should be called indirectly (i.e. though + * the C library close() routine) so that the file descriptor associated + * with the relevant stream (i.e. stdout) can be closed as well. This routine + * does not manage file descriptors. + * + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; +} + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c new file mode 100644 index 0000000..15d97a6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c @@ -0,0 +1,86 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + int rc = -ENOTTY; + + switch (req) + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + { + int timeout = *((int *)arg); + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + rc = 0; + } + break; + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + rc = 0; + } + break; + + default: + break; + } + + return rc; +} + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_read.c b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_read.c new file mode 100644 index 0000000..f97baa8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_read.c @@ -0,0 +1,205 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifdef __ucosii__ +#include "includes.h" +#endif /* __ucosii__ */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ----------------------- SMALL DRIVER ---------------------- */ +/* ----------------------------------------------------------- */ + +/* Read routine. The small version blocks until it has at least one byte + * available, it then returns as much as is immediately available without + * waiting any more. It's performance will be very poor without + * interrupts. + */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char* buffer, int space, int flags) +{ + unsigned int base = sp->base; + + char * ptr = buffer; + char * end = buffer + space; + + while (ptr < end) + { + unsigned int data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) + *ptr++ = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + else if (ptr != buffer) + break; + else if(flags & O_NONBLOCK) + break; + + } + + if (ptr != buffer) + return ptr - buffer; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; +} + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +/* ----------------------------------------------------------- */ +/* ----------------------- FAST DRIVER ----------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + char * ptr = buffer; + + alt_irq_context context; + unsigned int n; + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + { + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + out = sp->rx_out; + + if (in >= out) + n = in - out; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + + if (n == 0) + break; /* No more data available */ + + if (n > space) + n = space; + + memcpy(ptr, sp->rx_buf + out, n); + ptr += n; + space -= n; + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + while (space > 0); + + /* If we read any data then return it */ + if (ptr != buffer) + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + /* + * When running in a multi-threaded mode, we pend on the read event + * flag set and timeout event flag set in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + ALT_JTAG_UART_READ_RDY | ALT_JTAG_UART_TIMEOUT, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* Spin until more data arrives or until host disconnects */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; + } +#else + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + break; + } + + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + + if (ptr != buffer) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + alt_irq_enable_all(context); + } + + if (ptr != buffer) + return ptr - buffer; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_write.c b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_write.c new file mode 100644 index 0000000..9562562 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_jtag_uart_write.c @@ -0,0 +1,217 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifdef __ucosii__ +#include "includes.h" +#endif /* __ucosii__ */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------ SMALL DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* Write routine. The small version blocks when there is no space to write + * into, so it's performance will be very bad if you are writing more than + * one FIFOs worth of data. But you said you didn't want to use interrupts :-) + */ + +int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + unsigned int base = sp->base; + + const char * end = ptr + count; + + while (ptr < end) + if ((IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) != 0) + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, *ptr++); + + return count; +} + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + out = sp->tx_out; + + if (in < out) + n = out - 1 - in; + else if (out > 0) + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + + if (n == 0) + break; + + if (n > count) + n = count; + + memcpy(sp->tx_buf + in, ptr, n); + ptr += n; + count -= n; + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + + /* + * If interrupts are disabled then we could transmit here, we only need + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + alt_irq_enable_all(context); + + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + { + if (flags & O_NONBLOCK) + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + /* + * When running in a multi-threaded mode, we pend on the write event + * flag set or the timeout flag in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ +#ifdef ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + if(!sp->host_inactive) +#endif + ALT_FLAG_PEND (sp->events, + ALT_JTAG_UART_WRITE_RDY | ALT_JTAG_UART_TIMEOUT, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* + * OS not running: Wait for data to be removed from buffer. + * Once the interrupt routine has removed some data then we + * will be able to insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; + } +#else + /* + * No OS present: Always wait for data to be removed from buffer. Once + * the interrupt routine has removed some data then we will be able to + * insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (out == sp->tx_out) + break; + } + } + while (count > 0); + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + + if (ptr != start) + return ptr - start; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; +#ifdef ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + else if (sp->host_inactive >= sp->timeout) { + /* + * Reset the software FIFO, hardware FIFO could not be reset. + * Just throw away characters without reporting error. + */ + sp->tx_out = sp->tx_in = 0; + return ptr - start + count; + } +#endif + else + return -EIO; /* Host not connected */ +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_lcd_16207.c b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_lcd_16207.c new file mode 100644 index 0000000..102e202 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_lcd_16207.c @@ -0,0 +1,605 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* ===================================================================== */ + +/* + * This file provides the implementation of the functions used to drive a + * LCD panel. + * + * Characters written to the device will appear on the LCD panel as though + * it is a very small terminal. If the lines written to the terminal are + * longer than the number of characters on the terminal then it will scroll + * the lines of text automatically to display them all. + * + * If more lines are written than will fit on the terminal then it will scroll + * when characters are written to the line "below" the last displayed one - + * the cursor is allowed to sit below the visible area of the screen providing + * that this line is entirely blank. + * + * The following control sequences may be used to move around and do useful + * stuff: + * CR Moves back to the start of the current line + * LF Moves down a line and back to the start + * BS Moves back a character without erasing + * ESC Starts a VT100 style escape sequence + * + * The following escape sequences are recognised: + * ESC [ ; H Move to row and column specified (positions are + * counted from the top left which is 1;1) + * ESC [ K Clear from current position to end of line + * ESC [ 2 J Clear screen and go to top left + * + */ + +/* ===================================================================== */ + +#include +#include + +#include +#include +#include + +#include "sys/alt_alarm.h" + +#include "altera_avalon_lcd_16207_regs.h" +#include "altera_avalon_lcd_16207.h" + +/* --------------------------------------------------------------------- */ + +/* Commands which can be written to the COMMAND register */ + +enum /* Write to character RAM */ +{ + LCD_CMD_WRITE_DATA = 0x80 + /* Bits 6:0 hold character RAM address */ +}; + +enum /* Write to character generator RAM */ +{ + LCD_CMD_WRITE_CGR = 0x40 + /* Bits 5:0 hold character generator RAM address */ +}; + +enum /* Function Set command */ +{ + LCD_CMD_FUNCTION_SET = 0x20, + LCD_CMD_8BIT = 0x10, + LCD_CMD_TWO_LINE = 0x08, + LCD_CMD_BIGFONT = 0x04 +}; + +enum /* Shift command */ +{ + LCD_CMD_SHIFT = 0x10, + LCD_CMD_SHIFT_DISPLAY = 0x08, + LCD_CMD_SHIFT_RIGHT = 0x04 +}; + +enum /* On/Off command */ +{ + LCD_CMD_ONOFF = 0x08, + LCD_CMD_ENABLE_DISP = 0x04, + LCD_CMD_ENABLE_CURSOR = 0x02, + LCD_CMD_ENABLE_BLINK = 0x01 +}; + +enum /* Entry Mode command */ +{ + LCD_CMD_MODES = 0x04, + LCD_CMD_MODE_INC = 0x02, + LCD_CMD_MODE_SHIFT = 0x01 +}; + +enum /* Home command */ +{ + LCD_CMD_HOME = 0x02 +}; + +enum /* Clear command */ +{ + LCD_CMD_CLEAR = 0x01 +}; + +/* Where in LCD character space do the rows start */ +static char colstart[4] = { 0x00, 0x40, 0x20, 0x60 }; + +/* --------------------------------------------------------------------- */ + +static void lcd_write_command(altera_avalon_lcd_16207_state* sp, + unsigned char command) +{ + unsigned int base = sp->base; + + /* We impose a timeout on the driver in case the LCD panel isn't connected. + * The first time we call this function the timeout is approx 25ms + * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems + * with slower clocks, or debug builds, or slower memory will take longer. + */ + int i = 1000000; + + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + if (--i == 0) + { + sp->broken = 1; + return; + } + + /* Despite what it says in the datasheet, the LCD isn't ready to accept + * a write immediately after it returns BUSY=0. Wait for 100us more. + */ + usleep(100); + + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, command); +} + +/* --------------------------------------------------------------------- */ + +static void lcd_write_data(altera_avalon_lcd_16207_state* sp, + unsigned char data) +{ + unsigned int base = sp->base; + + /* We impose a timeout on the driver in case the LCD panel isn't connected. + * The first time we call this function the timeout is approx 25ms + * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems + * with slower clocks, or debug builds, or slower memory will take longer. + */ + int i = 1000000; + + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + if (--i == 0) + { + sp->broken = 1; + return; + } + + /* Despite what it says in the datasheet, the LCD isn't ready to accept + * a write immediately after it returns BUSY=0. Wait for 100us more. + */ + usleep(100); + + IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data); + + sp->address++; +} + +/* --------------------------------------------------------------------- */ + +static void lcd_clear_screen(altera_avalon_lcd_16207_state* sp) +{ + int y; + + lcd_write_command(sp, LCD_CMD_CLEAR); + + sp->x = 0; + sp->y = 0; + sp->address = 0; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + memset(sp->line[y].data, ' ', sizeof(sp->line[0].data)); + memset(sp->line[y].visible, ' ', sizeof(sp->line[0].visible)); + sp->line[y].width = 0; + } +} + +/* --------------------------------------------------------------------- */ + +static void lcd_repaint_screen(altera_avalon_lcd_16207_state* sp) +{ + int y, x; + + /* scrollpos controls how much the lines have scrolled round. The speed + * each line scrolls at is controlled by its speed variable - while + * scrolline lines will wrap at the position set by width + */ + + int scrollpos = sp->scrollpos; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + int width = sp->line[y].width; + int offset = (scrollpos * sp->line[y].speed) >> 8; + if (offset >= width) + offset = 0; + + for (x = 0 ; x < ALT_LCD_WIDTH ; x++) + { + char c = sp->line[y].data[(x + offset) % width]; + + /* Writing data takes 40us, so don't do it unless required */ + if (sp->line[y].visible[x] != c) + { + unsigned char address = x + colstart[y]; + + if (address != sp->address) + { + lcd_write_command(sp, LCD_CMD_WRITE_DATA | address); + sp->address = address; + } + + lcd_write_data(sp, c); + sp->line[y].visible[x] = c; + } + } + } +} + +/* --------------------------------------------------------------------- */ + +static void lcd_scroll_up(altera_avalon_lcd_16207_state* sp) +{ + int y; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + if (y < ALT_LCD_HEIGHT-1) + memcpy(sp->line[y].data, sp->line[y+1].data, ALT_LCD_VIRTUAL_WIDTH); + else + memset(sp->line[y].data, ' ', ALT_LCD_VIRTUAL_WIDTH); + } + + sp->y--; +} + +/* --------------------------------------------------------------------- */ + +static void lcd_handle_escape(altera_avalon_lcd_16207_state* sp, char c) +{ + int parm1 = 0, parm2 = 0; + + if (sp->escape[0] == '[') + { + char * ptr = sp->escape+1; + while (isdigit(*ptr)) + parm1 = (parm1 * 10) + (*ptr++ - '0'); + + if (*ptr == ';') + { + ptr++; + while (isdigit(*ptr)) + parm2 = (parm2 * 10) + (*ptr++ - '0'); + } + } + else + parm1 = -1; + + switch (c) + { + case 'H': /* ESC '[' ';' 'H' : Move cursor to location */ + case 'f': /* Same as above */ + if (parm2 > 0) + sp->x = parm2 - 1; + if (parm1 > 0) + { + sp->y = parm1 - 1; + if (sp->y > ALT_LCD_HEIGHT * 2) + sp->y = ALT_LCD_HEIGHT * 2; + while (sp->y > ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + } + break; + + case 'J': + /* ESC J is clear to beginning of line [unimplemented] + * ESC [ 0 J is clear to bottom of screen [unimplemented] + * ESC [ 1 J is clear to beginning of screen [unimplemented] + * ESC [ 2 J is clear screen + */ + if (parm1 == 2) + lcd_clear_screen(sp); + break; + + case 'K': + /* ESC K is clear to end of line + * ESC [ 0 K is clear to end of line + * ESC [ 1 K is clear to beginning of line [unimplemented] + * ESC [ 2 K is clear line [unimplemented] + */ + if (parm1 < 1) + { + if (sp->x < ALT_LCD_VIRTUAL_WIDTH) + memset(sp->line[sp->y].data + sp->x, ' ', ALT_LCD_VIRTUAL_WIDTH - sp->x); + } + break; + } +} + +/* --------------------------------------------------------------------- */ + +int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, + const char* ptr, int len, int flags) +{ + const char* end = ptr + len; + + int y; + int widthmax; + + /* When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + + /* Tell the routine which is called off the timer interrupt that the + * foreground routines are active so it must not repaint the display. */ + sp->active = 1; + + for ( ; ptr < end ; ptr++) + { + char c = *ptr; + + if (sp->esccount >= 0) + { + unsigned int esccount = sp->esccount; + + /* Single character escape sequences can end with any character + * Multi character escape sequences start with '[' and contain + * digits and semicolons before terminating + */ + if ((esccount == 0 && c != '[') || + (esccount > 0 && !isdigit(c) && c != ';')) + { + sp->escape[esccount] = 0; + + lcd_handle_escape(sp, c); + + sp->esccount = -1; + } + else if (sp->esccount < sizeof(sp->escape)-1) + { + sp->escape[esccount] = c; + sp->esccount++; + } + } + else if (c == 27) /* ESC */ + { + sp->esccount = 0; + } + else if (c == '\r') + { + sp->x = 0; + } + else if (c == '\n') + { + sp->x = 0; + sp->y++; + + /* Let the cursor sit at X=0, Y=HEIGHT without scrolling so the user + * can print two lines of data without losing one. + */ + if (sp->y > ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + } + else if (c == '\b') + { + if (sp->x > 0) + sp->x--; + } + else if (isprint(c)) + { + /* If we didn't scroll on the last linefeed then we might need to do + * it now. */ + if (sp->y >= ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + + if (sp->x < ALT_LCD_VIRTUAL_WIDTH) + sp->line[sp->y].data[sp->x] = c; + + sp->x++; + } + } + + /* Recalculate the scrolling parameters */ + widthmax = ALT_LCD_WIDTH; + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + int width; + for (width = ALT_LCD_VIRTUAL_WIDTH ; width > 0 ; width--) + if (sp->line[y].data[width-1] != ' ') + break; + + /* The minimum width is the size of the LCD panel. If the real width + * is long enough to require scrolling then add an extra space so the + * end of the message doesn't run into the beginning of it. + */ + if (width <= ALT_LCD_WIDTH) + width = ALT_LCD_WIDTH; + else + width++; + + sp->line[y].width = width; + if (widthmax < width) + widthmax = width; + sp->line[y].speed = 0; /* By default lines don't scroll */ + } + + if (widthmax <= ALT_LCD_WIDTH) + sp->scrollmax = 0; + else + { + widthmax *= 2; + sp->scrollmax = widthmax; + + /* Now calculate how fast each of the other lines should go */ + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + if (sp->line[y].width > ALT_LCD_WIDTH) + { + /* You have three options for how to make the display scroll, chosen + * using the preprocessor directives below + */ +#if 1 + /* This option makes all the lines scroll round at different speeds + * which are chosen so that all the scrolls finish at the same time. + */ + sp->line[y].speed = 256 * sp->line[y].width / widthmax; +#elif 1 + /* This option pads the shorter lines with spaces so that they all + * scroll together. + */ + sp->line[y].width = widthmax / 2; + sp->line[y].speed = 256/2; +#else + /* This option makes the shorter lines stop after they have rotated + * and waits for the longer lines to catch up + */ + sp->line[y].speed = 256/2; +#endif + } + } + + /* Repaint once, then check whether there has been a missed repaint + * (because active was set when the timer interrupt occurred). If there + * has been a missed repaint then paint again. And again. etc. + */ + for ( ; ; ) + { + int old_scrollpos = sp->scrollpos; + + lcd_repaint_screen(sp); + + /* Let the timer routines repaint the display again */ + sp->active = 0; + + /* Have the timer routines tried to scroll while we were painting? + * If not then we can exit */ + if (sp->scrollpos == old_scrollpos) + break; + + /* We need to repaint again since the display scrolled while we were + * painting last time */ + sp->active = 1; + } + + /* Now that access to the display is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + + return len; +} + +/* --------------------------------------------------------------------- */ + +/* This should be in a top level header file really */ +#define container_of(ptr, type, member) ((type *)((char *)ptr - offsetof(type, member))) + +/* + * Timeout routine is called every second + */ + +static alt_u32 alt_lcd_16207_timeout(void* context) +{ + altera_avalon_lcd_16207_state* sp = (altera_avalon_lcd_16207_state*)context; + + /* Update the scrolling position */ + if (sp->scrollpos + 1 >= sp->scrollmax) + sp->scrollpos = 0; + else + sp->scrollpos = sp->scrollpos + 1; + + /* Repaint the panel unless the foreground will do it again soon */ + if (sp->scrollmax > 0 && !sp->active) + lcd_repaint_screen(sp); + + return sp->period; +} + +/* --------------------------------------------------------------------- */ + +/* + * Called at boot time to initialise the LCD driver + */ +void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp) +{ + unsigned int base = sp->base; + + /* Mark the device as functional */ + sp->broken = 0; + + ALT_SEM_CREATE (&sp->write_lock, 1); + + /* The initialisation sequence below is copied from the datasheet for + * the 16207 LCD display. The first commands need to be timed because + * the BUSY bit in the status register doesn't work until the display + * has been reset three times. + */ + + /* Wait for 15 ms then reset */ + usleep(15000); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Wait for another 4.1ms and reset again */ + usleep(4100); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Wait a further 1 ms and reset a third time */ + usleep(1000); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Setup interface parameters: 8 bit bus, 2 rows, 5x7 font */ + lcd_write_command(sp, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT | LCD_CMD_TWO_LINE); + + /* Turn display off */ + lcd_write_command(sp, LCD_CMD_ONOFF); + + /* Clear display */ + lcd_clear_screen(sp); + + /* Set mode: increment after writing, don't shift display */ + lcd_write_command(sp, LCD_CMD_MODES | LCD_CMD_MODE_INC); + + /* Turn display on */ + lcd_write_command(sp, LCD_CMD_ONOFF | LCD_CMD_ENABLE_DISP); + + sp->esccount = -1; + memset(sp->escape, 0, sizeof(sp->escape)); + + sp->scrollpos = 0; + sp->scrollmax = 0; + sp->active = 0; + + sp->period = alt_ticks_per_second() / 10; /* Call every 100ms */ + + alt_alarm_start(&sp->alarm, sp->period, &alt_lcd_16207_timeout, sp); +} diff --git a/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_lcd_16207_fd.c b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_lcd_16207_fd.c new file mode 100644 index 0000000..08c9371 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/drivers/src/altera_avalon_lcd_16207_fd.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_lcd_16207.h" + +extern int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, + const char* ptr, int count, int flags); + +int +altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_lcd_16207_dev* dev = (altera_avalon_lcd_16207_dev*) fd->dev; + + return altera_avalon_lcd_16207_write(&dev->state, buffer, space, + fd->fd_flags); +} diff --git a/software/DE2_115_ASM3_release_bsp/libhal_bsp.a b/software/DE2_115_ASM3_release_bsp/libhal_bsp.a new file mode 100644 index 0000000..0502508 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/libhal_bsp.a Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/linker.h b/software/DE2_115_ASM3_release_bsp/linker.h new file mode 100644 index 0000000..223f99a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/linker.h @@ -0,0 +1,101 @@ +/* + * linker.h - Linker script mapping information + * + * Machine generated for CPU 'nios2_processor' in SOPC Builder design 'nios_system' + * SOPC Builder design path: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + * + * Generated: Thu Jan 26 11:02:29 JST 2017 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __LINKER_H_ +#define __LINKER_H_ + + +/* + * BSP controls alt_load() behavior in crt0. + * + */ + +#define ALT_LOAD_EXPLICITLY_CONTROLLED + + +/* + * Base address and span (size in bytes) of each linker region + * + */ + +#define ONCHIP_MEMORY_REGION_BASE 0x20 +#define ONCHIP_MEMORY_REGION_SPAN 204768 +#define RESET_REGION_BASE 0x0 +#define RESET_REGION_SPAN 32 + + +/* + * Devices associated with code sections + * + */ + +#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY +#define ALT_RESET_DEVICE ONCHIP_MEMORY +#define ALT_RODATA_DEVICE ONCHIP_MEMORY +#define ALT_RWDATA_DEVICE ONCHIP_MEMORY +#define ALT_TEXT_DEVICE ONCHIP_MEMORY + + +/* + * Initialization code at the reset address is allowed (e.g. no external bootloader). + * + */ + +#define ALT_ALLOW_CODE_AT_RESET + + +/* + * The alt_load() facility is called from crt0 to copy sections into RAM. + * + */ + +#define ALT_LOAD_COPY_RWDATA + +#endif /* __LINKER_H_ */ diff --git a/software/DE2_115_ASM3_release_bsp/linker.x b/software/DE2_115_ASM3_release_bsp/linker.x new file mode 100644 index 0000000..8256f99 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/linker.x @@ -0,0 +1,385 @@ +/* + * linker.x - Linker script + * + * Machine generated for CPU 'nios2_processor' in SOPC Builder design 'nios_system' + * SOPC Builder design path: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + * + * Generated: Thu Jan 26 11:02:29 JST 2017 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +MEMORY +{ + reset : ORIGIN = 0x0, LENGTH = 32 + onchip_memory : ORIGIN = 0x20, LENGTH = 204768 +} + +/* Define symbols for each memory base-address */ +__alt_mem_onchip_memory = 0x0; + +OUTPUT_FORMAT( "elf32-littlenios2", + "elf32-littlenios2", + "elf32-littlenios2" ) +OUTPUT_ARCH( nios2 ) +ENTRY( _start ) + +/* + * The alt_load() facility is enabled. This typically happens when there isn't + * an external bootloader (e.g. flash bootloader). + * The LMA (aka physical address) of each loaded section is + * set to the .text memory device. + * The HAL alt_load() routine called from crt0 copies sections from + * the .text memory to RAM as needed. + */ + +SECTIONS +{ + + /* + * Output sections associated with reset and exceptions (they have to be first) + */ + + .entry : + { + KEEP (*(.entry)) + } > reset + + .exceptions : + { + PROVIDE (__ram_exceptions_start = ABSOLUTE(.)); + . = ALIGN(0x20); + KEEP (*(.irq)); + KEEP (*(.exceptions.entry.label)); + KEEP (*(.exceptions.entry.user)); + KEEP (*(.exceptions.entry)); + KEEP (*(.exceptions.irqtest.user)); + KEEP (*(.exceptions.irqtest)); + KEEP (*(.exceptions.irqhandler.user)); + KEEP (*(.exceptions.irqhandler)); + KEEP (*(.exceptions.irqreturn.user)); + KEEP (*(.exceptions.irqreturn)); + KEEP (*(.exceptions.notirq.label)); + KEEP (*(.exceptions.notirq.user)); + KEEP (*(.exceptions.notirq)); + KEEP (*(.exceptions.soft.user)); + KEEP (*(.exceptions.soft)); + KEEP (*(.exceptions.unknown.user)); + KEEP (*(.exceptions.unknown)); + KEEP (*(.exceptions.exit.label)); + KEEP (*(.exceptions.exit.user)); + KEEP (*(.exceptions.exit)); + KEEP (*(.exceptions)); + PROVIDE (__ram_exceptions_end = ABSOLUTE(.)); + } > onchip_memory + + PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions)); + + .text : + { + /* + * All code sections are merged into the text output section, along with + * the read only data sections. + * + */ + + PROVIDE (stext = ABSOLUTE(.)); + + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + + KEEP (*(.init)) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + + /* .gnu.warning sections are handled specially by elf32.em. */ + + *(.gnu.warning.*) + KEEP (*(.fini)) + PROVIDE (__etext = ABSOLUTE(.)); + PROVIDE (_etext = ABSOLUTE(.)); + PROVIDE (etext = ABSOLUTE(.)); + + *(.eh_frame_hdr) + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(4); + PROVIDE (__preinit_array_start = ABSOLUTE(.)); + *(.preinit_array) + PROVIDE (__preinit_array_end = ABSOLUTE(.)); + PROVIDE (__init_array_start = ABSOLUTE(.)); + *(.init_array) + PROVIDE (__init_array_end = ABSOLUTE(.)); + PROVIDE (__fini_array_start = ABSOLUTE(.)); + *(.fini_array) + PROVIDE (__fini_array_end = ABSOLUTE(.)); + SORT(CONSTRUCTORS) + KEEP (*(.eh_frame)) + *(.gcc_except_table) + *(.dynamic) + PROVIDE (__CTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.ctors)) + KEEP (*(SORT(.ctors.*))) + PROVIDE (__CTOR_END__ = ABSOLUTE(.)); + PROVIDE (__DTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.dtors)) + KEEP (*(SORT(.dtors.*))) + PROVIDE (__DTOR_END__ = ABSOLUTE(.)); + KEEP (*(.jcr)) + . = ALIGN(4); + } > onchip_memory = 0x3a880100 /* Nios II NOP instruction */ + + .rodata : + { + PROVIDE (__ram_rodata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + . = ALIGN(4); + PROVIDE (__ram_rodata_end = ABSOLUTE(.)); + } > onchip_memory + + PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + * .rwdata region equals the .text region, and is set to be loaded into .text region. + * This requires two copies of .rwdata in the .text region. One read writable at VMA. + * and one read-only at LMA. crt0 will copy from LMA to VMA on reset + * + */ + + .rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) ) + { + PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.got.plt) *(.got) + *(.data1) + *(.data .data.* .gnu.linkonce.d.*) + + _gp = ABSOLUTE(. + 0x8000); + PROVIDE(gp = _gp); + + *(.rwdata .rwdata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + PROVIDE (edata = ABSOLUTE(.)); + PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); + } > onchip_memory + + PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) ) + { + __bss_start = ABSOLUTE(.); + PROVIDE (__sbss_start = ABSOLUTE(.)); + PROVIDE (___sbss_start = ABSOLUTE(.)); + + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + *(.scommon) + + PROVIDE (__sbss_end = ABSOLUTE(.)); + PROVIDE (___sbss_end = ABSOLUTE(.)); + + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } > onchip_memory + + /* + * + * One output section mapped to the associated memory device for each of + * the available memory devices. These are not used by default, but can + * be used by user applications by using the .section directive. + * + * The output section used for the heap is treated in a special way, + * i.e. the symbols "end" and "_end" are added to point to the heap start. + * + * Because alt_load() is enabled, these sections have + * their LMA set to be loaded into the .text memory region. + * However, the alt_load() code will NOT automatically copy + * these sections into their mapped memory region. + * + */ + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .onchip_memory LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) ) + { + PROVIDE (_alt_partition_onchip_memory_start = ABSOLUTE(.)); + *(.onchip_memory. onchip_memory.*) + . = ALIGN(4); + PROVIDE (_alt_partition_onchip_memory_end = ABSOLUTE(.)); + _end = ABSOLUTE(.); + end = ABSOLUTE(.); + __alt_stack_base = ABSOLUTE(.); + } > onchip_memory + + PROVIDE (_alt_partition_onchip_memory_load_addr = LOADADDR(.onchip_memory)); + + /* + * Stabs debugging sections. + * + */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Altera debug extensions */ + .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) } +} + +/* provide a pointer for the stack */ + +/* + * Don't override this, override the __alt_stack_* symbols instead. + */ +__alt_data_end = 0x32000; + +/* + * The next two symbols define the location of the default stack. You can + * override them to move the stack to a different memory. + */ +PROVIDE( __alt_stack_pointer = __alt_data_end ); +PROVIDE( __alt_stack_limit = __alt_stack_base ); + +/* + * This symbol controls where the start of the heap is. If the stack is + * contiguous with the heap then the stack will contract as memory is + * allocated to the heap. + * Override this symbol to put the heap in a different memory. + */ +PROVIDE( __alt_heap_start = end ); +PROVIDE( __alt_heap_limit = 0x32000 ); diff --git a/software/DE2_115_ASM3_release_bsp/mem_init.mk b/software/DE2_115_ASM3_release_bsp/mem_init.mk new file mode 100644 index 0000000..4bdd7f1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/mem_init.mk @@ -0,0 +1,322 @@ + +######################################################################### +####### M E M I N I T M A K E F I L E C O N T E N T ###### +######################################################################### + +######################################################################### +# This file is intended to be included by public.mk +# +# +# The following variables must be defined before including this file: +# - ELF +# +# The following variables may be defined to override the default behavior: +# - HDL_SIM_DIR +# - HDL_SIM_INSTALL_DIR +# - MEM_INIT_DIR +# - MEM_INIT_INSTALL_DIR +# - QUARTUS_PROJECT_DIR +# - SOPC_NAME +# - SIM_OPTIMIZE +# - RESET_ADDRESS +# +######################################################################### + +ifeq ($(MEM_INIT_FILE),) +# MEM_INIT_FILE should be set equal to the working relative path to this +# mem_init.mk makefile fragment +MEM_INIT_FILE := $(wildcard $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))) +endif + +ifeq ($(ELF2DAT),) +ELF2DAT := elf2dat +endif + +ifeq ($(ELF2HEX),) +ELF2HEX := elf2hex +endif + +ifeq ($(ELF2FLASH),) +ELF2FLASH := elf2flash +endif + +ifeq ($(FLASH2DAT),) +FLASH2DAT := flash2dat +endif + +ifeq ($(NM),) +NM := nios2-elf-nm +endif + +ifeq ($(MKDIR),) +MKDIR := mkdir -p +endif + +ifeq ($(RM),) +RM := rm -f +endif + +ifeq ($(CP),) +CP := cp +endif + +ifeq ($(ECHO),) +ECHO := echo +endif + +MEM_INIT_DIR ?= mem_init +HDL_SIM_DIR ?= $(MEM_INIT_DIR)/hdl_sim + +ifdef QUARTUS_PROJECT_DIR +MEM_INIT_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR)) +ifdef SOPC_NAME +HDL_SIM_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))/$(SOPC_NAME)_sim +endif +endif + +MEM_INIT_DESCRIPTOR_FILE ?= $(MEM_INIT_DIR)/meminit.spd + +MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip + +#------------------------------------- +# Default Flash Boot Loaders +#------------------------------------- + +BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2 +BOOT_LOADER_CFI ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec +BOOT_LOADER_CFI_BE ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec + + +#------------------------------------- +# Default Target +#------------------------------------- + +.PHONY: default_mem_init +ifeq ($(QSYS),1) +default_mem_init: mem_init_generate +else +default_mem_init: mem_init_install +endif +#------------------------------------- +# Runtime Macros +#------------------------------------- + +define post-process-info + @echo Post-processing to create $@... +endef + +target_stem = $(notdir $(basename $@)) + +mem_start_address = $($(target_stem)_START) +mem_end_address = $($(target_stem)_END) +mem_width = $($(target_stem)_WIDTH) +mem_endianness = $($(target_stem)_ENDIANNESS) +mem_create_lanes = $($(target_stem)_CREATE_LANES) + +mem_pad_flag = $($(target_stem)_PAD_FLAG) +mem_reloc_input_flag = $($(target_stem)_RELOC_INPUT_FLAG) +mem_no_zero_fill_flag = $($(target_stem)_NO_ZERO_FILL_FLAG) + +flash_mem_epcs_flag = $($(target_stem)_EPCS_FLAGS) +flash_mem_cfi_flag = $($(target_stem)_CFI_FLAGS) +flash_mem_boot_loader_flag = $($(target_stem)_BOOT_LOADER_FLAG) + +elf2dat_extra_args = $(mem_pad_flag) +elf2hex_extra_args = $(mem_no_zero_fill_flag) +elf2flash_extra_args = $(flash_mem_cfi_flag) $(flash_mem_epcs_flag) $(flash_mem_boot_loader_flag) +flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag) + +#------------------------------------------------------------------------------ +# BSP SPECIFIC CONTENT +# +# The content below is controlled by the BSP and SOPC System +#------------------------------------------------------------------------------ +#START OF BSP SPECIFIC + +#------------------------------------- +# Global Settings +#------------------------------------- + + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_MEMINIT_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +# Optimize for simulation +SIM_OPTIMIZE ?= 0 + +# The CPU reset address as needed by elf2flash +RESET_ADDRESS ?= 0x00000000 + +#------------------------------------- +# Pre-Initialized Memory Descriptions +#------------------------------------- + +# Memory: onchip_memory +MEM_0 := nios_system_onchip_memory +$(MEM_0)_NAME := onchip_memory +$(MEM_0)_MEM_INIT_FILE_PARAM_NAME := INIT_FILE +HEX_FILES += $(MEM_INIT_DIR)/$(MEM_0).hex +MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_0).hex +DAT_FILES += $(HDL_SIM_DIR)/$(MEM_0).dat +HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat +SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym +HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym +$(MEM_0)_START := 0x00000000 +$(MEM_0)_END := 0x00031fff +$(MEM_0)_HIERARCHICAL_PATH := onchip_memory +$(MEM_0)_WIDTH := 32 +$(MEM_0)_ENDIANNESS := --little-endian-mem +$(MEM_0)_CREATE_LANES := 0 + +.PHONY: onchip_memory +onchip_memory: check_elf_exists $(MEM_INIT_DIR)/$(MEM_0).hex $(HDL_SIM_DIR)/$(MEM_0).dat $(HDL_SIM_DIR)/$(MEM_0).sym + + +#END OF BSP SPECIFIC + +#------------------------------------- +# Pre-Initialized Memory Targets +#------------------------------------- + +.PHONY: mem_init_install mem_init_generate mem_init_clean + +ifeq ($(QSYS),1) +# Target mem_init_install is deprecated for QSys based systems +# To initialize onchip memories for Quartus II Synthesis with Qsys based systems: +# 1) Use "make mem_init_genearate" +# 2) Add the generated mem_init/meminit.qip file to your Quartus II Project +# +mem_init_install: + $(error Deprecated Makefile Target: '$@'. Use target 'mem_init_generate' and then add $(MEM_INIT_QIP_FILE) to your Quartus II Project) + +else # QSYS != 1, if SopcBuilder based system + +ifneq ($(MEM_INIT_INSTALL_DIR),) +mem_init_install: $(MEM_INIT_INSTALL_FILES) +endif + +ifneq ($(HDL_SIM_INSTALL_DIR),) +mem_init_install: $(HDL_SIM_INSTALL_FILES) +endif + +mem_init_install: mem_init_generate +ifeq ($(MEM_INIT_INSTALL_DIR),) + @echo "WARNING: MEM_INIT_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR environment variable." +endif +ifeq ($(HDL_SIM_INSTALL_DIR),) + @echo "WARNING: HDL_SIM_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR and SOPC_NAME environment variable." +endif + +$(MEM_INIT_INSTALL_FILES): $(MEM_INIT_INSTALL_DIR)/%: $(MEM_INIT_DIR)/% + @$(MKDIR) $(@D) + @$(CP) -v $< $@ + +$(HDL_SIM_INSTALL_FILES): $(HDL_SIM_INSTALL_DIR)/%: $(HDL_SIM_DIR)/% + @$(MKDIR) $(@D) + @$(CP) -v $< $@ + +endif # QSYS == 1 + + +mem_init_generate: hex dat sym flash $(MEM_INIT_DESCRIPTOR_FILE) $(MEM_INIT_QIP_FILE) + +mem_init_clean: + @$(RM) -r $(MEM_INIT_DIR) $(HDL_SIM_DIR) $(FLASH_FILES) + +.PHONY: hex dat sym flash + +hex: check_elf_exists $(HEX_FILES) + +dat: check_elf_exists $(DAT_FILES) + +sym: check_elf_exists $(SYM_FILES) + +flash: check_elf_exists $(FLASH_FILES) + +#------------------------------------- +# Pre-Initialized Memory Rules +#------------------------------------- + +.PHONY: check_elf_exists +check_elf_exists: $(ELF) +ifeq ($(ELF),) + $(error ELF var not set in mem_init.mk) +endif + +$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2DAT) --infile=$< --outfile=$@ \ + --base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \ + $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)' + +$(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat + @true + +$(HEX_FILES): %.hex: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_width) \ + $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@' + +$(SYM_FILES): %.sym: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + $(NM) -n $< > $@ + +$(FLASH_FILES): %.flash: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2FLASH) --input=$< --outfile=$@ --sim_optimize=$(SIM_OPTIMIZE) $(mem_endianness) \ + $(elf2flash_extra_args)' + +# +# Function generate_spd_entry +# Arg1: path to the memory initialization file +# Arg2: Type HEX or DAT +# Arg3: Output spd file to append +gen_spd_entry.BASE_FILE = $(basename $(notdir $1)) +gen_spd_entry.PARAM_NAME = $($(gen_spd_entry.BASE_FILE)_MEM_INIT_FILE_PARAM_NAME) +gen_spd_entry.MEM_PATH = $($(gen_spd_entry.BASE_FILE)_HIERARCHICAL_PATH) +gen_spd_entry.SETTINGS = $(strip \ + path=\"$1\" \ + type=\"$2\" \ + $(if $(gen_spd_entry.PARAM_NAME),initParamName=\"$(gen_spd_entry.PARAM_NAME)\") \ + $(if $(gen_spd_entry.MEM_PATH),memoryPath=\"$(gen_spd_entry.MEM_PATH)\") \ +) +define gen_spd_entry +$(ECHO) "" >> $3 +endef + +$(MEM_INIT_DESCRIPTOR_FILE).DAT_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(DAT_FILES)) +$(MEM_INIT_DESCRIPTOR_FILE).HEX_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(HEX_FILES)) + +$(MEM_INIT_DESCRIPTOR_FILE): %.spd: $(MEM_INIT_FILE) + $(post-process-info) + @$(MKDIR) $(@D) + @$(RM) $@ + @$(ECHO) "" > $@ + @$(ECHO) "" >> $@ + @$(foreach dat_file,$($@.DAT_FILESET),$(call gen_spd_entry,$(dat_file),DAT,$@) &&)true + @$(foreach hex_file,$($@.HEX_FILESET),$(call gen_spd_entry,$(hex_file),HEX,$@) &&)true + @$(ECHO) "" >> $@ + +.DELETE_ON_ERROR: $(MEM_INIT_DESCRIPTOR_FILE) + +$(MEM_INIT_QIP_FILE): %.qip: $(MEM_INIT_FILE) + $(post-process-info) + @$(MKDIR) $(@D) + @$(RM) $@ + @$(ECHO) "set_global_assignment -name SEARCH_PATH $$::quartus(qip_path)" > $@ + +.DELETE_ON_ERROR: $(MEM_INIT_QIP_FILE) diff --git a/software/DE2_115_ASM3_release_bsp/memory.gdb b/software/DE2_115_ASM3_release_bsp/memory.gdb new file mode 100644 index 0000000..7051541 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/memory.gdb @@ -0,0 +1,50 @@ +# memory.gdb - GDB memory region definitions +# +# Machine generated for CPU 'nios2_processor' in SOPC Builder design 'nios_system' +# SOPC Builder design path: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo +# +# Generated: Thu Jan 26 11:02:29 JST 2017 + +# DO NOT MODIFY THIS FILE +# +# Changing this file will have subtle consequences +# which will almost certainly lead to a nonfunctioning +# system. If you do modify this file, be aware that your +# changes will be overwritten and lost when this file +# is generated again. +# +# DO NOT MODIFY THIS FILE + +# License Agreement +# +# Copyright (c) 2008 +# Altera Corporation, San Jose, California, USA. +# All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# This agreement shall be governed in all respects by the laws of the State +# of California and by the laws of the United States of America. + +# Define memory regions for each memory connected to the CPU. +# The cache attribute is specified which improves GDB performance +# by allowing GDB to cache memory contents on the host. + +# onchip_memory +memory 0x0 0x32000 cache diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_alarm_start.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_alarm_start.d new file mode 100644 index 0000000..a293917 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_alarm_start.d @@ -0,0 +1,22 @@ +obj/HAL/src/alt_alarm_start.o: HAL/src/alt_alarm_start.c \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h linker.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_alarm_start.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_alarm_start.o new file mode 100644 index 0000000..9b7d022 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_alarm_start.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_busy_sleep.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_busy_sleep.d new file mode 100644 index 0000000..0441737 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_busy_sleep.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_busy_sleep.o: HAL/src/alt_busy_sleep.c system.h linker.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_busy_sleep.h + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_busy_sleep.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_busy_sleep.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_busy_sleep.o new file mode 100644 index 0000000..c335537 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_busy_sleep.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_close.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_close.d new file mode 100644 index 0000000..c678dc5 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_close.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_close.o: HAL/src/alt_close.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_close.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_close.o new file mode 100644 index 0000000..590ab60 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_close.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush.d new file mode 100644 index 0000000..cc01756 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_dcache_flush.o: HAL/src/alt_dcache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush.o new file mode 100644 index 0000000..7ffb0d3 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_all.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_all.d new file mode 100644 index 0000000..9b4b55d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_all.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_dcache_flush_all.o: HAL/src/alt_dcache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_all.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_all.o new file mode 100644 index 0000000..abbdc97 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_all.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d new file mode 100644 index 0000000..a1291f0 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d @@ -0,0 +1,16 @@ +obj/HAL/src/alt_dcache_flush_no_writeback.o: \ + HAL/src/alt_dcache_flush_no_writeback.c HAL/inc/nios2.h system.h \ + linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h \ + HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o new file mode 100644 index 0000000..1eec9ac --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev.d new file mode 100644 index 0000000..89b9883 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_dev.o: HAL/src/alt_dev.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev.o new file mode 100644 index 0000000..6a1f8e6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev_llist_insert.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev_llist_insert.d new file mode 100644 index 0000000..f23980f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev_llist_insert.d @@ -0,0 +1,13 @@ +obj/HAL/src/alt_dev_llist_insert.o: HAL/src/alt_dev_llist_insert.c \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev_llist_insert.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev_llist_insert.o new file mode 100644 index 0000000..d732b7c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dev_llist_insert.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_rxchan_open.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_rxchan_open.d new file mode 100644 index 0000000..71aa62d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_rxchan_open.d @@ -0,0 +1,35 @@ +obj/HAL/src/alt_dma_rxchan_open.o: HAL/src/alt_dma_rxchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_rxchan_open.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_rxchan_open.o new file mode 100644 index 0000000..0d63bc3 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_rxchan_open.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_txchan_open.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_txchan_open.d new file mode 100644 index 0000000..2a33dba --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_txchan_open.d @@ -0,0 +1,35 @@ +obj/HAL/src/alt_dma_txchan_open.o: HAL/src/alt_dma_txchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_txchan_open.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_txchan_open.o new file mode 100644 index 0000000..f68fbeb --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_dma_txchan_open.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_ctors.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_ctors.d new file mode 100644 index 0000000..0898fbc --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_ctors.d @@ -0,0 +1 @@ +obj/HAL/src/alt_do_ctors.o: HAL/src/alt_do_ctors.c diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_ctors.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_ctors.o new file mode 100644 index 0000000..633794f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_ctors.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_dtors.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_dtors.d new file mode 100644 index 0000000..abdadfa --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_dtors.d @@ -0,0 +1 @@ +obj/HAL/src/alt_do_dtors.o: HAL/src/alt_do_dtors.c diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_dtors.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_dtors.o new file mode 100644 index 0000000..5833fcd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_do_dtors.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_env_lock.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_env_lock.d new file mode 100644 index 0000000..fd8a733 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_env_lock.d @@ -0,0 +1 @@ +obj/HAL/src/alt_env_lock.o: HAL/src/alt_env_lock.c diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_env_lock.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_env_lock.o new file mode 100644 index 0000000..608ea7f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_env_lock.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_environ.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_environ.d new file mode 100644 index 0000000..b622e4b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_environ.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_environ.o: HAL/src/alt_environ.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_environ.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_environ.o new file mode 100644 index 0000000..25d491b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_environ.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_errno.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_errno.d new file mode 100644 index 0000000..51c7dcd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_errno.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_errno.o: HAL/src/alt_errno.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_errno.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_errno.o new file mode 100644 index 0000000..0f90826 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_errno.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_entry.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_entry.d new file mode 100644 index 0000000..7960631 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_entry.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_exception_entry.o: HAL/src/alt_exception_entry.S system.h \ + linker.h + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_entry.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_entry.o new file mode 100644 index 0000000..8059abd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_entry.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_muldiv.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_muldiv.d new file mode 100644 index 0000000..a1e5556 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_muldiv.d @@ -0,0 +1 @@ +obj/HAL/src/alt_exception_muldiv.o: HAL/src/alt_exception_muldiv.S diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_muldiv.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_muldiv.o new file mode 100644 index 0000000..b46375e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_muldiv.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_trap.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_trap.d new file mode 100644 index 0000000..ef4edc6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_trap.d @@ -0,0 +1 @@ +obj/HAL/src/alt_exception_trap.o: HAL/src/alt_exception_trap.S diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_trap.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_trap.o new file mode 100644 index 0000000..4746c42 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exception_trap.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_execve.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_execve.d new file mode 100644 index 0000000..0060a9d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_execve.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_execve.o: HAL/src/alt_execve.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_execve.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_execve.o new file mode 100644 index 0000000..9a28ffa --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_execve.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exit.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exit.d new file mode 100644 index 0000000..09ed618 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exit.d @@ -0,0 +1,26 @@ +obj/HAL/src/alt_exit.o: HAL/src/alt_exit.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_sim.h HAL/inc/os/alt_hooks.h HAL/inc/os/alt_syscall.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_sim.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exit.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exit.o new file mode 100644 index 0000000..11a92c3 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_exit.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fcntl.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fcntl.d new file mode 100644 index 0000000..b8835a6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fcntl.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_fcntl.o: HAL/src/alt_fcntl.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fcntl.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fcntl.o new file mode 100644 index 0000000..7ee40dd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fcntl.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_lock.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_lock.d new file mode 100644 index 0000000..f6d94e1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_lock.d @@ -0,0 +1,27 @@ +obj/HAL/src/alt_fd_lock.o: HAL/src/alt_fd_lock.c HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_lock.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_lock.o new file mode 100644 index 0000000..433e6c6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_lock.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_unlock.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_unlock.d new file mode 100644 index 0000000..9778463 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_unlock.d @@ -0,0 +1,27 @@ +obj/HAL/src/alt_fd_unlock.o: HAL/src/alt_fd_unlock.c \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_unlock.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_unlock.o new file mode 100644 index 0000000..c72245e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fd_unlock.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_dev.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_dev.d new file mode 100644 index 0000000..7b37308 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_dev.d @@ -0,0 +1,31 @@ +obj/HAL/src/alt_find_dev.o: HAL/src/alt_find_dev.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_dev.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_dev.o new file mode 100644 index 0000000..fbc6172 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_dev.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_file.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_file.d new file mode 100644 index 0000000..4f15c6d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_file.d @@ -0,0 +1,32 @@ +obj/HAL/src/alt_find_file.o: HAL/src/alt_find_file.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_file.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_file.o new file mode 100644 index 0000000..eca93fb --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_find_file.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_flash_dev.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_flash_dev.d new file mode 100644 index 0000000..e665b37 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_flash_dev.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_flash_dev.o: HAL/src/alt_flash_dev.c \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/sys/alt_flash_dev.h \ + HAL/inc/sys/alt_flash_types.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_flash_dev.h: + +HAL/inc/sys/alt_flash_types.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_flash_dev.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_flash_dev.o new file mode 100644 index 0000000..671fd82 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_flash_dev.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fork.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fork.d new file mode 100644 index 0000000..ef5b637 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fork.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_fork.o: HAL/src/alt_fork.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fork.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fork.o new file mode 100644 index 0000000..28091d1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fork.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fs_reg.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fs_reg.d new file mode 100644 index 0000000..f56b56f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fs_reg.d @@ -0,0 +1,29 @@ +obj/HAL/src/alt_fs_reg.o: HAL/src/alt_fs_reg.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fs_reg.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fs_reg.o new file mode 100644 index 0000000..7fca958 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fs_reg.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fstat.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fstat.d new file mode 100644 index 0000000..b1c4a1e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fstat.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_fstat.o: HAL/src/alt_fstat.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fstat.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fstat.o new file mode 100644 index 0000000..864536a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_fstat.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_get_fd.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_get_fd.d new file mode 100644 index 0000000..5524f68 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_get_fd.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_get_fd.o: HAL/src/alt_get_fd.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_get_fd.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_get_fd.o new file mode 100644 index 0000000..768a38d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_get_fd.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getchar.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getchar.d new file mode 100644 index 0000000..aa88591 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getchar.d @@ -0,0 +1 @@ +obj/HAL/src/alt_getchar.o: HAL/src/alt_getchar.c diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getchar.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getchar.o new file mode 100644 index 0000000..9ebad96 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getchar.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getpid.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getpid.d new file mode 100644 index 0000000..365651b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getpid.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_getpid.o: HAL/src/alt_getpid.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getpid.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getpid.o new file mode 100644 index 0000000..487f4b6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_getpid.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gettod.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gettod.d new file mode 100644 index 0000000..ffd23b8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gettod.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_gettod.o: HAL/src/alt_gettod.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gettod.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gettod.o new file mode 100644 index 0000000..6aaae0f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gettod.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gmon.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gmon.d new file mode 100644 index 0000000..6a213bf --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gmon.d @@ -0,0 +1,24 @@ +obj/HAL/src/alt_gmon.o: HAL/src/alt_gmon.c HAL/inc/priv/nios2_gmon_data.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h + +HAL/inc/priv/nios2_gmon_data.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gmon.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gmon.o new file mode 100644 index 0000000..9503333 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_gmon.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush.d new file mode 100644 index 0000000..a6048d7 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_icache_flush.o: HAL/src/alt_icache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush.o new file mode 100644 index 0000000..1821e6b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush_all.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush_all.d new file mode 100644 index 0000000..19ee42e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush_all.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_icache_flush_all.o: HAL/src/alt_icache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush_all.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush_all.o new file mode 100644 index 0000000..112b3cc --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_icache_flush_all.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic.d new file mode 100644 index 0000000..444ca68 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic.d @@ -0,0 +1,29 @@ +obj/HAL/src/alt_iic.o: HAL/src/alt_iic.c system.h linker.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_iic_isr_register.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_irq.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_iic_isr_register.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic.o new file mode 100644 index 0000000..7470a34 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic_isr_register.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic_isr_register.d new file mode 100644 index 0000000..93b9138 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic_isr_register.d @@ -0,0 +1,30 @@ +obj/HAL/src/alt_iic_isr_register.o: HAL/src/alt_iic_isr_register.c \ + system.h linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_iic_isr_register.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_irq_entry.h \ + HAL/inc/priv/alt_irq_table.h + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_iic_isr_register.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_irq_entry.h: + +HAL/inc/priv/alt_irq_table.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic_isr_register.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic_isr_register.o new file mode 100644 index 0000000..c804d22 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_iic_isr_register.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_entry.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_entry.d new file mode 100644 index 0000000..f91b75a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_entry.d @@ -0,0 +1,18 @@ +obj/HAL/src/alt_instruction_exception_entry.o: \ + HAL/src/alt_instruction_exception_entry.c HAL/inc/sys/alt_exceptions.h \ + HAL/inc/alt_types.h system.h linker.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_entry.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_entry.o new file mode 100644 index 0000000..b778715 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_entry.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_register.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_register.d new file mode 100644 index 0000000..24c4435 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_register.d @@ -0,0 +1,16 @@ +obj/HAL/src/alt_instruction_exception_register.o: \ + HAL/src/alt_instruction_exception_register.c \ + HAL/inc/sys/alt_exceptions.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_register.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_register.o new file mode 100644 index 0000000..312993d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_instruction_exception_register.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_io_redirect.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_io_redirect.d new file mode 100644 index 0000000..d84ac28 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_io_redirect.d @@ -0,0 +1,29 @@ +obj/HAL/src/alt_io_redirect.o: HAL/src/alt_io_redirect.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_io_redirect.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_io_redirect.o new file mode 100644 index 0000000..6dda3a8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_io_redirect.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_ioctl.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_ioctl.d new file mode 100644 index 0000000..0b46e82 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_ioctl.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_ioctl.o: HAL/src/alt_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_ioctl.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_ioctl.o new file mode 100644 index 0000000..b24a3e6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_ioctl.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_entry.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_entry.d new file mode 100644 index 0000000..c2477c1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_entry.d @@ -0,0 +1,5 @@ +obj/HAL/src/alt_irq_entry.o: HAL/src/alt_irq_entry.S system.h linker.h + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_entry.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_entry.o new file mode 100644 index 0000000..d02df70 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_entry.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_handler.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_handler.d new file mode 100644 index 0000000..c6ee821 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_handler.d @@ -0,0 +1,19 @@ +obj/HAL/src/alt_irq_handler.o: HAL/src/alt_irq_handler.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/os/alt_hooks.h HAL/inc/alt_types.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_handler.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_handler.o new file mode 100644 index 0000000..1a98d07 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_handler.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_register.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_register.d new file mode 100644 index 0000000..ad1830e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_register.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_irq_register.o: HAL/src/alt_irq_register.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/os/alt_hooks.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq_entry.h \ + HAL/inc/priv/alt_irq_table.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq_entry.h: + +HAL/inc/priv/alt_irq_table.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_register.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_register.o new file mode 100644 index 0000000..c760c75 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_register.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_vars.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_vars.d new file mode 100644 index 0000000..c339fc6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_vars.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_irq_vars.o: HAL/src/alt_irq_vars.c HAL/inc/alt_types.h \ + system.h linker.h + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_vars.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_vars.o new file mode 100644 index 0000000..213e8aa --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_irq_vars.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_isatty.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_isatty.d new file mode 100644 index 0000000..1b9868b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_isatty.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_isatty.o: HAL/src/alt_isatty.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_isatty.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_isatty.o new file mode 100644 index 0000000..9537068 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_isatty.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_kill.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_kill.d new file mode 100644 index 0000000..7ced1b6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_kill.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_kill.o: HAL/src/alt_kill.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_kill.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_kill.o new file mode 100644 index 0000000..781c4d1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_kill.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_link.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_link.d new file mode 100644 index 0000000..2156c3d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_link.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_link.o: HAL/src/alt_link.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_link.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_link.o new file mode 100644 index 0000000..d9bffa3 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_link.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_load.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_load.d new file mode 100644 index 0000000..ff64508 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_load.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_load.o: HAL/src/alt_load.c HAL/inc/sys/alt_load.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h + +HAL/inc/sys/alt_load.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_load.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_load.o new file mode 100644 index 0000000..c094957 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_load.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_macro.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_macro.d new file mode 100644 index 0000000..b6c30c4 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_macro.d @@ -0,0 +1 @@ +obj/HAL/src/alt_log_macro.o: HAL/src/alt_log_macro.S diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_macro.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_macro.o new file mode 100644 index 0000000..489e2cc --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_macro.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_printf.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_printf.d new file mode 100644 index 0000000..ddd7cdb --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_printf.d @@ -0,0 +1 @@ +obj/HAL/src/alt_log_printf.o: HAL/src/alt_log_printf.c diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_printf.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_printf.o new file mode 100644 index 0000000..a03c33d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_log_printf.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_lseek.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_lseek.d new file mode 100644 index 0000000..a103673 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_lseek.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_lseek.o: HAL/src/alt_lseek.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_lseek.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_lseek.o new file mode 100644 index 0000000..f6bd20c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_lseek.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_main.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_main.d new file mode 100644 index 0000000..67b6a7b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_main.d @@ -0,0 +1,47 @@ +obj/HAL/src/alt_main.o: HAL/src/alt_main.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_sys_init.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/os/alt_hooks.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h system.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_main.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_main.o new file mode 100644 index 0000000..2138029 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_main.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_malloc_lock.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_malloc_lock.d new file mode 100644 index 0000000..981b056 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_malloc_lock.d @@ -0,0 +1 @@ +obj/HAL/src/alt_malloc_lock.o: HAL/src/alt_malloc_lock.c diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_malloc_lock.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_malloc_lock.o new file mode 100644 index 0000000..9817fed --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_malloc_lock.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_mcount.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_mcount.d new file mode 100644 index 0000000..4fa3643 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_mcount.d @@ -0,0 +1 @@ +obj/HAL/src/alt_mcount.o: HAL/src/alt_mcount.S diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_mcount.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_mcount.o new file mode 100644 index 0000000..68bebd5 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_mcount.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_open.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_open.d new file mode 100644 index 0000000..a5c2358 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_open.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_open.o: HAL/src/alt_open.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_open.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_open.o new file mode 100644 index 0000000..0ef5a38 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_open.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_printf.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_printf.d new file mode 100644 index 0000000..0fe3550 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_printf.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_printf.o: HAL/src/alt_printf.c HAL/inc/sys/alt_stdio.h + +HAL/inc/sys/alt_stdio.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_printf.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_printf.o new file mode 100644 index 0000000..e05b2ae --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_printf.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putchar.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putchar.d new file mode 100644 index 0000000..fa6d19f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putchar.d @@ -0,0 +1 @@ +obj/HAL/src/alt_putchar.o: HAL/src/alt_putchar.c diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putchar.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putchar.o new file mode 100644 index 0000000..545dd19 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putchar.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putstr.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putstr.d new file mode 100644 index 0000000..a28ce55 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putstr.d @@ -0,0 +1 @@ +obj/HAL/src/alt_putstr.o: HAL/src/alt_putstr.c diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putstr.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putstr.o new file mode 100644 index 0000000..98a2df8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_putstr.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_read.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_read.d new file mode 100644 index 0000000..f5d459d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_read.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_read.o: HAL/src/alt_read.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_read.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_read.o new file mode 100644 index 0000000..1400e0c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_read.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_release_fd.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_release_fd.d new file mode 100644 index 0000000..137f496 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_release_fd.d @@ -0,0 +1,29 @@ +obj/HAL/src/alt_release_fd.o: HAL/src/alt_release_fd.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_release_fd.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_release_fd.o new file mode 100644 index 0000000..2092c7d --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_release_fd.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_cached.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_cached.d new file mode 100644 index 0000000..abacaa4 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_cached.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_remap_cached.o: HAL/src/alt_remap_cached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_cached.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_cached.o new file mode 100644 index 0000000..365b651 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_cached.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_uncached.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_uncached.d new file mode 100644 index 0000000..19b8e4c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_uncached.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_remap_uncached.o: HAL/src/alt_remap_uncached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_uncached.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_uncached.o new file mode 100644 index 0000000..de96c96 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_remap_uncached.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_rename.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_rename.d new file mode 100644 index 0000000..f16ad38 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_rename.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_rename.o: HAL/src/alt_rename.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_rename.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_rename.o new file mode 100644 index 0000000..65f2aaf --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_rename.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_sbrk.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_sbrk.d new file mode 100644 index 0000000..cc6de28 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_sbrk.d @@ -0,0 +1,19 @@ +obj/HAL/src/alt_sbrk.o: HAL/src/alt_sbrk.c HAL/inc/os/alt_syscall.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/sys/alt_stack.h system.h + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_stack.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_sbrk.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_sbrk.o new file mode 100644 index 0000000..68e74fd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_sbrk.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_settod.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_settod.d new file mode 100644 index 0000000..f8e7109 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_settod.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_settod.o: HAL/src/alt_settod.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_settod.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_settod.o new file mode 100644 index 0000000..cefb980 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_settod.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_software_exception.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_software_exception.d new file mode 100644 index 0000000..d17d10b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_software_exception.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_software_exception.o: HAL/src/alt_software_exception.S \ + system.h linker.h + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_software_exception.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_software_exception.o new file mode 100644 index 0000000..f9e01c2 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_software_exception.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_stat.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_stat.d new file mode 100644 index 0000000..b66e05e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_stat.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_stat.o: HAL/src/alt_stat.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_stat.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_stat.o new file mode 100644 index 0000000..6c250d7 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_stat.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_tick.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_tick.d new file mode 100644 index 0000000..88d8e2a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_tick.d @@ -0,0 +1,27 @@ +obj/HAL/src/alt_tick.o: HAL/src/alt_tick.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_hooks.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_tick.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_tick.o new file mode 100644 index 0000000..1c68bd6 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_tick.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_times.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_times.d new file mode 100644 index 0000000..e0ded1e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_times.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_times.o: HAL/src/alt_times.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_times.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_times.o new file mode 100644 index 0000000..c37555e --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_times.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_free.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_free.d new file mode 100644 index 0000000..7d5ae2b --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_free.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_uncached_free.o: HAL/src/alt_uncached_free.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_free.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_free.o new file mode 100644 index 0000000..1d9d0e0 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_free.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_malloc.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_malloc.d new file mode 100644 index 0000000..05d57d8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_malloc.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_uncached_malloc.o: HAL/src/alt_uncached_malloc.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_malloc.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_malloc.o new file mode 100644 index 0000000..1cdb55c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_uncached_malloc.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_unlink.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_unlink.d new file mode 100644 index 0000000..04b6dcd --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_unlink.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_unlink.o: HAL/src/alt_unlink.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_unlink.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_unlink.o new file mode 100644 index 0000000..17b5ae9 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_unlink.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_usleep.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_usleep.d new file mode 100644 index 0000000..c3ccee2 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_usleep.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_usleep.o: HAL/src/alt_usleep.c \ + HAL/inc/priv/alt_busy_sleep.h HAL/inc/os/alt_syscall.h + +HAL/inc/priv/alt_busy_sleep.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_usleep.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_usleep.o new file mode 100644 index 0000000..1b46b35 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_usleep.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_wait.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_wait.d new file mode 100644 index 0000000..98bf5df --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_wait.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_wait.o: HAL/src/alt_wait.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_wait.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_wait.o new file mode 100644 index 0000000..eb3a3da --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_wait.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_write.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_write.d new file mode 100644 index 0000000..722e8bc --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_write.d @@ -0,0 +1,38 @@ +obj/HAL/src/alt_write.o: HAL/src/alt_write.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_write.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_write.o new file mode 100644 index 0000000..d3aaded --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/alt_write.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/altera_nios2_qsys_irq.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/altera_nios2_qsys_irq.d new file mode 100644 index 0000000..45223c8 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/altera_nios2_qsys_irq.d @@ -0,0 +1,15 @@ +obj/HAL/src/altera_nios2_qsys_irq.o: HAL/src/altera_nios2_qsys_irq.c \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/altera_nios2_qsys_irq.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/altera_nios2_qsys_irq.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/altera_nios2_qsys_irq.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/altera_nios2_qsys_irq.o new file mode 100644 index 0000000..41f3ff2 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/altera_nios2_qsys_irq.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/crt0.d b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/crt0.d new file mode 100644 index 0000000..c1049a0 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/crt0.d @@ -0,0 +1,12 @@ +obj/HAL/src/crt0.o: HAL/src/crt0.S system.h linker.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_log_printf.h system.h + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/HAL/src/crt0.o b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/crt0.o new file mode 100644 index 0000000..631ef04 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/HAL/src/crt0.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/alt_sys_init.d b/software/DE2_115_ASM3_release_bsp/obj/alt_sys_init.d new file mode 100644 index 0000000..df7e15a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/alt_sys_init.d @@ -0,0 +1,59 @@ +obj/alt_sys_init.o: alt_sys_init.c system.h linker.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/sys/alt_sys_init.h HAL/inc/altera_nios2_qsys_irq.h \ + drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h drivers/inc/altera_avalon_lcd_16207.h \ + drivers/inc/altera_avalon_lcd_16207_fd.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/altera_nios2_qsys_irq.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/alt_sys_init.o b/software/DE2_115_ASM3_release_bsp/obj/alt_sys_init.o new file mode 100644 index 0000000..834c72f --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/alt_sys_init.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d new file mode 100644 index 0000000..5fd0251 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d @@ -0,0 +1,48 @@ +obj/drivers/src/altera_avalon_jtag_uart_fd.o: \ + drivers/src/altera_avalon_jtag_uart_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o new file mode 100644 index 0000000..8fed9bc --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d new file mode 100644 index 0000000..39101c1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d @@ -0,0 +1,66 @@ +obj/drivers/src/altera_avalon_jtag_uart_init.o: \ + drivers/src/altera_avalon_jtag_uart_init.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o new file mode 100644 index 0000000..f1e7a26 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d new file mode 100644 index 0000000..39508a1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d @@ -0,0 +1,58 @@ +obj/drivers/src/altera_avalon_jtag_uart_ioctl.o: \ + drivers/src/altera_avalon_jtag_uart_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o new file mode 100644 index 0000000..48d20e1 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d new file mode 100644 index 0000000..915c27a --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d @@ -0,0 +1,66 @@ +obj/drivers/src/altera_avalon_jtag_uart_read.o: \ + drivers/src/altera_avalon_jtag_uart_read.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o new file mode 100644 index 0000000..4a804ed --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d new file mode 100644 index 0000000..4e67aaa --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d @@ -0,0 +1,66 @@ +obj/drivers/src/altera_avalon_jtag_uart_write.o: \ + drivers/src/altera_avalon_jtag_uart_write.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o new file mode 100644 index 0000000..611a09c --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207.d b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207.d new file mode 100644 index 0000000..238baea --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207.d @@ -0,0 +1,47 @@ +obj/drivers/src/altera_avalon_lcd_16207.o: \ + drivers/src/altera_avalon_lcd_16207.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_lcd_16207_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_lcd_16207.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h drivers/inc/altera_avalon_lcd_16207_fd.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207.o b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207.o new file mode 100644 index 0000000..40ba7da --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d new file mode 100644 index 0000000..d45be02 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d @@ -0,0 +1,43 @@ +obj/drivers/src/altera_avalon_lcd_16207_fd.o: \ + drivers/src/altera_avalon_lcd_16207_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_lcd_16207.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h drivers/inc/altera_avalon_lcd_16207_fd.h \ + HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.o b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.o new file mode 100644 index 0000000..9052822 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.o Binary files differ diff --git a/software/DE2_115_ASM3_release_bsp/public.mk b/software/DE2_115_ASM3_release_bsp/public.mk new file mode 100644 index 0000000..a8f9076 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/public.mk @@ -0,0 +1,377 @@ +#------------------------------------------------------------------------------ +# BSP "PUBLIC" MAKEFILE CONTENT +# +# This file is intended to be included in an application or library +# Makefile that is using this BSP. You can create such a Makefile with +# the nios2-app-generate-makefile or nios2-lib-generate-makefile +# commands. +# +# The following variables must be defined before including this file: +# +# ALT_LIBRARY_ROOT_DIR +# Contains the path to the BSP top-level (aka root) directory +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# PATHS +#------------------------------------------------------------------------------ + + + +# Path to the provided linker script. +BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x + +# Include paths: +# The path to root of all header files that a library wishes to make +# available for an application's use is specified here. Note that this +# may not be *all* folders within a hierarchy. For example, if it is +# desired that the application developer type: +# #include +# #include +# With files laid out like this: +# /inc/sockets.h +# /inc/ip/tcpip.h +# +# Then, only /inc need be added to the list of include +# directories. Alternatively, if you wish to be able to directly include +# all files in a hierarchy, separate paths to each folder in that +# hierarchy must be defined. + +# The following are the "base" set of include paths for a BSP. +# These paths are appended to the list that individual software +# components, drivers, etc., add in the generated portion of this +# file (below). +ALT_INCLUDE_DIRS_TO_APPEND += \ + $(ALT_LIBRARY_ROOT_DIR) \ + $(ALT_LIBRARY_ROOT_DIR)/drivers/inc + +# Additions to linker library search-path: +# Here we provide a path to "our self" for the application to construct a +# "-L " out of. This should contain a list of directories, +# relative to the library root, of all directories with .a files to link +# against. +ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) + + +#------------------------------------------------------------------------------ +# COMPILATION FLAGS +#------------------------------------------------------------------------------ +# Default C pre-processor flags for a BSP: +ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ + -pipe + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +#------------------------------------------------------------------------------ +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PUBLIC_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with +# design component names. +SOPCINFO_FILE := C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + +# Big-Endian operation. +# setting BIG_ENDIAN is false +ALT_CFLAGS += -EL + +# Path to the provided C language runtime initialization code. +BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o + +# Name of BSP library as provided to linker using the "-msys-lib" flag or +# linker script GROUP command. +# setting BSP_SYS_LIB is hal_bsp +BSP_SYS_LIB := hal_bsp +ELF_PATCH_FLAG += --thread_model hal + +# Type identifier of the BSP library +# setting BSP_TYPE is hal +ALT_CPPFLAGS += -D__hal__ +BSP_TYPE := hal + +# CPU Name +# setting CPU_NAME is nios2_processor +CPU_NAME = nios2_processor +ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) + +# Hardware Divider present. +# setting HARDWARE_DIVIDE is false +ALT_CFLAGS += -mno-hw-div + +# Hardware Multiplier present. +# setting HARDWARE_MULTIPLY is false +ALT_CFLAGS += -mno-hw-mul + +# Hardware Mulx present. +# setting HARDWARE_MULX is false +ALT_CFLAGS += -mno-hw-mulx + +# Debug Core present. +# setting HAS_DEBUG_CORE is true +CPU_HAS_DEBUG_CORE = 1 + +# Qsys generated design +# setting QSYS is 1 +QSYS := 1 +ELF_PATCH_FLAG += --qsys true + +# Design Name +# setting SOPC_NAME is nios_system +SOPC_NAME := nios_system + +# SopcBuilder Simulation Enabled +# setting SOPC_SIMULATION_ENABLED is false +ELF_PATCH_FLAG += --simulation_enabled false + +# Enable JTAG UART driver to recover when host is inactive causing buffer to +# full without returning error. Printf will not fail with this recovery. none +# setting altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error is false + +# Small-footprint (polled mode) driver none +# setting altera_avalon_jtag_uart_driver.enable_small_driver is false + +# Build a custom version of newlib with the specified space-separated compiler +# flags. The custom newlib build will be placed in the <bsp root>/newlib +# directory, and will be used only for applications that utilize this BSP. +# setting hal.custom_newlib_flags is none + +# Enable support for a subset of the C++ language. This option increases code +# footprint by adding support for C++ constructors. Certain features, such as +# multiple inheritance and exceptions are not supported. If false, adds +# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code +# footprint. none +# setting hal.enable_c_plus_plus is true + +# When your application exits, close file descriptors, call C++ destructors, +# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds +# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to +# ALT_LDFLAGS in public.mk. none +# setting hal.enable_clean_exit is true + +# Add exit() support. This option increases code footprint if your "main()" +# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to +# ALT_CPPFLAGS in public.mk, and reduces footprint none +# setting hal.enable_exit is true + +# Causes code to be compiled with gprof profiling enabled and the application +# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to +# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none +# setting hal.enable_gprof is false + +# Enables lightweight device driver API. This reduces code and data footprint +# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file +# descriptors. Instead, driver routines are called directly. The open(), +# close(), and lseek() routines will always fail if called. The read(), +# write(), fstat(), ioctl(), and isatty() routines only work for the stdio +# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. +# The Altera Host and read-only ZIP file systems can't be used if +# hal.enable_lightweight_device_driver_api is true. +# setting hal.enable_lightweight_device_driver_api is false + +# Adds code to emulate multiply and divide instructions in case they are +# executed but aren't present in the CPU. Normally this isn't required because +# the compiler won't use multiply and divide instructions that aren't present +# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_mul_div_emulation is false +ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION + +# Certain drivers are compiled with reduced functionality to reduce code +# footprint. Not all drivers observe this setting. The altera_avalon_uart and +# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled +# operation. CAUTION: Several device drivers are disabled entirely. These +# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and +# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash +# access routines) to fail. You can define a symbol provided by each driver to +# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to +# ALT_CPPFLAGS in public.mk. none +# setting hal.enable_reduced_device_drivers is false + +# Turns on HAL runtime stack checking feature. Enabling this setting causes +# additional code to be placed into each subroutine call to generate an +# exception if a stack collision occurs with the heap or statically allocated +# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_runtime_stack_checking is false + +# The BSP is compiled with optimizations to speedup HDL simulation such as +# initializing the cache, clearing the .bss section, and skipping long delay +# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When +# this setting is true, the BSP shouldn't be used to build applications that +# are expected to run real hardware. +# setting hal.enable_sim_optimize is false + +# Causes the small newlib (C library) to be used. This reduces code and data +# footprint at the expense of reduced functionality. Several newlib features +# are removed such as floating-point support in printf(), stdin input routines, +# and buffered I/O. The small C library is not compatible with Micrium +# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none +# setting hal.enable_small_c_library is false + +# Enable SOPC Builder System ID. If a System ID SOPC Builder component is +# connected to the CPU associated with this BSP, it will be enabled in the +# creation of command-line arguments to download an ELF to the target. +# Otherwise, system ID and timestamp values are left out of public.mk for +# application Makefile "download-elf" target definition. With the system ID +# check disabled, the Nios II EDS tools will not automatically ensure that the +# application .elf file (and BSP it is linked against) corresponds to the +# hardware design on the target. If false, adds --accept-bad-sysid to +# SOPC_SYSID_FLAG in public.mk. none +# setting hal.enable_sopc_sysid_check is true + +# Enable BSP generation to query if SOPC system is big endian. If true ignores +# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true +# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none +# setting hal.make.ignore_system_derived.big_endian is false + +# Enable BSP generation to query if SOPC system has a debug core present. If +# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core +# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if +# no debug core is found in the system. none +# setting hal.make.ignore_system_derived.debug_core_present is false + +# Enable BSP generation to query if SOPC system has FPU present. If true +# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found +# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU +# is not found in the system. none +# setting hal.make.ignore_system_derived.fpu_present is false + +# Enable BSP generation to query if SOPC system has hardware divide present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no +# division is found in system. If true ignores export of 'ALT_CFLAGS += +# -mhw-div' if division is found in the system. none +# setting hal.make.ignore_system_derived.hardware_divide_present is false + +# Enable BSP generation to query if SOPC system floating point custom +# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS +# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to +# public.mk if the custom instruction is found in the system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is false + +# Enable BSP generation to query if SOPC system floating point custom +# instruction without a divider is present. If true ignores export of +# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += +# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the +# system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is false + +# Enable BSP generation to query if SOPC system has multiplier present. If true +# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if +# multiplier is found in the system. none +# setting hal.make.ignore_system_derived.hardware_multiplier_present is false + +# Enable BSP generation to query if SOPC system has hardware mulx present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' +# if mulx is found in the system. none +# setting hal.make.ignore_system_derived.hardware_mulx_present is false + +# Enable BSP generation to query if SOPC system has simulation enabled. If true +# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_simulation_enabled is false + +# Enable BSP generation to query SOPC system for system ID base address. If +# true ignores export of 'SOPC_SYSID_FLAG += --sidp=

' and +# 'ELF_PATCH_FLAG += --sidp=

' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_base_address is false + +# Enable BSP generation to query SOPC system for system ID. If true ignores +# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += +# --id=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_id is false + +# Enable BSP generation to query SOPC system for system timestamp. If true +# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and +# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_timestamp is false + +# Slave descriptor of STDERR character-mode device. This setting is used by the +# ALT_STDERR family of defines in system.h. none +# setting hal.stderr is jtag_uart +ELF_PATCH_FLAG += --stderr_dev jtag_uart + +# Slave descriptor of STDIN character-mode device. This setting is used by the +# ALT_STDIN family of defines in system.h. none +# setting hal.stdin is jtag_uart +ELF_PATCH_FLAG += --stdin_dev jtag_uart + +# Slave descriptor of STDOUT character-mode device. This setting is used by the +# ALT_STDOUT family of defines in system.h. none +# setting hal.stdout is jtag_uart +ELF_PATCH_FLAG += --stdout_dev jtag_uart + + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS +#------------------------------------------------------------------------------ + +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS +#------------------------------------------------------------------------------ + +ALT_CPPFLAGS += -DALT_SINGLE_THREADED + +#END MANAGED + + +#------------------------------------------------------------------------------ +# LIBRARY INFORMATION +#------------------------------------------------------------------------------ +# Assemble the name of the BSP *.a file using the BSP library name +# (BSP_SYS_LIB) in generated content above. +BSP_LIB := lib$(BSP_SYS_LIB).a + +# Additional libraries to link against: +# An application including this file will prefix each library with "-l". +# For example, to include the Newlib math library "m" is included, which +# becomes "-lm" when linking the application. +ALT_LIBRARY_NAMES += m + +# Additions to linker dependencies: +# An application Makefile will typically add these directly to the list +# of dependencies required to build the executable target(s). The BSP +# library (*.a) file is specified here. +ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) + +# Is this library "Makeable"? +# Add to list of root library directories that support running 'make' +# to build them. Because libraries may or may not have a Makefile in their +# root, appending to this variable tells an application to run 'make' in +# the library root to build/update this library. +MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) + +# Additional Assembler Flags +# -gdwarf2 flag is required for stepping through assembly code +ALT_ASFLAGS += -gdwarf2 + +#------------------------------------------------------------------------------ +# FINAL INCLUDE PATH LIST +#------------------------------------------------------------------------------ +# Append static include paths to paths specified by OS/driver/sw package +# additions to the BSP thus giving them precedence in case a BSP addition +# is attempting to override BSP sources. +ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) + + + diff --git a/software/DE2_115_ASM3_release_bsp/settings.bsp b/software/DE2_115_ASM3_release_bsp/settings.bsp new file mode 100644 index 0000000..404c1b7 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/settings.bsp @@ -0,0 +1,991 @@ + + + hal + default + 2017/01/26 11:02:28 + 1485396148639 + C:\Users\takayun\Documents\DE2-115\qsys_tutorial\software\DE2_115_ASM3_release_bsp + .\settings.bsp + C:\Users\takayun\Documents\DE2-115\qsys_tutorial\nios_system.sopcinfo + default + nios2_processor + 1.9 + + hal.sys_clk_timer + ALT_SYS_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. + none + false + common + + + hal.timestamp_timer + ALT_TIMESTAMP_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. + none + false + common + + + hal.max_file_descriptors + ALT_MAX_FD + DecimalNumber + 32 + 32 + system_h_define + Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. + If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. + false + + + + hal.enable_instruction_related_exceptions_api + ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + BooleanDefineOnly + false + false + system_h_define + Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. + These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. + false + + + + hal.linker.allow_code_at_reset + ALT_ALLOW_CODE_AT_RESET + Boolean + 1 + 0 + none + Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. + If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load + NONE + Boolean + 1 + 0 + none + Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. + This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load_copy_rodata + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_rwdata + NONE + Boolean + 1 + 0 + none + Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_exceptions + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. + none + false + + + + hal.linker.enable_exception_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. + The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.exception_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the exception stack in bytes. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.exception_stack_memory_region_name + NONE + UnquotedString + onchip_memory + none + none + Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.enable_interrupt_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. + The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.interrupt_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the interrupt stack in bytes. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.linker.interrupt_stack_memory_region_name + NONE + UnquotedString + onchip_memory + none + none + Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.stdin + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. + none + false + common + + + hal.stdout + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. + none + false + common + + + hal.stderr + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. + none + false + common + + + hal.log_port + NONE + UnquotedString + none + none + public_mk_define + Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. + none + false + none + + + hal.make.build_pre_process + BUILD_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before BSP built. + none + false + none + + + hal.make.ar_pre_process + AR_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before archiver execution. + none + false + none + + + hal.make.bsp_cflags_defined_symbols + BSP_CFLAGS_DEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.ar_post_process + AR_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after archiver execution. + none + false + none + + + hal.make.as + AS + UnquotedString + nios2-elf-gcc + nios2-elf-gcc + makefile_variable + Assembler command. Note that CC is used for .S files. + none + false + none + + + hal.make.build_post_process + BUILD_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after BSP built. + none + false + none + + + hal.make.bsp_cflags_debug + BSP_CFLAGS_DEBUG + UnquotedString + -g + -g + makefile_variable + C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. + none + false + common + + + hal.make.ar + AR + UnquotedString + nios2-elf-ar + nios2-elf-ar + makefile_variable + Archiver command. Creates library files. + none + false + none + + + hal.make.rm + RM + UnquotedString + rm -f + rm -f + makefile_variable + Command used to remove files during 'clean' target. + none + false + none + + + hal.make.cxx_pre_process + CXX_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.bsp_cflags_warnings + BSP_CFLAGS_WARNINGS + UnquotedString + -Wall + -Wall + makefile_variable + C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. + none + false + none + + + hal.make.bsp_arflags + BSP_ARFLAGS + UnquotedString + -src + -src + makefile_variable + Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. + none + false + none + + + hal.make.bsp_cflags_optimization + BSP_CFLAGS_OPTIMIZATION + UnquotedString + -O0 + -O0 + makefile_variable + C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. + none + false + common + + + hal.make.as_post_process + AS_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each assembly file is compiled. + none + false + none + + + hal.make.cc_pre_process + CC_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each .c/.S file is compiled. + none + false + none + + + hal.make.bsp_asflags + BSP_ASFLAGS + UnquotedString + -Wa,-gdwarf2 + -Wa,-gdwarf2 + makefile_variable + Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. + none + false + none + + + hal.make.as_pre_process + AS_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each assembly file is compiled. + none + false + none + + + hal.make.bsp_cflags_undefined_symbols + BSP_CFLAGS_UNDEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.cc_post_process + CC_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each .c/.S file is compiled. + none + false + none + + + hal.make.cxx_post_process + CXX_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.cc + CC + UnquotedString + nios2-elf-gcc -xc + nios2-elf-gcc -xc + makefile_variable + C compiler command. + none + false + none + + + hal.make.bsp_cxx_flags + BSP_CXXFLAGS + UnquotedString + none + none + makefile_variable + Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. + none + false + none + + + hal.make.bsp_inc_dirs + BSP_INC_DIRS + UnquotedString + none + none + makefile_variable + Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. + none + false + none + + + hal.make.cxx + CXX + UnquotedString + nios2-elf-gcc -xc++ + nios2-elf-gcc -xc++ + makefile_variable + C++ compiler command. + none + false + none + + + hal.make.bsp_cflags_user_flags + BSP_CFLAGS_USER_FLAGS + UnquotedString + none + none + makefile_variable + Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_id + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_timestamp + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_base_address + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_simulation_enabled + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.fpu_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_multiplier_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_mulx_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_divide_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. + none + false + none + + + hal.make.ignore_system_derived.debug_core_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. + none + false + none + + + hal.make.ignore_system_derived.big_endian + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.enable_exit + ALT_NO_EXIT + Boolean + 1 + 1 + public_mk_define + Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint + none + false + none + + + hal.enable_small_c_library + NONE + Boolean + 0 + 0 + public_mk_define + Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. + none + false + common + + + hal.enable_clean_exit + ALT_NO_CLEAN_EXIT + Boolean + 1 + 1 + public_mk_define + When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. + none + false + none + + + hal.enable_runtime_stack_checking + ALT_STACK_CHECK + Boolean + 0 + 0 + public_mk_define + Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_gprof + ALT_PROVIDE_GMON + Boolean + 0 + 0 + public_mk_define + Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. + none + false + common + + + hal.enable_c_plus_plus + ALT_NO_C_PLUS_PLUS + Boolean + 1 + 1 + public_mk_define + Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. + none + false + none + + + hal.enable_reduced_device_drivers + ALT_USE_SMALL_DRIVERS + Boolean + 0 + 0 + public_mk_define + Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. + none + false + common + + + hal.enable_lightweight_device_driver_api + ALT_USE_DIRECT_DRIVERS + Boolean + 0 + 0 + public_mk_define + Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. + The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. + false + none + + + hal.enable_mul_div_emulation + ALT_NO_INSTRUCTION_EMULATION + Boolean + 0 + 0 + public_mk_define + Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_sim_optimize + ALT_SIM_OPTIMIZE + Boolean + 0 + 0 + public_mk_define + The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. + When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. + false + common + + + hal.enable_sopc_sysid_check + NONE + Boolean + 1 + 1 + public_mk_define + Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. + none + false + none + + + hal.custom_newlib_flags + CUSTOM_NEWLIB_FLAGS + UnquotedString + none + none + public_mk_define + Build a custom version of newlib with the specified space-separated compiler flags. + The custom newlib build will be placed in the <bsp root>/newlib directory, and will be used only for applications that utilize this BSP. + false + none + + + hal.log_flags + ALT_LOG_FLAGS + DecimalNumber + 0 + 0 + public_mk_define + The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. + hal.log_port must be set for this to be used. + false + none + + + altera_avalon_jtag_uart_driver.enable_small_driver + ALTERA_AVALON_JTAG_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error + ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + BooleanDefineOnly + false + false + public_mk_define + Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery. + none + false + + + + onchip_memory + 0x00000000 - 0x00031FFF + 204800 + memory + + + lcd_on + 0x00041010 - 0x0004101F + 16 + + + + lcd_blon + 0x00041020 - 0x0004102F + 16 + + + + lcd_16207_0 + 0x00041030 - 0x0004103F + 16 + printable + + + hex7 + 0x00041040 - 0x0004104F + 16 + + + + hex6 + 0x00041050 - 0x0004105F + 16 + + + + hex5 + 0x00041060 - 0x0004106F + 16 + + + + hex4 + 0x00041070 - 0x0004107F + 16 + + + + hex3 + 0x00041080 - 0x0004108F + 16 + + + + hex2 + 0x00041090 - 0x0004109F + 16 + + + + hex1 + 0x000410A0 - 0x000410AF + 16 + + + + hex0 + 0x000410B0 - 0x000410BF + 16 + + + + push_switches + 0x000410C0 - 0x000410CF + 16 + + + + switches + 0x000410D0 - 0x000410DF + 16 + + + + LEDRs + 0x000410E0 - 0x000410EF + 16 + + + + LEDs + 0x000410F0 - 0x000410FF + 16 + + + + jtag_uart + 0x00041100 - 0x00041107 + 8 + printable + + + .text + onchip_memory + + + .rodata + onchip_memory + + + .rwdata + onchip_memory + + + .bss + onchip_memory + + + .heap + onchip_memory + + + .stack + onchip_memory + + \ No newline at end of file diff --git a/software/DE2_115_ASM3_release_bsp/summary.html b/software/DE2_115_ASM3_release_bsp/summary.html new file mode 100644 index 0000000..77c7739 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/summary.html @@ -0,0 +1,2047 @@ + +Altera Nios II BSP Summary + +

BSP Description

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

BSP Type:	hal
SOPC Design File:	C:\Users\takayun\Documents\DE2-115\qsys_tutorial\nios_system.sopcinfo
Quartus JDI File:	default
CPU:	nios2_processor
BSP Settings File:	.\settings.bsp
BSP Version:	default
BSP Generated On:	2017/01/26 11:02:28
BSP Generated Timestamp:	1485396148639
BSP Generated Location:	C:\Users\takayun\Documents\DE2-115\qsys_tutorial\software\DE2_115_ASM3_release_bsp

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Nios II Memory Map

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Slave Descriptor	Address Range	Size	Attributes
jtag_uart	0x00041100 - 0x00041107	8	printable
LEDs	0x000410F0 - 0x000410FF	16
LEDRs	0x000410E0 - 0x000410EF	16
switches	0x000410D0 - 0x000410DF	16
push_switches	0x000410C0 - 0x000410CF	16
hex0	0x000410B0 - 0x000410BF	16
hex1	0x000410A0 - 0x000410AF	16
hex2	0x00041090 - 0x0004109F	16
hex3	0x00041080 - 0x0004108F	16
hex4	0x00041070 - 0x0004107F	16
hex5	0x00041060 - 0x0004106F	16
hex6	0x00041050 - 0x0004105F	16
hex7	0x00041040 - 0x0004104F	16
lcd_16207_0	0x00041030 - 0x0004103F	16	printable
lcd_blon	0x00041020 - 0x0004102F	16
lcd_on	0x00041010 - 0x0004101F	16
onchip_memory	0x00000000 - 0x00031FFF	204800	memory

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Linker Regions

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Region	Address Range	Size	Memory	Offset

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Linker Section Mappings

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Section	Region
.text	onchip_memory
.rodata	onchip_memory
.rwdata	onchip_memory
.bss	onchip_memory
.heap	onchip_memory
.stack	onchip_memory

Settings

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Setting Name:	altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error
Identifier:	ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	public_mk_define
Description:	Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery.
Restrictions:	none

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Setting Name:	altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:	ALTERA_AVALON_JTAG_UART_SMALL
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	public_mk_define
Description:	Small-footprint (polled mode) driver
Restrictions:	none

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Setting Name:	hal.custom_newlib_flags
Identifier:	CUSTOM_NEWLIB_FLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	public_mk_define
Description:	Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:	The custom newlib build will be placed in the <bsp root>/newlib directory, and will be used only for applications that utilize this BSP.

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Setting Name:	hal.enable_c_plus_plus
Identifier:	ALT_NO_C_PLUS_PLUS
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:	none

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Setting Name:	hal.enable_clean_exit
Identifier:	ALT_NO_CLEAN_EXIT
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_exit
Identifier:	ALT_NO_EXIT
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:	none

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Setting Name:	hal.enable_gprof
Identifier:	ALT_PROVIDE_GMON
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_instruction_related_exceptions_api
Identifier:	ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	system_h_define
Description:	Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:	These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.

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Setting Name:	hal.enable_lightweight_device_driver_api
Identifier:	ALT_USE_DIRECT_DRIVERS
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:	The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.

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Setting Name:	hal.enable_mul_div_emulation
Identifier:	ALT_NO_INSTRUCTION_EMULATION
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_reduced_device_drivers
Identifier:	ALT_USE_SMALL_DRIVERS
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_runtime_stack_checking
Identifier:	ALT_STACK_CHECK
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_sim_optimize
Identifier:	ALT_SIM_OPTIMIZE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:	When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.

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Setting Name:	hal.enable_small_c_library
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_sopc_sysid_check
Identifier:	NONE
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:	none

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Setting Name:	hal.linker.allow_code_at_reset
Identifier:	ALT_ALLOW_CODE_AT_RESET
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:	If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.

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Setting Name:	hal.linker.enable_alt_load
Identifier:	NONE
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:	This setting is typically false if an external bootloader (e.g. flash bootloader) is present.

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Setting Name:	hal.linker.enable_alt_load_copy_exceptions
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_alt_load_copy_rodata
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_alt_load_copy_rwdata
Identifier:	NONE
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_exception_stack
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:	The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is not used.

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Setting Name:	hal.linker.enable_interrupt_stack
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:	The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is not used.

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Setting Name:	hal.linker.exception_stack_memory_region_name
Identifier:	NONE
Default Value:	none
Value:	onchip_memory
Type:	UnquotedString
Destination:	none
Description:	Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:	Only used if hal.linker.enable_exception_stack is true.

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Setting Name:	hal.linker.exception_stack_size
Identifier:	NONE
Default Value:	1024
Value:	1024
Type:	DecimalNumber
Destination:	none
Description:	Size of the exception stack in bytes.
Restrictions:	Only used if hal.linker.enable_exception_stack is true.

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Setting Name:	hal.linker.interrupt_stack_memory_region_name
Identifier:	NONE
Default Value:	none
Value:	onchip_memory
Type:	UnquotedString
Destination:	none
Description:	Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:	Only used if hal.linker.enable_interrupt_stack is true.

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Setting Name:	hal.linker.interrupt_stack_size
Identifier:	NONE
Default Value:	1024
Value:	1024
Type:	DecimalNumber
Destination:	none
Description:	Size of the interrupt stack in bytes.
Restrictions:	Only used if hal.linker.enable_interrupt_stack is true.

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Setting Name:	hal.log_flags
Identifier:	ALT_LOG_FLAGS
Default Value:	0
Value:	0
Type:	DecimalNumber
Destination:	public_mk_define
Description:	The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:	hal.log_port must be set for this to be used.

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Setting Name:	hal.log_port
Identifier:	NONE
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	public_mk_define
Description:	Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:	none

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Setting Name:	hal.make.ar
Identifier:	AR
Default Value:	nios2-elf-ar
Value:	nios2-elf-ar
Type:	UnquotedString
Destination:	makefile_variable
Description:	Archiver command. Creates library files.
Restrictions:	none

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Setting Name:	hal.make.ar_post_process
Identifier:	AR_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after archiver execution.
Restrictions:	none

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Setting Name:	hal.make.ar_pre_process
Identifier:	AR_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before archiver execution.
Restrictions:	none

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Setting Name:	hal.make.as
Identifier:	AS
Default Value:	nios2-elf-gcc
Value:	nios2-elf-gcc
Type:	UnquotedString
Destination:	makefile_variable
Description:	Assembler command. Note that CC is used for .S files.
Restrictions:	none

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Setting Name:	hal.make.as_post_process
Identifier:	AS_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after each assembly file is compiled.
Restrictions:	none

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Setting Name:	hal.make.as_pre_process
Identifier:	AS_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each assembly file is compiled.
Restrictions:	none

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Setting Name:	hal.make.bsp_arflags
Identifier:	BSP_ARFLAGS
Default Value:	-src
Value:	-src
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_asflags
Identifier:	BSP_ASFLAGS
Default Value:	-Wa,-gdwarf2
Value:	-Wa,-gdwarf2
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_debug
Identifier:	BSP_CFLAGS_DEBUG
Default Value:	-g
Value:	-g
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_defined_symbols
Identifier:	BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_optimization
Identifier:	BSP_CFLAGS_OPTIMIZATION
Default Value:	-O0
Value:	-O0
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_undefined_symbols
Identifier:	BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_user_flags
Identifier:	BSP_CFLAGS_USER_FLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_warnings
Identifier:	BSP_CFLAGS_WARNINGS
Default Value:	-Wall
Value:	-Wall
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cxx_flags
Identifier:	BSP_CXXFLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_inc_dirs
Identifier:	BSP_INC_DIRS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.build_post_process
Identifier:	BUILD_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after BSP built.
Restrictions:	none

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Setting Name:	hal.make.build_pre_process
Identifier:	BUILD_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before BSP built.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cc
Identifier:	CC
Default Value:	nios2-elf-gcc -xc
Value:	nios2-elf-gcc -xc
Type:	UnquotedString
Destination:	makefile_variable
Description:	C compiler command.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cc_post_process
Identifier:	CC_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after each .c/.S file is compiled.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cc_pre_process
Identifier:	CC_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each .c/.S file is compiled.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cxx
Identifier:	CXX
Default Value:	nios2-elf-gcc -xc++
Value:	nios2-elf-gcc -xc++
Type:	UnquotedString
Destination:	makefile_variable
Description:	C++ compiler command.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cxx_post_process
Identifier:	CXX_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each C++ file is compiled.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cxx_pre_process
Identifier:	CXX_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each C++ file is compiled.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.big_endian
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.debug_core_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.fpu_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.hardware_divide_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.hardware_mulx_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.sopc_system_base_address
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.sopc_system_id
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.rm
Identifier:	RM
Default Value:	rm -f
Value:	rm -f
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command used to remove files during 'clean' target.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.max_file_descriptors
Identifier:	ALT_MAX_FD
Default Value:	32
Value:	32
Type:	DecimalNumber
Destination:	system_h_define
Description:	Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:	If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.stderr
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.stdin
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.stdout
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.sys_clk_timer
Identifier:	ALT_SYS_CLK
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:	none

+
+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.timestamp_timer
Identifier:	ALT_TIMESTAMP_CLK
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:	none

+
+
+
+ + diff --git a/software/DE2_115_ASM3_release_bsp/system.h b/software/DE2_115_ASM3_release_bsp/system.h new file mode 100644 index 0000000..650cf13 --- /dev/null +++ b/software/DE2_115_ASM3_release_bsp/system.h @@ -0,0 +1,617 @@ +/* + * system.h - SOPC Builder system and BSP software package information + * + * Machine generated for CPU 'nios2_processor' in SOPC Builder design 'nios_system' + * SOPC Builder design path: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + * + * Generated: Thu Jan 26 11:02:29 JST 2017 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __SYSTEM_H_ +#define __SYSTEM_H_ + +/* Include definitions from linker script generator */ +#include "linker.h" + + +/* + * CPU configuration + * + */ + +#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys" +#define ALT_CPU_BIG_ENDIAN 0 +#define ALT_CPU_BREAK_ADDR 0x40820 +#define ALT_CPU_CPU_FREQ 50000000u +#define ALT_CPU_CPU_ID_SIZE 1 +#define ALT_CPU_CPU_ID_VALUE 0x00000000 +#define ALT_CPU_CPU_IMPLEMENTATION "tiny" +#define ALT_CPU_DATA_ADDR_WIDTH 0x13 +#define ALT_CPU_DCACHE_LINE_SIZE 0 +#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0 +#define ALT_CPU_DCACHE_SIZE 0 +#define ALT_CPU_EXCEPTION_ADDR 0x20 +#define ALT_CPU_FLUSHDA_SUPPORTED +#define ALT_CPU_FREQ 50000000 +#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0 +#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0 +#define ALT_CPU_HARDWARE_MULX_PRESENT 0 +#define ALT_CPU_HAS_DEBUG_CORE 1 +#define ALT_CPU_HAS_DEBUG_STUB +#define ALT_CPU_HAS_JMPI_INSTRUCTION +#define ALT_CPU_ICACHE_LINE_SIZE 0 +#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0 +#define ALT_CPU_ICACHE_SIZE 0 +#define ALT_CPU_INST_ADDR_WIDTH 0x13 +#define ALT_CPU_NAME "nios2_processor" +#define ALT_CPU_RESET_ADDR 0x0 + + +/* + * CPU configuration (with legacy prefix - don't use these anymore) + * + */ + +#define NIOS2_BIG_ENDIAN 0 +#define NIOS2_BREAK_ADDR 0x40820 +#define NIOS2_CPU_FREQ 50000000u +#define NIOS2_CPU_ID_SIZE 1 +#define NIOS2_CPU_ID_VALUE 0x00000000 +#define NIOS2_CPU_IMPLEMENTATION "tiny" +#define NIOS2_DATA_ADDR_WIDTH 0x13 +#define NIOS2_DCACHE_LINE_SIZE 0 +#define NIOS2_DCACHE_LINE_SIZE_LOG2 0 +#define NIOS2_DCACHE_SIZE 0 +#define NIOS2_EXCEPTION_ADDR 0x20 +#define NIOS2_FLUSHDA_SUPPORTED +#define NIOS2_HARDWARE_DIVIDE_PRESENT 0 +#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0 +#define NIOS2_HARDWARE_MULX_PRESENT 0 +#define NIOS2_HAS_DEBUG_CORE 1 +#define NIOS2_HAS_DEBUG_STUB +#define NIOS2_HAS_JMPI_INSTRUCTION +#define NIOS2_ICACHE_LINE_SIZE 0 +#define NIOS2_ICACHE_LINE_SIZE_LOG2 0 +#define NIOS2_ICACHE_SIZE 0 +#define NIOS2_INST_ADDR_WIDTH 0x13 +#define NIOS2_RESET_ADDR 0x0 + + +/* + * Define for each module class mastered by the CPU + * + */ + +#define __ALTERA_AVALON_JTAG_UART +#define __ALTERA_AVALON_LCD_16207 +#define __ALTERA_AVALON_ONCHIP_MEMORY2 +#define __ALTERA_AVALON_PIO +#define __ALTERA_NIOS2_QSYS + + +/* + * LEDRs configuration + * + */ + +#define ALT_MODULE_CLASS_LEDRs altera_avalon_pio +#define LEDRS_BASE 0x410e0 +#define LEDRS_BIT_CLEARING_EDGE_REGISTER 0 +#define LEDRS_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LEDRS_CAPTURE 0 +#define LEDRS_DATA_WIDTH 18 +#define LEDRS_DO_TEST_BENCH_WIRING 0 +#define LEDRS_DRIVEN_SIM_VALUE 0 +#define LEDRS_EDGE_TYPE "NONE" +#define LEDRS_FREQ 50000000 +#define LEDRS_HAS_IN 0 +#define LEDRS_HAS_OUT 1 +#define LEDRS_HAS_TRI 0 +#define LEDRS_IRQ -1 +#define LEDRS_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LEDRS_IRQ_TYPE "NONE" +#define LEDRS_NAME "/dev/LEDRs" +#define LEDRS_RESET_VALUE 0 +#define LEDRS_SPAN 16 +#define LEDRS_TYPE "altera_avalon_pio" + + +/* + * LEDs configuration + * + */ + +#define ALT_MODULE_CLASS_LEDs altera_avalon_pio +#define LEDS_BASE 0x410f0 +#define LEDS_BIT_CLEARING_EDGE_REGISTER 0 +#define LEDS_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LEDS_CAPTURE 0 +#define LEDS_DATA_WIDTH 8 +#define LEDS_DO_TEST_BENCH_WIRING 0 +#define LEDS_DRIVEN_SIM_VALUE 0 +#define LEDS_EDGE_TYPE "NONE" +#define LEDS_FREQ 50000000 +#define LEDS_HAS_IN 0 +#define LEDS_HAS_OUT 1 +#define LEDS_HAS_TRI 0 +#define LEDS_IRQ -1 +#define LEDS_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LEDS_IRQ_TYPE "NONE" +#define LEDS_NAME "/dev/LEDs" +#define LEDS_RESET_VALUE 0 +#define LEDS_SPAN 16 +#define LEDS_TYPE "altera_avalon_pio" + + +/* + * System configuration + * + */ + +#define ALT_DEVICE_FAMILY "Cyclone IV E" +#define ALT_ENHANCED_INTERRUPT_API_PRESENT +#define ALT_IRQ_BASE NULL +#define ALT_LOG_PORT "/dev/null" +#define ALT_LOG_PORT_BASE 0x0 +#define ALT_LOG_PORT_DEV null +#define ALT_LOG_PORT_TYPE "" +#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 +#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 +#define ALT_NUM_INTERRUPT_CONTROLLERS 1 +#define ALT_STDERR "/dev/jtag_uart" +#define ALT_STDERR_BASE 0x41100 +#define ALT_STDERR_DEV jtag_uart +#define ALT_STDERR_IS_JTAG_UART +#define ALT_STDERR_PRESENT +#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" +#define ALT_STDIN "/dev/jtag_uart" +#define ALT_STDIN_BASE 0x41100 +#define ALT_STDIN_DEV jtag_uart +#define ALT_STDIN_IS_JTAG_UART +#define ALT_STDIN_PRESENT +#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" +#define ALT_STDOUT "/dev/jtag_uart" +#define ALT_STDOUT_BASE 0x41100 +#define ALT_STDOUT_DEV jtag_uart +#define ALT_STDOUT_IS_JTAG_UART +#define ALT_STDOUT_PRESENT +#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" +#define ALT_SYSTEM_NAME "nios_system" + + +/* + * hal configuration + * + */ + +#define ALT_MAX_FD 32 +#define ALT_SYS_CLK none +#define ALT_TIMESTAMP_CLK none + + +/* + * hex0 configuration + * + */ + +#define ALT_MODULE_CLASS_hex0 altera_avalon_pio +#define HEX0_BASE 0x410b0 +#define HEX0_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX0_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX0_CAPTURE 0 +#define HEX0_DATA_WIDTH 7 +#define HEX0_DO_TEST_BENCH_WIRING 0 +#define HEX0_DRIVEN_SIM_VALUE 0 +#define HEX0_EDGE_TYPE "NONE" +#define HEX0_FREQ 50000000 +#define HEX0_HAS_IN 0 +#define HEX0_HAS_OUT 1 +#define HEX0_HAS_TRI 0 +#define HEX0_IRQ -1 +#define HEX0_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX0_IRQ_TYPE "NONE" +#define HEX0_NAME "/dev/hex0" +#define HEX0_RESET_VALUE 0 +#define HEX0_SPAN 16 +#define HEX0_TYPE "altera_avalon_pio" + + +/* + * hex1 configuration + * + */ + +#define ALT_MODULE_CLASS_hex1 altera_avalon_pio +#define HEX1_BASE 0x410a0 +#define HEX1_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX1_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX1_CAPTURE 0 +#define HEX1_DATA_WIDTH 7 +#define HEX1_DO_TEST_BENCH_WIRING 0 +#define HEX1_DRIVEN_SIM_VALUE 0 +#define HEX1_EDGE_TYPE "NONE" +#define HEX1_FREQ 50000000 +#define HEX1_HAS_IN 0 +#define HEX1_HAS_OUT 1 +#define HEX1_HAS_TRI 0 +#define HEX1_IRQ -1 +#define HEX1_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX1_IRQ_TYPE "NONE" +#define HEX1_NAME "/dev/hex1" +#define HEX1_RESET_VALUE 0 +#define HEX1_SPAN 16 +#define HEX1_TYPE "altera_avalon_pio" + + +/* + * hex2 configuration + * + */ + +#define ALT_MODULE_CLASS_hex2 altera_avalon_pio +#define HEX2_BASE 0x41090 +#define HEX2_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX2_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX2_CAPTURE 0 +#define HEX2_DATA_WIDTH 7 +#define HEX2_DO_TEST_BENCH_WIRING 0 +#define HEX2_DRIVEN_SIM_VALUE 0 +#define HEX2_EDGE_TYPE "NONE" +#define HEX2_FREQ 50000000 +#define HEX2_HAS_IN 0 +#define HEX2_HAS_OUT 1 +#define HEX2_HAS_TRI 0 +#define HEX2_IRQ -1 +#define HEX2_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX2_IRQ_TYPE "NONE" +#define HEX2_NAME "/dev/hex2" +#define HEX2_RESET_VALUE 0 +#define HEX2_SPAN 16 +#define HEX2_TYPE "altera_avalon_pio" + + +/* + * hex3 configuration + * + */ + +#define ALT_MODULE_CLASS_hex3 altera_avalon_pio +#define HEX3_BASE 0x41080 +#define HEX3_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX3_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX3_CAPTURE 0 +#define HEX3_DATA_WIDTH 7 +#define HEX3_DO_TEST_BENCH_WIRING 0 +#define HEX3_DRIVEN_SIM_VALUE 0 +#define HEX3_EDGE_TYPE "NONE" +#define HEX3_FREQ 50000000 +#define HEX3_HAS_IN 0 +#define HEX3_HAS_OUT 1 +#define HEX3_HAS_TRI 0 +#define HEX3_IRQ -1 +#define HEX3_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX3_IRQ_TYPE "NONE" +#define HEX3_NAME "/dev/hex3" +#define HEX3_RESET_VALUE 0 +#define HEX3_SPAN 16 +#define HEX3_TYPE "altera_avalon_pio" + + +/* + * hex4 configuration + * + */ + +#define ALT_MODULE_CLASS_hex4 altera_avalon_pio +#define HEX4_BASE 0x41070 +#define HEX4_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX4_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX4_CAPTURE 0 +#define HEX4_DATA_WIDTH 7 +#define HEX4_DO_TEST_BENCH_WIRING 0 +#define HEX4_DRIVEN_SIM_VALUE 0 +#define HEX4_EDGE_TYPE "NONE" +#define HEX4_FREQ 50000000 +#define HEX4_HAS_IN 0 +#define HEX4_HAS_OUT 1 +#define HEX4_HAS_TRI 0 +#define HEX4_IRQ -1 +#define HEX4_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX4_IRQ_TYPE "NONE" +#define HEX4_NAME "/dev/hex4" +#define HEX4_RESET_VALUE 0 +#define HEX4_SPAN 16 +#define HEX4_TYPE "altera_avalon_pio" + + +/* + * hex5 configuration + * + */ + +#define ALT_MODULE_CLASS_hex5 altera_avalon_pio +#define HEX5_BASE 0x41060 +#define HEX5_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX5_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX5_CAPTURE 0 +#define HEX5_DATA_WIDTH 7 +#define HEX5_DO_TEST_BENCH_WIRING 0 +#define HEX5_DRIVEN_SIM_VALUE 0 +#define HEX5_EDGE_TYPE "NONE" +#define HEX5_FREQ 50000000 +#define HEX5_HAS_IN 0 +#define HEX5_HAS_OUT 1 +#define HEX5_HAS_TRI 0 +#define HEX5_IRQ -1 +#define HEX5_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX5_IRQ_TYPE "NONE" +#define HEX5_NAME "/dev/hex5" +#define HEX5_RESET_VALUE 0 +#define HEX5_SPAN 16 +#define HEX5_TYPE "altera_avalon_pio" + + +/* + * hex6 configuration + * + */ + +#define ALT_MODULE_CLASS_hex6 altera_avalon_pio +#define HEX6_BASE 0x41050 +#define HEX6_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX6_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX6_CAPTURE 0 +#define HEX6_DATA_WIDTH 7 +#define HEX6_DO_TEST_BENCH_WIRING 0 +#define HEX6_DRIVEN_SIM_VALUE 0 +#define HEX6_EDGE_TYPE "NONE" +#define HEX6_FREQ 50000000 +#define HEX6_HAS_IN 0 +#define HEX6_HAS_OUT 1 +#define HEX6_HAS_TRI 0 +#define HEX6_IRQ -1 +#define HEX6_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX6_IRQ_TYPE "NONE" +#define HEX6_NAME "/dev/hex6" +#define HEX6_RESET_VALUE 0 +#define HEX6_SPAN 16 +#define HEX6_TYPE "altera_avalon_pio" + + +/* + * hex7 configuration + * + */ + +#define ALT_MODULE_CLASS_hex7 altera_avalon_pio +#define HEX7_BASE 0x41040 +#define HEX7_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX7_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX7_CAPTURE 0 +#define HEX7_DATA_WIDTH 7 +#define HEX7_DO_TEST_BENCH_WIRING 0 +#define HEX7_DRIVEN_SIM_VALUE 0 +#define HEX7_EDGE_TYPE "NONE" +#define HEX7_FREQ 50000000 +#define HEX7_HAS_IN 0 +#define HEX7_HAS_OUT 1 +#define HEX7_HAS_TRI 0 +#define HEX7_IRQ -1 +#define HEX7_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX7_IRQ_TYPE "NONE" +#define HEX7_NAME "/dev/hex7" +#define HEX7_RESET_VALUE 0 +#define HEX7_SPAN 16 +#define HEX7_TYPE "altera_avalon_pio" + + +/* + * jtag_uart configuration + * + */ + +#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart +#define JTAG_UART_BASE 0x41100 +#define JTAG_UART_IRQ 5 +#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define JTAG_UART_NAME "/dev/jtag_uart" +#define JTAG_UART_READ_DEPTH 64 +#define JTAG_UART_READ_THRESHOLD 8 +#define JTAG_UART_SPAN 8 +#define JTAG_UART_TYPE "altera_avalon_jtag_uart" +#define JTAG_UART_WRITE_DEPTH 64 +#define JTAG_UART_WRITE_THRESHOLD 8 + + +/* + * lcd_16207_0 configuration + * + */ + +#define ALT_MODULE_CLASS_lcd_16207_0 altera_avalon_lcd_16207 +#define LCD_16207_0_BASE 0x41030 +#define LCD_16207_0_IRQ -1 +#define LCD_16207_0_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LCD_16207_0_NAME "/dev/lcd_16207_0" +#define LCD_16207_0_SPAN 16 +#define LCD_16207_0_TYPE "altera_avalon_lcd_16207" + + +/* + * lcd_blon configuration + * + */ + +#define ALT_MODULE_CLASS_lcd_blon altera_avalon_pio +#define LCD_BLON_BASE 0x41020 +#define LCD_BLON_BIT_CLEARING_EDGE_REGISTER 0 +#define LCD_BLON_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LCD_BLON_CAPTURE 0 +#define LCD_BLON_DATA_WIDTH 1 +#define LCD_BLON_DO_TEST_BENCH_WIRING 0 +#define LCD_BLON_DRIVEN_SIM_VALUE 0 +#define LCD_BLON_EDGE_TYPE "NONE" +#define LCD_BLON_FREQ 50000000 +#define LCD_BLON_HAS_IN 0 +#define LCD_BLON_HAS_OUT 1 +#define LCD_BLON_HAS_TRI 0 +#define LCD_BLON_IRQ -1 +#define LCD_BLON_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LCD_BLON_IRQ_TYPE "NONE" +#define LCD_BLON_NAME "/dev/lcd_blon" +#define LCD_BLON_RESET_VALUE 0 +#define LCD_BLON_SPAN 16 +#define LCD_BLON_TYPE "altera_avalon_pio" + + +/* + * lcd_on configuration + * + */ + +#define ALT_MODULE_CLASS_lcd_on altera_avalon_pio +#define LCD_ON_BASE 0x41010 +#define LCD_ON_BIT_CLEARING_EDGE_REGISTER 0 +#define LCD_ON_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LCD_ON_CAPTURE 0 +#define LCD_ON_DATA_WIDTH 1 +#define LCD_ON_DO_TEST_BENCH_WIRING 0 +#define LCD_ON_DRIVEN_SIM_VALUE 0 +#define LCD_ON_EDGE_TYPE "NONE" +#define LCD_ON_FREQ 50000000 +#define LCD_ON_HAS_IN 0 +#define LCD_ON_HAS_OUT 1 +#define LCD_ON_HAS_TRI 0 +#define LCD_ON_IRQ -1 +#define LCD_ON_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LCD_ON_IRQ_TYPE "NONE" +#define LCD_ON_NAME "/dev/lcd_on" +#define LCD_ON_RESET_VALUE 0 +#define LCD_ON_SPAN 16 +#define LCD_ON_TYPE "altera_avalon_pio" + + +/* + * onchip_memory configuration + * + */ + +#define ALT_MODULE_CLASS_onchip_memory altera_avalon_onchip_memory2 +#define ONCHIP_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 +#define ONCHIP_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define ONCHIP_MEMORY_BASE 0x0 +#define ONCHIP_MEMORY_CONTENTS_INFO "" +#define ONCHIP_MEMORY_DUAL_PORT 0 +#define ONCHIP_MEMORY_GUI_RAM_BLOCK_TYPE "AUTO" +#define ONCHIP_MEMORY_INIT_CONTENTS_FILE "nios_system_onchip_memory" +#define ONCHIP_MEMORY_INIT_MEM_CONTENT 1 +#define ONCHIP_MEMORY_INSTANCE_ID "NONE" +#define ONCHIP_MEMORY_IRQ -1 +#define ONCHIP_MEMORY_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define ONCHIP_MEMORY_NAME "/dev/onchip_memory" +#define ONCHIP_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0 +#define ONCHIP_MEMORY_RAM_BLOCK_TYPE "AUTO" +#define ONCHIP_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE" +#define ONCHIP_MEMORY_SINGLE_CLOCK_OP 0 +#define ONCHIP_MEMORY_SIZE_MULTIPLE 1 +#define ONCHIP_MEMORY_SIZE_VALUE 204800 +#define ONCHIP_MEMORY_SPAN 204800 +#define ONCHIP_MEMORY_TYPE "altera_avalon_onchip_memory2" +#define ONCHIP_MEMORY_WRITABLE 1 + + +/* + * push_switches configuration + * + */ + +#define ALT_MODULE_CLASS_push_switches altera_avalon_pio +#define PUSH_SWITCHES_BASE 0x410c0 +#define PUSH_SWITCHES_BIT_CLEARING_EDGE_REGISTER 0 +#define PUSH_SWITCHES_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PUSH_SWITCHES_CAPTURE 0 +#define PUSH_SWITCHES_DATA_WIDTH 3 +#define PUSH_SWITCHES_DO_TEST_BENCH_WIRING 0 +#define PUSH_SWITCHES_DRIVEN_SIM_VALUE 0 +#define PUSH_SWITCHES_EDGE_TYPE "NONE" +#define PUSH_SWITCHES_FREQ 50000000 +#define PUSH_SWITCHES_HAS_IN 1 +#define PUSH_SWITCHES_HAS_OUT 0 +#define PUSH_SWITCHES_HAS_TRI 0 +#define PUSH_SWITCHES_IRQ -1 +#define PUSH_SWITCHES_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PUSH_SWITCHES_IRQ_TYPE "NONE" +#define PUSH_SWITCHES_NAME "/dev/push_switches" +#define PUSH_SWITCHES_RESET_VALUE 0 +#define PUSH_SWITCHES_SPAN 16 +#define PUSH_SWITCHES_TYPE "altera_avalon_pio" + + +/* + * switches configuration + * + */ + +#define ALT_MODULE_CLASS_switches altera_avalon_pio +#define SWITCHES_BASE 0x410d0 +#define SWITCHES_BIT_CLEARING_EDGE_REGISTER 0 +#define SWITCHES_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define SWITCHES_CAPTURE 0 +#define SWITCHES_DATA_WIDTH 18 +#define SWITCHES_DO_TEST_BENCH_WIRING 0 +#define SWITCHES_DRIVEN_SIM_VALUE 0 +#define SWITCHES_EDGE_TYPE "NONE" +#define SWITCHES_FREQ 50000000 +#define SWITCHES_HAS_IN 1 +#define SWITCHES_HAS_OUT 0 +#define SWITCHES_HAS_TRI 0 +#define SWITCHES_IRQ -1 +#define SWITCHES_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define SWITCHES_IRQ_TYPE "NONE" +#define SWITCHES_NAME "/dev/switches" +#define SWITCHES_RESET_VALUE 0 +#define SWITCHES_SPAN 16 +#define SWITCHES_TYPE "altera_avalon_pio" + +#endif /* __SYSTEM_H_ */ diff --git a/software/DE2_115_ASM_bsp/.project b/software/DE2_115_ASM_bsp/.project new file mode 100644 index 0000000..8c2089c --- /dev/null +++ b/software/DE2_115_ASM_bsp/.project @@ -0,0 +1,85 @@ + + + DE2_115_ASM_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/software/qsys_tutorial_lcd4/.project b/software/qsys_tutorial_lcd4/.project new file mode 100644 index 0000000..9112c8d --- /dev/null +++ b/software/qsys_tutorial_lcd4/.project @@ -0,0 +1,96 @@ + + + qsys_tutorial_lcd4 + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://qsys_tutorial_lcd4} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/software/qsys_tutorial_lcd4_bsp/.project b/software/qsys_tutorial_lcd4_bsp/.project new file mode 100644 index 0000000..0598622 --- /dev/null +++ b/software/qsys_tutorial_lcd4_bsp/.project @@ -0,0 +1,85 @@ + + + qsys_tutorial_lcd4_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://qsys_tutorial_lcd4_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + +