Altera Nios II BSP Summary

diff --git a/.gitignore b/.gitignore index 556a2db..c670072 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,10 @@ -*.flock \ No newline at end of file +*.flock +*/incremental_db/ +*/output_files/ +*/nios_system/ +*.bsf +*.cmp +*.sopcinfo +*.rpt +*.qsys_edit +*/db/ \ No newline at end of file diff --git a/.qsys_edit/filters.xml b/.qsys_edit/filters.xml deleted file mode 100644 index 519c8a6..0000000 --- a/.qsys_edit/filters.xml +++ /dev/null @@ -1,2 +0,0 @@ - - diff --git a/.qsys_edit/preferences.xml b/.qsys_edit/preferences.xml deleted file mode 100644 index 623aacc..0000000 --- a/.qsys_edit/preferences.xml +++ /dev/null @@ -1,21 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/app_software/.cproject b/app_software/.cproject index f967ae2..d07a4c4 100644 --- a/app_software/.cproject +++ b/app_software/.cproject @@ -1,481 +1,481 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/app_software/.project b/app_software/.project index ece6158..b583772 100644 --- a/app_software/.project +++ b/app_software/.project @@ -1,90 +1,90 @@ - - - qsys_turorial_green - - - - - - com.altera.sbtgui.project.makefileBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc://qsys_turorial_green} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.core.ccnature - com.altera.sbtgui.project.SBTGUINature - com.altera.sbtgui.project.SBTGUICustomAppNature - - + + + qsys_turorial_green + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://qsys_turorial_green} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUICustomAppNature + + diff --git a/app_software/lights.c b/app_software/lights.c index 708bb00..763f1ed 100644 --- a/app_software/lights.c +++ b/app_software/lights.c @@ -1,7 +1,7 @@ -#define switches (volatile char *) 0x0002000 -#define leds (char *) 0x0002010 - -void main() -{ - while(1) *leds = *switches; +#define switches (volatile char *) 0x0002000 +#define leds (char *) 0x0002010 + +void main() +{ + while(1) *leds = *switches; } \ No newline at end of file diff --git a/db/a_dpfifo_q131.tdf b/db/a_dpfifo_q131.tdf index 3ab4865..e177be3 100644 --- a/db/a_dpfifo_q131.tdf +++ b/db/a_dpfifo_q131.tdf @@ -1,79 +1,79 @@ ---a_dpfifo ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" ---VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION a_fefifo_7cf (aclr, clock, rreq, sclr, wreq) -RETURNS ( empty, full, usedw_out[5..0]); -FUNCTION dpram_nl21 (data[7..0], inclock, outclock, outclocken, rdaddress[5..0], wraddress[5..0], wren) -RETURNS ( q[7..0]); -FUNCTION cntr_1ob (aclr, clock, cnt_en, sclr) -RETURNS ( q[5..0]); - ---synthesis_resources = lut 18 M9K 1 reg 20 -SUBDESIGN a_dpfifo_q131 -( - aclr : input; - clock : input; - data[7..0] : input; - empty : output; - full : output; - q[7..0] : output; - rreq : input; - sclr : input; - usedw[5..0] : output; - wreq : input; -) -VARIABLE - fifo_state : a_fefifo_7cf; - FIFOram : dpram_nl21; - rd_ptr_count : cntr_1ob; - wr_ptr : cntr_1ob; - rd_ptr[5..0] : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - -BEGIN - fifo_state.aclr = aclr; - fifo_state.clock = clock; - fifo_state.rreq = rreq; - fifo_state.sclr = sclr; - fifo_state.wreq = wreq; - FIFOram.data[] = data[]; - FIFOram.inclock = clock; - FIFOram.outclock = clock; - FIFOram.outclocken = (valid_rreq # sclr); - FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]); - FIFOram.wraddress[] = wr_ptr.q[]; - FIFOram.wren = valid_wreq; - rd_ptr_count.aclr = aclr; - rd_ptr_count.clock = clock; - rd_ptr_count.cnt_en = valid_rreq; - rd_ptr_count.sclr = sclr; - wr_ptr.aclr = aclr; - wr_ptr.clock = clock; - wr_ptr.cnt_en = valid_wreq; - wr_ptr.sclr = sclr; - empty = fifo_state.empty; - full = fifo_state.full; - q[] = FIFOram.q[]; - rd_ptr[] = rd_ptr_count.q[]; - usedw[] = fifo_state.usedw_out[]; - valid_rreq = rreq; - valid_wreq = wreq; -END; ---VALID FILE +--a_dpfifo ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" +--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION a_fefifo_7cf (aclr, clock, rreq, sclr, wreq) +RETURNS ( empty, full, usedw_out[5..0]); +FUNCTION dpram_nl21 (data[7..0], inclock, outclock, outclocken, rdaddress[5..0], wraddress[5..0], wren) +RETURNS ( q[7..0]); +FUNCTION cntr_1ob (aclr, clock, cnt_en, sclr) +RETURNS ( q[5..0]); + +--synthesis_resources = lut 18 M9K 1 reg 20 +SUBDESIGN a_dpfifo_q131 +( + aclr : input; + clock : input; + data[7..0] : input; + empty : output; + full : output; + q[7..0] : output; + rreq : input; + sclr : input; + usedw[5..0] : output; + wreq : input; +) +VARIABLE + fifo_state : a_fefifo_7cf; + FIFOram : dpram_nl21; + rd_ptr_count : cntr_1ob; + wr_ptr : cntr_1ob; + rd_ptr[5..0] : WIRE; + valid_rreq : WIRE; + valid_wreq : WIRE; + +BEGIN + fifo_state.aclr = aclr; + fifo_state.clock = clock; + fifo_state.rreq = rreq; + fifo_state.sclr = sclr; + fifo_state.wreq = wreq; + FIFOram.data[] = data[]; + FIFOram.inclock = clock; + FIFOram.outclock = clock; + FIFOram.outclocken = (valid_rreq # sclr); + FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]); + FIFOram.wraddress[] = wr_ptr.q[]; + FIFOram.wren = valid_wreq; + rd_ptr_count.aclr = aclr; + rd_ptr_count.clock = clock; + rd_ptr_count.cnt_en = valid_rreq; + rd_ptr_count.sclr = sclr; + wr_ptr.aclr = aclr; + wr_ptr.clock = clock; + wr_ptr.cnt_en = valid_wreq; + wr_ptr.sclr = sclr; + empty = fifo_state.empty; + full = fifo_state.full; + q[] = FIFOram.q[]; + rd_ptr[] = rd_ptr_count.q[]; + usedw[] = fifo_state.usedw_out[]; + valid_rreq = rreq; + valid_wreq = wreq; +END; +--VALID FILE diff --git a/db/a_fefifo_7cf.tdf b/db/a_fefifo_7cf.tdf index 77853fd..3398db0 100644 --- a/db/a_fefifo_7cf.tdf +++ b/db/a_fefifo_7cf.tdf @@ -1,90 +1,90 @@ ---a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=64 lpm_widthad=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock empty full rreq sclr usedw_out wreq ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cntr_do7 (aclr, clock, cnt_en, sclr, updown) -RETURNS ( q[5..0]); - ---synthesis_resources = lut 6 reg 8 -SUBDESIGN a_fefifo_7cf -( - aclr : input; - clock : input; - empty : output; - full : output; - rreq : input; - sclr : input; - usedw_out[5..0] : output; - wreq : input; -) -VARIABLE - b_full : dffe; - b_non_empty : dffe; - count_usedw : cntr_do7; - equal_af1w[5..0] : WIRE; - equal_one[5..0] : WIRE; - is_almost_empty0 : WIRE; - is_almost_empty1 : WIRE; - is_almost_empty2 : WIRE; - is_almost_empty3 : WIRE; - is_almost_empty4 : WIRE; - is_almost_empty5 : WIRE; - is_almost_full0 : WIRE; - is_almost_full1 : WIRE; - is_almost_full2 : WIRE; - is_almost_full3 : WIRE; - is_almost_full4 : WIRE; - is_almost_full5 : WIRE; - usedw[5..0] : WIRE; - valid_rreq : WIRE; - valid_wreq : WIRE; - -BEGIN - b_full.clk = clock; - b_full.clrn = (! aclr); - b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full5 & wreq) & (! rreq))))); - b_non_empty.clk = clock; - b_non_empty.clrn = (! aclr); - b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty5 & rreq) & (! wreq)))))); - count_usedw.aclr = aclr; - count_usedw.clock = clock; - count_usedw.cnt_en = (valid_wreq $ valid_rreq); - count_usedw.sclr = sclr; - count_usedw.updown = valid_wreq; - empty = (! b_non_empty.q); - equal_af1w[] = ( B"0", B"0", B"0", B"0", B"0", B"0"); - equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"0"); - full = b_full.q; - is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]); - is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0); - is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1); - is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2); - is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3); - is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4); - is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]); - is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0); - is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1); - is_almost_full3 = ((usedw[3..3] $ equal_af1w[3..3]) & is_almost_full2); - is_almost_full4 = ((usedw[4..4] $ equal_af1w[4..4]) & is_almost_full3); - is_almost_full5 = ((usedw[5..5] $ equal_af1w[5..5]) & is_almost_full4); - usedw[] = count_usedw.q[]; - usedw_out[] = usedw[]; - valid_rreq = rreq; - valid_wreq = wreq; -END; ---VALID FILE +--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=64 lpm_widthad=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock empty full rreq sclr usedw_out wreq +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cntr_do7 (aclr, clock, cnt_en, sclr, updown) +RETURNS ( q[5..0]); + +--synthesis_resources = lut 6 reg 8 +SUBDESIGN a_fefifo_7cf +( + aclr : input; + clock : input; + empty : output; + full : output; + rreq : input; + sclr : input; + usedw_out[5..0] : output; + wreq : input; +) +VARIABLE + b_full : dffe; + b_non_empty : dffe; + count_usedw : cntr_do7; + equal_af1w[5..0] : WIRE; + equal_one[5..0] : WIRE; + is_almost_empty0 : WIRE; + is_almost_empty1 : WIRE; + is_almost_empty2 : WIRE; + is_almost_empty3 : WIRE; + is_almost_empty4 : WIRE; + is_almost_empty5 : WIRE; + is_almost_full0 : WIRE; + is_almost_full1 : WIRE; + is_almost_full2 : WIRE; + is_almost_full3 : WIRE; + is_almost_full4 : WIRE; + is_almost_full5 : WIRE; + usedw[5..0] : WIRE; + valid_rreq : WIRE; + valid_wreq : WIRE; + +BEGIN + b_full.clk = clock; + b_full.clrn = (! aclr); + b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full5 & wreq) & (! rreq))))); + b_non_empty.clk = clock; + b_non_empty.clrn = (! aclr); + b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty5 & rreq) & (! wreq)))))); + count_usedw.aclr = aclr; + count_usedw.clock = clock; + count_usedw.cnt_en = (valid_wreq $ valid_rreq); + count_usedw.sclr = sclr; + count_usedw.updown = valid_wreq; + empty = (! b_non_empty.q); + equal_af1w[] = ( B"0", B"0", B"0", B"0", B"0", B"0"); + equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"0"); + full = b_full.q; + is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]); + is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0); + is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1); + is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2); + is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3); + is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4); + is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]); + is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0); + is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1); + is_almost_full3 = ((usedw[3..3] $ equal_af1w[3..3]) & is_almost_full2); + is_almost_full4 = ((usedw[4..4] $ equal_af1w[4..4]) & is_almost_full3); + is_almost_full5 = ((usedw[5..5] $ equal_af1w[5..5]) & is_almost_full4); + usedw[] = count_usedw.q[]; + usedw_out[] = usedw[]; + valid_rreq = rreq; + valid_wreq = wreq; +END; +--VALID FILE diff --git a/db/altsyncram_0rh1.tdf b/db/altsyncram_0rh1.tdf index 44a0205..660af43 100644 --- a/db/altsyncram_0rh1.tdf +++ b/db/altsyncram_0rh1.tdf @@ -1,1042 +1,1042 @@ ---altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_rf_ram_a.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_0rh1 -( - address_a[4..0] : input; - address_b[4..0] : input; - clock0 : input; - data_a[31..0] : input; - q_b[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 25, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 26, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 27, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 28, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 29, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 30, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 31, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[4..0] : WIRE; - address_b_wire[4..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portawe = wren_a; - ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); - ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); -END; ---VALID FILE +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_rf_ram_a.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_0rh1 +( + address_a[4..0] : input; + address_b[4..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[4..0] : WIRE; + address_b_wire[4..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_1rh1.tdf b/db/altsyncram_1rh1.tdf index c0c64f2..987a124 100644 --- a/db/altsyncram_1rh1.tdf +++ b/db/altsyncram_1rh1.tdf @@ -1,1042 +1,1042 @@ ---altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_rf_ram_b.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_1rh1 -( - address_a[4..0] : input; - address_b[4..0] : input; - clock0 : input; - data_a[31..0] : input; - q_b[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 8, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 9, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 10, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 11, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 12, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 13, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 14, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 15, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 16, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 17, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 18, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 19, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 20, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 21, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 22, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 23, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 24, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 25, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 26, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 27, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 28, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 29, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 30, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", - INIT_FILE_LAYOUT = "port_b", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 5, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 31, - PORT_A_LOGICAL_RAM_DEPTH = 32, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock0", - PORT_B_ADDRESS_WIDTH = 5, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 31, - PORT_B_LAST_ADDRESS = 31, - PORT_B_LOGICAL_RAM_DEPTH = 32, - PORT_B_LOGICAL_RAM_WIDTH = 32, - PORT_B_READ_ENABLE_CLOCK = "clock0", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[4..0] : WIRE; - address_b_wire[4..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portawe = wren_a; - ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); - ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); -END; ---VALID FILE +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_rf_ram_b.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_1rh1 +( + address_a[4..0] : input; + address_b[4..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[4..0] : WIRE; + address_b_wire[4..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_4891.tdf b/db/altsyncram_4891.tdf index f3f162b..f9cb0e6 100644 --- a/db/altsyncram_4891.tdf +++ b/db/altsyncram_4891.tdf @@ -1,819 +1,819 @@ ---altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_ociram_default_contents.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 address_a byteena_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_4891 -( - address_a[7..0] : input; - byteena_a[3..0] : input; - clock0 : input; - data_a[31..0] : input; - q_a[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "none", - CLK0_INPUT_CLOCK_ENABLE = "none", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 8, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 255, - PORT_A_LOGICAL_RAM_DEPTH = 256, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[7..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]); - ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portare = B"11111111111111111111111111111111"; - ram_block1a[31..0].portawe = wren_a; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[31..0].portadataout[0..0]); -END; ---VALID FILE +--altsyncram CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_nios2_processor_ociram_default_contents.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 address_a byteena_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_4891 +( + address_a[7..0] : input; + byteena_a[3..0] : input; + clock0 : input; + data_a[31..0] : input; + q_a[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_nios2_processor_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[7..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + ram_block1a[31..0].portawe = wren_a; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[31..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_4ed1.tdf b/db/altsyncram_4ed1.tdf index cc1ada5..edb6130 100644 --- a/db/altsyncram_4ed1.tdf +++ b/db/altsyncram_4ed1.tdf @@ -1,5470 +1,5470 @@ ---altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=51200 NUMWORDS_A=51200 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=16 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION decode_qsa (data[2..0], enable) -RETURNS ( eq[6..0]); -FUNCTION mux_nob (data[223..0], sel[2..0]) -RETURNS ( result[31..0]); -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = lut 168 M9K 200 reg 3 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_4ed1 -( - address_a[15..0] : input; - byteena_a[3..0] : input; - clock0 : input; - clocken0 : input; - data_a[31..0] : input; - q_a[31..0] : output; - wren_a : input; -) -VARIABLE - address_reg_a[2..0] : dffe; - decode3 : decode_qsa; - mux2 : mux_nob; - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 8191, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a32 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a33 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a34 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a35 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a36 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a37 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a38 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a39 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a40 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a41 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a42 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a43 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a44 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a45 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a46 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a47 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a48 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a49 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a50 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a51 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a52 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a53 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a54 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a55 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a56 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a57 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a58 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a59 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a60 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a61 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a62 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a63 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 8192, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 16383, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a64 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a65 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a66 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a67 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a68 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a69 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a70 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a71 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a72 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a73 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a74 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a75 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a76 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a77 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a78 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a79 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a80 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a81 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a82 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a83 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a84 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a85 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a86 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a87 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a88 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a89 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a90 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a91 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a92 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a93 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a94 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a95 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 16384, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 24575, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a96 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a97 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a98 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a99 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a100 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a101 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a102 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a103 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a104 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a105 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a106 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a107 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a108 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a109 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a110 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a111 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a112 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a113 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a114 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a115 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a116 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a117 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a118 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a119 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a120 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a121 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a122 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a123 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a124 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a125 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a126 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a127 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 24576, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 32767, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a128 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a129 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a130 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a131 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a132 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a133 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a134 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a135 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a136 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a137 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a138 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a139 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a140 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a141 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a142 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a143 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a144 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a145 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a146 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a147 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a148 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a149 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a150 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a151 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a152 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a153 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a154 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a155 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a156 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a157 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a158 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a159 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 32768, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 40959, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a160 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a161 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a162 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a163 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a164 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a165 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a166 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a167 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a168 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a169 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a170 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a171 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a172 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a173 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a174 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a175 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a176 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a177 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a178 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a179 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a180 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a181 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a182 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a183 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a184 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a185 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a186 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a187 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a188 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a189 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a190 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a191 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 13, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 40960, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 49151, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a192 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a193 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a194 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a195 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a196 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a197 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a198 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a199 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a200 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a201 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a202 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a203 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a204 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a205 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a206 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a207 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a208 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a209 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a210 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a211 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a212 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a213 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a214 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a215 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a216 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a217 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a218 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a219 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a220 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a221 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a222 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a223 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 11, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 49152, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 51199, - PORT_A_LOGICAL_RAM_DEPTH = 51200, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_sel[2..0] : WIRE; - address_a_wire[15..0] : WIRE; - -BEGIN - address_reg_a[].clk = clock0; - address_reg_a[].d = address_a_sel[]; - address_reg_a[].ena = clocken0; - decode3.data[2..0] = address_a_wire[15..13]; - decode3.enable = wren_a; - mux2.data[] = ( ram_block1a[223..0].portadataout[0..0]); - mux2.sel[] = address_reg_a[].q; - ram_block1a[223..0].clk0 = clock0; - ram_block1a[223..0].ena0 = clocken0; - ram_block1a[191..0].portaaddr[] = ( address_a_wire[12..0]); - ram_block1a[223..192].portaaddr[] = ( address_a_wire[10..0]); - ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[39..32].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[47..40].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[55..48].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[63..56].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[71..64].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[79..72].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[87..80].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[95..88].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[103..96].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[111..104].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[119..112].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[127..120].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[135..128].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[143..136].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[151..144].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[159..152].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[167..160].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[175..168].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[183..176].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[191..184].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[199..192].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[207..200].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[215..208].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[223..216].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[32].portadatain[] = ( data_a[0..0]); - ram_block1a[33].portadatain[] = ( data_a[1..1]); - ram_block1a[34].portadatain[] = ( data_a[2..2]); - ram_block1a[35].portadatain[] = ( data_a[3..3]); - ram_block1a[36].portadatain[] = ( data_a[4..4]); - ram_block1a[37].portadatain[] = ( data_a[5..5]); - ram_block1a[38].portadatain[] = ( data_a[6..6]); - ram_block1a[39].portadatain[] = ( data_a[7..7]); - ram_block1a[40].portadatain[] = ( data_a[8..8]); - ram_block1a[41].portadatain[] = ( data_a[9..9]); - ram_block1a[42].portadatain[] = ( data_a[10..10]); - ram_block1a[43].portadatain[] = ( data_a[11..11]); - ram_block1a[44].portadatain[] = ( data_a[12..12]); - ram_block1a[45].portadatain[] = ( data_a[13..13]); - ram_block1a[46].portadatain[] = ( data_a[14..14]); - ram_block1a[47].portadatain[] = ( data_a[15..15]); - ram_block1a[48].portadatain[] = ( data_a[16..16]); - ram_block1a[49].portadatain[] = ( data_a[17..17]); - ram_block1a[50].portadatain[] = ( data_a[18..18]); - ram_block1a[51].portadatain[] = ( data_a[19..19]); - ram_block1a[52].portadatain[] = ( data_a[20..20]); - ram_block1a[53].portadatain[] = ( data_a[21..21]); - ram_block1a[54].portadatain[] = ( data_a[22..22]); - ram_block1a[55].portadatain[] = ( data_a[23..23]); - ram_block1a[56].portadatain[] = ( data_a[24..24]); - ram_block1a[57].portadatain[] = ( data_a[25..25]); - ram_block1a[58].portadatain[] = ( data_a[26..26]); - ram_block1a[59].portadatain[] = ( data_a[27..27]); - ram_block1a[60].portadatain[] = ( data_a[28..28]); - ram_block1a[61].portadatain[] = ( data_a[29..29]); - ram_block1a[62].portadatain[] = ( data_a[30..30]); - ram_block1a[63].portadatain[] = ( data_a[31..31]); - ram_block1a[64].portadatain[] = ( data_a[0..0]); - ram_block1a[65].portadatain[] = ( data_a[1..1]); - ram_block1a[66].portadatain[] = ( data_a[2..2]); - ram_block1a[67].portadatain[] = ( data_a[3..3]); - ram_block1a[68].portadatain[] = ( data_a[4..4]); - ram_block1a[69].portadatain[] = ( data_a[5..5]); - ram_block1a[70].portadatain[] = ( data_a[6..6]); - ram_block1a[71].portadatain[] = ( data_a[7..7]); - ram_block1a[72].portadatain[] = ( data_a[8..8]); - ram_block1a[73].portadatain[] = ( data_a[9..9]); - ram_block1a[74].portadatain[] = ( data_a[10..10]); - ram_block1a[75].portadatain[] = ( data_a[11..11]); - ram_block1a[76].portadatain[] = ( data_a[12..12]); - ram_block1a[77].portadatain[] = ( data_a[13..13]); - ram_block1a[78].portadatain[] = ( data_a[14..14]); - ram_block1a[79].portadatain[] = ( data_a[15..15]); - ram_block1a[80].portadatain[] = ( data_a[16..16]); - ram_block1a[81].portadatain[] = ( data_a[17..17]); - ram_block1a[82].portadatain[] = ( data_a[18..18]); - ram_block1a[83].portadatain[] = ( data_a[19..19]); - ram_block1a[84].portadatain[] = ( data_a[20..20]); - ram_block1a[85].portadatain[] = ( data_a[21..21]); - ram_block1a[86].portadatain[] = ( data_a[22..22]); - ram_block1a[87].portadatain[] = ( data_a[23..23]); - ram_block1a[88].portadatain[] = ( data_a[24..24]); - ram_block1a[89].portadatain[] = ( data_a[25..25]); - ram_block1a[90].portadatain[] = ( data_a[26..26]); - ram_block1a[91].portadatain[] = ( data_a[27..27]); - ram_block1a[92].portadatain[] = ( data_a[28..28]); - ram_block1a[93].portadatain[] = ( data_a[29..29]); - ram_block1a[94].portadatain[] = ( data_a[30..30]); - ram_block1a[95].portadatain[] = ( data_a[31..31]); - ram_block1a[96].portadatain[] = ( data_a[0..0]); - ram_block1a[97].portadatain[] = ( data_a[1..1]); - ram_block1a[98].portadatain[] = ( data_a[2..2]); - ram_block1a[99].portadatain[] = ( data_a[3..3]); - ram_block1a[100].portadatain[] = ( data_a[4..4]); - ram_block1a[101].portadatain[] = ( data_a[5..5]); - ram_block1a[102].portadatain[] = ( data_a[6..6]); - ram_block1a[103].portadatain[] = ( data_a[7..7]); - ram_block1a[104].portadatain[] = ( data_a[8..8]); - ram_block1a[105].portadatain[] = ( data_a[9..9]); - ram_block1a[106].portadatain[] = ( data_a[10..10]); - ram_block1a[107].portadatain[] = ( data_a[11..11]); - ram_block1a[108].portadatain[] = ( data_a[12..12]); - ram_block1a[109].portadatain[] = ( data_a[13..13]); - ram_block1a[110].portadatain[] = ( data_a[14..14]); - ram_block1a[111].portadatain[] = ( data_a[15..15]); - ram_block1a[112].portadatain[] = ( data_a[16..16]); - ram_block1a[113].portadatain[] = ( data_a[17..17]); - ram_block1a[114].portadatain[] = ( data_a[18..18]); - ram_block1a[115].portadatain[] = ( data_a[19..19]); - ram_block1a[116].portadatain[] = ( data_a[20..20]); - ram_block1a[117].portadatain[] = ( data_a[21..21]); - ram_block1a[118].portadatain[] = ( data_a[22..22]); - ram_block1a[119].portadatain[] = ( data_a[23..23]); - ram_block1a[120].portadatain[] = ( data_a[24..24]); - ram_block1a[121].portadatain[] = ( data_a[25..25]); - ram_block1a[122].portadatain[] = ( data_a[26..26]); - ram_block1a[123].portadatain[] = ( data_a[27..27]); - ram_block1a[124].portadatain[] = ( data_a[28..28]); - ram_block1a[125].portadatain[] = ( data_a[29..29]); - ram_block1a[126].portadatain[] = ( data_a[30..30]); - ram_block1a[127].portadatain[] = ( data_a[31..31]); - ram_block1a[128].portadatain[] = ( data_a[0..0]); - ram_block1a[129].portadatain[] = ( data_a[1..1]); - ram_block1a[130].portadatain[] = ( data_a[2..2]); - ram_block1a[131].portadatain[] = ( data_a[3..3]); - ram_block1a[132].portadatain[] = ( data_a[4..4]); - ram_block1a[133].portadatain[] = ( data_a[5..5]); - ram_block1a[134].portadatain[] = ( data_a[6..6]); - ram_block1a[135].portadatain[] = ( data_a[7..7]); - ram_block1a[136].portadatain[] = ( data_a[8..8]); - ram_block1a[137].portadatain[] = ( data_a[9..9]); - ram_block1a[138].portadatain[] = ( data_a[10..10]); - ram_block1a[139].portadatain[] = ( data_a[11..11]); - ram_block1a[140].portadatain[] = ( data_a[12..12]); - ram_block1a[141].portadatain[] = ( data_a[13..13]); - ram_block1a[142].portadatain[] = ( data_a[14..14]); - ram_block1a[143].portadatain[] = ( data_a[15..15]); - ram_block1a[144].portadatain[] = ( data_a[16..16]); - ram_block1a[145].portadatain[] = ( data_a[17..17]); - ram_block1a[146].portadatain[] = ( data_a[18..18]); - ram_block1a[147].portadatain[] = ( data_a[19..19]); - ram_block1a[148].portadatain[] = ( data_a[20..20]); - ram_block1a[149].portadatain[] = ( data_a[21..21]); - ram_block1a[150].portadatain[] = ( data_a[22..22]); - ram_block1a[151].portadatain[] = ( data_a[23..23]); - ram_block1a[152].portadatain[] = ( data_a[24..24]); - ram_block1a[153].portadatain[] = ( data_a[25..25]); - ram_block1a[154].portadatain[] = ( data_a[26..26]); - ram_block1a[155].portadatain[] = ( data_a[27..27]); - ram_block1a[156].portadatain[] = ( data_a[28..28]); - ram_block1a[157].portadatain[] = ( data_a[29..29]); - ram_block1a[158].portadatain[] = ( data_a[30..30]); - ram_block1a[159].portadatain[] = ( data_a[31..31]); - ram_block1a[160].portadatain[] = ( data_a[0..0]); - ram_block1a[161].portadatain[] = ( data_a[1..1]); - ram_block1a[162].portadatain[] = ( data_a[2..2]); - ram_block1a[163].portadatain[] = ( data_a[3..3]); - ram_block1a[164].portadatain[] = ( data_a[4..4]); - ram_block1a[165].portadatain[] = ( data_a[5..5]); - ram_block1a[166].portadatain[] = ( data_a[6..6]); - ram_block1a[167].portadatain[] = ( data_a[7..7]); - ram_block1a[168].portadatain[] = ( data_a[8..8]); - ram_block1a[169].portadatain[] = ( data_a[9..9]); - ram_block1a[170].portadatain[] = ( data_a[10..10]); - ram_block1a[171].portadatain[] = ( data_a[11..11]); - ram_block1a[172].portadatain[] = ( data_a[12..12]); - ram_block1a[173].portadatain[] = ( data_a[13..13]); - ram_block1a[174].portadatain[] = ( data_a[14..14]); - ram_block1a[175].portadatain[] = ( data_a[15..15]); - ram_block1a[176].portadatain[] = ( data_a[16..16]); - ram_block1a[177].portadatain[] = ( data_a[17..17]); - ram_block1a[178].portadatain[] = ( data_a[18..18]); - ram_block1a[179].portadatain[] = ( data_a[19..19]); - ram_block1a[180].portadatain[] = ( data_a[20..20]); - ram_block1a[181].portadatain[] = ( data_a[21..21]); - ram_block1a[182].portadatain[] = ( data_a[22..22]); - ram_block1a[183].portadatain[] = ( data_a[23..23]); - ram_block1a[184].portadatain[] = ( data_a[24..24]); - ram_block1a[185].portadatain[] = ( data_a[25..25]); - ram_block1a[186].portadatain[] = ( data_a[26..26]); - ram_block1a[187].portadatain[] = ( data_a[27..27]); - ram_block1a[188].portadatain[] = ( data_a[28..28]); - ram_block1a[189].portadatain[] = ( data_a[29..29]); - ram_block1a[190].portadatain[] = ( data_a[30..30]); - ram_block1a[191].portadatain[] = ( data_a[31..31]); - ram_block1a[192].portadatain[] = ( data_a[0..0]); - ram_block1a[193].portadatain[] = ( data_a[1..1]); - ram_block1a[194].portadatain[] = ( data_a[2..2]); - ram_block1a[195].portadatain[] = ( data_a[3..3]); - ram_block1a[196].portadatain[] = ( data_a[4..4]); - ram_block1a[197].portadatain[] = ( data_a[5..5]); - ram_block1a[198].portadatain[] = ( data_a[6..6]); - ram_block1a[199].portadatain[] = ( data_a[7..7]); - ram_block1a[200].portadatain[] = ( data_a[8..8]); - ram_block1a[201].portadatain[] = ( data_a[9..9]); - ram_block1a[202].portadatain[] = ( data_a[10..10]); - ram_block1a[203].portadatain[] = ( data_a[11..11]); - ram_block1a[204].portadatain[] = ( data_a[12..12]); - ram_block1a[205].portadatain[] = ( data_a[13..13]); - ram_block1a[206].portadatain[] = ( data_a[14..14]); - ram_block1a[207].portadatain[] = ( data_a[15..15]); - ram_block1a[208].portadatain[] = ( data_a[16..16]); - ram_block1a[209].portadatain[] = ( data_a[17..17]); - ram_block1a[210].portadatain[] = ( data_a[18..18]); - ram_block1a[211].portadatain[] = ( data_a[19..19]); - ram_block1a[212].portadatain[] = ( data_a[20..20]); - ram_block1a[213].portadatain[] = ( data_a[21..21]); - ram_block1a[214].portadatain[] = ( data_a[22..22]); - ram_block1a[215].portadatain[] = ( data_a[23..23]); - ram_block1a[216].portadatain[] = ( data_a[24..24]); - ram_block1a[217].portadatain[] = ( data_a[25..25]); - ram_block1a[218].portadatain[] = ( data_a[26..26]); - ram_block1a[219].portadatain[] = ( data_a[27..27]); - ram_block1a[220].portadatain[] = ( data_a[28..28]); - ram_block1a[221].portadatain[] = ( data_a[29..29]); - ram_block1a[222].portadatain[] = ( data_a[30..30]); - ram_block1a[223].portadatain[] = ( data_a[31..31]); - ram_block1a[223..0].portare = B"11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; - ram_block1a[223..0].portawe = ( decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); - address_a_sel[2..0] = address_a[15..13]; - address_a_wire[] = address_a[]; - q_a[] = mux2.result[]; -END; ---VALID FILE +--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=51200 NUMWORDS_A=51200 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=16 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_qsa (data[2..0], enable) +RETURNS ( eq[6..0]); +FUNCTION mux_nob (data[223..0], sel[2..0]) +RETURNS ( result[31..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 168 M9K 200 reg 3 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_4ed1 +( + address_a[15..0] : input; + byteena_a[3..0] : input; + clock0 : input; + clocken0 : input; + data_a[31..0] : input; + q_a[31..0] : output; + wren_a : input; +) +VARIABLE + address_reg_a[2..0] : dffe; + decode3 : decode_qsa; + mux2 : mux_nob; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a32 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a33 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a34 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a35 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a36 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a37 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a38 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a39 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a40 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a41 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a42 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a43 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a44 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a45 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a46 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a47 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a48 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a49 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a50 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a51 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a52 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a53 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a54 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a55 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a56 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a57 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a58 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a59 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a60 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a61 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a62 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a63 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a64 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a65 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a66 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a67 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a68 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a69 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a70 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a71 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a72 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a73 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a74 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a75 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a76 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a77 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a78 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a79 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a80 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a81 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a82 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a83 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a84 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a85 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a86 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a87 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a88 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a89 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a90 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a91 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a92 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a93 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a94 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a95 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 16384, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 24575, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a96 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a97 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a98 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a99 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a100 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a101 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a102 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a103 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a104 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a105 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a106 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a107 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a108 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a109 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a110 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a111 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a112 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a113 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a114 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a115 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a116 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a117 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a118 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a119 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a120 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a121 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a122 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a123 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a124 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a125 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a126 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a127 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 24576, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 32767, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a128 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a129 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a130 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a131 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a132 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a133 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a134 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a135 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a136 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a137 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a138 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a139 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a140 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a141 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a142 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a143 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a144 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a145 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a146 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a147 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a148 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a149 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a150 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a151 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a152 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a153 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a154 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a155 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a156 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a157 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a158 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a159 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 32768, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 40959, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a160 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a161 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a162 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a163 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a164 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a165 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a166 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a167 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a168 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a169 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a170 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a171 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a172 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a173 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a174 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a175 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a176 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a177 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a178 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a179 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a180 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a181 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a182 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a183 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a184 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a185 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a186 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a187 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a188 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a189 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a190 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a191 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 40960, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 49151, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a192 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a193 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a194 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a195 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a196 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a197 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a198 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a199 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a200 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a201 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a202 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a203 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a204 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a205 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a206 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a207 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a208 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a209 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a210 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a211 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a212 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a213 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a214 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a215 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a216 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a217 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a218 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a219 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a220 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a221 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a222 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a223 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 49152, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 51199, + PORT_A_LOGICAL_RAM_DEPTH = 51200, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[2..0] : WIRE; + address_a_wire[15..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + address_reg_a[].ena = clocken0; + decode3.data[2..0] = address_a_wire[15..13]; + decode3.enable = wren_a; + mux2.data[] = ( ram_block1a[223..0].portadataout[0..0]); + mux2.sel[] = address_reg_a[].q; + ram_block1a[223..0].clk0 = clock0; + ram_block1a[223..0].ena0 = clocken0; + ram_block1a[191..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[223..192].portaaddr[] = ( address_a_wire[10..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[39..32].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[47..40].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[55..48].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[63..56].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[71..64].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[79..72].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[87..80].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[95..88].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[103..96].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[111..104].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[119..112].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[127..120].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[135..128].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[143..136].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[151..144].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[159..152].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[167..160].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[175..168].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[183..176].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[191..184].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[199..192].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[207..200].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[215..208].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[223..216].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[32].portadatain[] = ( data_a[0..0]); + ram_block1a[33].portadatain[] = ( data_a[1..1]); + ram_block1a[34].portadatain[] = ( data_a[2..2]); + ram_block1a[35].portadatain[] = ( data_a[3..3]); + ram_block1a[36].portadatain[] = ( data_a[4..4]); + ram_block1a[37].portadatain[] = ( data_a[5..5]); + ram_block1a[38].portadatain[] = ( data_a[6..6]); + ram_block1a[39].portadatain[] = ( data_a[7..7]); + ram_block1a[40].portadatain[] = ( data_a[8..8]); + ram_block1a[41].portadatain[] = ( data_a[9..9]); + ram_block1a[42].portadatain[] = ( data_a[10..10]); + ram_block1a[43].portadatain[] = ( data_a[11..11]); + ram_block1a[44].portadatain[] = ( data_a[12..12]); + ram_block1a[45].portadatain[] = ( data_a[13..13]); + ram_block1a[46].portadatain[] = ( data_a[14..14]); + ram_block1a[47].portadatain[] = ( data_a[15..15]); + ram_block1a[48].portadatain[] = ( data_a[16..16]); + ram_block1a[49].portadatain[] = ( data_a[17..17]); + ram_block1a[50].portadatain[] = ( data_a[18..18]); + ram_block1a[51].portadatain[] = ( data_a[19..19]); + ram_block1a[52].portadatain[] = ( data_a[20..20]); + ram_block1a[53].portadatain[] = ( data_a[21..21]); + ram_block1a[54].portadatain[] = ( data_a[22..22]); + ram_block1a[55].portadatain[] = ( data_a[23..23]); + ram_block1a[56].portadatain[] = ( data_a[24..24]); + ram_block1a[57].portadatain[] = ( data_a[25..25]); + ram_block1a[58].portadatain[] = ( data_a[26..26]); + ram_block1a[59].portadatain[] = ( data_a[27..27]); + ram_block1a[60].portadatain[] = ( data_a[28..28]); + ram_block1a[61].portadatain[] = ( data_a[29..29]); + ram_block1a[62].portadatain[] = ( data_a[30..30]); + ram_block1a[63].portadatain[] = ( data_a[31..31]); + ram_block1a[64].portadatain[] = ( data_a[0..0]); + ram_block1a[65].portadatain[] = ( data_a[1..1]); + ram_block1a[66].portadatain[] = ( data_a[2..2]); + ram_block1a[67].portadatain[] = ( data_a[3..3]); + ram_block1a[68].portadatain[] = ( data_a[4..4]); + ram_block1a[69].portadatain[] = ( data_a[5..5]); + ram_block1a[70].portadatain[] = ( data_a[6..6]); + ram_block1a[71].portadatain[] = ( data_a[7..7]); + ram_block1a[72].portadatain[] = ( data_a[8..8]); + ram_block1a[73].portadatain[] = ( data_a[9..9]); + ram_block1a[74].portadatain[] = ( data_a[10..10]); + ram_block1a[75].portadatain[] = ( data_a[11..11]); + ram_block1a[76].portadatain[] = ( data_a[12..12]); + ram_block1a[77].portadatain[] = ( data_a[13..13]); + ram_block1a[78].portadatain[] = ( data_a[14..14]); + ram_block1a[79].portadatain[] = ( data_a[15..15]); + ram_block1a[80].portadatain[] = ( data_a[16..16]); + ram_block1a[81].portadatain[] = ( data_a[17..17]); + ram_block1a[82].portadatain[] = ( data_a[18..18]); + ram_block1a[83].portadatain[] = ( data_a[19..19]); + ram_block1a[84].portadatain[] = ( data_a[20..20]); + ram_block1a[85].portadatain[] = ( data_a[21..21]); + ram_block1a[86].portadatain[] = ( data_a[22..22]); + ram_block1a[87].portadatain[] = ( data_a[23..23]); + ram_block1a[88].portadatain[] = ( data_a[24..24]); + ram_block1a[89].portadatain[] = ( data_a[25..25]); + ram_block1a[90].portadatain[] = ( data_a[26..26]); + ram_block1a[91].portadatain[] = ( data_a[27..27]); + ram_block1a[92].portadatain[] = ( data_a[28..28]); + ram_block1a[93].portadatain[] = ( data_a[29..29]); + ram_block1a[94].portadatain[] = ( data_a[30..30]); + ram_block1a[95].portadatain[] = ( data_a[31..31]); + ram_block1a[96].portadatain[] = ( data_a[0..0]); + ram_block1a[97].portadatain[] = ( data_a[1..1]); + ram_block1a[98].portadatain[] = ( data_a[2..2]); + ram_block1a[99].portadatain[] = ( data_a[3..3]); + ram_block1a[100].portadatain[] = ( data_a[4..4]); + ram_block1a[101].portadatain[] = ( data_a[5..5]); + ram_block1a[102].portadatain[] = ( data_a[6..6]); + ram_block1a[103].portadatain[] = ( data_a[7..7]); + ram_block1a[104].portadatain[] = ( data_a[8..8]); + ram_block1a[105].portadatain[] = ( data_a[9..9]); + ram_block1a[106].portadatain[] = ( data_a[10..10]); + ram_block1a[107].portadatain[] = ( data_a[11..11]); + ram_block1a[108].portadatain[] = ( data_a[12..12]); + ram_block1a[109].portadatain[] = ( data_a[13..13]); + ram_block1a[110].portadatain[] = ( data_a[14..14]); + ram_block1a[111].portadatain[] = ( data_a[15..15]); + ram_block1a[112].portadatain[] = ( data_a[16..16]); + ram_block1a[113].portadatain[] = ( data_a[17..17]); + ram_block1a[114].portadatain[] = ( data_a[18..18]); + ram_block1a[115].portadatain[] = ( data_a[19..19]); + ram_block1a[116].portadatain[] = ( data_a[20..20]); + ram_block1a[117].portadatain[] = ( data_a[21..21]); + ram_block1a[118].portadatain[] = ( data_a[22..22]); + ram_block1a[119].portadatain[] = ( data_a[23..23]); + ram_block1a[120].portadatain[] = ( data_a[24..24]); + ram_block1a[121].portadatain[] = ( data_a[25..25]); + ram_block1a[122].portadatain[] = ( data_a[26..26]); + ram_block1a[123].portadatain[] = ( data_a[27..27]); + ram_block1a[124].portadatain[] = ( data_a[28..28]); + ram_block1a[125].portadatain[] = ( data_a[29..29]); + ram_block1a[126].portadatain[] = ( data_a[30..30]); + ram_block1a[127].portadatain[] = ( data_a[31..31]); + ram_block1a[128].portadatain[] = ( data_a[0..0]); + ram_block1a[129].portadatain[] = ( data_a[1..1]); + ram_block1a[130].portadatain[] = ( data_a[2..2]); + ram_block1a[131].portadatain[] = ( data_a[3..3]); + ram_block1a[132].portadatain[] = ( data_a[4..4]); + ram_block1a[133].portadatain[] = ( data_a[5..5]); + ram_block1a[134].portadatain[] = ( data_a[6..6]); + ram_block1a[135].portadatain[] = ( data_a[7..7]); + ram_block1a[136].portadatain[] = ( data_a[8..8]); + ram_block1a[137].portadatain[] = ( data_a[9..9]); + ram_block1a[138].portadatain[] = ( data_a[10..10]); + ram_block1a[139].portadatain[] = ( data_a[11..11]); + ram_block1a[140].portadatain[] = ( data_a[12..12]); + ram_block1a[141].portadatain[] = ( data_a[13..13]); + ram_block1a[142].portadatain[] = ( data_a[14..14]); + ram_block1a[143].portadatain[] = ( data_a[15..15]); + ram_block1a[144].portadatain[] = ( data_a[16..16]); + ram_block1a[145].portadatain[] = ( data_a[17..17]); + ram_block1a[146].portadatain[] = ( data_a[18..18]); + ram_block1a[147].portadatain[] = ( data_a[19..19]); + ram_block1a[148].portadatain[] = ( data_a[20..20]); + ram_block1a[149].portadatain[] = ( data_a[21..21]); + ram_block1a[150].portadatain[] = ( data_a[22..22]); + ram_block1a[151].portadatain[] = ( data_a[23..23]); + ram_block1a[152].portadatain[] = ( data_a[24..24]); + ram_block1a[153].portadatain[] = ( data_a[25..25]); + ram_block1a[154].portadatain[] = ( data_a[26..26]); + ram_block1a[155].portadatain[] = ( data_a[27..27]); + ram_block1a[156].portadatain[] = ( data_a[28..28]); + ram_block1a[157].portadatain[] = ( data_a[29..29]); + ram_block1a[158].portadatain[] = ( data_a[30..30]); + ram_block1a[159].portadatain[] = ( data_a[31..31]); + ram_block1a[160].portadatain[] = ( data_a[0..0]); + ram_block1a[161].portadatain[] = ( data_a[1..1]); + ram_block1a[162].portadatain[] = ( data_a[2..2]); + ram_block1a[163].portadatain[] = ( data_a[3..3]); + ram_block1a[164].portadatain[] = ( data_a[4..4]); + ram_block1a[165].portadatain[] = ( data_a[5..5]); + ram_block1a[166].portadatain[] = ( data_a[6..6]); + ram_block1a[167].portadatain[] = ( data_a[7..7]); + ram_block1a[168].portadatain[] = ( data_a[8..8]); + ram_block1a[169].portadatain[] = ( data_a[9..9]); + ram_block1a[170].portadatain[] = ( data_a[10..10]); + ram_block1a[171].portadatain[] = ( data_a[11..11]); + ram_block1a[172].portadatain[] = ( data_a[12..12]); + ram_block1a[173].portadatain[] = ( data_a[13..13]); + ram_block1a[174].portadatain[] = ( data_a[14..14]); + ram_block1a[175].portadatain[] = ( data_a[15..15]); + ram_block1a[176].portadatain[] = ( data_a[16..16]); + ram_block1a[177].portadatain[] = ( data_a[17..17]); + ram_block1a[178].portadatain[] = ( data_a[18..18]); + ram_block1a[179].portadatain[] = ( data_a[19..19]); + ram_block1a[180].portadatain[] = ( data_a[20..20]); + ram_block1a[181].portadatain[] = ( data_a[21..21]); + ram_block1a[182].portadatain[] = ( data_a[22..22]); + ram_block1a[183].portadatain[] = ( data_a[23..23]); + ram_block1a[184].portadatain[] = ( data_a[24..24]); + ram_block1a[185].portadatain[] = ( data_a[25..25]); + ram_block1a[186].portadatain[] = ( data_a[26..26]); + ram_block1a[187].portadatain[] = ( data_a[27..27]); + ram_block1a[188].portadatain[] = ( data_a[28..28]); + ram_block1a[189].portadatain[] = ( data_a[29..29]); + ram_block1a[190].portadatain[] = ( data_a[30..30]); + ram_block1a[191].portadatain[] = ( data_a[31..31]); + ram_block1a[192].portadatain[] = ( data_a[0..0]); + ram_block1a[193].portadatain[] = ( data_a[1..1]); + ram_block1a[194].portadatain[] = ( data_a[2..2]); + ram_block1a[195].portadatain[] = ( data_a[3..3]); + ram_block1a[196].portadatain[] = ( data_a[4..4]); + ram_block1a[197].portadatain[] = ( data_a[5..5]); + ram_block1a[198].portadatain[] = ( data_a[6..6]); + ram_block1a[199].portadatain[] = ( data_a[7..7]); + ram_block1a[200].portadatain[] = ( data_a[8..8]); + ram_block1a[201].portadatain[] = ( data_a[9..9]); + ram_block1a[202].portadatain[] = ( data_a[10..10]); + ram_block1a[203].portadatain[] = ( data_a[11..11]); + ram_block1a[204].portadatain[] = ( data_a[12..12]); + ram_block1a[205].portadatain[] = ( data_a[13..13]); + ram_block1a[206].portadatain[] = ( data_a[14..14]); + ram_block1a[207].portadatain[] = ( data_a[15..15]); + ram_block1a[208].portadatain[] = ( data_a[16..16]); + ram_block1a[209].portadatain[] = ( data_a[17..17]); + ram_block1a[210].portadatain[] = ( data_a[18..18]); + ram_block1a[211].portadatain[] = ( data_a[19..19]); + ram_block1a[212].portadatain[] = ( data_a[20..20]); + ram_block1a[213].portadatain[] = ( data_a[21..21]); + ram_block1a[214].portadatain[] = ( data_a[22..22]); + ram_block1a[215].portadatain[] = ( data_a[23..23]); + ram_block1a[216].portadatain[] = ( data_a[24..24]); + ram_block1a[217].portadatain[] = ( data_a[25..25]); + ram_block1a[218].portadatain[] = ( data_a[26..26]); + ram_block1a[219].portadatain[] = ( data_a[27..27]); + ram_block1a[220].portadatain[] = ( data_a[28..28]); + ram_block1a[221].portadatain[] = ( data_a[29..29]); + ram_block1a[222].portadatain[] = ( data_a[30..30]); + ram_block1a[223].portadatain[] = ( data_a[31..31]); + ram_block1a[223..0].portare = B"11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; + ram_block1a[223..0].portawe = ( decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]); + address_a_sel[2..0] = address_a[15..13]; + address_a_wire[] = address_a[]; + q_a[] = mux2.result[]; +END; +--VALID FILE diff --git a/db/altsyncram_mbd1.tdf b/db/altsyncram_mbd1.tdf index 4e2ebe5..638b810 100644 --- a/db/altsyncram_mbd1.tdf +++ b/db/altsyncram_mbd1.tdf @@ -1,821 +1,821 @@ ---altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=4096 NUMWORDS_A=4096 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=12 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 16 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_mbd1 -( - address_a[11..0] : input; - byteena_a[3..0] : input; - clock0 : input; - clocken0 : input; - data_a[31..0] : input; - q_a[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 12, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 4095, - PORT_A_LOGICAL_RAM_DEPTH = 4096, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[11..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].ena0 = clocken0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[11..0]); - ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portare = B"11111111111111111111111111111111"; - ram_block1a[31..0].portawe = wren_a; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[31..0].portadataout[0..0]); -END; ---VALID FILE +--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=4096 NUMWORDS_A=4096 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=12 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 16 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_mbd1 +( + address_a[11..0] : input; + byteena_a[3..0] : input; + clock0 : input; + clocken0 : input; + data_a[31..0] : input; + q_a[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 12, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 4095, + PORT_A_LOGICAL_RAM_DEPTH = 4096, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[11..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].ena0 = clocken0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[11..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + ram_block1a[31..0].portawe = wren_a; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[31..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_r1m1.tdf b/db/altsyncram_r1m1.tdf index 7a0fc2e..15e2d8b 100644 --- a/db/altsyncram_r1m1.tdf +++ b/db/altsyncram_r1m1.tdf @@ -1,303 +1,303 @@ ---altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 1 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_r1m1 -( - address_a[5..0] : input; - address_b[5..0] : input; - clock0 : input; - clock1 : input; - clocken1 : input; - data_a[7..0] : input; - q_b[7..0] : output; - wren_a : input; -) -VARIABLE - ram_block2a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 0, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 1, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 2, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 3, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 4, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 5, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 6, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block2a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "none", - CLK1_CORE_CLOCK_ENABLE = "ena1", - CLK1_INPUT_CLOCK_ENABLE = "ena1", - CONNECTIVITY_CHECKING = "OFF", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - MIXED_PORT_FEED_THROUGH_MODE = "dont_care", - OPERATION_MODE = "dual_port", - PORT_A_ADDRESS_WIDTH = 6, - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 63, - PORT_A_LOGICAL_RAM_DEPTH = 64, - PORT_A_LOGICAL_RAM_WIDTH = 8, - PORT_B_ADDRESS_CLEAR = "none", - PORT_B_ADDRESS_CLOCK = "clock1", - PORT_B_ADDRESS_WIDTH = 6, - PORT_B_DATA_OUT_CLEAR = "none", - PORT_B_DATA_WIDTH = 1, - PORT_B_FIRST_ADDRESS = 0, - PORT_B_FIRST_BIT_NUMBER = 7, - PORT_B_LAST_ADDRESS = 63, - PORT_B_LOGICAL_RAM_DEPTH = 64, - PORT_B_LOGICAL_RAM_WIDTH = 8, - PORT_B_READ_ENABLE_CLOCK = "clock1", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[5..0] : WIRE; - address_b_wire[5..0] : WIRE; - -BEGIN - ram_block2a[7..0].clk0 = clock0; - ram_block2a[7..0].clk1 = clock1; - ram_block2a[7..0].ena0 = wren_a; - ram_block2a[7..0].ena1 = clocken1; - ram_block2a[7..0].portaaddr[] = ( address_a_wire[5..0]); - ram_block2a[0].portadatain[] = ( data_a[0..0]); - ram_block2a[1].portadatain[] = ( data_a[1..1]); - ram_block2a[2].portadatain[] = ( data_a[2..2]); - ram_block2a[3].portadatain[] = ( data_a[3..3]); - ram_block2a[4].portadatain[] = ( data_a[4..4]); - ram_block2a[5].portadatain[] = ( data_a[5..5]); - ram_block2a[6].portadatain[] = ( data_a[6..6]); - ram_block2a[7].portadatain[] = ( data_a[7..7]); - ram_block2a[7..0].portawe = wren_a; - ram_block2a[7..0].portbaddr[] = ( address_b_wire[5..0]); - ram_block2a[7..0].portbre = B"11111111"; - address_a_wire[] = address_a[]; - address_b_wire[] = address_b[]; - q_b[] = ( ram_block2a[7..0].portbdataout[0..0]); -END; ---VALID FILE +--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_r1m1 +( + address_a[5..0] : input; + address_b[5..0] : input; + clock0 : input; + clock1 : input; + clocken1 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block2a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[5..0] : WIRE; + address_b_wire[5..0] : WIRE; + +BEGIN + ram_block2a[7..0].clk0 = clock0; + ram_block2a[7..0].clk1 = clock1; + ram_block2a[7..0].ena0 = wren_a; + ram_block2a[7..0].ena1 = clocken1; + ram_block2a[7..0].portaaddr[] = ( address_a_wire[5..0]); + ram_block2a[0].portadatain[] = ( data_a[0..0]); + ram_block2a[1].portadatain[] = ( data_a[1..1]); + ram_block2a[2].portadatain[] = ( data_a[2..2]); + ram_block2a[3].portadatain[] = ( data_a[3..3]); + ram_block2a[4].portadatain[] = ( data_a[4..4]); + ram_block2a[5].portadatain[] = ( data_a[5..5]); + ram_block2a[6].portadatain[] = ( data_a[6..6]); + ram_block2a[7].portadatain[] = ( data_a[7..7]); + ram_block2a[7..0].portawe = wren_a; + ram_block2a[7..0].portbaddr[] = ( address_b_wire[5..0]); + ram_block2a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block2a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/db/altsyncram_sad1.tdf b/db/altsyncram_sad1.tdf index a692a4f..674477b 100644 --- a/db/altsyncram_sad1.tdf +++ b/db/altsyncram_sad1.tdf @@ -1,821 +1,821 @@ ---altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=1024 NUMWORDS_A=1024 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=10 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 ---VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) -WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) -RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); - ---synthesis_resources = M9K 4 -OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; - -SUBDESIGN altsyncram_sad1 -( - address_a[9..0] : input; - byteena_a[3..0] : input; - clock0 : input; - clocken0 : input; - data_a[31..0] : input; - q_a[31..0] : output; - wren_a : input; -) -VARIABLE - ram_block1a0 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 0, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a1 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 1, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a2 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 2, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a3 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 3, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a4 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 4, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a5 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 5, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a6 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 6, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a7 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 7, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a8 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 8, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a9 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 9, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a10 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 10, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a11 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 11, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a12 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 12, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a13 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 13, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a14 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 14, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a15 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 15, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a16 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 16, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a17 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 17, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a18 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 18, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a19 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 19, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a20 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 20, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a21 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 21, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a22 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 22, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a23 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 23, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a24 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 24, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a25 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 25, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a26 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 26, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a27 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 27, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a28 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 28, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a29 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 29, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a30 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 30, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - ram_block1a31 : cycloneive_ram_block - WITH ( - CLK0_CORE_CLOCK_ENABLE = "ena0", - CLK0_INPUT_CLOCK_ENABLE = "ena0", - CONNECTIVITY_CHECKING = "OFF", - INIT_FILE = "nios_system_onchip_memory.hex", - INIT_FILE_LAYOUT = "port_a", - LOGICAL_RAM_NAME = "ALTSYNCRAM", - OPERATION_MODE = "single_port", - PORT_A_ADDRESS_WIDTH = 10, - PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, - PORT_A_BYTE_SIZE = 1, - PORT_A_DATA_OUT_CLEAR = "none", - PORT_A_DATA_OUT_CLOCK = "none", - PORT_A_DATA_WIDTH = 1, - PORT_A_FIRST_ADDRESS = 0, - PORT_A_FIRST_BIT_NUMBER = 31, - PORT_A_LAST_ADDRESS = 1023, - PORT_A_LOGICAL_RAM_DEPTH = 1024, - PORT_A_LOGICAL_RAM_WIDTH = 32, - PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", - RAM_BLOCK_TYPE = "AUTO" - ); - address_a_wire[9..0] : WIRE; - -BEGIN - ram_block1a[31..0].clk0 = clock0; - ram_block1a[31..0].ena0 = clocken0; - ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]); - ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); - ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); - ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); - ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); - ram_block1a[0].portadatain[] = ( data_a[0..0]); - ram_block1a[1].portadatain[] = ( data_a[1..1]); - ram_block1a[2].portadatain[] = ( data_a[2..2]); - ram_block1a[3].portadatain[] = ( data_a[3..3]); - ram_block1a[4].portadatain[] = ( data_a[4..4]); - ram_block1a[5].portadatain[] = ( data_a[5..5]); - ram_block1a[6].portadatain[] = ( data_a[6..6]); - ram_block1a[7].portadatain[] = ( data_a[7..7]); - ram_block1a[8].portadatain[] = ( data_a[8..8]); - ram_block1a[9].portadatain[] = ( data_a[9..9]); - ram_block1a[10].portadatain[] = ( data_a[10..10]); - ram_block1a[11].portadatain[] = ( data_a[11..11]); - ram_block1a[12].portadatain[] = ( data_a[12..12]); - ram_block1a[13].portadatain[] = ( data_a[13..13]); - ram_block1a[14].portadatain[] = ( data_a[14..14]); - ram_block1a[15].portadatain[] = ( data_a[15..15]); - ram_block1a[16].portadatain[] = ( data_a[16..16]); - ram_block1a[17].portadatain[] = ( data_a[17..17]); - ram_block1a[18].portadatain[] = ( data_a[18..18]); - ram_block1a[19].portadatain[] = ( data_a[19..19]); - ram_block1a[20].portadatain[] = ( data_a[20..20]); - ram_block1a[21].portadatain[] = ( data_a[21..21]); - ram_block1a[22].portadatain[] = ( data_a[22..22]); - ram_block1a[23].portadatain[] = ( data_a[23..23]); - ram_block1a[24].portadatain[] = ( data_a[24..24]); - ram_block1a[25].portadatain[] = ( data_a[25..25]); - ram_block1a[26].portadatain[] = ( data_a[26..26]); - ram_block1a[27].portadatain[] = ( data_a[27..27]); - ram_block1a[28].portadatain[] = ( data_a[28..28]); - ram_block1a[29].portadatain[] = ( data_a[29..29]); - ram_block1a[30].portadatain[] = ( data_a[30..30]); - ram_block1a[31].portadatain[] = ( data_a[31..31]); - ram_block1a[31..0].portare = B"11111111111111111111111111111111"; - ram_block1a[31..0].portawe = wren_a; - address_a_wire[] = address_a[]; - q_a[] = ( ram_block1a[31..0].portadataout[0..0]); -END; ---VALID FILE +--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="nios_system_onchip_memory.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=1024 NUMWORDS_A=1024 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=10 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_sad1 +( + address_a[9..0] : input; + byteena_a[3..0] : input; + clock0 : input; + clocken0 : input; + data_a[31..0] : input; + q_a[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "nios_system_onchip_memory.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "single_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[9..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].ena0 = clocken0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + ram_block1a[31..0].portawe = wren_a; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[31..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/db/cntr_1ob.tdf b/db/cntr_1ob.tdf index 48889a0..f20e091 100644 --- a/db/cntr_1ob.tdf +++ b/db/cntr_1ob.tdf @@ -1,97 +1,97 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=6 aclr clock cnt_en q sclr ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 6 reg 6 -SUBDESIGN cntr_1ob -( - aclr : input; - clock : input; - cnt_en : input; - q[5..0] : output; - sclr : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita3 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita4 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita5 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[5..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[5..0] : NODE; - external_cin : WIRE; - s_val[5..0] : WIRE; - safe_q[5..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); - counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); - counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); - counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = aclr; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"111111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = B"1"; -END; ---VALID FILE +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=6 aclr clock cnt_en q sclr +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 6 reg 6 +SUBDESIGN cntr_1ob +( + aclr : input; + clock : input; + cnt_en : input; + q[5..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[5..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[5..0] : NODE; + external_cin : WIRE; + s_val[5..0] : WIRE; + safe_q[5..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); + counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); + counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = aclr; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/db/cntr_do7.tdf b/db/cntr_do7.tdf index f49ff1c..cf34edf 100644 --- a/db/cntr_do7.tdf +++ b/db/cntr_do7.tdf @@ -1,98 +1,98 @@ ---lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=6 aclr clock cnt_en q sclr updown ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) -WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) -RETURNS ( combout, cout); - ---synthesis_resources = lut 6 reg 6 -SUBDESIGN cntr_do7 -( - aclr : input; - clock : input; - cnt_en : input; - q[5..0] : output; - sclr : input; - updown : input; -) -VARIABLE - counter_comb_bita0 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita1 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita2 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita3 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita4 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_comb_bita5 : cycloneive_lcell_comb - WITH ( - LUT_MASK = "5A90", - SUM_LUTC_INPUT = "cin" - ); - counter_reg_bit[5..0] : dffeas; - aclr_actual : WIRE; - clk_en : NODE; - data[5..0] : NODE; - external_cin : WIRE; - s_val[5..0] : WIRE; - safe_q[5..0] : WIRE; - sload : NODE; - sset : NODE; - updown_dir : WIRE; - -BEGIN - counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); - counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); - counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); - counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); - counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); - counter_reg_bit[].clk = clock; - counter_reg_bit[].clrn = (! aclr_actual); - counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); - counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); - counter_reg_bit[].sload = ((sclr # sset) # sload); - aclr_actual = aclr; - clk_en = VCC; - data[] = GND; - external_cin = B"1"; - q[] = safe_q[]; - s_val[] = B"111111"; - safe_q[] = counter_reg_bit[].q; - sload = GND; - sset = GND; - updown_dir = updown; -END; ---VALID FILE +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=6 aclr clock cnt_en q sclr updown +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 6 reg 6 +SUBDESIGN cntr_do7 +( + aclr : input; + clock : input; + cnt_en : input; + q[5..0] : output; + sclr : input; + updown : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[5..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[5..0] : NODE; + external_cin : WIRE; + s_val[5..0] : WIRE; + safe_q[5..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); + counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); + counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = aclr; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = updown; +END; +--VALID FILE diff --git a/db/decode_qsa.tdf b/db/decode_qsa.tdf index 01e442e..78baf29 100644 --- a/db/decode_qsa.tdf +++ b/db/decode_qsa.tdf @@ -1,57 +1,57 @@ ---lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=7 LPM_WIDTH=3 data enable eq ---VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - - ---synthesis_resources = lut 8 -SUBDESIGN decode_qsa -( - data[2..0] : input; - enable : input; - eq[6..0] : output; -) -VARIABLE - data_wire[2..0] : WIRE; - enable_wire : WIRE; - eq_node[6..0] : WIRE; - eq_wire[7..0] : WIRE; - w_anode1849w[3..0] : WIRE; - w_anode1866w[3..0] : WIRE; - w_anode1876w[3..0] : WIRE; - w_anode1886w[3..0] : WIRE; - w_anode1896w[3..0] : WIRE; - w_anode1906w[3..0] : WIRE; - w_anode1916w[3..0] : WIRE; - w_anode1926w[3..0] : WIRE; - -BEGIN - data_wire[] = data[]; - enable_wire = enable; - eq[] = eq_node[]; - eq_node[6..0] = eq_wire[6..0]; - eq_wire[] = ( w_anode1926w[3..3], w_anode1916w[3..3], w_anode1906w[3..3], w_anode1896w[3..3], w_anode1886w[3..3], w_anode1876w[3..3], w_anode1866w[3..3], w_anode1849w[3..3]); - w_anode1849w[] = ( (w_anode1849w[2..2] & (! data_wire[2..2])), (w_anode1849w[1..1] & (! data_wire[1..1])), (w_anode1849w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode1866w[] = ( (w_anode1866w[2..2] & (! data_wire[2..2])), (w_anode1866w[1..1] & (! data_wire[1..1])), (w_anode1866w[0..0] & data_wire[0..0]), enable_wire); - w_anode1876w[] = ( (w_anode1876w[2..2] & (! data_wire[2..2])), (w_anode1876w[1..1] & data_wire[1..1]), (w_anode1876w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode1886w[] = ( (w_anode1886w[2..2] & (! data_wire[2..2])), (w_anode1886w[1..1] & data_wire[1..1]), (w_anode1886w[0..0] & data_wire[0..0]), enable_wire); - w_anode1896w[] = ( (w_anode1896w[2..2] & data_wire[2..2]), (w_anode1896w[1..1] & (! data_wire[1..1])), (w_anode1896w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode1906w[] = ( (w_anode1906w[2..2] & data_wire[2..2]), (w_anode1906w[1..1] & (! data_wire[1..1])), (w_anode1906w[0..0] & data_wire[0..0]), enable_wire); - w_anode1916w[] = ( (w_anode1916w[2..2] & data_wire[2..2]), (w_anode1916w[1..1] & data_wire[1..1]), (w_anode1916w[0..0] & (! data_wire[0..0])), enable_wire); - w_anode1926w[] = ( (w_anode1926w[2..2] & data_wire[2..2]), (w_anode1926w[1..1] & data_wire[1..1]), (w_anode1926w[0..0] & data_wire[0..0]), enable_wire); -END; ---VALID FILE +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=7 LPM_WIDTH=3 data enable eq +--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 8 +SUBDESIGN decode_qsa +( + data[2..0] : input; + enable : input; + eq[6..0] : output; +) +VARIABLE + data_wire[2..0] : WIRE; + enable_wire : WIRE; + eq_node[6..0] : WIRE; + eq_wire[7..0] : WIRE; + w_anode1849w[3..0] : WIRE; + w_anode1866w[3..0] : WIRE; + w_anode1876w[3..0] : WIRE; + w_anode1886w[3..0] : WIRE; + w_anode1896w[3..0] : WIRE; + w_anode1906w[3..0] : WIRE; + w_anode1916w[3..0] : WIRE; + w_anode1926w[3..0] : WIRE; + +BEGIN + data_wire[] = data[]; + enable_wire = enable; + eq[] = eq_node[]; + eq_node[6..0] = eq_wire[6..0]; + eq_wire[] = ( w_anode1926w[3..3], w_anode1916w[3..3], w_anode1906w[3..3], w_anode1896w[3..3], w_anode1886w[3..3], w_anode1876w[3..3], w_anode1866w[3..3], w_anode1849w[3..3]); + w_anode1849w[] = ( (w_anode1849w[2..2] & (! data_wire[2..2])), (w_anode1849w[1..1] & (! data_wire[1..1])), (w_anode1849w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode1866w[] = ( (w_anode1866w[2..2] & (! data_wire[2..2])), (w_anode1866w[1..1] & (! data_wire[1..1])), (w_anode1866w[0..0] & data_wire[0..0]), enable_wire); + w_anode1876w[] = ( (w_anode1876w[2..2] & (! data_wire[2..2])), (w_anode1876w[1..1] & data_wire[1..1]), (w_anode1876w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode1886w[] = ( (w_anode1886w[2..2] & (! data_wire[2..2])), (w_anode1886w[1..1] & data_wire[1..1]), (w_anode1886w[0..0] & data_wire[0..0]), enable_wire); + w_anode1896w[] = ( (w_anode1896w[2..2] & data_wire[2..2]), (w_anode1896w[1..1] & (! data_wire[1..1])), (w_anode1896w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode1906w[] = ( (w_anode1906w[2..2] & data_wire[2..2]), (w_anode1906w[1..1] & (! data_wire[1..1])), (w_anode1906w[0..0] & data_wire[0..0]), enable_wire); + w_anode1916w[] = ( (w_anode1916w[2..2] & data_wire[2..2]), (w_anode1916w[1..1] & data_wire[1..1]), (w_anode1916w[0..0] & (! data_wire[0..0])), enable_wire); + w_anode1926w[] = ( (w_anode1926w[2..2] & data_wire[2..2]), (w_anode1926w[1..1] & data_wire[1..1]), (w_anode1926w[0..0] & data_wire[0..0]), enable_wire); +END; +--VALID FILE diff --git a/db/dpram_nl21.tdf b/db/dpram_nl21.tdf index b9d037d..ed4cc69 100644 --- a/db/dpram_nl21.tdf +++ b/db/dpram_nl21.tdf @@ -1,48 +1,48 @@ ---altdpram DEVICE_FAMILY="Cyclone IV E" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=8 WIDTHAD=6 data inclock outclock outclocken q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" ---VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION altsyncram_r1m1 (address_a[5..0], address_b[5..0], clock0, clock1, clocken1, data_a[7..0], wren_a) -RETURNS ( q_b[7..0]); - ---synthesis_resources = M9K 1 -SUBDESIGN dpram_nl21 -( - data[7..0] : input; - inclock : input; - outclock : input; - outclocken : input; - q[7..0] : output; - rdaddress[5..0] : input; - wraddress[5..0] : input; - wren : input; -) -VARIABLE - altsyncram1 : altsyncram_r1m1; - -BEGIN - altsyncram1.address_a[] = wraddress[]; - altsyncram1.address_b[] = rdaddress[]; - altsyncram1.clock0 = inclock; - altsyncram1.clock1 = outclock; - altsyncram1.clocken1 = outclocken; - altsyncram1.data_a[] = data[]; - altsyncram1.wren_a = wren; - q[] = altsyncram1.q_b[]; -END; ---VALID FILE +--altdpram DEVICE_FAMILY="Cyclone IV E" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=8 WIDTHAD=6 data inclock outclock outclocken q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" +--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION altsyncram_r1m1 (address_a[5..0], address_b[5..0], clock0, clock1, clocken1, data_a[7..0], wren_a) +RETURNS ( q_b[7..0]); + +--synthesis_resources = M9K 1 +SUBDESIGN dpram_nl21 +( + data[7..0] : input; + inclock : input; + outclock : input; + outclocken : input; + q[7..0] : output; + rdaddress[5..0] : input; + wraddress[5..0] : input; + wren : input; +) +VARIABLE + altsyncram1 : altsyncram_r1m1; + +BEGIN + altsyncram1.address_a[] = wraddress[]; + altsyncram1.address_b[] = rdaddress[]; + altsyncram1.clock0 = inclock; + altsyncram1.clock1 = outclock; + altsyncram1.clocken1 = outclocken; + altsyncram1.data_a[] = data[]; + altsyncram1.wren_a = wren; + q[] = altsyncram1.q_b[]; +END; +--VALID FILE diff --git a/db/ip/nios_system/nios_system.bsf b/db/ip/nios_system/nios_system.bsf deleted file mode 100644 index dac37b1..0000000 --- a/db/ip/nios_system/nios_system.bsf +++ /dev/null @@ -1,248 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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(line (pt 161 740)(pt 161 764)(line_width 1)) - (line (pt 162 740)(pt 162 764)(line_width 1)) - (line (pt 160 32)(pt 224 32)(line_width 1)) - (line (pt 224 32)(pt 224 776)(line_width 1)) - (line (pt 160 776)(pt 224 776)(line_width 1)) - (line (pt 160 32)(pt 160 776)(line_width 1)) - (line (pt 0 0)(pt 384 0)(line_width 1)) - (line (pt 384 0)(pt 384 792)(line_width 1)) - (line (pt 0 792)(pt 384 792)(line_width 1)) - (line (pt 0 0)(pt 0 792)(line_width 1)) - ) -) diff --git a/db/ip/nios_system/submodules/nios_system_id_router_003.sv b/db/ip/nios_system/submodules/nios_system_id_router_003.sv index 7cfdd0c..5eb343c 100644 --- a/db/ip/nios_system/submodules/nios_system_id_router_003.sv +++ b/db/ip/nios_system/submodules/nios_system_id_router_003.sv @@ -1,217 +1,217 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_003_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 0 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router_003 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_003_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 0 ) begin - src_channel = 18'b1; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_003_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router_003 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_003_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 18'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_lcd.v b/db/ip/nios_system/submodules/nios_system_lcd.v index 942f142..18c2d15 100644 --- a/db/ip/nios_system/submodules/nios_system_lcd.v +++ b/db/ip/nios_system/submodules/nios_system_lcd.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd ( - // inputs: - address, - begintransfer, - clk, - read, - reset_n, - write, - writedata, - - // outputs: - LCD_E, - LCD_RS, - LCD_RW, - LCD_data, - readdata - ) -; - - output LCD_E; - output LCD_RS; - output LCD_RW; - inout [ 7: 0] LCD_data; - output [ 7: 0] readdata; - input [ 1: 0] address; - input begintransfer; - input clk; - input read; - input reset_n; - input write; - input [ 7: 0] writedata; - - wire LCD_E; - wire LCD_RS; - wire LCD_RW; - wire [ 7: 0] LCD_data; - wire [ 7: 0] readdata; - assign LCD_RW = address[0]; - assign LCD_RS = address[1]; - assign LCD_E = read | write; - assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; - assign readdata = LCD_data; - //control_slave, which is an e_avalon_slave - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd ( + // inputs: + address, + begintransfer, + clk, + read, + reset_n, + write, + writedata, + + // outputs: + LCD_E, + LCD_RS, + LCD_RW, + LCD_data, + readdata + ) +; + + output LCD_E; + output LCD_RS; + output LCD_RW; + inout [ 7: 0] LCD_data; + output [ 7: 0] readdata; + input [ 1: 0] address; + input begintransfer; + input clk; + input read; + input reset_n; + input write; + input [ 7: 0] writedata; + + wire LCD_E; + wire LCD_RS; + wire LCD_RW; + wire [ 7: 0] LCD_data; + wire [ 7: 0] readdata; + assign LCD_RW = address[0]; + assign LCD_RS = address[1]; + assign LCD_E = read | write; + assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; + assign readdata = LCD_data; + //control_slave, which is an e_avalon_slave + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_lcd_E.v b/db/ip/nios_system/submodules/nios_system_lcd_E.v index 0d9a8b1..c5680d0 100644 --- a/db/ip/nios_system/submodules/nios_system_lcd_E.v +++ b/db/ip/nios_system/submodules/nios_system_lcd_E.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_E ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg data_out; - wire out_port; - wire read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {1 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_E ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_pio_0.v b/db/ip/nios_system/submodules/nios_system_pio_0.v index 4f92a98..9cd2e61 100644 --- a/db/ip/nios_system/submodules/nios_system_pio_0.v +++ b/db/ip/nios_system/submodules/nios_system_pio_0.v @@ -1,58 +1,58 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_pio_0 ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 17: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 17: 0] data_in; - wire [ 17: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_pio_0 ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 17: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 17: 0] data_in; + wire [ 17: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv index f34687d..44c4d45 100644 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux.sv @@ -1,116 +1,116 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 2 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 2; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - - assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv index a362586..755ac9e 100644 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_003.sv @@ -1,101 +1,101 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux_003 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 1 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux_003 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 1; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - - assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux_003 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux_003 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/db/lights.db_info b/db/lights.db_info index 4b78a0f..485a3e4 100644 --- a/db/lights.db_info +++ b/db/lights.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Thu Dec 22 10:01:16 2016 +Creation_Time = Thu Dec 22 10:31:00 2016 diff --git a/db/lights.tmw_info b/db/lights.tmw_info index e8b5b31..00bcc65 100644 --- a/db/lights.tmw_info +++ b/db/lights.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:02:07 -start_analysis_synthesis:s:00:00:58-start_full_compilation +start_full_compilation:s:00:01:36 +start_analysis_synthesis:s:00:00:41-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:46-start_full_compilation -start_assembler:s:00:00:10-start_full_compilation -start_timing_analyzer:s:00:00:13-start_full_compilation +start_fitter:s:00:00:40-start_full_compilation +start_assembler:s:00:00:08-start_full_compilation +start_timing_analyzer:s:00:00:07-start_full_compilation diff --git a/db/mux_nob.tdf b/db/mux_nob.tdf index bb77807..f31664f 100644 --- a/db/mux_nob.tdf +++ b/db/mux_nob.tdf @@ -1,295 +1,295 @@ ---lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=7 LPM_WIDTH=32 LPM_WIDTHS=3 data result sel ---VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - - ---synthesis_resources = lut 160 -SUBDESIGN mux_nob -( - data[223..0] : input; - result[31..0] : output; - sel[2..0] : input; -) -VARIABLE - result_node[31..0] : WIRE; - sel_ffs_wire[2..0] : WIRE; - sel_node[2..0] : WIRE; - w_data1945w[7..0] : WIRE; - w_data1967w[3..0] : WIRE; - w_data1968w[3..0] : WIRE; - w_data2016w[7..0] : WIRE; - w_data2038w[3..0] : WIRE; - w_data2039w[3..0] : WIRE; - w_data2085w[7..0] : WIRE; - w_data2107w[3..0] : WIRE; - w_data2108w[3..0] : WIRE; - w_data2154w[7..0] : WIRE; - w_data2176w[3..0] : WIRE; - w_data2177w[3..0] : WIRE; - w_data2223w[7..0] : WIRE; - w_data2245w[3..0] : WIRE; - w_data2246w[3..0] : WIRE; - w_data2292w[7..0] : WIRE; - w_data2314w[3..0] : WIRE; - w_data2315w[3..0] : WIRE; - w_data2361w[7..0] : WIRE; - w_data2383w[3..0] : WIRE; - w_data2384w[3..0] : WIRE; - w_data2430w[7..0] : WIRE; - w_data2452w[3..0] : WIRE; - w_data2453w[3..0] : WIRE; - w_data2499w[7..0] : WIRE; - w_data2521w[3..0] : WIRE; - w_data2522w[3..0] : WIRE; - w_data2568w[7..0] : WIRE; - w_data2590w[3..0] : WIRE; - w_data2591w[3..0] : WIRE; - w_data2637w[7..0] : WIRE; - w_data2659w[3..0] : WIRE; - w_data2660w[3..0] : WIRE; - w_data2706w[7..0] : WIRE; - w_data2728w[3..0] : WIRE; - w_data2729w[3..0] : WIRE; - w_data2775w[7..0] : WIRE; - w_data2797w[3..0] : WIRE; - w_data2798w[3..0] : WIRE; - w_data2844w[7..0] : WIRE; - w_data2866w[3..0] : WIRE; - w_data2867w[3..0] : WIRE; - w_data2913w[7..0] : WIRE; - w_data2935w[3..0] : WIRE; - w_data2936w[3..0] : WIRE; - w_data2982w[7..0] : WIRE; - w_data3004w[3..0] : WIRE; - w_data3005w[3..0] : WIRE; - w_data3051w[7..0] : WIRE; - w_data3073w[3..0] : WIRE; - w_data3074w[3..0] : WIRE; - w_data3120w[7..0] : WIRE; - w_data3142w[3..0] : WIRE; - w_data3143w[3..0] : WIRE; - w_data3189w[7..0] : WIRE; - w_data3211w[3..0] : WIRE; - w_data3212w[3..0] : WIRE; - w_data3258w[7..0] : WIRE; - w_data3280w[3..0] : WIRE; - w_data3281w[3..0] : WIRE; - w_data3327w[7..0] : WIRE; - w_data3349w[3..0] : WIRE; - w_data3350w[3..0] : WIRE; - w_data3396w[7..0] : WIRE; - w_data3418w[3..0] : WIRE; - w_data3419w[3..0] : WIRE; - w_data3465w[7..0] : WIRE; - w_data3487w[3..0] : WIRE; - w_data3488w[3..0] : WIRE; - w_data3534w[7..0] : WIRE; - w_data3556w[3..0] : WIRE; - w_data3557w[3..0] : WIRE; - w_data3603w[7..0] : WIRE; - w_data3625w[3..0] : WIRE; - w_data3626w[3..0] : WIRE; - w_data3672w[7..0] : WIRE; - w_data3694w[3..0] : WIRE; - w_data3695w[3..0] : WIRE; - w_data3741w[7..0] : WIRE; - w_data3763w[3..0] : WIRE; - w_data3764w[3..0] : WIRE; - w_data3810w[7..0] : WIRE; - w_data3832w[3..0] : WIRE; - w_data3833w[3..0] : WIRE; - w_data3879w[7..0] : WIRE; - w_data3901w[3..0] : WIRE; - w_data3902w[3..0] : WIRE; - w_data3948w[7..0] : WIRE; - w_data3970w[3..0] : WIRE; - w_data3971w[3..0] : WIRE; - w_data4017w[7..0] : WIRE; - w_data4039w[3..0] : WIRE; - w_data4040w[3..0] : WIRE; - w_data4086w[7..0] : WIRE; - w_data4108w[3..0] : WIRE; - w_data4109w[3..0] : WIRE; - w_sel1969w[1..0] : WIRE; - w_sel2040w[1..0] : WIRE; - w_sel2109w[1..0] : WIRE; - w_sel2178w[1..0] : WIRE; - w_sel2247w[1..0] : WIRE; - w_sel2316w[1..0] : WIRE; - w_sel2385w[1..0] : WIRE; - w_sel2454w[1..0] : WIRE; - w_sel2523w[1..0] : WIRE; - w_sel2592w[1..0] : WIRE; - w_sel2661w[1..0] : WIRE; - w_sel2730w[1..0] : WIRE; - w_sel2799w[1..0] : WIRE; - w_sel2868w[1..0] : WIRE; - w_sel2937w[1..0] : WIRE; - w_sel3006w[1..0] : WIRE; - w_sel3075w[1..0] : WIRE; - w_sel3144w[1..0] : WIRE; - w_sel3213w[1..0] : WIRE; - w_sel3282w[1..0] : WIRE; - w_sel3351w[1..0] : WIRE; - w_sel3420w[1..0] : WIRE; - w_sel3489w[1..0] : WIRE; - w_sel3558w[1..0] : WIRE; - w_sel3627w[1..0] : WIRE; - w_sel3696w[1..0] : WIRE; - w_sel3765w[1..0] : WIRE; - w_sel3834w[1..0] : WIRE; - w_sel3903w[1..0] : WIRE; - w_sel3972w[1..0] : WIRE; - w_sel4041w[1..0] : WIRE; - w_sel4110w[1..0] : WIRE; - -BEGIN - result[] = result_node[]; - result_node[] = ( ((sel_node[2..2] & (((w_data4109w[1..1] & w_sel4110w[0..0]) & (! (((w_data4109w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4109w[2..2]))))) # ((((w_data4109w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4109w[2..2]))) & (w_data4109w[3..3] # (! w_sel4110w[0..0]))))) # ((! sel_node[2..2]) & (((w_data4108w[1..1] & w_sel4110w[0..0]) & (! (((w_data4108w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4108w[2..2]))))) # ((((w_data4108w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4108w[2..2]))) & (w_data4108w[3..3] # (! w_sel4110w[0..0])))))), ((sel_node[2..2] & (((w_data4040w[1..1] & w_sel4041w[0..0]) & (! (((w_data4040w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4040w[2..2]))))) # ((((w_data4040w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4040w[2..2]))) & (w_data4040w[3..3] # (! w_sel4041w[0..0]))))) # ((! sel_node[2..2]) & (((w_data4039w[1..1] & w_sel4041w[0..0]) & (! (((w_data4039w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4039w[2..2]))))) # ((((w_data4039w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4039w[2..2]))) & (w_data4039w[3..3] # (! w_sel4041w[0..0])))))), ((sel_node[2..2] & (((w_data3971w[1..1] & w_sel3972w[0..0]) & (! (((w_data3971w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3971w[2..2]))))) # ((((w_data3971w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3971w[2..2]))) & (w_data3971w[3..3] # (! w_sel3972w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3970w[1..1] & w_sel3972w[0..0]) & (! (((w_data3970w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3970w[2..2]))))) # ((((w_data3970w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3970w[2..2]))) & (w_data3970w[3..3] # (! w_sel3972w[0..0])))))), ((sel_node[2..2] & (((w_data3902w[1..1] & w_sel3903w[0..0]) & (! (((w_data3902w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3902w[2..2]))))) # ((((w_data3902w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3902w[2..2]))) & (w_data3902w[3..3] # (! w_sel3903w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3901w[1..1] & w_sel3903w[0..0]) & (! (((w_data3901w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3901w[2..2]))))) # ((((w_data3901w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3901w[2..2]))) & (w_data3901w[3..3] # (! w_sel3903w[0..0])))))), ((sel_node[2..2] & (((w_data3833w[1..1] & w_sel3834w[0..0]) & (! (((w_data3833w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3833w[2..2]))))) # ((((w_data3833w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3833w[2..2]))) & (w_data3833w[3..3] # (! w_sel3834w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3832w[1..1] & w_sel3834w[0..0]) & (! (((w_data3832w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3832w[2..2]))))) # ((((w_data3832w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3832w[2..2]))) & (w_data3832w[3..3] # (! w_sel3834w[0..0])))))), ((sel_node[2..2] & (((w_data3764w[1..1] & w_sel3765w[0..0]) & (! (((w_data3764w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3764w[2..2]))))) # ((((w_data3764w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3764w[2..2]))) & (w_data3764w[3..3] # (! w_sel3765w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3763w[1..1] & w_sel3765w[0..0]) & (! (((w_data3763w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3763w[2..2]))))) # ((((w_data3763w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3763w[2..2]))) & (w_data3763w[3..3] # (! w_sel3765w[0..0])))))), ((sel_node[2..2] & (((w_data3695w[1..1] & w_sel3696w[0..0]) & (! (((w_data3695w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3695w[2..2]))))) # ((((w_data3695w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3695w[2..2]))) & (w_data3695w[3..3] # (! w_sel3696w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3694w[1..1] & w_sel3696w[0..0]) & (! (((w_data3694w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3694w[2..2]))))) # ((((w_data3694w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3694w[2..2]))) & (w_data3694w[3..3] # (! w_sel3696w[0..0])))))), ((sel_node[2..2] & (((w_data3626w[1..1] & w_sel3627w[0..0]) & (! (((w_data3626w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3626w[2..2]))))) # ((((w_data3626w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3626w[2..2]))) & (w_data3626w[3..3] # (! w_sel3627w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3625w[1..1] & w_sel3627w[0..0]) & (! (((w_data3625w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3625w[2..2]))))) # ((((w_data3625w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3625w[2..2]))) & (w_data3625w[3..3] # (! w_sel3627w[0..0])))))), ((sel_node[2..2] & (((w_data3557w[1..1] & w_sel3558w[0..0]) & (! (((w_data3557w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3557w[2..2]))))) # ((((w_data3557w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3557w[2..2]))) & (w_data3557w[3..3] # (! w_sel3558w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3556w[1..1] & w_sel3558w[0..0]) & (! (((w_data3556w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3556w[2..2]))))) # ((((w_data3556w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3556w[2..2]))) & (w_data3556w[3..3] # (! w_sel3558w[0..0])))))), ((sel_node[2..2] & (((w_data3488w[1..1] & w_sel3489w[0..0]) & (! (((w_data3488w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3488w[2..2]))))) # ((((w_data3488w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3488w[2..2]))) & (w_data3488w[3..3] # (! w_sel3489w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3487w[1..1] & w_sel3489w[0..0]) & (! (((w_data3487w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3487w[2..2]))))) # ((((w_data3487w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3487w[2..2]))) & (w_data3487w[3..3] # (! w_sel3489w[0..0])))))), ((sel_node[2..2] & (((w_data3419w[1..1] & w_sel3420w[0..0]) & (! (((w_data3419w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3419w[2..2]))))) # ((((w_data3419w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3419w[2..2]))) & (w_data3419w[3..3] # (! w_sel3420w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3418w[1..1] & w_sel3420w[0..0]) & (! (((w_data3418w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3418w[2..2]))))) # ((((w_data3418w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3418w[2..2]))) & (w_data3418w[3..3] # (! w_sel3420w[0..0])))))), ((sel_node[2..2] & (((w_data3350w[1..1] & w_sel3351w[0..0]) & (! (((w_data3350w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3350w[2..2]))))) # ((((w_data3350w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3350w[2..2]))) & (w_data3350w[3..3] # (! w_sel3351w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3349w[1..1] & w_sel3351w[0..0]) & (! (((w_data3349w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3349w[2..2]))))) # ((((w_data3349w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3349w[2..2]))) & (w_data3349w[3..3] # (! w_sel3351w[0..0])))))), ((sel_node[2..2] & (((w_data3281w[1..1] & w_sel3282w[0..0]) & (! (((w_data3281w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3281w[2..2]))))) # ((((w_data3281w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3281w[2..2]))) & (w_data3281w[3..3] # (! w_sel3282w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3280w[1..1] & w_sel3282w[0..0]) & (! (((w_data3280w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3280w[2..2]))))) # ((((w_data3280w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3280w[2..2]))) & (w_data3280w[3..3] # (! w_sel3282w[0..0])))))), ((sel_node[2..2] & (((w_data3212w[1..1] & w_sel3213w[0..0]) & (! (((w_data3212w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3212w[2..2]))))) # ((((w_data3212w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3212w[2..2]))) & (w_data3212w[3..3] # (! w_sel3213w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3211w[1..1] & w_sel3213w[0..0]) & (! (((w_data3211w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3211w[2..2]))))) # ((((w_data3211w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3211w[2..2]))) & (w_data3211w[3..3] # (! w_sel3213w[0..0])))))), ((sel_node[2..2] & (((w_data3143w[1..1] & w_sel3144w[0..0]) & (! (((w_data3143w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3143w[2..2]))))) # ((((w_data3143w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3143w[2..2]))) & (w_data3143w[3..3] # (! w_sel3144w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3142w[1..1] & w_sel3144w[0..0]) & (! (((w_data3142w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3142w[2..2]))))) # ((((w_data3142w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3142w[2..2]))) & (w_data3142w[3..3] # (! w_sel3144w[0..0])))))), ((sel_node[2..2] & (((w_data3074w[1..1] & w_sel3075w[0..0]) & (! (((w_data3074w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3074w[2..2]))))) # ((((w_data3074w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3074w[2..2]))) & (w_data3074w[3..3] # (! w_sel3075w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3073w[1..1] & w_sel3075w[0..0]) & (! (((w_data3073w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3073w[2..2]))))) # ((((w_data3073w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3073w[2..2]))) & (w_data3073w[3..3] # (! w_sel3075w[0..0])))))), ((sel_node[2..2] & (((w_data3005w[1..1] & w_sel3006w[0..0]) & (! (((w_data3005w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3005w[2..2]))))) # ((((w_data3005w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3005w[2..2]))) & (w_data3005w[3..3] # (! w_sel3006w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3004w[1..1] & w_sel3006w[0..0]) & (! (((w_data3004w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3004w[2..2]))))) # ((((w_data3004w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3004w[2..2]))) & (w_data3004w[3..3] # (! w_sel3006w[0..0])))))), ((sel_node[2..2] & (((w_data2936w[1..1] & w_sel2937w[0..0]) & (! (((w_data2936w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2936w[2..2]))))) # ((((w_data2936w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2936w[2..2]))) & (w_data2936w[3..3] # (! w_sel2937w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2935w[1..1] & w_sel2937w[0..0]) & (! (((w_data2935w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2935w[2..2]))))) # ((((w_data2935w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2935w[2..2]))) & (w_data2935w[3..3] # (! w_sel2937w[0..0])))))), ((sel_node[2..2] & (((w_data2867w[1..1] & w_sel2868w[0..0]) & (! (((w_data2867w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2867w[2..2]))))) # ((((w_data2867w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2867w[2..2]))) & (w_data2867w[3..3] # (! w_sel2868w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2866w[1..1] & w_sel2868w[0..0]) & (! (((w_data2866w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2866w[2..2]))))) # ((((w_data2866w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2866w[2..2]))) & (w_data2866w[3..3] # (! w_sel2868w[0..0])))))), ((sel_node[2..2] & (((w_data2798w[1..1] & w_sel2799w[0..0]) & (! (((w_data2798w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2798w[2..2]))))) # ((((w_data2798w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2798w[2..2]))) & (w_data2798w[3..3] # (! w_sel2799w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2797w[1..1] & w_sel2799w[0..0]) & (! (((w_data2797w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2797w[2..2]))))) # ((((w_data2797w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2797w[2..2]))) & (w_data2797w[3..3] # (! w_sel2799w[0..0])))))), ((sel_node[2..2] & (((w_data2729w[1..1] & w_sel2730w[0..0]) & (! (((w_data2729w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2729w[2..2]))))) # ((((w_data2729w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2729w[2..2]))) & (w_data2729w[3..3] # (! w_sel2730w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2728w[1..1] & w_sel2730w[0..0]) & (! (((w_data2728w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2728w[2..2]))))) # ((((w_data2728w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2728w[2..2]))) & (w_data2728w[3..3] # (! w_sel2730w[0..0])))))), ((sel_node[2..2] & (((w_data2660w[1..1] & w_sel2661w[0..0]) & (! (((w_data2660w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2660w[2..2]))))) # ((((w_data2660w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2660w[2..2]))) & (w_data2660w[3..3] # (! w_sel2661w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2659w[1..1] & w_sel2661w[0..0]) & (! (((w_data2659w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2659w[2..2]))))) # ((((w_data2659w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2659w[2..2]))) & (w_data2659w[3..3] # (! w_sel2661w[0..0])))))), ((sel_node[2..2] & (((w_data2591w[1..1] & w_sel2592w[0..0]) & (! (((w_data2591w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2591w[2..2]))))) # ((((w_data2591w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2591w[2..2]))) & (w_data2591w[3..3] # (! w_sel2592w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2590w[1..1] & w_sel2592w[0..0]) & (! (((w_data2590w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2590w[2..2]))))) # ((((w_data2590w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2590w[2..2]))) & (w_data2590w[3..3] # (! w_sel2592w[0..0])))))), ((sel_node[2..2] & (((w_data2522w[1..1] & w_sel2523w[0..0]) & (! (((w_data2522w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2522w[2..2]))))) # ((((w_data2522w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2522w[2..2]))) & (w_data2522w[3..3] # (! w_sel2523w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2521w[1..1] & w_sel2523w[0..0]) & (! (((w_data2521w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2521w[2..2]))))) # ((((w_data2521w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2521w[2..2]))) & (w_data2521w[3..3] # (! w_sel2523w[0..0])))))), ((sel_node[2..2] & (((w_data2453w[1..1] & w_sel2454w[0..0]) & (! (((w_data2453w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2453w[2..2]))))) # ((((w_data2453w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2453w[2..2]))) & (w_data2453w[3..3] # (! w_sel2454w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2452w[1..1] & w_sel2454w[0..0]) & (! (((w_data2452w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2452w[2..2]))))) # ((((w_data2452w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2452w[2..2]))) & (w_data2452w[3..3] # (! w_sel2454w[0..0])))))), ((sel_node[2..2] & (((w_data2384w[1..1] & w_sel2385w[0..0]) & (! (((w_data2384w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2384w[2..2]))))) # ((((w_data2384w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2384w[2..2]))) & (w_data2384w[3..3] # (! w_sel2385w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2383w[1..1] & w_sel2385w[0..0]) & (! (((w_data2383w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2383w[2..2]))))) # ((((w_data2383w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2383w[2..2]))) & (w_data2383w[3..3] # (! w_sel2385w[0..0])))))), ((sel_node[2..2] & (((w_data2315w[1..1] & w_sel2316w[0..0]) & (! (((w_data2315w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2315w[2..2]))))) # ((((w_data2315w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2315w[2..2]))) & (w_data2315w[3..3] # (! w_sel2316w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2314w[1..1] & w_sel2316w[0..0]) & (! (((w_data2314w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2314w[2..2]))))) # ((((w_data2314w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2314w[2..2]))) & (w_data2314w[3..3] # (! w_sel2316w[0..0])))))), ((sel_node[2..2] & (((w_data2246w[1..1] & w_sel2247w[0..0]) & (! (((w_data2246w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2246w[2..2]))))) # ((((w_data2246w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2246w[2..2]))) & (w_data2246w[3..3] # (! w_sel2247w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2245w[1..1] & w_sel2247w[0..0]) & (! (((w_data2245w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2245w[2..2]))))) # ((((w_data2245w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2245w[2..2]))) & (w_data2245w[3..3] # (! w_sel2247w[0..0])))))), ((sel_node[2..2] & (((w_data2177w[1..1] & w_sel2178w[0..0]) & (! (((w_data2177w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2177w[2..2]))))) # ((((w_data2177w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2177w[2..2]))) & (w_data2177w[3..3] # (! w_sel2178w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2176w[1..1] & w_sel2178w[0..0]) & (! (((w_data2176w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2176w[2..2]))))) # ((((w_data2176w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2176w[2..2]))) & (w_data2176w[3..3] # (! w_sel2178w[0..0])))))), ((sel_node[2..2] & (((w_data2108w[1..1] & w_sel2109w[0..0]) & (! (((w_data2108w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2108w[2..2]))))) # ((((w_data2108w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2108w[2..2]))) & (w_data2108w[3..3] # (! w_sel2109w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2107w[1..1] & w_sel2109w[0..0]) & (! (((w_data2107w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2107w[2..2]))))) # ((((w_data2107w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2107w[2..2]))) & (w_data2107w[3..3] # (! w_sel2109w[0..0])))))), ((sel_node[2..2] & (((w_data2039w[1..1] & w_sel2040w[0..0]) & (! (((w_data2039w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2039w[2..2]))))) # ((((w_data2039w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2039w[2..2]))) & (w_data2039w[3..3] # (! w_sel2040w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2038w[1..1] & w_sel2040w[0..0]) & (! (((w_data2038w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2038w[2..2]))))) # ((((w_data2038w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2038w[2..2]))) & (w_data2038w[3..3] # (! w_sel2040w[0..0])))))), ((sel_node[2..2] & (((w_data1968w[1..1] & w_sel1969w[0..0]) & (! (((w_data1968w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1968w[2..2]))))) # ((((w_data1968w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1968w[2..2]))) & (w_data1968w[3..3] # (! w_sel1969w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1967w[1..1] & w_sel1969w[0..0]) & (! (((w_data1967w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1967w[2..2]))))) # ((((w_data1967w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1967w[2..2]))) & (w_data1967w[3..3] # (! w_sel1969w[0..0]))))))); - sel_ffs_wire[] = ( sel[2..0]); - sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]); - w_data1945w[] = ( B"0", data[192..192], data[160..160], data[128..128], data[96..96], data[64..64], data[32..32], data[0..0]); - w_data1967w[3..0] = w_data1945w[3..0]; - w_data1968w[3..0] = w_data1945w[7..4]; - w_data2016w[] = ( B"0", data[193..193], data[161..161], data[129..129], data[97..97], data[65..65], data[33..33], data[1..1]); - w_data2038w[3..0] = w_data2016w[3..0]; - w_data2039w[3..0] = w_data2016w[7..4]; - w_data2085w[] = ( B"0", data[194..194], data[162..162], data[130..130], data[98..98], data[66..66], data[34..34], data[2..2]); - w_data2107w[3..0] = w_data2085w[3..0]; - w_data2108w[3..0] = w_data2085w[7..4]; - w_data2154w[] = ( B"0", data[195..195], data[163..163], data[131..131], data[99..99], data[67..67], data[35..35], data[3..3]); - w_data2176w[3..0] = w_data2154w[3..0]; - w_data2177w[3..0] = w_data2154w[7..4]; - w_data2223w[] = ( B"0", data[196..196], data[164..164], data[132..132], data[100..100], data[68..68], data[36..36], data[4..4]); - w_data2245w[3..0] = w_data2223w[3..0]; - w_data2246w[3..0] = w_data2223w[7..4]; - w_data2292w[] = ( B"0", data[197..197], data[165..165], data[133..133], data[101..101], data[69..69], data[37..37], data[5..5]); - w_data2314w[3..0] = w_data2292w[3..0]; - w_data2315w[3..0] = w_data2292w[7..4]; - w_data2361w[] = ( B"0", data[198..198], data[166..166], data[134..134], data[102..102], data[70..70], data[38..38], data[6..6]); - w_data2383w[3..0] = w_data2361w[3..0]; - w_data2384w[3..0] = w_data2361w[7..4]; - w_data2430w[] = ( B"0", data[199..199], data[167..167], data[135..135], data[103..103], data[71..71], data[39..39], data[7..7]); - w_data2452w[3..0] = w_data2430w[3..0]; - w_data2453w[3..0] = w_data2430w[7..4]; - w_data2499w[] = ( B"0", data[200..200], data[168..168], data[136..136], data[104..104], data[72..72], data[40..40], data[8..8]); - w_data2521w[3..0] = w_data2499w[3..0]; - w_data2522w[3..0] = w_data2499w[7..4]; - w_data2568w[] = ( B"0", data[201..201], data[169..169], data[137..137], data[105..105], data[73..73], data[41..41], data[9..9]); - w_data2590w[3..0] = w_data2568w[3..0]; - w_data2591w[3..0] = w_data2568w[7..4]; - w_data2637w[] = ( B"0", data[202..202], data[170..170], data[138..138], data[106..106], data[74..74], data[42..42], data[10..10]); - w_data2659w[3..0] = w_data2637w[3..0]; - w_data2660w[3..0] = w_data2637w[7..4]; - w_data2706w[] = ( B"0", data[203..203], data[171..171], data[139..139], data[107..107], data[75..75], data[43..43], data[11..11]); - w_data2728w[3..0] = w_data2706w[3..0]; - w_data2729w[3..0] = w_data2706w[7..4]; - w_data2775w[] = ( B"0", data[204..204], data[172..172], data[140..140], data[108..108], data[76..76], data[44..44], data[12..12]); - w_data2797w[3..0] = w_data2775w[3..0]; - w_data2798w[3..0] = w_data2775w[7..4]; - w_data2844w[] = ( B"0", data[205..205], data[173..173], data[141..141], data[109..109], data[77..77], data[45..45], data[13..13]); - w_data2866w[3..0] = w_data2844w[3..0]; - w_data2867w[3..0] = w_data2844w[7..4]; - w_data2913w[] = ( B"0", data[206..206], data[174..174], data[142..142], data[110..110], data[78..78], data[46..46], data[14..14]); - w_data2935w[3..0] = w_data2913w[3..0]; - w_data2936w[3..0] = w_data2913w[7..4]; - w_data2982w[] = ( B"0", data[207..207], data[175..175], data[143..143], data[111..111], data[79..79], data[47..47], data[15..15]); - w_data3004w[3..0] = w_data2982w[3..0]; - w_data3005w[3..0] = w_data2982w[7..4]; - w_data3051w[] = ( B"0", data[208..208], data[176..176], data[144..144], data[112..112], data[80..80], data[48..48], data[16..16]); - w_data3073w[3..0] = w_data3051w[3..0]; - w_data3074w[3..0] = w_data3051w[7..4]; - w_data3120w[] = ( B"0", data[209..209], data[177..177], data[145..145], data[113..113], data[81..81], data[49..49], data[17..17]); - w_data3142w[3..0] = w_data3120w[3..0]; - w_data3143w[3..0] = w_data3120w[7..4]; - w_data3189w[] = ( B"0", data[210..210], data[178..178], data[146..146], data[114..114], data[82..82], data[50..50], data[18..18]); - w_data3211w[3..0] = w_data3189w[3..0]; - w_data3212w[3..0] = w_data3189w[7..4]; - w_data3258w[] = ( B"0", data[211..211], data[179..179], data[147..147], data[115..115], data[83..83], data[51..51], data[19..19]); - w_data3280w[3..0] = w_data3258w[3..0]; - w_data3281w[3..0] = w_data3258w[7..4]; - w_data3327w[] = ( B"0", data[212..212], data[180..180], data[148..148], data[116..116], data[84..84], data[52..52], data[20..20]); - w_data3349w[3..0] = w_data3327w[3..0]; - w_data3350w[3..0] = w_data3327w[7..4]; - w_data3396w[] = ( B"0", data[213..213], data[181..181], data[149..149], data[117..117], data[85..85], data[53..53], data[21..21]); - w_data3418w[3..0] = w_data3396w[3..0]; - w_data3419w[3..0] = w_data3396w[7..4]; - w_data3465w[] = ( B"0", data[214..214], data[182..182], data[150..150], data[118..118], data[86..86], data[54..54], data[22..22]); - w_data3487w[3..0] = w_data3465w[3..0]; - w_data3488w[3..0] = w_data3465w[7..4]; - w_data3534w[] = ( B"0", data[215..215], data[183..183], data[151..151], data[119..119], data[87..87], data[55..55], data[23..23]); - w_data3556w[3..0] = w_data3534w[3..0]; - w_data3557w[3..0] = w_data3534w[7..4]; - w_data3603w[] = ( B"0", data[216..216], data[184..184], data[152..152], data[120..120], data[88..88], data[56..56], data[24..24]); - w_data3625w[3..0] = w_data3603w[3..0]; - w_data3626w[3..0] = w_data3603w[7..4]; - w_data3672w[] = ( B"0", data[217..217], data[185..185], data[153..153], data[121..121], data[89..89], data[57..57], data[25..25]); - w_data3694w[3..0] = w_data3672w[3..0]; - w_data3695w[3..0] = w_data3672w[7..4]; - w_data3741w[] = ( B"0", data[218..218], data[186..186], data[154..154], data[122..122], data[90..90], data[58..58], data[26..26]); - w_data3763w[3..0] = w_data3741w[3..0]; - w_data3764w[3..0] = w_data3741w[7..4]; - w_data3810w[] = ( B"0", data[219..219], data[187..187], data[155..155], data[123..123], data[91..91], data[59..59], data[27..27]); - w_data3832w[3..0] = w_data3810w[3..0]; - w_data3833w[3..0] = w_data3810w[7..4]; - w_data3879w[] = ( B"0", data[220..220], data[188..188], data[156..156], data[124..124], data[92..92], data[60..60], data[28..28]); - w_data3901w[3..0] = w_data3879w[3..0]; - w_data3902w[3..0] = w_data3879w[7..4]; - w_data3948w[] = ( B"0", data[221..221], data[189..189], data[157..157], data[125..125], data[93..93], data[61..61], data[29..29]); - w_data3970w[3..0] = w_data3948w[3..0]; - w_data3971w[3..0] = w_data3948w[7..4]; - w_data4017w[] = ( B"0", data[222..222], data[190..190], data[158..158], data[126..126], data[94..94], data[62..62], data[30..30]); - w_data4039w[3..0] = w_data4017w[3..0]; - w_data4040w[3..0] = w_data4017w[7..4]; - w_data4086w[] = ( B"0", data[223..223], data[191..191], data[159..159], data[127..127], data[95..95], data[63..63], data[31..31]); - w_data4108w[3..0] = w_data4086w[3..0]; - w_data4109w[3..0] = w_data4086w[7..4]; - w_sel1969w[1..0] = sel_node[1..0]; - w_sel2040w[1..0] = sel_node[1..0]; - w_sel2109w[1..0] = sel_node[1..0]; - w_sel2178w[1..0] = sel_node[1..0]; - w_sel2247w[1..0] = sel_node[1..0]; - w_sel2316w[1..0] = sel_node[1..0]; - w_sel2385w[1..0] = sel_node[1..0]; - w_sel2454w[1..0] = sel_node[1..0]; - w_sel2523w[1..0] = sel_node[1..0]; - w_sel2592w[1..0] = sel_node[1..0]; - w_sel2661w[1..0] = sel_node[1..0]; - w_sel2730w[1..0] = sel_node[1..0]; - w_sel2799w[1..0] = sel_node[1..0]; - w_sel2868w[1..0] = sel_node[1..0]; - w_sel2937w[1..0] = sel_node[1..0]; - w_sel3006w[1..0] = sel_node[1..0]; - w_sel3075w[1..0] = sel_node[1..0]; - w_sel3144w[1..0] = sel_node[1..0]; - w_sel3213w[1..0] = sel_node[1..0]; - w_sel3282w[1..0] = sel_node[1..0]; - w_sel3351w[1..0] = sel_node[1..0]; - w_sel3420w[1..0] = sel_node[1..0]; - w_sel3489w[1..0] = sel_node[1..0]; - w_sel3558w[1..0] = sel_node[1..0]; - w_sel3627w[1..0] = sel_node[1..0]; - w_sel3696w[1..0] = sel_node[1..0]; - w_sel3765w[1..0] = sel_node[1..0]; - w_sel3834w[1..0] = sel_node[1..0]; - w_sel3903w[1..0] = sel_node[1..0]; - w_sel3972w[1..0] = sel_node[1..0]; - w_sel4041w[1..0] = sel_node[1..0]; - w_sel4110w[1..0] = sel_node[1..0]; -END; ---VALID FILE +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=7 LPM_WIDTH=32 LPM_WIDTHS=3 data result sel +--VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 160 +SUBDESIGN mux_nob +( + data[223..0] : input; + result[31..0] : output; + sel[2..0] : input; +) +VARIABLE + result_node[31..0] : WIRE; + sel_ffs_wire[2..0] : WIRE; + sel_node[2..0] : WIRE; + w_data1945w[7..0] : WIRE; + w_data1967w[3..0] : WIRE; + w_data1968w[3..0] : WIRE; + w_data2016w[7..0] : WIRE; + w_data2038w[3..0] : WIRE; + w_data2039w[3..0] : WIRE; + w_data2085w[7..0] : WIRE; + w_data2107w[3..0] : WIRE; + w_data2108w[3..0] : WIRE; + w_data2154w[7..0] : WIRE; + w_data2176w[3..0] : WIRE; + w_data2177w[3..0] : WIRE; + w_data2223w[7..0] : WIRE; + w_data2245w[3..0] : WIRE; + w_data2246w[3..0] : WIRE; + w_data2292w[7..0] : WIRE; + w_data2314w[3..0] : WIRE; + w_data2315w[3..0] : WIRE; + w_data2361w[7..0] : WIRE; + w_data2383w[3..0] : WIRE; + w_data2384w[3..0] : WIRE; + w_data2430w[7..0] : WIRE; + w_data2452w[3..0] : WIRE; + w_data2453w[3..0] : WIRE; + w_data2499w[7..0] : WIRE; + w_data2521w[3..0] : WIRE; + w_data2522w[3..0] : WIRE; + w_data2568w[7..0] : WIRE; + w_data2590w[3..0] : WIRE; + w_data2591w[3..0] : WIRE; + w_data2637w[7..0] : WIRE; + w_data2659w[3..0] : WIRE; + w_data2660w[3..0] : WIRE; + w_data2706w[7..0] : WIRE; + w_data2728w[3..0] : WIRE; + w_data2729w[3..0] : WIRE; + w_data2775w[7..0] : WIRE; + w_data2797w[3..0] : WIRE; + w_data2798w[3..0] : WIRE; + w_data2844w[7..0] : WIRE; + w_data2866w[3..0] : WIRE; + w_data2867w[3..0] : WIRE; + w_data2913w[7..0] : WIRE; + w_data2935w[3..0] : WIRE; + w_data2936w[3..0] : WIRE; + w_data2982w[7..0] : WIRE; + w_data3004w[3..0] : WIRE; + w_data3005w[3..0] : WIRE; + w_data3051w[7..0] : WIRE; + w_data3073w[3..0] : WIRE; + w_data3074w[3..0] : WIRE; + w_data3120w[7..0] : WIRE; + w_data3142w[3..0] : WIRE; + w_data3143w[3..0] : WIRE; + w_data3189w[7..0] : WIRE; + w_data3211w[3..0] : WIRE; + w_data3212w[3..0] : WIRE; + w_data3258w[7..0] : WIRE; + w_data3280w[3..0] : WIRE; + w_data3281w[3..0] : WIRE; + w_data3327w[7..0] : WIRE; + w_data3349w[3..0] : WIRE; + w_data3350w[3..0] : WIRE; + w_data3396w[7..0] : WIRE; + w_data3418w[3..0] : WIRE; + w_data3419w[3..0] : WIRE; + w_data3465w[7..0] : WIRE; + w_data3487w[3..0] : WIRE; + w_data3488w[3..0] : WIRE; + w_data3534w[7..0] : WIRE; + w_data3556w[3..0] : WIRE; + w_data3557w[3..0] : WIRE; + w_data3603w[7..0] : WIRE; + w_data3625w[3..0] : WIRE; + w_data3626w[3..0] : WIRE; + w_data3672w[7..0] : WIRE; + w_data3694w[3..0] : WIRE; + w_data3695w[3..0] : WIRE; + w_data3741w[7..0] : WIRE; + w_data3763w[3..0] : WIRE; + w_data3764w[3..0] : WIRE; + w_data3810w[7..0] : WIRE; + w_data3832w[3..0] : WIRE; + w_data3833w[3..0] : WIRE; + w_data3879w[7..0] : WIRE; + w_data3901w[3..0] : WIRE; + w_data3902w[3..0] : WIRE; + w_data3948w[7..0] : WIRE; + w_data3970w[3..0] : WIRE; + w_data3971w[3..0] : WIRE; + w_data4017w[7..0] : WIRE; + w_data4039w[3..0] : WIRE; + w_data4040w[3..0] : WIRE; + w_data4086w[7..0] : WIRE; + w_data4108w[3..0] : WIRE; + w_data4109w[3..0] : WIRE; + w_sel1969w[1..0] : WIRE; + w_sel2040w[1..0] : WIRE; + w_sel2109w[1..0] : WIRE; + w_sel2178w[1..0] : WIRE; + w_sel2247w[1..0] : WIRE; + w_sel2316w[1..0] : WIRE; + w_sel2385w[1..0] : WIRE; + w_sel2454w[1..0] : WIRE; + w_sel2523w[1..0] : WIRE; + w_sel2592w[1..0] : WIRE; + w_sel2661w[1..0] : WIRE; + w_sel2730w[1..0] : WIRE; + w_sel2799w[1..0] : WIRE; + w_sel2868w[1..0] : WIRE; + w_sel2937w[1..0] : WIRE; + w_sel3006w[1..0] : WIRE; + w_sel3075w[1..0] : WIRE; + w_sel3144w[1..0] : WIRE; + w_sel3213w[1..0] : WIRE; + w_sel3282w[1..0] : WIRE; + w_sel3351w[1..0] : WIRE; + w_sel3420w[1..0] : WIRE; + w_sel3489w[1..0] : WIRE; + w_sel3558w[1..0] : WIRE; + w_sel3627w[1..0] : WIRE; + w_sel3696w[1..0] : WIRE; + w_sel3765w[1..0] : WIRE; + w_sel3834w[1..0] : WIRE; + w_sel3903w[1..0] : WIRE; + w_sel3972w[1..0] : WIRE; + w_sel4041w[1..0] : WIRE; + w_sel4110w[1..0] : WIRE; + +BEGIN + result[] = result_node[]; + result_node[] = ( ((sel_node[2..2] & (((w_data4109w[1..1] & w_sel4110w[0..0]) & (! (((w_data4109w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4109w[2..2]))))) # ((((w_data4109w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4109w[2..2]))) & (w_data4109w[3..3] # (! w_sel4110w[0..0]))))) # ((! sel_node[2..2]) & (((w_data4108w[1..1] & w_sel4110w[0..0]) & (! (((w_data4108w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4108w[2..2]))))) # ((((w_data4108w[0..0] & (! w_sel4110w[1..1])) & (! w_sel4110w[0..0])) # (w_sel4110w[1..1] & (w_sel4110w[0..0] # w_data4108w[2..2]))) & (w_data4108w[3..3] # (! w_sel4110w[0..0])))))), ((sel_node[2..2] & (((w_data4040w[1..1] & w_sel4041w[0..0]) & (! (((w_data4040w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4040w[2..2]))))) # ((((w_data4040w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4040w[2..2]))) & (w_data4040w[3..3] # (! w_sel4041w[0..0]))))) # ((! sel_node[2..2]) & (((w_data4039w[1..1] & w_sel4041w[0..0]) & (! (((w_data4039w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4039w[2..2]))))) # ((((w_data4039w[0..0] & (! w_sel4041w[1..1])) & (! w_sel4041w[0..0])) # (w_sel4041w[1..1] & (w_sel4041w[0..0] # w_data4039w[2..2]))) & (w_data4039w[3..3] # (! w_sel4041w[0..0])))))), ((sel_node[2..2] & (((w_data3971w[1..1] & w_sel3972w[0..0]) & (! (((w_data3971w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3971w[2..2]))))) # ((((w_data3971w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3971w[2..2]))) & (w_data3971w[3..3] # (! w_sel3972w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3970w[1..1] & w_sel3972w[0..0]) & (! (((w_data3970w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3970w[2..2]))))) # ((((w_data3970w[0..0] & (! w_sel3972w[1..1])) & (! w_sel3972w[0..0])) # (w_sel3972w[1..1] & (w_sel3972w[0..0] # w_data3970w[2..2]))) & (w_data3970w[3..3] # (! w_sel3972w[0..0])))))), ((sel_node[2..2] & (((w_data3902w[1..1] & w_sel3903w[0..0]) & (! (((w_data3902w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3902w[2..2]))))) # ((((w_data3902w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3902w[2..2]))) & (w_data3902w[3..3] # (! w_sel3903w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3901w[1..1] & w_sel3903w[0..0]) & (! (((w_data3901w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3901w[2..2]))))) # ((((w_data3901w[0..0] & (! w_sel3903w[1..1])) & (! w_sel3903w[0..0])) # (w_sel3903w[1..1] & (w_sel3903w[0..0] # w_data3901w[2..2]))) & (w_data3901w[3..3] # (! w_sel3903w[0..0])))))), ((sel_node[2..2] & (((w_data3833w[1..1] & w_sel3834w[0..0]) & (! (((w_data3833w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3833w[2..2]))))) # ((((w_data3833w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3833w[2..2]))) & (w_data3833w[3..3] # (! w_sel3834w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3832w[1..1] & w_sel3834w[0..0]) & (! (((w_data3832w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3832w[2..2]))))) # ((((w_data3832w[0..0] & (! w_sel3834w[1..1])) & (! w_sel3834w[0..0])) # (w_sel3834w[1..1] & (w_sel3834w[0..0] # w_data3832w[2..2]))) & (w_data3832w[3..3] # (! w_sel3834w[0..0])))))), ((sel_node[2..2] & (((w_data3764w[1..1] & w_sel3765w[0..0]) & (! (((w_data3764w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3764w[2..2]))))) # ((((w_data3764w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3764w[2..2]))) & (w_data3764w[3..3] # (! w_sel3765w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3763w[1..1] & w_sel3765w[0..0]) & (! (((w_data3763w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3763w[2..2]))))) # ((((w_data3763w[0..0] & (! w_sel3765w[1..1])) & (! w_sel3765w[0..0])) # (w_sel3765w[1..1] & (w_sel3765w[0..0] # w_data3763w[2..2]))) & (w_data3763w[3..3] # (! w_sel3765w[0..0])))))), ((sel_node[2..2] & (((w_data3695w[1..1] & w_sel3696w[0..0]) & (! (((w_data3695w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3695w[2..2]))))) # ((((w_data3695w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3695w[2..2]))) & (w_data3695w[3..3] # (! w_sel3696w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3694w[1..1] & w_sel3696w[0..0]) & (! (((w_data3694w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3694w[2..2]))))) # ((((w_data3694w[0..0] & (! w_sel3696w[1..1])) & (! w_sel3696w[0..0])) # (w_sel3696w[1..1] & (w_sel3696w[0..0] # w_data3694w[2..2]))) & (w_data3694w[3..3] # (! w_sel3696w[0..0])))))), ((sel_node[2..2] & (((w_data3626w[1..1] & w_sel3627w[0..0]) & (! (((w_data3626w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3626w[2..2]))))) # ((((w_data3626w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3626w[2..2]))) & (w_data3626w[3..3] # (! w_sel3627w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3625w[1..1] & w_sel3627w[0..0]) & (! (((w_data3625w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3625w[2..2]))))) # ((((w_data3625w[0..0] & (! w_sel3627w[1..1])) & (! w_sel3627w[0..0])) # (w_sel3627w[1..1] & (w_sel3627w[0..0] # w_data3625w[2..2]))) & (w_data3625w[3..3] # (! w_sel3627w[0..0])))))), ((sel_node[2..2] & (((w_data3557w[1..1] & w_sel3558w[0..0]) & (! (((w_data3557w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3557w[2..2]))))) # ((((w_data3557w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3557w[2..2]))) & (w_data3557w[3..3] # (! w_sel3558w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3556w[1..1] & w_sel3558w[0..0]) & (! (((w_data3556w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3556w[2..2]))))) # ((((w_data3556w[0..0] & (! w_sel3558w[1..1])) & (! w_sel3558w[0..0])) # (w_sel3558w[1..1] & (w_sel3558w[0..0] # w_data3556w[2..2]))) & (w_data3556w[3..3] # (! w_sel3558w[0..0])))))), ((sel_node[2..2] & (((w_data3488w[1..1] & w_sel3489w[0..0]) & (! (((w_data3488w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3488w[2..2]))))) # ((((w_data3488w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3488w[2..2]))) & (w_data3488w[3..3] # (! w_sel3489w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3487w[1..1] & w_sel3489w[0..0]) & (! (((w_data3487w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3487w[2..2]))))) # ((((w_data3487w[0..0] & (! w_sel3489w[1..1])) & (! w_sel3489w[0..0])) # (w_sel3489w[1..1] & (w_sel3489w[0..0] # w_data3487w[2..2]))) & (w_data3487w[3..3] # (! w_sel3489w[0..0])))))), ((sel_node[2..2] & (((w_data3419w[1..1] & w_sel3420w[0..0]) & (! (((w_data3419w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3419w[2..2]))))) # ((((w_data3419w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3419w[2..2]))) & (w_data3419w[3..3] # (! w_sel3420w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3418w[1..1] & w_sel3420w[0..0]) & (! (((w_data3418w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3418w[2..2]))))) # ((((w_data3418w[0..0] & (! w_sel3420w[1..1])) & (! w_sel3420w[0..0])) # (w_sel3420w[1..1] & (w_sel3420w[0..0] # w_data3418w[2..2]))) & (w_data3418w[3..3] # (! w_sel3420w[0..0])))))), ((sel_node[2..2] & (((w_data3350w[1..1] & w_sel3351w[0..0]) & (! (((w_data3350w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3350w[2..2]))))) # ((((w_data3350w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3350w[2..2]))) & (w_data3350w[3..3] # (! w_sel3351w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3349w[1..1] & w_sel3351w[0..0]) & (! (((w_data3349w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3349w[2..2]))))) # ((((w_data3349w[0..0] & (! w_sel3351w[1..1])) & (! w_sel3351w[0..0])) # (w_sel3351w[1..1] & (w_sel3351w[0..0] # w_data3349w[2..2]))) & (w_data3349w[3..3] # (! w_sel3351w[0..0])))))), ((sel_node[2..2] & (((w_data3281w[1..1] & w_sel3282w[0..0]) & (! (((w_data3281w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3281w[2..2]))))) # ((((w_data3281w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3281w[2..2]))) & (w_data3281w[3..3] # (! w_sel3282w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3280w[1..1] & w_sel3282w[0..0]) & (! (((w_data3280w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3280w[2..2]))))) # ((((w_data3280w[0..0] & (! w_sel3282w[1..1])) & (! w_sel3282w[0..0])) # (w_sel3282w[1..1] & (w_sel3282w[0..0] # w_data3280w[2..2]))) & (w_data3280w[3..3] # (! w_sel3282w[0..0])))))), ((sel_node[2..2] & (((w_data3212w[1..1] & w_sel3213w[0..0]) & (! (((w_data3212w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3212w[2..2]))))) # ((((w_data3212w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3212w[2..2]))) & (w_data3212w[3..3] # (! w_sel3213w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3211w[1..1] & w_sel3213w[0..0]) & (! (((w_data3211w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3211w[2..2]))))) # ((((w_data3211w[0..0] & (! w_sel3213w[1..1])) & (! w_sel3213w[0..0])) # (w_sel3213w[1..1] & (w_sel3213w[0..0] # w_data3211w[2..2]))) & (w_data3211w[3..3] # (! w_sel3213w[0..0])))))), ((sel_node[2..2] & (((w_data3143w[1..1] & w_sel3144w[0..0]) & (! (((w_data3143w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3143w[2..2]))))) # ((((w_data3143w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3143w[2..2]))) & (w_data3143w[3..3] # (! w_sel3144w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3142w[1..1] & w_sel3144w[0..0]) & (! (((w_data3142w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3142w[2..2]))))) # ((((w_data3142w[0..0] & (! w_sel3144w[1..1])) & (! w_sel3144w[0..0])) # (w_sel3144w[1..1] & (w_sel3144w[0..0] # w_data3142w[2..2]))) & (w_data3142w[3..3] # (! w_sel3144w[0..0])))))), ((sel_node[2..2] & (((w_data3074w[1..1] & w_sel3075w[0..0]) & (! (((w_data3074w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3074w[2..2]))))) # ((((w_data3074w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3074w[2..2]))) & (w_data3074w[3..3] # (! w_sel3075w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3073w[1..1] & w_sel3075w[0..0]) & (! (((w_data3073w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3073w[2..2]))))) # ((((w_data3073w[0..0] & (! w_sel3075w[1..1])) & (! w_sel3075w[0..0])) # (w_sel3075w[1..1] & (w_sel3075w[0..0] # w_data3073w[2..2]))) & (w_data3073w[3..3] # (! w_sel3075w[0..0])))))), ((sel_node[2..2] & (((w_data3005w[1..1] & w_sel3006w[0..0]) & (! (((w_data3005w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3005w[2..2]))))) # ((((w_data3005w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3005w[2..2]))) & (w_data3005w[3..3] # (! w_sel3006w[0..0]))))) # ((! sel_node[2..2]) & (((w_data3004w[1..1] & w_sel3006w[0..0]) & (! (((w_data3004w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3004w[2..2]))))) # ((((w_data3004w[0..0] & (! w_sel3006w[1..1])) & (! w_sel3006w[0..0])) # (w_sel3006w[1..1] & (w_sel3006w[0..0] # w_data3004w[2..2]))) & (w_data3004w[3..3] # (! w_sel3006w[0..0])))))), ((sel_node[2..2] & (((w_data2936w[1..1] & w_sel2937w[0..0]) & (! (((w_data2936w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2936w[2..2]))))) # ((((w_data2936w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2936w[2..2]))) & (w_data2936w[3..3] # (! w_sel2937w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2935w[1..1] & w_sel2937w[0..0]) & (! (((w_data2935w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2935w[2..2]))))) # ((((w_data2935w[0..0] & (! w_sel2937w[1..1])) & (! w_sel2937w[0..0])) # (w_sel2937w[1..1] & (w_sel2937w[0..0] # w_data2935w[2..2]))) & (w_data2935w[3..3] # (! w_sel2937w[0..0])))))), ((sel_node[2..2] & (((w_data2867w[1..1] & w_sel2868w[0..0]) & (! (((w_data2867w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2867w[2..2]))))) # ((((w_data2867w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2867w[2..2]))) & (w_data2867w[3..3] # (! w_sel2868w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2866w[1..1] & w_sel2868w[0..0]) & (! (((w_data2866w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2866w[2..2]))))) # ((((w_data2866w[0..0] & (! w_sel2868w[1..1])) & (! w_sel2868w[0..0])) # (w_sel2868w[1..1] & (w_sel2868w[0..0] # w_data2866w[2..2]))) & (w_data2866w[3..3] # (! w_sel2868w[0..0])))))), ((sel_node[2..2] & (((w_data2798w[1..1] & w_sel2799w[0..0]) & (! (((w_data2798w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2798w[2..2]))))) # ((((w_data2798w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2798w[2..2]))) & (w_data2798w[3..3] # (! w_sel2799w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2797w[1..1] & w_sel2799w[0..0]) & (! (((w_data2797w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2797w[2..2]))))) # ((((w_data2797w[0..0] & (! w_sel2799w[1..1])) & (! w_sel2799w[0..0])) # (w_sel2799w[1..1] & (w_sel2799w[0..0] # w_data2797w[2..2]))) & (w_data2797w[3..3] # (! w_sel2799w[0..0])))))), ((sel_node[2..2] & (((w_data2729w[1..1] & w_sel2730w[0..0]) & (! (((w_data2729w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2729w[2..2]))))) # ((((w_data2729w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2729w[2..2]))) & (w_data2729w[3..3] # (! w_sel2730w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2728w[1..1] & w_sel2730w[0..0]) & (! (((w_data2728w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2728w[2..2]))))) # ((((w_data2728w[0..0] & (! w_sel2730w[1..1])) & (! w_sel2730w[0..0])) # (w_sel2730w[1..1] & (w_sel2730w[0..0] # w_data2728w[2..2]))) & (w_data2728w[3..3] # (! w_sel2730w[0..0])))))), ((sel_node[2..2] & (((w_data2660w[1..1] & w_sel2661w[0..0]) & (! (((w_data2660w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2660w[2..2]))))) # ((((w_data2660w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2660w[2..2]))) & (w_data2660w[3..3] # (! w_sel2661w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2659w[1..1] & w_sel2661w[0..0]) & (! (((w_data2659w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2659w[2..2]))))) # ((((w_data2659w[0..0] & (! w_sel2661w[1..1])) & (! w_sel2661w[0..0])) # (w_sel2661w[1..1] & (w_sel2661w[0..0] # w_data2659w[2..2]))) & (w_data2659w[3..3] # (! w_sel2661w[0..0])))))), ((sel_node[2..2] & (((w_data2591w[1..1] & w_sel2592w[0..0]) & (! (((w_data2591w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2591w[2..2]))))) # ((((w_data2591w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2591w[2..2]))) & (w_data2591w[3..3] # (! w_sel2592w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2590w[1..1] & w_sel2592w[0..0]) & (! (((w_data2590w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2590w[2..2]))))) # ((((w_data2590w[0..0] & (! w_sel2592w[1..1])) & (! w_sel2592w[0..0])) # (w_sel2592w[1..1] & (w_sel2592w[0..0] # w_data2590w[2..2]))) & (w_data2590w[3..3] # (! w_sel2592w[0..0])))))), ((sel_node[2..2] & (((w_data2522w[1..1] & w_sel2523w[0..0]) & (! (((w_data2522w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2522w[2..2]))))) # ((((w_data2522w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2522w[2..2]))) & (w_data2522w[3..3] # (! w_sel2523w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2521w[1..1] & w_sel2523w[0..0]) & (! (((w_data2521w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2521w[2..2]))))) # ((((w_data2521w[0..0] & (! w_sel2523w[1..1])) & (! w_sel2523w[0..0])) # (w_sel2523w[1..1] & (w_sel2523w[0..0] # w_data2521w[2..2]))) & (w_data2521w[3..3] # (! w_sel2523w[0..0])))))), ((sel_node[2..2] & (((w_data2453w[1..1] & w_sel2454w[0..0]) & (! (((w_data2453w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2453w[2..2]))))) # ((((w_data2453w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2453w[2..2]))) & (w_data2453w[3..3] # (! w_sel2454w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2452w[1..1] & w_sel2454w[0..0]) & (! (((w_data2452w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2452w[2..2]))))) # ((((w_data2452w[0..0] & (! w_sel2454w[1..1])) & (! w_sel2454w[0..0])) # (w_sel2454w[1..1] & (w_sel2454w[0..0] # w_data2452w[2..2]))) & (w_data2452w[3..3] # (! w_sel2454w[0..0])))))), ((sel_node[2..2] & (((w_data2384w[1..1] & w_sel2385w[0..0]) & (! (((w_data2384w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2384w[2..2]))))) # ((((w_data2384w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2384w[2..2]))) & (w_data2384w[3..3] # (! w_sel2385w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2383w[1..1] & w_sel2385w[0..0]) & (! (((w_data2383w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2383w[2..2]))))) # ((((w_data2383w[0..0] & (! w_sel2385w[1..1])) & (! w_sel2385w[0..0])) # (w_sel2385w[1..1] & (w_sel2385w[0..0] # w_data2383w[2..2]))) & (w_data2383w[3..3] # (! w_sel2385w[0..0])))))), ((sel_node[2..2] & (((w_data2315w[1..1] & w_sel2316w[0..0]) & (! (((w_data2315w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2315w[2..2]))))) # ((((w_data2315w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2315w[2..2]))) & (w_data2315w[3..3] # (! w_sel2316w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2314w[1..1] & w_sel2316w[0..0]) & (! (((w_data2314w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2314w[2..2]))))) # ((((w_data2314w[0..0] & (! w_sel2316w[1..1])) & (! w_sel2316w[0..0])) # (w_sel2316w[1..1] & (w_sel2316w[0..0] # w_data2314w[2..2]))) & (w_data2314w[3..3] # (! w_sel2316w[0..0])))))), ((sel_node[2..2] & (((w_data2246w[1..1] & w_sel2247w[0..0]) & (! (((w_data2246w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2246w[2..2]))))) # ((((w_data2246w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2246w[2..2]))) & (w_data2246w[3..3] # (! w_sel2247w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2245w[1..1] & w_sel2247w[0..0]) & (! (((w_data2245w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2245w[2..2]))))) # ((((w_data2245w[0..0] & (! w_sel2247w[1..1])) & (! w_sel2247w[0..0])) # (w_sel2247w[1..1] & (w_sel2247w[0..0] # w_data2245w[2..2]))) & (w_data2245w[3..3] # (! w_sel2247w[0..0])))))), ((sel_node[2..2] & (((w_data2177w[1..1] & w_sel2178w[0..0]) & (! (((w_data2177w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2177w[2..2]))))) # ((((w_data2177w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2177w[2..2]))) & (w_data2177w[3..3] # (! w_sel2178w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2176w[1..1] & w_sel2178w[0..0]) & (! (((w_data2176w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2176w[2..2]))))) # ((((w_data2176w[0..0] & (! w_sel2178w[1..1])) & (! w_sel2178w[0..0])) # (w_sel2178w[1..1] & (w_sel2178w[0..0] # w_data2176w[2..2]))) & (w_data2176w[3..3] # (! w_sel2178w[0..0])))))), ((sel_node[2..2] & (((w_data2108w[1..1] & w_sel2109w[0..0]) & (! (((w_data2108w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2108w[2..2]))))) # ((((w_data2108w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2108w[2..2]))) & (w_data2108w[3..3] # (! w_sel2109w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2107w[1..1] & w_sel2109w[0..0]) & (! (((w_data2107w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2107w[2..2]))))) # ((((w_data2107w[0..0] & (! w_sel2109w[1..1])) & (! w_sel2109w[0..0])) # (w_sel2109w[1..1] & (w_sel2109w[0..0] # w_data2107w[2..2]))) & (w_data2107w[3..3] # (! w_sel2109w[0..0])))))), ((sel_node[2..2] & (((w_data2039w[1..1] & w_sel2040w[0..0]) & (! (((w_data2039w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2039w[2..2]))))) # ((((w_data2039w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2039w[2..2]))) & (w_data2039w[3..3] # (! w_sel2040w[0..0]))))) # ((! sel_node[2..2]) & (((w_data2038w[1..1] & w_sel2040w[0..0]) & (! (((w_data2038w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2038w[2..2]))))) # ((((w_data2038w[0..0] & (! w_sel2040w[1..1])) & (! w_sel2040w[0..0])) # (w_sel2040w[1..1] & (w_sel2040w[0..0] # w_data2038w[2..2]))) & (w_data2038w[3..3] # (! w_sel2040w[0..0])))))), ((sel_node[2..2] & (((w_data1968w[1..1] & w_sel1969w[0..0]) & (! (((w_data1968w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1968w[2..2]))))) # ((((w_data1968w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1968w[2..2]))) & (w_data1968w[3..3] # (! w_sel1969w[0..0]))))) # ((! sel_node[2..2]) & (((w_data1967w[1..1] & w_sel1969w[0..0]) & (! (((w_data1967w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1967w[2..2]))))) # ((((w_data1967w[0..0] & (! w_sel1969w[1..1])) & (! w_sel1969w[0..0])) # (w_sel1969w[1..1] & (w_sel1969w[0..0] # w_data1967w[2..2]))) & (w_data1967w[3..3] # (! w_sel1969w[0..0]))))))); + sel_ffs_wire[] = ( sel[2..0]); + sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]); + w_data1945w[] = ( B"0", data[192..192], data[160..160], data[128..128], data[96..96], data[64..64], data[32..32], data[0..0]); + w_data1967w[3..0] = w_data1945w[3..0]; + w_data1968w[3..0] = w_data1945w[7..4]; + w_data2016w[] = ( B"0", data[193..193], data[161..161], data[129..129], data[97..97], data[65..65], data[33..33], data[1..1]); + w_data2038w[3..0] = w_data2016w[3..0]; + w_data2039w[3..0] = w_data2016w[7..4]; + w_data2085w[] = ( B"0", data[194..194], data[162..162], data[130..130], data[98..98], data[66..66], data[34..34], data[2..2]); + w_data2107w[3..0] = w_data2085w[3..0]; + w_data2108w[3..0] = w_data2085w[7..4]; + w_data2154w[] = ( B"0", data[195..195], data[163..163], data[131..131], data[99..99], data[67..67], data[35..35], data[3..3]); + w_data2176w[3..0] = w_data2154w[3..0]; + w_data2177w[3..0] = w_data2154w[7..4]; + w_data2223w[] = ( B"0", data[196..196], data[164..164], data[132..132], data[100..100], data[68..68], data[36..36], data[4..4]); + w_data2245w[3..0] = w_data2223w[3..0]; + w_data2246w[3..0] = w_data2223w[7..4]; + w_data2292w[] = ( B"0", data[197..197], data[165..165], data[133..133], data[101..101], data[69..69], data[37..37], data[5..5]); + w_data2314w[3..0] = w_data2292w[3..0]; + w_data2315w[3..0] = w_data2292w[7..4]; + w_data2361w[] = ( B"0", data[198..198], data[166..166], data[134..134], data[102..102], data[70..70], data[38..38], data[6..6]); + w_data2383w[3..0] = w_data2361w[3..0]; + w_data2384w[3..0] = w_data2361w[7..4]; + w_data2430w[] = ( B"0", data[199..199], data[167..167], data[135..135], data[103..103], data[71..71], data[39..39], data[7..7]); + w_data2452w[3..0] = w_data2430w[3..0]; + w_data2453w[3..0] = w_data2430w[7..4]; + w_data2499w[] = ( B"0", data[200..200], data[168..168], data[136..136], data[104..104], data[72..72], data[40..40], data[8..8]); + w_data2521w[3..0] = w_data2499w[3..0]; + w_data2522w[3..0] = w_data2499w[7..4]; + w_data2568w[] = ( B"0", data[201..201], data[169..169], data[137..137], data[105..105], data[73..73], data[41..41], data[9..9]); + w_data2590w[3..0] = w_data2568w[3..0]; + w_data2591w[3..0] = w_data2568w[7..4]; + w_data2637w[] = ( B"0", data[202..202], data[170..170], data[138..138], data[106..106], data[74..74], data[42..42], data[10..10]); + w_data2659w[3..0] = w_data2637w[3..0]; + w_data2660w[3..0] = w_data2637w[7..4]; + w_data2706w[] = ( B"0", data[203..203], data[171..171], data[139..139], data[107..107], data[75..75], data[43..43], data[11..11]); + w_data2728w[3..0] = w_data2706w[3..0]; + w_data2729w[3..0] = w_data2706w[7..4]; + w_data2775w[] = ( B"0", data[204..204], data[172..172], data[140..140], data[108..108], data[76..76], data[44..44], data[12..12]); + w_data2797w[3..0] = w_data2775w[3..0]; + w_data2798w[3..0] = w_data2775w[7..4]; + w_data2844w[] = ( B"0", data[205..205], data[173..173], data[141..141], data[109..109], data[77..77], data[45..45], data[13..13]); + w_data2866w[3..0] = w_data2844w[3..0]; + w_data2867w[3..0] = w_data2844w[7..4]; + w_data2913w[] = ( B"0", data[206..206], data[174..174], data[142..142], data[110..110], data[78..78], data[46..46], data[14..14]); + w_data2935w[3..0] = w_data2913w[3..0]; + w_data2936w[3..0] = w_data2913w[7..4]; + w_data2982w[] = ( B"0", data[207..207], data[175..175], data[143..143], data[111..111], data[79..79], data[47..47], data[15..15]); + w_data3004w[3..0] = w_data2982w[3..0]; + w_data3005w[3..0] = w_data2982w[7..4]; + w_data3051w[] = ( B"0", data[208..208], data[176..176], data[144..144], data[112..112], data[80..80], data[48..48], data[16..16]); + w_data3073w[3..0] = w_data3051w[3..0]; + w_data3074w[3..0] = w_data3051w[7..4]; + w_data3120w[] = ( B"0", data[209..209], data[177..177], data[145..145], data[113..113], data[81..81], data[49..49], data[17..17]); + w_data3142w[3..0] = w_data3120w[3..0]; + w_data3143w[3..0] = w_data3120w[7..4]; + w_data3189w[] = ( B"0", data[210..210], data[178..178], data[146..146], data[114..114], data[82..82], data[50..50], data[18..18]); + w_data3211w[3..0] = w_data3189w[3..0]; + w_data3212w[3..0] = w_data3189w[7..4]; + w_data3258w[] = ( B"0", data[211..211], data[179..179], data[147..147], data[115..115], data[83..83], data[51..51], data[19..19]); + w_data3280w[3..0] = w_data3258w[3..0]; + w_data3281w[3..0] = w_data3258w[7..4]; + w_data3327w[] = ( B"0", data[212..212], data[180..180], data[148..148], data[116..116], data[84..84], data[52..52], data[20..20]); + w_data3349w[3..0] = w_data3327w[3..0]; + w_data3350w[3..0] = w_data3327w[7..4]; + w_data3396w[] = ( B"0", data[213..213], data[181..181], data[149..149], data[117..117], data[85..85], data[53..53], data[21..21]); + w_data3418w[3..0] = w_data3396w[3..0]; + w_data3419w[3..0] = w_data3396w[7..4]; + w_data3465w[] = ( B"0", data[214..214], data[182..182], data[150..150], data[118..118], data[86..86], data[54..54], data[22..22]); + w_data3487w[3..0] = w_data3465w[3..0]; + w_data3488w[3..0] = w_data3465w[7..4]; + w_data3534w[] = ( B"0", data[215..215], data[183..183], data[151..151], data[119..119], data[87..87], data[55..55], data[23..23]); + w_data3556w[3..0] = w_data3534w[3..0]; + w_data3557w[3..0] = w_data3534w[7..4]; + w_data3603w[] = ( B"0", data[216..216], data[184..184], data[152..152], data[120..120], data[88..88], data[56..56], data[24..24]); + w_data3625w[3..0] = w_data3603w[3..0]; + w_data3626w[3..0] = w_data3603w[7..4]; + w_data3672w[] = ( B"0", data[217..217], data[185..185], data[153..153], data[121..121], data[89..89], data[57..57], data[25..25]); + w_data3694w[3..0] = w_data3672w[3..0]; + w_data3695w[3..0] = w_data3672w[7..4]; + w_data3741w[] = ( B"0", data[218..218], data[186..186], data[154..154], data[122..122], data[90..90], data[58..58], data[26..26]); + w_data3763w[3..0] = w_data3741w[3..0]; + w_data3764w[3..0] = w_data3741w[7..4]; + w_data3810w[] = ( B"0", data[219..219], data[187..187], data[155..155], data[123..123], data[91..91], data[59..59], data[27..27]); + w_data3832w[3..0] = w_data3810w[3..0]; + w_data3833w[3..0] = w_data3810w[7..4]; + w_data3879w[] = ( B"0", data[220..220], data[188..188], data[156..156], data[124..124], data[92..92], data[60..60], data[28..28]); + w_data3901w[3..0] = w_data3879w[3..0]; + w_data3902w[3..0] = w_data3879w[7..4]; + w_data3948w[] = ( B"0", data[221..221], data[189..189], data[157..157], data[125..125], data[93..93], data[61..61], data[29..29]); + w_data3970w[3..0] = w_data3948w[3..0]; + w_data3971w[3..0] = w_data3948w[7..4]; + w_data4017w[] = ( B"0", data[222..222], data[190..190], data[158..158], data[126..126], data[94..94], data[62..62], data[30..30]); + w_data4039w[3..0] = w_data4017w[3..0]; + w_data4040w[3..0] = w_data4017w[7..4]; + w_data4086w[] = ( B"0", data[223..223], data[191..191], data[159..159], data[127..127], data[95..95], data[63..63], data[31..31]); + w_data4108w[3..0] = w_data4086w[3..0]; + w_data4109w[3..0] = w_data4086w[7..4]; + w_sel1969w[1..0] = sel_node[1..0]; + w_sel2040w[1..0] = sel_node[1..0]; + w_sel2109w[1..0] = sel_node[1..0]; + w_sel2178w[1..0] = sel_node[1..0]; + w_sel2247w[1..0] = sel_node[1..0]; + w_sel2316w[1..0] = sel_node[1..0]; + w_sel2385w[1..0] = sel_node[1..0]; + w_sel2454w[1..0] = sel_node[1..0]; + w_sel2523w[1..0] = sel_node[1..0]; + w_sel2592w[1..0] = sel_node[1..0]; + w_sel2661w[1..0] = sel_node[1..0]; + w_sel2730w[1..0] = sel_node[1..0]; + w_sel2799w[1..0] = sel_node[1..0]; + w_sel2868w[1..0] = sel_node[1..0]; + w_sel2937w[1..0] = sel_node[1..0]; + w_sel3006w[1..0] = sel_node[1..0]; + w_sel3075w[1..0] = sel_node[1..0]; + w_sel3144w[1..0] = sel_node[1..0]; + w_sel3213w[1..0] = sel_node[1..0]; + w_sel3282w[1..0] = sel_node[1..0]; + w_sel3351w[1..0] = sel_node[1..0]; + w_sel3420w[1..0] = sel_node[1..0]; + w_sel3489w[1..0] = sel_node[1..0]; + w_sel3558w[1..0] = sel_node[1..0]; + w_sel3627w[1..0] = sel_node[1..0]; + w_sel3696w[1..0] = sel_node[1..0]; + w_sel3765w[1..0] = sel_node[1..0]; + w_sel3834w[1..0] = sel_node[1..0]; + w_sel3903w[1..0] = sel_node[1..0]; + w_sel3972w[1..0] = sel_node[1..0]; + w_sel4041w[1..0] = sel_node[1..0]; + w_sel4110w[1..0] = sel_node[1..0]; +END; +--VALID FILE diff --git a/db/prev_cmp_lights.qmsg b/db/prev_cmp_lights.qmsg index 3b1ea70..88e1361 100644 --- a/db/prev_cmp_lights.qmsg +++ b/db/prev_cmp_lights.qmsg @@ -1,572 +1,572 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480609244120 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:20:43 2016 " "Processing started: Fri Dec 02 01:20:43 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lights -c lights " "Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1480609244493 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "nios_system.qsys " "Elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12248 "Elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609244532 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Loading qsys_tutorial/nios_system.qsys " "2016.12.02.01:20:45 Progress: Loading qsys_tutorial/nios_system.qsys" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245237 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Reading input file " "2016.12.02.01:20:45 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245421 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Adding clk_0 \[clock_source 13.0\] " "2016.12.02.01:20:45 Progress: Adding clk_0 \[clock_source 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245465 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Parameterizing module clk_0 " "2016.12.02.01:20:45 Progress: Parameterizing module clk_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245657 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\] " "2016.12.02.01:20:45 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245661 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module nios2_processor " "2016.12.02.01:20:46 Progress: Parameterizing module nios2_processor" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246366 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246369 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module onchip_memory " "2016.12.02.01:20:46 Progress: Parameterizing module onchip_memory" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246433 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246434 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module jtag_uart " "2016.12.02.01:20:46 Progress: Parameterizing module jtag_uart" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246474 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246474 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module LEDs " "2016.12.02.01:20:46 Progress: Parameterizing module LEDs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246518 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246519 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module LEDRs " "2016.12.02.01:20:46 Progress: Parameterizing module LEDRs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246522 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246523 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module switches " "2016.12.02.01:20:46 Progress: Parameterizing module switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246524 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246524 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module push_switches " "2016.12.02.01:20:46 Progress: Parameterizing module push_switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246526 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246527 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex0 " "2016.12.02.01:20:46 Progress: Parameterizing module hex0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246528 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246529 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex1 " "2016.12.02.01:20:46 Progress: Parameterizing module hex1" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246530 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246531 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex2 " "2016.12.02.01:20:46 Progress: Parameterizing module hex2" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246532 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246533 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex3 " "2016.12.02.01:20:46 Progress: Parameterizing module hex3" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246534 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246535 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex4 " "2016.12.02.01:20:46 Progress: Parameterizing module hex4" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246536 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246537 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex5 " "2016.12.02.01:20:46 Progress: Parameterizing module hex5" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246538 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246539 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex6 " "2016.12.02.01:20:46 Progress: Parameterizing module hex6" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246540 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246540 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex7 " "2016.12.02.01:20:46 Progress: Parameterizing module hex7" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246542 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246542 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_16207_0 " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_16207_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246563 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246564 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_on " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_on" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246566 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246567 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_blon " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_blon" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246569 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Building connections " "2016.12.02.01:20:46 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246569 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing connections " "2016.12.02.01:20:46 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246883 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Validating " "2016.12.02.01:20:46 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246886 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:47 Progress: Done reading input file " "2016.12.02.01:20:47 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247552 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247857 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247857 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH " "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248752 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections " "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248978 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "No custom instruction connections, skipping transform " "No custom instruction connections, skipping transform " { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248985 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_translator_transform: After transform: 39 modules, 155 connections " "Merlin_translator_transform: After transform: 39 modules, 155 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609249536 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_domain_transform: After transform: 78 modules, 423 connections " "Merlin_domain_transform: After transform: 78 modules, 423 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250547 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_router_transform: After transform: 98 modules, 503 connections " "Merlin_router_transform: After transform: 98 modules, 503 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250874 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reset_adaptation_transform: After transform: 99 modules, 390 connections " "Reset_adaptation_transform: After transform: 99 modules, 390 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250950 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections " "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251203 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_mm_transform: After transform: 138 modules, 470 connections " "Merlin_mm_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251295 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections " "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251335 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252303 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252303 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252306 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252306 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252306 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252306 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252307 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252307 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252307 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252307 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252308 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252308 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252308 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252308 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252311 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252311 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252311 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252311 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252311 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252311 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252312 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252312 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252312 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252312 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252312 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252313 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252313 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252313 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252313 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252709 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \] " "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252709 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Starting Nios II generation " "Nios2_processor: # 2016.12.02 01:20:53 (*) Starting Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Checking for plaintext license. " "Nios2_processor: # 2016.12.02 01:20:53 (*) Checking for plaintext license." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus " "Nios2_processor: # 2016.12.02 01:20:53 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable " "Nios2_processor: # 2016.12.02 01:20:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) LM_LICENSE_FILE environment variable is empty " "Nios2_processor: # 2016.12.02 01:20:53 (*) LM_LICENSE_FILE environment variable is empty" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Plaintext license not found. " "Nios2_processor: # 2016.12.02 01:20:53 (*) Plaintext license not found." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) No license required to generate encrypted Nios II/e. " "Nios2_processor: # 2016.12.02 01:20:53 (*) No license required to generate encrypted Nios II/e." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Elaborating CPU configuration settings " "Nios2_processor: # 2016.12.02 01:20:53 (*) Elaborating CPU configuration settings" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Creating all objects for CPU " "Nios2_processor: # 2016.12.02 01:20:53 (*) Creating all objects for CPU" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:54 (*) Generating RTL from CPU objects " "Nios2_processor: # 2016.12.02 01:20:54 (*) Generating RTL from CPU objects" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:54 (*) Creating plain-text RTL " "Nios2_processor: # 2016.12.02 01:20:54 (*) Creating plain-text RTL" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:56 (*) Done Nios II generation " "Nios2_processor: # 2016.12.02 01:20:56 (*) Done Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256735 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\" " "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256747 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \] " "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257861 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\" " "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257874 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257894 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \] " "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257894 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258183 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\" " "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258187 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Starting RTL generation for module 'nios_system_LEDs' " "LEDs: Starting RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258209 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \] " "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258209 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Done RTL generation for module 'nios_system_LEDs' " "LEDs: Done RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258399 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\" " "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258401 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Starting RTL generation for module 'nios_system_LEDRs' " "LEDRs: Starting RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258414 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \] " "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258415 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Done RTL generation for module 'nios_system_LEDRs' " "LEDRs: Done RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258596 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\" " "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258598 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Starting RTL generation for module 'nios_system_switches' " "Switches: Starting RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258613 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \] " "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258613 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Done RTL generation for module 'nios_system_switches' " "Switches: Done RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258799 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\" " "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258801 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Starting RTL generation for module 'nios_system_push_switches' " "Push_switches: Starting RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258817 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \] " "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258817 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Done RTL generation for module 'nios_system_push_switches' " "Push_switches: Done RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259002 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\" " "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259005 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Starting RTL generation for module 'nios_system_hex0' " "Hex0: Starting RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259021 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \] " "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259021 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Done RTL generation for module 'nios_system_hex0' " "Hex0: Done RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259206 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\" " "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259208 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259222 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \] " "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259222 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259404 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\" " "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259407 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259419 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \] " "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259420 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Done RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Done RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259615 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\" " "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259618 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\" " "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259620 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\" " "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259629 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\" " "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259637 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259645 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259659 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\" " "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259678 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\" " "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259697 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\" " "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259714 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\" " "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259726 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\" " "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259729 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\" " "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259754 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\" " "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\" " "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259831 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\" " "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259857 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\" " "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259890 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259891 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\" " "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259951 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259952 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\" " "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259971 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes " "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259972 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "nios_system.qsys " "Finished elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12249 "Finished elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609260929 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lights.vhd 2 1 " "Found 2 design units, including 1 entities, in source file lights.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lights-lights_rtl " "Found design unit 1: lights-lights_rtl" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 27 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} { "Info" "ISGN_ENTITY_NAME" "1 lights " "Found entity 1: lights" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_system/synthesis/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "nios_system/synthesis/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261383 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "db/ip/nios_system/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261402 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261402 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261406 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261414 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261418 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261422 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261426 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261431 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261431 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261435 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261438 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261438 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_ledrs.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDRs " "Found entity 1: nios_system_LEDRs" { } { { "db/ip/nios_system/submodules/nios_system_LEDRs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261441 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261441 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDs " "Found entity 1: nios_system_LEDs" { } { { "db/ip/nios_system/submodules/nios_system_LEDs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261444 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261444 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261447 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261447 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_default_decode " "Found entity 1: nios_system_addr_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router " "Found entity 2: nios_system_addr_router" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router_001.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261451 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router_001.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261451 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_001_default_decode " "Found entity 1: nios_system_addr_router_001_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router_001 " "Found entity 2: nios_system_addr_router_001" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux " "Found entity 1: nios_system_cmd_xbar_demux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261455 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux_001 " "Found entity 1: nios_system_cmd_xbar_demux_001" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261459 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_mux " "Found entity 1: nios_system_cmd_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261463 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_hex0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_hex0 " "Found entity 1: nios_system_hex0" { } { { "db/ip/nios_system/submodules/nios_system_hex0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261467 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router.sv(48) " "Verilog HDL Declaration information at nios_system_id_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261470 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router.sv(49) " "Verilog HDL Declaration information at nios_system_id_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261470 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_default_decode " "Found entity 1: nios_system_id_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router " "Found entity 2: nios_system_id_router" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router_002.sv(48) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261474 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router_002.sv(49) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261475 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_002_default_decode " "Found entity 1: nios_system_id_router_002_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router_002 " "Found entity 2: nios_system_id_router_002" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_irq_mapper " "Found entity 1: nios_system_irq_mapper" { } { { "db/ip/nios_system/submodules/nios_system_irq_mapper.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261479 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_jtag_uart.v 5 5 " "Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_jtag_uart_sim_scfifo_w " "Found entity 1: nios_system_jtag_uart_sim_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_jtag_uart_scfifo_w " "Found entity 2: nios_system_jtag_uart_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_jtag_uart_sim_scfifo_r " "Found entity 3: nios_system_jtag_uart_sim_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 162 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_jtag_uart_scfifo_r " "Found entity 4: nios_system_jtag_uart_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 240 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_jtag_uart " "Found entity 5: nios_system_jtag_uart" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 327 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_16207_0 " "Found entity 1: nios_system_lcd_16207_0" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_on.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_on " "Found entity 1: nios_system_lcd_on" { } { { "db/ip/nios_system/submodules/nios_system_lcd_on.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261492 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor.v 21 21 " "Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_register_bank_a_module " "Found entity 1: nios_system_nios2_processor_register_bank_a_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_nios2_processor_register_bank_b_module " "Found entity 2: nios_system_nios2_processor_register_bank_b_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_nios2_processor_nios2_oci_debug " "Found entity 3: nios_system_nios2_processor_nios2_oci_debug" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_nios2_processor_ociram_sp_ram_module " "Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 288 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_nios2_processor_nios2_ocimem " "Found entity 5: nios_system_nios2_processor_nios2_ocimem" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 346 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "6 nios_system_nios2_processor_nios2_avalon_reg " "Found entity 6: nios_system_nios2_processor_nios2_avalon_reg" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 524 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "7 nios_system_nios2_processor_nios2_oci_break " "Found entity 7: nios_system_nios2_processor_nios2_oci_break" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 616 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "8 nios_system_nios2_processor_nios2_oci_xbrk " "Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 910 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "9 nios_system_nios2_processor_nios2_oci_dbrk " "Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1116 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "10 nios_system_nios2_processor_nios2_oci_itrace " "Found entity 10: nios_system_nios2_processor_nios2_oci_itrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1302 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "11 nios_system_nios2_processor_nios2_oci_td_mode " "Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1599 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "12 nios_system_nios2_processor_nios2_oci_dtrace " "Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "13 nios_system_nios2_processor_nios2_oci_compute_tm_count " "Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1760 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "14 nios_system_nios2_processor_nios2_oci_fifowp_inc " "Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1831 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "15 nios_system_nios2_processor_nios2_oci_fifocount_inc " "Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1873 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "16 nios_system_nios2_processor_nios2_oci_fifo " "Found entity 16: nios_system_nios2_processor_nios2_oci_fifo" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1919 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "17 nios_system_nios2_processor_nios2_oci_pib " "Found entity 17: nios_system_nios2_processor_nios2_oci_pib" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2424 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "18 nios_system_nios2_processor_nios2_oci_im " "Found entity 18: nios_system_nios2_processor_nios2_oci_im" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "19 nios_system_nios2_processor_nios2_performance_monitors " "Found entity 19: nios_system_nios2_processor_nios2_performance_monitors" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2608 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "20 nios_system_nios2_processor_nios2_oci " "Found entity 20: nios_system_nios2_processor_nios2_oci" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2624 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "21 nios_system_nios2_processor " "Found entity 21: nios_system_nios2_processor" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3129 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_sysclk " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261516 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261516 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_tck " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261519 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_wrapper " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261523 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_oci_test_bench " "Found entity 1: nios_system_nios2_processor_oci_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261526 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_test_bench " "Found entity 1: nios_system_nios2_processor_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261530 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261530 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_onchip_memory.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_onchip_memory " "Found entity 1: nios_system_onchip_memory" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261533 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261533 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_push_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_push_switches " "Found entity 1: nios_system_push_switches" { } { { "db/ip/nios_system/submodules/nios_system_push_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261537 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_demux_002 " "Found entity 1: nios_system_rsp_xbar_demux_002" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261541 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux " "Found entity 1: nios_system_rsp_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261545 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261545 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux_001 " "Found entity 1: nios_system_rsp_xbar_mux_001" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261550 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_switches " "Found entity 1: nios_system_switches" { } { { "db/ip/nios_system/submodules/nios_system_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261554 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261554 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1567) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1567 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261584 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1569) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1569 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261584 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1725) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1725 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261585 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(2553) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2553 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261588 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "lights " "Elaborating entity \"lights\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1480609261703 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system nios_system:NiosII " "Elaborating entity \"nios_system\" for hierarchy \"nios_system:NiosII\"" { } { { "lights.vhd" "NiosII" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 53 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609261724 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor nios_system:NiosII\|nios_system_nios2_processor:nios2_processor " "Elaborating entity \"nios_system_nios2_processor\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262516 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench " "Elaborating entity \"nios_system_nios2_processor_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262643 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_a_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a " "Elaborating entity \"nios_system_nios2_processor_register_bank_a_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_a" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262685 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262737 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_a.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609262758 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0rh1 " "Found entity 1: altsyncram_0rh1" { } { { "db/altsyncram_0rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609262827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609262827 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated " "Elaborating entity \"altsyncram_0rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262829 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_b_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b " "Elaborating entity \"nios_system_nios2_processor_register_bank_b_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_b" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4300 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262955 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262975 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_b.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609262994 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1rh1 " "Found entity 1: altsyncram_1rh1" { } { { "db/altsyncram_1rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609263063 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609263063 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated " "Elaborating entity \"altsyncram_1rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263066 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci " "Elaborating entity \"nios_system_nios2_processor_nios2_oci\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4758 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263193 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_debug nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_debug\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_debug" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263239 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altera_std_synchronizer" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263267 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609263279 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263279 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609263279 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_ocimem nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem " "Elaborating entity \"nios_system_nios2_processor_nios2_ocimem\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_ocimem" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2821 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263282 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_ociram_sp_ram_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram " "Elaborating entity \"nios_system_nios2_processor_ociram_sp_ram_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_ociram_sp_ram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 491 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263310 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263727 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609263751 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_ociram_default_contents.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609263752 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4891.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4891 " "Found entity 1: altsyncram_4891" { } { { "db/altsyncram_4891.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609263817 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609263817 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4891 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated " "Elaborating entity \"altsyncram_4891\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263819 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_avalon_reg nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg " "Elaborating entity \"nios_system_nios2_processor_nios2_avalon_reg\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_avalon_reg" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2840 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263950 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_break nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_break\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_break" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2871 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263968 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_xbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_xbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_xbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2892 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264008 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264024 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_itrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_itrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_itrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2937 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264041 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dtrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dtrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dtrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2952 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264068 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_td_mode nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_td_mode\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264093 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifo nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifo\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2971 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264108 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_compute_tm_count\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2046 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264154 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifowp_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2056 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264171 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifocount_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2066 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264189 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_oci_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench " "Elaborating entity \"nios_system_nios2_processor_oci_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264205 ""} -{ "Warning" "WSGN_EMPTY_SHELL" "nios_system_nios2_processor_oci_test_bench " "Entity \"nios_system_nios2_processor_oci_test_bench\" contains only dangling pins" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12158 "Entity \"%1!s!\" contains only dangling pins" 0 0 "Quartus II" 0 -1 1480609264206 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_pib nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_pib\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_pib" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2981 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264222 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_im nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_im\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_im" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3002 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264235 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_wrapper nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_wrapper\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_jtag_debug_module_wrapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3107 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264430 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_tck nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_tck\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_tck" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264450 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_sysclk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_sysclk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_sysclk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264479 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "nios_system_nios2_processor_jtag_debug_module_phy" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264517 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609264531 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264533 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264548 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_onchip_memory nios_system:NiosII\|nios_system_onchip_memory:onchip_memory " "Elaborating entity \"nios_system_onchip_memory\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264552 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264571 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_onchip_memory.hex " "Parameter \"init_file\" = \"nios_system_onchip_memory.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 51200 " "Parameter \"maximum_depth\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 51200 " "Parameter \"numwords_a\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 16 " "Parameter \"widthad_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609264591 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4ed1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4ed1 " "Found entity 1: altsyncram_4ed1" { } { { "db/altsyncram_4ed1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609264688 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609264688 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4ed1 nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated " "Elaborating entity \"altsyncram_4ed1\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264690 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_qsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_qsa " "Found entity 1: decode_qsa" { } { { "db/decode_qsa.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609266788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609266788 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_qsa nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3 " "Elaborating entity \"decode_qsa\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3\"" { } { { "db/altsyncram_4ed1.tdf" "decode3" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609266790 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_nob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_nob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_nob " "Found entity 1: mux_nob" { } { { "db/mux_nob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609266919 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609266919 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_nob nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2 " "Elaborating entity \"mux_nob\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2\"" { } { { "db/altsyncram_4ed1.tdf" "mux2" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609266921 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart nios_system:NiosII\|nios_system_jtag_uart:jtag_uart " "Elaborating entity \"nios_system_jtag_uart\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1129 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267161 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_w nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w " "Elaborating entity \"nios_system_jtag_uart_scfifo_w\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_w" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 415 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267404 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "wfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267473 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609267488 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267556 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267556 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267558 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267585 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267585 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267588 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267611 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267614 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267703 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267703 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267705 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267794 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267794 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267797 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609268450 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609268450 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268452 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609268547 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609268547 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268550 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_r nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r " "Elaborating entity \"nios_system_jtag_uart_scfifo_r\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_r" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 429 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268582 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "nios_system_jtag_uart_alt_jtag_atlantic" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268734 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609268765 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDs nios_system:NiosII\|nios_system_LEDs:leds " "Elaborating entity \"nios_system_LEDs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDs:leds\"" { } { { "nios_system/synthesis/nios_system.v" "leds" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268774 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDRs nios_system:NiosII\|nios_system_LEDRs:ledrs " "Elaborating entity \"nios_system_LEDRs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDRs:ledrs\"" { } { { "nios_system/synthesis/nios_system.v" "ledrs" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268792 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_switches nios_system:NiosII\|nios_system_switches:switches " "Elaborating entity \"nios_system_switches\" for hierarchy \"nios_system:NiosII\|nios_system_switches:switches\"" { } { { "nios_system/synthesis/nios_system.v" "switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1159 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268812 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_push_switches nios_system:NiosII\|nios_system_push_switches:push_switches " "Elaborating entity \"nios_system_push_switches\" for hierarchy \"nios_system:NiosII\|nios_system_push_switches:push_switches\"" { } { { "nios_system/synthesis/nios_system.v" "push_switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268835 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_hex0 nios_system:NiosII\|nios_system_hex0:hex0 " "Elaborating entity \"nios_system_hex0\" for hierarchy \"nios_system:NiosII\|nios_system_hex0:hex0\"" { } { { "nios_system/synthesis/nios_system.v" "hex0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268854 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_16207_0 nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0 " "Elaborating entity \"nios_system_lcd_16207_0\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268889 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_on nios_system:NiosII\|nios_system_lcd_on:lcd_on " "Elaborating entity \"nios_system_lcd_on\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_on:lcd_on\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_on" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1281 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268908 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1354 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268928 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1416 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268956 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1482 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268985 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1548 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269019 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "leds_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1614 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269051 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart_avalon_jtag_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1680 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269081 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0_control_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269142 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2684 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269180 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2764 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269242 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2845 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269266 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269302 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2886 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269337 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router nios_system:NiosII\|nios_system_addr_router:addr_router " "Elaborating entity \"nios_system_addr_router\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4976 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269535 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_default_decode nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 177 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269571 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001 nios_system:NiosII\|nios_system_addr_router_001:addr_router_001 " "Elaborating entity \"nios_system_addr_router_001\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4992 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269589 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001_default_decode nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_001_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269655 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router nios_system:NiosII\|nios_system_id_router:id_router " "Elaborating entity \"nios_system_id_router\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\"" { } { { "nios_system/synthesis/nios_system.v" "id_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5008 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269670 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_default_decode nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269696 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002 nios_system:NiosII\|nios_system_id_router_002:id_router_002 " "Elaborating entity \"nios_system_id_router_002\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\"" { } { { "nios_system/synthesis/nios_system.v" "id_router_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5040 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269717 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002_default_decode nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_002_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269739 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller nios_system:NiosII\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\"" { } { { "nios_system/synthesis/nios_system.v" "rst_controller" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5307 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269835 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 120 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269858 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"nios_system_cmd_xbar_demux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5330 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269883 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux_001 nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"nios_system_cmd_xbar_demux_001\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5449 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269910 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_mux nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"nios_system_cmd_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269979 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270014 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270033 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_demux_002 nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"nios_system_rsp_xbar_demux_002\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_demux_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5558 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270061 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"nios_system_rsp_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5836 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270124 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270155 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux_001 nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"nios_system_rsp_xbar_mux_001\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5955 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270177 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 552 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270333 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270353 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_irq_mapper nios_system:NiosII\|nios_system_irq_mapper:irq_mapper " "Elaborating entity \"nios_system_irq_mapper\" for hierarchy \"nios_system:NiosII\|nios_system_irq_mapper:irq_mapper\"" { } { { "nios_system/synthesis/nios_system.v" "irq_mapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270368 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "5 " "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1480609279462 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1480609279649 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 276 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 348 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3167 -1 0 } } { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3740 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 393 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 599 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 62 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1480609279714 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1480609279714 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609281555 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "166 " "166 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1480609284267 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 384 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 521 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1480609284431 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1480609284431 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" { } { { "sld_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd" 181 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1480609284529 "|lights|sld_hub:auto_hub|receive[0][0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1480609284529 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609284691 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1480609285369 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1480609286405 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609286405 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2880 " "Implemented 2880 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2421 " "Implemented 2421 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_RAMS" "336 " "Implemented 336 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1480609287063 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1480609287063 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 150 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 150 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "650 " "Peak virtual memory: 650 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:21:27 2016 " "Processing ended: Fri Dec 02 01:21:27 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:44 " "Elapsed time: 00:00:44" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480609288328 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609288329 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:21:27 2016 " "Processing started: Fri Dec 02 01:21:27 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609288329 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480609288329 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480609288329 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480609288398 ""} -{ "Info" "0" "" "Project = lights" { } { } 0 0 "Project = lights" 0 0 "Fitter" 0 0 1480609288399 ""} -{ "Info" "0" "" "Revision = lights" { } { } 0 0 "Revision = lights" 0 0 "Fitter" 0 0 1480609288399 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1480609288552 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "lights EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"lights\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480609288596 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480609288891 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1480609288902 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1480609289561 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11997 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11999 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12001 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12003 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12005 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1480609289572 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480609289576 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480609289623 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 118 " "No exact pin location assignment(s) for 1 pins of 118 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LCD_E " "Pin LCD_E not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_E } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_E } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 363 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1480609292219 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1480609292219 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1480609293128 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480609293201 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1480609293215 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1480609293273 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1480609293273 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1480609293274 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293621 ""} } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11965 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293621 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293621 ""} } { { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4020 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293621 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 177 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4471 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3700 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 3290 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0 " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0" { } { { "altera_std_synchronizer.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5951 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1480609293622 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 172 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 906 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293622 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293623 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 68 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5707 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293623 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480609294840 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1480609294848 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1480609294848 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480609294859 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480609294870 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480609294878 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480609294879 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480609294887 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480609294987 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 EC " "Packed 8 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1480609294996 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480609294996 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 2.5V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1480609295071 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1480609295071 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1480609295071 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 20 40 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 62 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 62 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 1 72 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 1 total pin(s) used -- 72 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 32 39 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 2.5V 34 31 " "I/O bank number 5 does not use VREF pins and has 2.5V VCCIO pins. 34 total pin(s) used -- 31 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 2.5V 9 49 " "I/O bank number 6 does not use VREF pins and has 2.5V VCCIO pins. 9 total pin(s) used -- 49 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 29 43 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 29 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 71 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1480609295073 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1480609295073 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK2_50 " "Ignored I/O standard assignment to node \"CLOCK2_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK3_50 " "Ignored I/O standard assignment to node \"CLOCK3_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[0\] " "Ignored I/O standard assignment to node \"DRAM_BA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[1\] " "Ignored I/O standard assignment to node \"DRAM_BA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CAS_N " "Ignored I/O standard assignment to node \"DRAM_CAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CKE " "Ignored I/O standard assignment to node \"DRAM_CKE\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CLK " "Ignored I/O standard assignment to node \"DRAM_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CS_N " "Ignored I/O standard assignment to node \"DRAM_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[16\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[17\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[18\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[19\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[20\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[21\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[22\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[23\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[24\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[25\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[26\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[27\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[28\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[29\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[30\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[31\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_RAS_N " "Ignored I/O standard assignment to node \"DRAM_RAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_WE_N " "Ignored I/O standard assignment to node \"DRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SCLK " "Ignored I/O standard assignment to node \"EEP_I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SDAT " "Ignored I/O standard assignment to node \"EEP_I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_GTX_CLK " "Ignored I/O standard assignment to node \"ENET0_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_INT_N " "Ignored I/O standard assignment to node \"ENET0_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_LINK100 " "Ignored I/O standard assignment to node \"ENET0_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDC " "Ignored I/O standard assignment to node \"ENET0_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDIO " "Ignored I/O standard assignment to node \"ENET0_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RST_N " "Ignored I/O standard assignment to node \"ENET0_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CLK " "Ignored I/O standard assignment to node \"ENET0_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_COL " "Ignored I/O standard assignment to node \"ENET0_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CRS " "Ignored I/O standard assignment to node \"ENET0_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DV " "Ignored I/O standard assignment to node \"ENET0_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_ER " "Ignored I/O standard assignment to node \"ENET0_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_CLK " "Ignored I/O standard assignment to node \"ENET0_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_EN " "Ignored I/O standard assignment to node \"ENET0_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_ER " "Ignored I/O standard assignment to node \"ENET0_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_GTX_CLK " "Ignored I/O standard assignment to node \"ENET1_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_INT_N " "Ignored I/O standard assignment to node \"ENET1_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_LINK100 " "Ignored I/O standard assignment to node \"ENET1_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDC " "Ignored I/O standard assignment to node \"ENET1_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDIO " "Ignored I/O standard assignment to node \"ENET1_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RST_N " "Ignored I/O standard assignment to node \"ENET1_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CLK " "Ignored I/O standard assignment to node \"ENET1_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_COL " "Ignored I/O standard assignment to node \"ENET1_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CRS " "Ignored I/O standard assignment to node \"ENET1_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DV " "Ignored I/O standard assignment to node \"ENET1_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_ER " "Ignored I/O standard assignment to node \"ENET1_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_CLK " "Ignored I/O standard assignment to node \"ENET1_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_EN " "Ignored I/O standard assignment to node \"ENET1_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_ER " "Ignored I/O standard assignment to node \"ENET1_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENETCLK_25 " "Ignored I/O standard assignment to node \"ENETCLK_25\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[0\] " "Ignored I/O standard assignment to node \"EX_IO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[1\] " "Ignored I/O standard assignment to node \"EX_IO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[2\] " "Ignored I/O standard assignment to node \"EX_IO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[3\] " "Ignored I/O standard assignment to node \"EX_IO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[4\] " "Ignored I/O standard assignment to node \"EX_IO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[5\] " "Ignored I/O standard assignment to node \"EX_IO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[6\] " "Ignored I/O standard assignment to node \"EX_IO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[22\] " "Ignored I/O standard assignment to node \"FL_ADDR\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[0\] " "Ignored I/O standard assignment to node \"GPIO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[10\] " "Ignored I/O standard assignment to node \"GPIO\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[11\] " "Ignored I/O standard assignment to node \"GPIO\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[12\] " "Ignored I/O standard assignment to node \"GPIO\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[13\] " "Ignored I/O standard assignment to node \"GPIO\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[14\] " "Ignored I/O standard assignment to node \"GPIO\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[15\] " "Ignored I/O standard assignment to node \"GPIO\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[16\] " "Ignored I/O standard assignment to node \"GPIO\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[17\] " "Ignored I/O standard assignment to node \"GPIO\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[18\] " "Ignored I/O standard assignment to node \"GPIO\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[19\] " "Ignored I/O standard assignment to node \"GPIO\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[1\] " "Ignored I/O standard assignment to node \"GPIO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[20\] " "Ignored I/O standard assignment to node \"GPIO\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[21\] " "Ignored I/O standard assignment to node \"GPIO\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[22\] " "Ignored I/O standard assignment to node \"GPIO\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[23\] " "Ignored I/O standard assignment to node \"GPIO\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[24\] " "Ignored I/O standard assignment to node \"GPIO\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[25\] " "Ignored I/O standard assignment to node \"GPIO\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[26\] " "Ignored I/O standard assignment to node \"GPIO\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[27\] " "Ignored I/O standard assignment to node \"GPIO\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[28\] " "Ignored I/O standard assignment to node \"GPIO\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[29\] " "Ignored I/O standard assignment to node \"GPIO\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[2\] " "Ignored I/O standard assignment to node \"GPIO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[30\] " "Ignored I/O standard assignment to node \"GPIO\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[31\] " "Ignored I/O standard assignment to node \"GPIO\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[32\] " "Ignored I/O standard assignment to node \"GPIO\[32\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[33\] " "Ignored I/O standard assignment to node \"GPIO\[33\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[34\] " "Ignored I/O standard assignment to node \"GPIO\[34\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[35\] " "Ignored I/O standard assignment to node \"GPIO\[35\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[3\] " "Ignored I/O standard assignment to node \"GPIO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[4\] " "Ignored I/O standard assignment to node \"GPIO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[5\] " "Ignored I/O standard assignment to node \"GPIO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[6\] " "Ignored I/O standard assignment to node \"GPIO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[7\] " "Ignored I/O standard assignment to node \"GPIO\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[8\] " "Ignored I/O standard assignment to node \"GPIO\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[9\] " "Ignored I/O standard assignment to node \"GPIO\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN0 " "Ignored I/O standard assignment to node \"HSMC_CLKIN0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT0 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[0\] " "Ignored I/O standard assignment to node \"HSMC_D\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[1\] " "Ignored I/O standard assignment to node \"HSMC_D\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[2\] " "Ignored I/O standard assignment to node \"HSMC_D\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[3\] " "Ignored I/O standard assignment to node \"HSMC_D\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "IRDA_RXD " "Ignored I/O standard assignment to node \"IRDA_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LEDG\[8\] " "Ignored I/O standard assignment to node \"LEDG\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[0\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[1\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_CS_N " "Ignored I/O standard assignment to node \"OTG_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[0\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[1\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[0\] " "Ignored I/O standard assignment to node \"OTG_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[10\] " "Ignored I/O standard assignment to node \"OTG_DATA\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[11\] " "Ignored I/O standard assignment to node \"OTG_DATA\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[12\] " "Ignored I/O standard assignment to node \"OTG_DATA\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[13\] " "Ignored I/O standard assignment to node \"OTG_DATA\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[14\] " "Ignored I/O standard assignment to node \"OTG_DATA\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[15\] " "Ignored I/O standard assignment to node \"OTG_DATA\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[1\] " "Ignored I/O standard assignment to node \"OTG_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[2\] " "Ignored I/O standard assignment to node \"OTG_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[3\] " "Ignored I/O standard assignment to node \"OTG_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[4\] " "Ignored I/O standard assignment to node \"OTG_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[5\] " "Ignored I/O standard assignment to node \"OTG_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[6\] " "Ignored I/O standard assignment to node \"OTG_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[7\] " "Ignored I/O standard assignment to node \"OTG_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[8\] " "Ignored I/O standard assignment to node \"OTG_DATA\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[9\] " "Ignored I/O standard assignment to node \"OTG_DATA\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[0\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[1\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_FSPEED " "Ignored I/O standard assignment to node \"OTG_FSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[0\] " "Ignored I/O standard assignment to node \"OTG_INT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[1\] " "Ignored I/O standard assignment to node \"OTG_INT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_LSPEED " "Ignored I/O standard assignment to node \"OTG_LSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RD_N " "Ignored I/O standard assignment to node \"OTG_RD_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RST_N " "Ignored I/O standard assignment to node \"OTG_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_WR_N " "Ignored I/O standard assignment to node \"OTG_WR_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK " "Ignored I/O standard assignment to node \"PS2_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK2 " "Ignored I/O standard assignment to node \"PS2_CLK2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT " "Ignored I/O standard assignment to node \"PS2_DAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT2 " "Ignored I/O standard assignment to node \"PS2_DAT2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[0\] " "Ignored I/O standard assignment to node \"SD_DAT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[1\] " "Ignored I/O standard assignment to node \"SD_DAT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[2\] " "Ignored I/O standard assignment to node \"SD_DAT\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[3\] " "Ignored I/O standard assignment to node \"SD_DAT\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKIN " "Ignored I/O standard assignment to node \"SMA_CLKIN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKOUT " "Ignored I/O standard assignment to node \"SMA_CLKOUT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[13\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[14\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[15\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[16\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[17\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[18\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[19\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_CE_N " "Ignored I/O standard assignment to node \"SRAM_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_LB_N " "Ignored I/O standard assignment to node \"SRAM_LB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_OE_N " "Ignored I/O standard assignment to node \"SRAM_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_UB_N " "Ignored I/O standard assignment to node \"SRAM_UB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_WE_N " "Ignored I/O standard assignment to node \"SRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_CLK27 " "Ignored I/O standard assignment to node \"TD_CLK27\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[0\] " "Ignored I/O standard assignment to node \"TD_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[1\] " "Ignored I/O standard assignment to node \"TD_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[2\] " "Ignored I/O standard assignment to node \"TD_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[3\] " "Ignored I/O standard assignment to node \"TD_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[4\] " "Ignored I/O standard assignment to node \"TD_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[5\] " "Ignored I/O standard assignment to node \"TD_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[6\] " "Ignored I/O standard assignment to node \"TD_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[7\] " "Ignored I/O standard assignment to node \"TD_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_HS " "Ignored I/O standard assignment to node \"TD_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_RESET_N " "Ignored I/O standard assignment to node \"TD_RESET_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_VS " "Ignored I/O standard assignment to node \"TD_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_BLANK_N " "Ignored I/O standard assignment to node \"VGA_BLANK_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[0\] " "Ignored I/O standard assignment to node \"VGA_B\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[1\] " "Ignored I/O standard assignment to node \"VGA_B\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[2\] " "Ignored I/O standard assignment to node \"VGA_B\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[3\] " "Ignored I/O standard assignment to node \"VGA_B\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[4\] " "Ignored I/O standard assignment to node \"VGA_B\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[5\] " "Ignored I/O standard assignment to node \"VGA_B\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[6\] " "Ignored I/O standard assignment to node \"VGA_B\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[7\] " "Ignored I/O standard assignment to node \"VGA_B\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_CLK " "Ignored I/O standard assignment to node \"VGA_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[0\] " "Ignored I/O standard assignment to node \"VGA_G\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[1\] " "Ignored I/O standard assignment to node \"VGA_G\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[2\] " "Ignored I/O standard assignment to node \"VGA_G\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[3\] " "Ignored I/O standard assignment to node \"VGA_G\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[4\] " "Ignored I/O standard assignment to node \"VGA_G\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[5\] " "Ignored I/O standard assignment to node \"VGA_G\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[6\] " "Ignored I/O standard assignment to node \"VGA_G\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[7\] " "Ignored I/O standard assignment to node \"VGA_G\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_HS " "Ignored I/O standard assignment to node \"VGA_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[0\] " "Ignored I/O standard assignment to node \"VGA_R\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[1\] " "Ignored I/O standard assignment to node \"VGA_R\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[2\] " "Ignored I/O standard assignment to node \"VGA_R\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[3\] " "Ignored I/O standard assignment to node \"VGA_R\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[4\] " "Ignored I/O standard assignment to node \"VGA_R\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[5\] " "Ignored I/O standard assignment to node \"VGA_R\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[6\] " "Ignored I/O standard assignment to node \"VGA_R\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[7\] " "Ignored I/O standard assignment to node \"VGA_R\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_SYNC_N " "Ignored I/O standard assignment to node \"VGA_SYNC_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_VS " "Ignored I/O standard assignment to node \"VGA_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} } { } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1480609295298 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[0\] " "Node \"OTG_DACK_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[1\] " "Node \"OTG_DACK_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[1\] " "Node \"OTG_DREQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[0\] " "Node \"OTG_INT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[1\] " "Node \"OTG_INT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480609295327 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:06 " "Fitter preparation operations ending: elapsed time is 00:00:06" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609295357 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480609302965 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609304725 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480609304769 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480609307778 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609307779 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480609309715 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X58_Y37 X68_Y48 " "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48" { } { { "loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 1 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48"} { { 11 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48"} 58 37 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1480609316983 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480609316983 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609318123 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1480609318126 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1480609318126 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480609318126 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.83 " "Total time spent on timing analysis during the Fitter is 0.83 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1480609318321 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480609318412 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480609319674 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480609319768 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480609320969 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609322400 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480609324348 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "9 Cyclone IV E " "9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[0\] 3.3-V LVTTL L3 " "Pin LCD_data\[0\] uses I/O standard 3.3-V LVTTL at L3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[0\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 352 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[1\] 3.3-V LVTTL L1 " "Pin LCD_data\[1\] uses I/O standard 3.3-V LVTTL at L1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[1\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 353 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[2\] 3.3-V LVTTL L2 " "Pin LCD_data\[2\] uses I/O standard 3.3-V LVTTL at L2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[2\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 354 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[3\] 3.3-V LVTTL K7 " "Pin LCD_data\[3\] uses I/O standard 3.3-V LVTTL at K7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[3\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 355 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[4\] 3.3-V LVTTL K1 " "Pin LCD_data\[4\] uses I/O standard 3.3-V LVTTL at K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[4\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[5\] 3.3-V LVTTL K2 " "Pin LCD_data\[5\] uses I/O standard 3.3-V LVTTL at K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[5\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 357 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[6\] 3.3-V LVTTL M3 " "Pin LCD_data\[6\] uses I/O standard 3.3-V LVTTL at M3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[6\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 358 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[7\] 3.3-V LVTTL M5 " "Pin LCD_data\[7\] uses I/O standard 3.3-V LVTTL at M5" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[7\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 359 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL Y2 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 360 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1480609324401 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480609325076 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 830 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 830 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1010 " "Peak virtual memory: 1010 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:07 2016 " "Processing ended: Fri Dec 02 01:22:07 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480609327596 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480609328752 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609328752 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:22:08 2016 " "Processing started: Fri Dec 02 01:22:08 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609328752 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480609328752 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480609328752 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1480609334141 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480609334300 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "481 " "Peak virtual memory: 481 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:16 2016 " "Processing ended: Fri Dec 02 01:22:16 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480609336088 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480609336795 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480609337278 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:22:16 2016 " "Processing started: Fri Dec 02 01:22:16 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta lights -c lights " "Command: quartus_sta lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1480609337369 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1480609337763 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337763 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337851 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337851 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1480609338651 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1480609338693 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609338703 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609339290 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1480609339291 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1480609339369 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.773 " "Worst-case setup slack is 46.773" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 46.773 0.000 altera_reserved_tck " " 46.773 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.402 " "Worst-case hold slack is 0.402" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.402 0.000 altera_reserved_tck " " 0.402 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.354 " "Worst-case recovery slack is 47.354" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.354 0.000 altera_reserved_tck " " 47.354 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.459 " "Worst-case removal slack is 1.459" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.459 0.000 altera_reserved_tck " " 1.459 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.549 " "Worst-case minimum pulse width slack is 49.549" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.549 0.000 altera_reserved_tck " " 49.549 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.086 ns " "Worst Case Available Settling Time: 197.086 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1480609339584 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1480609339634 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1480609341036 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609341383 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609341393 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.135 " "Worst-case setup slack is 47.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.135 0.000 altera_reserved_tck " " 47.135 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.354 " "Worst-case hold slack is 0.354" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.354 0.000 altera_reserved_tck " " 0.354 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.646 " "Worst-case recovery slack is 47.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.646 0.000 altera_reserved_tck " " 47.646 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.333 " "Worst-case removal slack is 1.333" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.333 0.000 altera_reserved_tck " " 1.333 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.477 " "Worst-case minimum pulse width slack is 49.477" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.477 0.000 altera_reserved_tck " " 49.477 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.373 ns " "Worst Case Available Settling Time: 197.373 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1480609341798 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609342233 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609342245 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.795 " "Worst-case setup slack is 48.795" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.795 0.000 altera_reserved_tck " " 48.795 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 altera_reserved_tck " " 0.179 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.990 " "Worst-case recovery slack is 48.990" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.990 0.000 altera_reserved_tck " " 48.990 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.677 " "Worst-case removal slack is 0.677" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.677 0.000 altera_reserved_tck " " 0.677 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.299 " "Worst-case minimum pulse width slack is 49.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.299 0.000 altera_reserved_tck " " 49.299 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.609 ns " "Worst Case Available Settling Time: 198.609 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1480609344179 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1480609344179 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "603 " "Peak virtual memory: 603 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:24 2016 " "Processing ended: Fri Dec 02 01:22:24 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 997 s " "Quartus II Full Compilation was successful. 0 errors, 997 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609345332 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480609244120 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:20:43 2016 " "Processing started: Fri Dec 02 01:20:43 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lights -c lights " "Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1480609244121 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1480609244493 ""} +{ "Info" "ISGN_START_ELABORATION_QSYS" "nios_system.qsys " "Elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12248 "Elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609244532 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Loading qsys_tutorial/nios_system.qsys " "2016.12.02.01:20:45 Progress: Loading qsys_tutorial/nios_system.qsys" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245237 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Reading input file " "2016.12.02.01:20:45 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245421 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Adding clk_0 \[clock_source 13.0\] " "2016.12.02.01:20:45 Progress: Adding clk_0 \[clock_source 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245465 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Parameterizing module clk_0 " "2016.12.02.01:20:45 Progress: Parameterizing module clk_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245657 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:45 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\] " "2016.12.02.01:20:45 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609245661 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module nios2_processor " "2016.12.02.01:20:46 Progress: Parameterizing module nios2_processor" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246366 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246369 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module onchip_memory " "2016.12.02.01:20:46 Progress: Parameterizing module onchip_memory" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246433 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246434 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module jtag_uart " "2016.12.02.01:20:46 Progress: Parameterizing module jtag_uart" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246474 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246474 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module LEDs " "2016.12.02.01:20:46 Progress: Parameterizing module LEDs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246518 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246519 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module LEDRs " "2016.12.02.01:20:46 Progress: Parameterizing module LEDRs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246522 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246523 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module switches " "2016.12.02.01:20:46 Progress: Parameterizing module switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246524 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246524 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module push_switches " "2016.12.02.01:20:46 Progress: Parameterizing module push_switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246526 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246527 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex0 " "2016.12.02.01:20:46 Progress: Parameterizing module hex0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246528 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246529 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex1 " "2016.12.02.01:20:46 Progress: Parameterizing module hex1" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246530 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246531 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex2 " "2016.12.02.01:20:46 Progress: Parameterizing module hex2" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246532 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246533 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex3 " "2016.12.02.01:20:46 Progress: Parameterizing module hex3" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246534 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246535 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex4 " "2016.12.02.01:20:46 Progress: Parameterizing module hex4" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246536 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246537 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex5 " "2016.12.02.01:20:46 Progress: Parameterizing module hex5" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246538 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246539 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex6 " "2016.12.02.01:20:46 Progress: Parameterizing module hex6" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246540 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246540 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module hex7 " "2016.12.02.01:20:46 Progress: Parameterizing module hex7" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246542 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246542 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_16207_0 " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_16207_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246563 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246564 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_on " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_on" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246566 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:20:46 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246567 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing module lcd_blon " "2016.12.02.01:20:46 Progress: Parameterizing module lcd_blon" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246569 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Building connections " "2016.12.02.01:20:46 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246569 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Parameterizing connections " "2016.12.02.01:20:46 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246883 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:46 Progress: Validating " "2016.12.02.01:20:46 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609246886 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:20:47 Progress: Done reading input file " "2016.12.02.01:20:47 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247552 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247857 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609247857 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH " "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248752 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections " "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248978 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "No custom instruction connections, skipping transform " "No custom instruction connections, skipping transform " { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609248985 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_translator_transform: After transform: 39 modules, 155 connections " "Merlin_translator_transform: After transform: 39 modules, 155 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609249536 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_domain_transform: After transform: 78 modules, 423 connections " "Merlin_domain_transform: After transform: 78 modules, 423 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250547 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_router_transform: After transform: 98 modules, 503 connections " "Merlin_router_transform: After transform: 98 modules, 503 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250874 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reset_adaptation_transform: After transform: 99 modules, 390 connections " "Reset_adaptation_transform: After transform: 99 modules, 390 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609250950 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections " "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251203 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_mm_transform: After transform: 138 modules, 470 connections " "Merlin_mm_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251295 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections " "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609251335 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252303 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252303 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252304 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252305 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252306 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252306 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252306 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252306 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252307 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252307 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252307 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252307 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252308 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252308 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252308 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252308 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252309 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req 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"%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252310 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252311 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252312 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252312 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req 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"%1!s!" 0 0 "Quartus II" 0 -1 1480609252313 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252313 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252313 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252313 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252314 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252314 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252315 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req 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"%1!s!" 0 0 "Quartus II" 0 -1 1480609252315 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252315 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252316 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252316 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252317 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252317 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252317 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req 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"%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252318 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252319 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252319 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252319 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252319 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252319 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252319 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252319 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252321 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252322 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252322 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252322 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252322 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252322 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252323 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252323 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252323 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252323 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252324 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252324 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252324 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252324 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252325 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252326 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252327 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252328 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252329 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252330 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252709 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \] " "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609252709 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Starting Nios II generation " "Nios2_processor: # 2016.12.02 01:20:53 (*) Starting Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Checking for plaintext license. " "Nios2_processor: # 2016.12.02 01:20:53 (*) Checking for plaintext license." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus " "Nios2_processor: # 2016.12.02 01:20:53 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable " "Nios2_processor: # 2016.12.02 01:20:53 (*) Defaulting to contents of LM_LICENSE_FILE environment variable" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) LM_LICENSE_FILE environment variable is empty " "Nios2_processor: # 2016.12.02 01:20:53 (*) LM_LICENSE_FILE environment variable is empty" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256733 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Plaintext license not found. " "Nios2_processor: # 2016.12.02 01:20:53 (*) Plaintext license not found." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) No license required to generate encrypted Nios II/e. " "Nios2_processor: # 2016.12.02 01:20:53 (*) No license required to generate encrypted Nios II/e." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Elaborating CPU configuration settings " "Nios2_processor: # 2016.12.02 01:20:53 (*) Elaborating CPU configuration settings" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:53 (*) Creating all objects for CPU " "Nios2_processor: # 2016.12.02 01:20:53 (*) Creating all objects for CPU" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:54 (*) Generating RTL from CPU objects " "Nios2_processor: # 2016.12.02 01:20:54 (*) Generating RTL from CPU objects" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:54 (*) Creating plain-text RTL " "Nios2_processor: # 2016.12.02 01:20:54 (*) Creating plain-text RTL" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:20:56 (*) Done Nios II generation " "Nios2_processor: # 2016.12.02 01:20:56 (*) Done Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256734 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256735 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\" " "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256747 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256787 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \] " "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609256787 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257861 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\" " "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257874 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257894 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \] " "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609257894 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258183 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\" " "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258187 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Starting RTL generation for module 'nios_system_LEDs' " "LEDs: Starting RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258209 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \] " "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258209 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Done RTL generation for module 'nios_system_LEDs' " "LEDs: Done RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258399 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\" " "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258401 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Starting RTL generation for module 'nios_system_LEDRs' " "LEDRs: Starting RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258414 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \] " "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258415 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Done RTL generation for module 'nios_system_LEDRs' " "LEDRs: Done RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258596 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\" " "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258598 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Starting RTL generation for module 'nios_system_switches' " "Switches: Starting RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258613 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \] " "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258613 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Done RTL generation for module 'nios_system_switches' " "Switches: Done RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258799 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\" " "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258801 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Starting RTL generation for module 'nios_system_push_switches' " "Push_switches: Starting RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258817 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \] " "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609258817 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Done RTL generation for module 'nios_system_push_switches' " "Push_switches: Done RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259002 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\" " "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259005 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Starting RTL generation for module 'nios_system_hex0' " "Hex0: Starting RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259021 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \] " "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259021 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Done RTL generation for module 'nios_system_hex0' " "Hex0: Done RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259206 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\" " "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259208 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259222 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \] " "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259222 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259404 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\" " "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259407 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259419 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \] " "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_448397646303925983.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259420 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Done RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Done RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259615 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\" " "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259618 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\" " "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259620 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\" " "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259629 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\" " "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259637 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259645 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259659 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\" " "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259678 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\" " "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259697 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\" " "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259714 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\" " "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259726 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\" " "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259729 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\" " "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259754 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\" " "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259787 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\" " "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259831 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\" " "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259857 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\" " "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259890 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259891 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\" " "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259951 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259952 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\" " "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259971 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes " "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609259972 ""} +{ "Info" "ISGN_END_ELABORATION_QSYS" "nios_system.qsys " "Finished elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12249 "Finished elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609260929 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lights.vhd 2 1 " "Found 2 design units, including 1 entities, in source file lights.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lights-lights_rtl " "Found design unit 1: lights-lights_rtl" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 27 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} { "Info" "ISGN_ENTITY_NAME" "1 lights " "Found entity 1: lights" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261363 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_system/synthesis/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "nios_system/synthesis/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261383 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "db/ip/nios_system/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261402 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261402 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261406 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261410 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261414 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261418 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261422 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261422 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261426 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261431 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261431 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261435 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261438 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261438 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_ledrs.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDRs " "Found entity 1: nios_system_LEDRs" { } { { "db/ip/nios_system/submodules/nios_system_LEDRs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261441 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261441 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDs " "Found entity 1: nios_system_LEDs" { } { { "db/ip/nios_system/submodules/nios_system_LEDs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261444 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261444 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261447 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261447 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_default_decode " "Found entity 1: nios_system_addr_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router " "Found entity 2: nios_system_addr_router" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261448 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router_001.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261451 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router_001.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261451 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_001_default_decode " "Found entity 1: nios_system_addr_router_001_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router_001 " "Found entity 2: nios_system_addr_router_001" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261452 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux " "Found entity 1: nios_system_cmd_xbar_demux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261455 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261455 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux_001 " "Found entity 1: nios_system_cmd_xbar_demux_001" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261459 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_mux " "Found entity 1: nios_system_cmd_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261463 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_hex0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_hex0 " "Found entity 1: nios_system_hex0" { } { { "db/ip/nios_system/submodules/nios_system_hex0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261467 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router.sv(48) " "Verilog HDL Declaration information at nios_system_id_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261470 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router.sv(49) " "Verilog HDL Declaration information at nios_system_id_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261470 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_default_decode " "Found entity 1: nios_system_id_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router " "Found entity 2: nios_system_id_router" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261471 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router_002.sv(48) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261474 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router_002.sv(49) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609261475 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_002_default_decode " "Found entity 1: nios_system_id_router_002_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router_002 " "Found entity 2: nios_system_id_router_002" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261476 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_irq_mapper " "Found entity 1: nios_system_irq_mapper" { } { { "db/ip/nios_system/submodules/nios_system_irq_mapper.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261479 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_jtag_uart.v 5 5 " "Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_jtag_uart_sim_scfifo_w " "Found entity 1: nios_system_jtag_uart_sim_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_jtag_uart_scfifo_w " "Found entity 2: nios_system_jtag_uart_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_jtag_uart_sim_scfifo_r " "Found entity 3: nios_system_jtag_uart_sim_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 162 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_jtag_uart_scfifo_r " "Found entity 4: nios_system_jtag_uart_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 240 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_jtag_uart " "Found entity 5: nios_system_jtag_uart" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 327 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261485 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_16207_0 " "Found entity 1: nios_system_lcd_16207_0" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261488 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_on.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_on " "Found entity 1: nios_system_lcd_on" { } { { "db/ip/nios_system/submodules/nios_system_lcd_on.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261492 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor.v 21 21 " "Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_register_bank_a_module " "Found entity 1: nios_system_nios2_processor_register_bank_a_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_nios2_processor_register_bank_b_module " "Found entity 2: nios_system_nios2_processor_register_bank_b_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_nios2_processor_nios2_oci_debug " "Found entity 3: nios_system_nios2_processor_nios2_oci_debug" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_nios2_processor_ociram_sp_ram_module " "Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 288 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_nios2_processor_nios2_ocimem " "Found entity 5: nios_system_nios2_processor_nios2_ocimem" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 346 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "6 nios_system_nios2_processor_nios2_avalon_reg " "Found entity 6: nios_system_nios2_processor_nios2_avalon_reg" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 524 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "7 nios_system_nios2_processor_nios2_oci_break " "Found entity 7: nios_system_nios2_processor_nios2_oci_break" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 616 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "8 nios_system_nios2_processor_nios2_oci_xbrk " "Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 910 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "9 nios_system_nios2_processor_nios2_oci_dbrk " "Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1116 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "10 nios_system_nios2_processor_nios2_oci_itrace " "Found entity 10: nios_system_nios2_processor_nios2_oci_itrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1302 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "11 nios_system_nios2_processor_nios2_oci_td_mode " "Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1599 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "12 nios_system_nios2_processor_nios2_oci_dtrace " "Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "13 nios_system_nios2_processor_nios2_oci_compute_tm_count " "Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1760 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "14 nios_system_nios2_processor_nios2_oci_fifowp_inc " "Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1831 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "15 nios_system_nios2_processor_nios2_oci_fifocount_inc " "Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1873 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "16 nios_system_nios2_processor_nios2_oci_fifo " "Found entity 16: nios_system_nios2_processor_nios2_oci_fifo" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1919 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "17 nios_system_nios2_processor_nios2_oci_pib " "Found entity 17: nios_system_nios2_processor_nios2_oci_pib" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2424 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "18 nios_system_nios2_processor_nios2_oci_im " "Found entity 18: nios_system_nios2_processor_nios2_oci_im" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "19 nios_system_nios2_processor_nios2_performance_monitors " "Found entity 19: nios_system_nios2_processor_nios2_performance_monitors" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2608 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "20 nios_system_nios2_processor_nios2_oci " "Found entity 20: nios_system_nios2_processor_nios2_oci" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2624 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} { "Info" "ISGN_ENTITY_NAME" "21 nios_system_nios2_processor " "Found entity 21: nios_system_nios2_processor" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3129 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261511 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_sysclk " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261516 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261516 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_tck " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261519 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_wrapper " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261523 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_oci_test_bench " "Found entity 1: nios_system_nios2_processor_oci_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261526 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_test_bench " "Found entity 1: nios_system_nios2_processor_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261530 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261530 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_onchip_memory.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_onchip_memory " "Found entity 1: nios_system_onchip_memory" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261533 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261533 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_push_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_push_switches " "Found entity 1: nios_system_push_switches" { } { { "db/ip/nios_system/submodules/nios_system_push_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261537 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_demux_002 " "Found entity 1: nios_system_rsp_xbar_demux_002" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261541 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux " "Found entity 1: nios_system_rsp_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261545 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261545 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux_001 " "Found entity 1: nios_system_rsp_xbar_mux_001" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261550 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_switches " "Found entity 1: nios_system_switches" { } { { "db/ip/nios_system/submodules/nios_system_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609261554 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609261554 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1567) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1567 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261584 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1569) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1569 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261584 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1725) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1725 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261585 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(2553) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2553 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609261588 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "lights " "Elaborating entity \"lights\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1480609261703 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system nios_system:NiosII " "Elaborating entity \"nios_system\" for hierarchy \"nios_system:NiosII\"" { } { { "lights.vhd" "NiosII" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 53 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609261724 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor nios_system:NiosII\|nios_system_nios2_processor:nios2_processor " "Elaborating entity \"nios_system_nios2_processor\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262516 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench " "Elaborating entity \"nios_system_nios2_processor_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262643 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_a_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a " "Elaborating entity \"nios_system_nios2_processor_register_bank_a_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_a" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262685 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262737 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_a.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262758 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609262758 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0rh1 " "Found entity 1: altsyncram_0rh1" { } { { "db/altsyncram_0rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609262827 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609262827 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated " "Elaborating entity \"altsyncram_0rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262829 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_b_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b " "Elaborating entity \"nios_system_nios2_processor_register_bank_b_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_b" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4300 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262955 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262975 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_b.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609262994 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609262994 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1rh1 " "Found entity 1: altsyncram_1rh1" { } { { "db/altsyncram_1rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609263063 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609263063 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated " "Elaborating entity \"altsyncram_1rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263066 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci " "Elaborating entity \"nios_system_nios2_processor_nios2_oci\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4758 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263193 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_debug nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_debug\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_debug" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263239 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altera_std_synchronizer" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263267 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609263279 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263279 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609263279 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_ocimem nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem " "Elaborating entity \"nios_system_nios2_processor_nios2_ocimem\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_ocimem" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2821 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263282 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_ociram_sp_ram_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram " "Elaborating entity \"nios_system_nios2_processor_ociram_sp_ram_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_ociram_sp_ram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 491 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263310 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263727 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609263751 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_ociram_default_contents.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263752 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609263752 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4891.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4891 " "Found entity 1: altsyncram_4891" { } { { "db/altsyncram_4891.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609263817 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609263817 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4891 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated " "Elaborating entity \"altsyncram_4891\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263819 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_avalon_reg nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg " "Elaborating entity \"nios_system_nios2_processor_nios2_avalon_reg\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_avalon_reg" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2840 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263950 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_break nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_break\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_break" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2871 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609263968 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_xbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_xbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_xbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2892 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264008 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264024 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_itrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_itrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_itrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2937 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264041 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dtrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dtrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dtrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2952 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264068 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_td_mode nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_td_mode\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264093 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifo nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifo\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2971 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264108 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_compute_tm_count\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2046 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264154 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifowp_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2056 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264171 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifocount_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2066 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264189 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_oci_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench " "Elaborating entity \"nios_system_nios2_processor_oci_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264205 ""} +{ "Warning" "WSGN_EMPTY_SHELL" "nios_system_nios2_processor_oci_test_bench " "Entity \"nios_system_nios2_processor_oci_test_bench\" contains only dangling pins" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12158 "Entity \"%1!s!\" contains only dangling pins" 0 0 "Quartus II" 0 -1 1480609264206 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_pib nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_pib\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_pib" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2981 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264222 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_im nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_im\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_im" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3002 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264235 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_wrapper nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_wrapper\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_jtag_debug_module_wrapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3107 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264430 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_tck nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_tck\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_tck" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264450 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_sysclk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_sysclk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_sysclk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264479 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "nios_system_nios2_processor_jtag_debug_module_phy" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264517 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264531 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609264531 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264533 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264548 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_onchip_memory nios_system:NiosII\|nios_system_onchip_memory:onchip_memory " "Elaborating entity \"nios_system_onchip_memory\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264552 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264571 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_onchip_memory.hex " "Parameter \"init_file\" = \"nios_system_onchip_memory.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 51200 " "Parameter \"maximum_depth\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 51200 " "Parameter \"numwords_a\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 16 " "Parameter \"widthad_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264591 ""} } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609264591 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4ed1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4ed1 " "Found entity 1: altsyncram_4ed1" { } { { "db/altsyncram_4ed1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609264688 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609264688 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4ed1 nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated " "Elaborating entity \"altsyncram_4ed1\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609264690 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_qsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_qsa " "Found entity 1: decode_qsa" { } { { "db/decode_qsa.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609266788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609266788 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_qsa nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3 " "Elaborating entity \"decode_qsa\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3\"" { } { { "db/altsyncram_4ed1.tdf" "decode3" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609266790 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_nob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_nob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_nob " "Found entity 1: mux_nob" { } { { "db/mux_nob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609266919 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609266919 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_nob nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2 " "Elaborating entity \"mux_nob\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2\"" { } { { "db/altsyncram_4ed1.tdf" "mux2" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609266921 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart nios_system:NiosII\|nios_system_jtag_uart:jtag_uart " "Elaborating entity \"nios_system_jtag_uart\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1129 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267161 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_w nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w " "Elaborating entity \"nios_system_jtag_uart_scfifo_w\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_w" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 415 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267404 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "wfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267473 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267488 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609267488 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267556 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267556 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267558 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267585 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267585 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267588 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267611 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267614 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267703 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267703 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267705 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609267794 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609267794 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609267797 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609268450 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609268450 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268452 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609268547 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609268547 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268550 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_r nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r " "Elaborating entity \"nios_system_jtag_uart_scfifo_r\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_r" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 429 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268582 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "nios_system_jtag_uart_alt_jtag_atlantic" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268734 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268765 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609268765 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDs nios_system:NiosII\|nios_system_LEDs:leds " "Elaborating entity \"nios_system_LEDs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDs:leds\"" { } { { "nios_system/synthesis/nios_system.v" "leds" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268774 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDRs nios_system:NiosII\|nios_system_LEDRs:ledrs " "Elaborating entity \"nios_system_LEDRs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDRs:ledrs\"" { } { { "nios_system/synthesis/nios_system.v" "ledrs" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268792 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_switches nios_system:NiosII\|nios_system_switches:switches " "Elaborating entity \"nios_system_switches\" for hierarchy \"nios_system:NiosII\|nios_system_switches:switches\"" { } { { "nios_system/synthesis/nios_system.v" "switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1159 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268812 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_push_switches nios_system:NiosII\|nios_system_push_switches:push_switches " "Elaborating entity \"nios_system_push_switches\" for hierarchy \"nios_system:NiosII\|nios_system_push_switches:push_switches\"" { } { { "nios_system/synthesis/nios_system.v" "push_switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268835 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_hex0 nios_system:NiosII\|nios_system_hex0:hex0 " "Elaborating entity \"nios_system_hex0\" for hierarchy \"nios_system:NiosII\|nios_system_hex0:hex0\"" { } { { "nios_system/synthesis/nios_system.v" "hex0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268854 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_16207_0 nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0 " "Elaborating entity \"nios_system_lcd_16207_0\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268889 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_on nios_system:NiosII\|nios_system_lcd_on:lcd_on " "Elaborating entity \"nios_system_lcd_on\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_on:lcd_on\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_on" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1281 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268908 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1354 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268928 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1416 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268956 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1482 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609268985 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1548 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269019 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "leds_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1614 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269051 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart_avalon_jtag_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1680 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269081 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0_control_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269142 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2684 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269180 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2764 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269242 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2845 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269266 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269302 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2886 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269337 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router nios_system:NiosII\|nios_system_addr_router:addr_router " "Elaborating entity \"nios_system_addr_router\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4976 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269535 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_default_decode nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 177 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269571 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001 nios_system:NiosII\|nios_system_addr_router_001:addr_router_001 " "Elaborating entity \"nios_system_addr_router_001\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4992 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269589 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001_default_decode nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_001_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269655 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router nios_system:NiosII\|nios_system_id_router:id_router " "Elaborating entity \"nios_system_id_router\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\"" { } { { "nios_system/synthesis/nios_system.v" "id_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5008 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269670 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_default_decode nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269696 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002 nios_system:NiosII\|nios_system_id_router_002:id_router_002 " "Elaborating entity \"nios_system_id_router_002\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\"" { } { { "nios_system/synthesis/nios_system.v" "id_router_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5040 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269717 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002_default_decode nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_002_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269739 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller nios_system:NiosII\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\"" { } { { "nios_system/synthesis/nios_system.v" "rst_controller" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5307 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269835 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 120 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269858 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"nios_system_cmd_xbar_demux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5330 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269883 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux_001 nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"nios_system_cmd_xbar_demux_001\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5449 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269910 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_mux nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"nios_system_cmd_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609269979 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270014 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270033 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_demux_002 nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"nios_system_rsp_xbar_demux_002\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_demux_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5558 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270061 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"nios_system_rsp_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5836 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270124 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270155 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux_001 nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"nios_system_rsp_xbar_mux_001\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5955 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270177 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 552 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270333 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270353 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_irq_mapper nios_system:NiosII\|nios_system_irq_mapper:irq_mapper " "Elaborating entity \"nios_system_irq_mapper\" for hierarchy \"nios_system:NiosII\|nios_system_irq_mapper:irq_mapper\"" { } { { "nios_system/synthesis/nios_system.v" "irq_mapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609270368 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "5 " "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1480609279462 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609279649 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1480609279649 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 276 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 348 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3167 -1 0 } } { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3740 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 393 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 599 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 62 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1480609279714 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1480609279714 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609281555 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "166 " "166 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1480609284267 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 384 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 521 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1480609284431 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1480609284431 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" { } { { "sld_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd" 181 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1480609284529 "|lights|sld_hub:auto_hub|receive[0][0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1480609284529 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609284691 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1480609285369 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1480609286405 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609286405 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "2880 " "Implemented 2880 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2421 " "Implemented 2421 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1480609287063 ""} { "Info" "ICUT_CUT_TM_RAMS" "336 " "Implemented 336 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1480609287063 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1480609287063 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 150 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 150 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "650 " "Peak virtual memory: 650 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:21:27 2016 " "Processing ended: Fri Dec 02 01:21:27 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:44 " "Elapsed time: 00:00:44" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609287183 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480609288328 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609288329 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:21:27 2016 " "Processing started: Fri Dec 02 01:21:27 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609288329 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480609288329 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480609288329 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480609288398 ""} +{ "Info" "0" "" "Project = lights" { } { } 0 0 "Project = lights" 0 0 "Fitter" 0 0 1480609288399 ""} +{ "Info" "0" "" "Revision = lights" { } { } 0 0 "Revision = lights" 0 0 "Fitter" 0 0 1480609288399 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1480609288552 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "lights EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"lights\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480609288596 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609288662 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480609288891 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1480609288902 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609289561 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1480609289561 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11997 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11999 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12001 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12003 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12005 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609289572 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1480609289572 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480609289576 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480609289623 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 118 " "No exact pin location assignment(s) for 1 pins of 118 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LCD_E " "Pin LCD_E not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_E } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_E } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 363 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1480609292219 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1480609292219 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609293128 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1480609293128 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480609293201 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1480609293215 "|lights|CLOCK_50"} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609293273 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1480609293273 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1480609293273 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609293274 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1480609293274 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293621 ""} } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11965 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293621 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293621 ""} } { { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4020 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293621 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 177 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4471 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3700 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 3290 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0 " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0" { } { { "altera_std_synchronizer.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5951 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609293622 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1480609293622 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 172 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 906 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293622 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609293623 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 68 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5707 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609293623 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480609294840 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1480609294848 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1480609294848 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480609294859 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480609294870 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480609294878 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480609294879 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480609294887 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480609294987 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 EC " "Packed 8 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1480609294996 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480609294996 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 2.5V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1480609295071 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1480609295071 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1480609295071 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 20 40 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 62 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 62 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 1 72 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 1 total pin(s) used -- 72 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 32 39 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 2.5V 34 31 " "I/O bank number 5 does not use VREF pins and has 2.5V VCCIO pins. 34 total pin(s) used -- 31 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 2.5V 9 49 " "I/O bank number 6 does not use VREF pins and has 2.5V VCCIO pins. 9 total pin(s) used -- 49 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 2.5V 29 43 " "I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 29 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 71 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 71 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1480609295073 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1480609295073 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1480609295073 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK2_50 " "Ignored I/O standard assignment to node \"CLOCK2_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK3_50 " "Ignored I/O standard assignment to node \"CLOCK3_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[0\] " "Ignored I/O standard assignment to node \"DRAM_BA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[1\] " "Ignored I/O standard assignment to node \"DRAM_BA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CAS_N " "Ignored I/O standard assignment to node \"DRAM_CAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CKE " "Ignored I/O standard assignment to node \"DRAM_CKE\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CLK " "Ignored I/O standard assignment to node \"DRAM_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CS_N " "Ignored I/O standard assignment to node \"DRAM_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[16\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[17\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[18\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[19\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[20\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[21\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[22\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[23\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[24\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[25\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[26\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[27\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[28\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[29\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[30\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[31\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_RAS_N " "Ignored I/O standard assignment to node \"DRAM_RAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_WE_N " "Ignored I/O standard assignment to node \"DRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SCLK " "Ignored I/O standard assignment to node \"EEP_I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SDAT " "Ignored I/O standard assignment to node \"EEP_I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_GTX_CLK " "Ignored I/O standard assignment to node \"ENET0_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_INT_N " "Ignored I/O standard assignment to node \"ENET0_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_LINK100 " "Ignored I/O standard assignment to node \"ENET0_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDC " "Ignored I/O standard assignment to node \"ENET0_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDIO " "Ignored I/O standard assignment to node \"ENET0_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RST_N " "Ignored I/O standard assignment to node \"ENET0_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CLK " "Ignored I/O standard assignment to node \"ENET0_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_COL " "Ignored I/O standard assignment to node \"ENET0_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CRS " "Ignored I/O standard assignment to node \"ENET0_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DV " "Ignored I/O standard assignment to node \"ENET0_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_ER " "Ignored I/O standard assignment to node \"ENET0_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_CLK " "Ignored I/O standard assignment to node \"ENET0_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_EN " "Ignored I/O standard assignment to node \"ENET0_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_ER " "Ignored I/O standard assignment to node \"ENET0_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_GTX_CLK " "Ignored I/O standard assignment to node \"ENET1_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_INT_N " "Ignored I/O standard assignment to node \"ENET1_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_LINK100 " "Ignored I/O standard assignment to node \"ENET1_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDC " "Ignored I/O standard assignment to node \"ENET1_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDIO " "Ignored I/O standard assignment to node \"ENET1_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RST_N " "Ignored I/O standard assignment to node \"ENET1_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CLK " "Ignored I/O standard assignment to node \"ENET1_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_COL " "Ignored I/O standard assignment to node \"ENET1_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CRS " "Ignored I/O standard assignment to node \"ENET1_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DV " "Ignored I/O standard assignment to node \"ENET1_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_ER " "Ignored I/O standard assignment to node \"ENET1_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_CLK " "Ignored I/O standard assignment to node \"ENET1_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_EN " "Ignored I/O standard assignment to node \"ENET1_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_ER " "Ignored I/O standard assignment to node \"ENET1_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENETCLK_25 " "Ignored I/O standard assignment to node \"ENETCLK_25\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[0\] " "Ignored I/O standard assignment to node \"EX_IO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[1\] " "Ignored I/O standard assignment to node \"EX_IO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[2\] " "Ignored I/O standard assignment to node \"EX_IO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[3\] " "Ignored I/O standard assignment to node \"EX_IO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[4\] " "Ignored I/O standard assignment to node \"EX_IO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[5\] " "Ignored I/O standard assignment to node \"EX_IO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[6\] " "Ignored I/O standard assignment to node \"EX_IO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[22\] " "Ignored I/O standard assignment to node \"FL_ADDR\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[0\] " "Ignored I/O standard assignment to node \"GPIO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[10\] " "Ignored I/O standard assignment to node \"GPIO\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[11\] " "Ignored I/O standard assignment to node \"GPIO\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[12\] " "Ignored I/O standard assignment to node \"GPIO\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[13\] " "Ignored I/O standard assignment to node \"GPIO\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[14\] " "Ignored I/O standard assignment to node \"GPIO\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[15\] " "Ignored I/O standard assignment to node \"GPIO\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[16\] " "Ignored I/O standard assignment to node \"GPIO\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[17\] " "Ignored I/O standard assignment to node \"GPIO\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[18\] " "Ignored I/O standard assignment to node \"GPIO\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[19\] " "Ignored I/O standard assignment to node \"GPIO\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[1\] " "Ignored I/O standard assignment to node \"GPIO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[20\] " "Ignored I/O standard assignment to node \"GPIO\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[21\] " "Ignored I/O standard assignment to node \"GPIO\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[22\] " "Ignored I/O standard assignment to node \"GPIO\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[23\] " "Ignored I/O standard assignment to node \"GPIO\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[24\] " "Ignored I/O standard assignment to node \"GPIO\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[25\] " "Ignored I/O standard assignment to node \"GPIO\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[26\] " "Ignored I/O standard assignment to node \"GPIO\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[27\] " "Ignored I/O standard assignment to node \"GPIO\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[28\] " "Ignored I/O standard assignment to node \"GPIO\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[29\] " "Ignored I/O standard assignment to node \"GPIO\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[2\] " "Ignored I/O standard assignment to node \"GPIO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[30\] " "Ignored I/O standard assignment to node \"GPIO\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[31\] " "Ignored I/O standard assignment to node \"GPIO\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[32\] " "Ignored I/O standard assignment to node \"GPIO\[32\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[33\] " "Ignored I/O standard assignment to node \"GPIO\[33\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[34\] " "Ignored I/O standard assignment to node \"GPIO\[34\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[35\] " "Ignored I/O standard assignment to node \"GPIO\[35\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[3\] " "Ignored I/O standard assignment to node \"GPIO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[4\] " "Ignored I/O standard assignment to node \"GPIO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[5\] " "Ignored I/O standard assignment to node \"GPIO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[6\] " "Ignored I/O standard assignment to node \"GPIO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[7\] " "Ignored I/O standard assignment to node \"GPIO\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[8\] " "Ignored I/O standard assignment to node \"GPIO\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[9\] " "Ignored I/O standard assignment to node \"GPIO\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN0 " "Ignored I/O standard assignment to node \"HSMC_CLKIN0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT0 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[0\] " "Ignored I/O standard assignment to node \"HSMC_D\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[1\] " "Ignored I/O standard assignment to node \"HSMC_D\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[2\] " "Ignored I/O standard assignment to node \"HSMC_D\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[3\] " "Ignored I/O standard assignment to node \"HSMC_D\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "IRDA_RXD " "Ignored I/O standard assignment to node \"IRDA_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LEDG\[8\] " "Ignored I/O standard assignment to node \"LEDG\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[0\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[1\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_CS_N " "Ignored I/O standard assignment to node \"OTG_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[0\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[1\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[0\] " "Ignored I/O standard assignment to node \"OTG_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[10\] " "Ignored I/O standard assignment to node \"OTG_DATA\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[11\] " "Ignored I/O standard assignment to node \"OTG_DATA\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[12\] " "Ignored I/O standard assignment to node \"OTG_DATA\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[13\] " "Ignored I/O standard assignment to node \"OTG_DATA\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[14\] " "Ignored I/O standard assignment to node \"OTG_DATA\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[15\] " "Ignored I/O standard assignment to node \"OTG_DATA\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[1\] " "Ignored I/O standard assignment to node \"OTG_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[2\] " "Ignored I/O standard assignment to node \"OTG_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[3\] " "Ignored I/O standard assignment to node \"OTG_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[4\] " "Ignored I/O standard assignment to node \"OTG_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[5\] " "Ignored I/O standard assignment to node \"OTG_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[6\] " "Ignored I/O standard assignment to node \"OTG_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[7\] " "Ignored I/O standard assignment to node \"OTG_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[8\] " "Ignored I/O standard assignment to node \"OTG_DATA\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[9\] " "Ignored I/O standard assignment to node \"OTG_DATA\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[0\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[1\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_FSPEED " "Ignored I/O standard assignment to node \"OTG_FSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[0\] " "Ignored I/O standard assignment to node \"OTG_INT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[1\] " "Ignored I/O standard assignment to node \"OTG_INT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_LSPEED " "Ignored I/O standard assignment to node \"OTG_LSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RD_N " "Ignored I/O standard assignment to node \"OTG_RD_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RST_N " "Ignored I/O standard assignment to node \"OTG_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_WR_N " "Ignored I/O standard assignment to node \"OTG_WR_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK " "Ignored I/O standard assignment to node \"PS2_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK2 " "Ignored I/O standard assignment to node \"PS2_CLK2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT " "Ignored I/O standard assignment to node \"PS2_DAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT2 " "Ignored I/O standard assignment to node \"PS2_DAT2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[0\] " "Ignored I/O standard assignment to node \"SD_DAT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[1\] " "Ignored I/O standard assignment to node \"SD_DAT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[2\] " "Ignored I/O standard assignment to node \"SD_DAT\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[3\] " "Ignored I/O standard assignment to node \"SD_DAT\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKIN " "Ignored I/O standard assignment to node \"SMA_CLKIN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKOUT " "Ignored I/O standard assignment to node \"SMA_CLKOUT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[13\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[14\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[15\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[16\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[17\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[18\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[19\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_CE_N " "Ignored I/O standard assignment to node \"SRAM_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_LB_N " "Ignored I/O standard assignment to node \"SRAM_LB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_OE_N " "Ignored I/O standard assignment to node \"SRAM_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_UB_N " "Ignored I/O standard assignment to node \"SRAM_UB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_WE_N " "Ignored I/O standard assignment to node \"SRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_CLK27 " "Ignored I/O standard assignment to node \"TD_CLK27\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[0\] " "Ignored I/O standard assignment to node \"TD_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[1\] " "Ignored I/O standard assignment to node \"TD_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[2\] " "Ignored I/O standard assignment to node \"TD_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[3\] " "Ignored I/O standard assignment to node \"TD_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[4\] " "Ignored I/O standard assignment to node \"TD_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[5\] " "Ignored I/O standard assignment to node \"TD_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[6\] " "Ignored I/O standard assignment to node \"TD_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[7\] " "Ignored I/O standard assignment to node \"TD_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_HS " "Ignored I/O standard assignment to node \"TD_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_RESET_N " "Ignored I/O standard assignment to node \"TD_RESET_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_VS " "Ignored I/O standard assignment to node \"TD_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_BLANK_N " "Ignored I/O standard assignment to node \"VGA_BLANK_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[0\] " "Ignored I/O standard assignment to node \"VGA_B\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[1\] " "Ignored I/O standard assignment to node \"VGA_B\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[2\] " "Ignored I/O standard assignment to node \"VGA_B\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[3\] " "Ignored I/O standard assignment to node \"VGA_B\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[4\] " "Ignored I/O standard assignment to node \"VGA_B\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[5\] " "Ignored I/O standard assignment to node \"VGA_B\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[6\] " "Ignored I/O standard assignment to node \"VGA_B\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[7\] " "Ignored I/O standard assignment to node \"VGA_B\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_CLK " "Ignored I/O standard assignment to node \"VGA_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[0\] " "Ignored I/O standard assignment to node \"VGA_G\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[1\] " "Ignored I/O standard assignment to node \"VGA_G\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[2\] " "Ignored I/O standard assignment to node \"VGA_G\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[3\] " "Ignored I/O standard assignment to node \"VGA_G\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[4\] " "Ignored I/O standard assignment to node \"VGA_G\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[5\] " "Ignored I/O standard assignment to node \"VGA_G\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[6\] " "Ignored I/O standard assignment to node \"VGA_G\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[7\] " "Ignored I/O standard assignment to node \"VGA_G\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_HS " "Ignored I/O standard assignment to node \"VGA_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[0\] " "Ignored I/O standard assignment to node \"VGA_R\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[1\] " "Ignored I/O standard assignment to node \"VGA_R\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[2\] " "Ignored I/O standard assignment to node \"VGA_R\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[3\] " "Ignored I/O standard assignment to node \"VGA_R\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[4\] " "Ignored I/O standard assignment to node \"VGA_R\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[5\] " "Ignored I/O standard assignment to node \"VGA_R\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[6\] " "Ignored I/O standard assignment to node \"VGA_R\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[7\] " "Ignored I/O standard assignment to node \"VGA_R\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_SYNC_N " "Ignored I/O standard assignment to node \"VGA_SYNC_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_VS " "Ignored I/O standard assignment to node \"VGA_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609295298 ""} } { } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1480609295298 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[0\] " "Node \"OTG_DACK_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[1\] " "Node \"OTG_DACK_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[1\] " "Node \"OTG_DREQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[0\] " "Node \"OTG_INT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[1\] " "Node \"OTG_INT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609295327 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480609295327 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:06 " "Fitter preparation operations ending: elapsed time is 00:00:06" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609295357 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480609302965 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609304725 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480609304769 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480609307778 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609307779 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480609309715 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X58_Y37 X68_Y48 " "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48" { } { { "loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 1 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48"} { { 11 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48"} 58 37 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1480609316983 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480609316983 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609318123 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1480609318126 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1480609318126 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480609318126 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.83 " "Total time spent on timing analysis during the Fitter is 0.83 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1480609318321 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480609318412 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480609319674 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480609319768 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480609320969 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609322400 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480609324348 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "9 Cyclone IV E " "9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[0\] 3.3-V LVTTL L3 " "Pin LCD_data\[0\] uses I/O standard 3.3-V LVTTL at L3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[0\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 352 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[1\] 3.3-V LVTTL L1 " "Pin LCD_data\[1\] uses I/O standard 3.3-V LVTTL at L1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[1\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 353 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[2\] 3.3-V LVTTL L2 " "Pin LCD_data\[2\] uses I/O standard 3.3-V LVTTL at L2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[2\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 354 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[3\] 3.3-V LVTTL K7 " "Pin LCD_data\[3\] uses I/O standard 3.3-V LVTTL at K7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[3\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 355 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[4\] 3.3-V LVTTL K1 " "Pin LCD_data\[4\] uses I/O standard 3.3-V LVTTL at K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[4\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[5\] 3.3-V LVTTL K2 " "Pin LCD_data\[5\] uses I/O standard 3.3-V LVTTL at K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[5\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 357 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[6\] 3.3-V LVTTL M3 " "Pin LCD_data\[6\] uses I/O standard 3.3-V LVTTL at M3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[6\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 358 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[7\] 3.3-V LVTTL M5 " "Pin LCD_data\[7\] uses I/O standard 3.3-V LVTTL at M5" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[7\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 359 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL Y2 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 360 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609324401 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1480609324401 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480609325076 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 830 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 830 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1010 " "Peak virtual memory: 1010 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:07 2016 " "Processing ended: Fri Dec 02 01:22:07 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609327596 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480609327596 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480609328752 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609328752 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:22:08 2016 " "Processing started: Fri Dec 02 01:22:08 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609328752 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480609328752 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480609328752 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1480609334141 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480609334300 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "481 " "Peak virtual memory: 481 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:16 2016 " "Processing ended: Fri Dec 02 01:22:16 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609336088 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480609336088 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480609336795 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480609337278 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:22:16 2016 " "Processing started: Fri Dec 02 01:22:16 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta lights -c lights " "Command: quartus_sta lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1480609337279 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1480609337369 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1480609337763 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337763 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337851 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480609337851 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609338651 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1480609338651 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1480609338693 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609338703 "|lights|CLOCK_50"} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609339290 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609339290 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1480609339291 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1480609339369 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.773 " "Worst-case setup slack is 46.773" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 46.773 0.000 altera_reserved_tck " " 46.773 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339398 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.402 " "Worst-case hold slack is 0.402" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.402 0.000 altera_reserved_tck " " 0.402 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339405 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.354 " "Worst-case recovery slack is 47.354" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.354 0.000 altera_reserved_tck " " 47.354 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339415 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.459 " "Worst-case removal slack is 1.459" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.459 0.000 altera_reserved_tck " " 1.459 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339424 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.549 " "Worst-case minimum pulse width slack is 49.549" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.549 0.000 altera_reserved_tck " " 49.549 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609339433 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.086 ns " "Worst Case Available Settling Time: 197.086 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609339570 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1480609339584 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1480609339634 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1480609341036 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609341383 "|lights|CLOCK_50"} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609341393 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609341393 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.135 " "Worst-case setup slack is 47.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.135 0.000 altera_reserved_tck " " 47.135 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341447 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.354 " "Worst-case hold slack is 0.354" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.354 0.000 altera_reserved_tck " " 0.354 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341634 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.646 " "Worst-case recovery slack is 47.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.646 0.000 altera_reserved_tck " " 47.646 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341651 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.333 " "Worst-case removal slack is 1.333" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.333 0.000 altera_reserved_tck " " 1.333 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341661 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.477 " "Worst-case minimum pulse width slack is 49.477" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.477 0.000 altera_reserved_tck " " 49.477 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609341670 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.373 ns " "Worst Case Available Settling Time: 197.373 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609341783 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1480609341798 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480609342233 "|lights|CLOCK_50"} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609342245 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480609342245 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.795 " "Worst-case setup slack is 48.795" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.795 0.000 altera_reserved_tck " " 48.795 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342295 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 altera_reserved_tck " " 0.179 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342310 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.990 " "Worst-case recovery slack is 48.990" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.990 0.000 altera_reserved_tck " " 48.990 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342347 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.677 " "Worst-case removal slack is 0.677" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.677 0.000 altera_reserved_tck " " 0.677 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342359 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.299 " "Worst-case minimum pulse width slack is 49.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.299 0.000 altera_reserved_tck " " 49.299 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480609342403 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.609 ns " "Worst Case Available Settling Time: 198.609 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480609342540 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1480609344179 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1480609344179 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "603 " "Peak virtual memory: 603 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:22:24 2016 " "Processing ended: Fri Dec 02 01:22:24 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609344470 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 997 s " "Quartus II Full Compilation was successful. 0 errors, 997 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609345332 ""} diff --git a/db/scfifo_jr21.tdf b/db/scfifo_jr21.tdf index a19d155..3e1d114 100644 --- a/db/scfifo_jr21.tdf +++ b/db/scfifo_jr21.tdf @@ -1,53 +1,53 @@ ---scfifo DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTHU=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" ---VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END - - --- Copyright (C) 1991-2013 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - -FUNCTION a_dpfifo_q131 (aclr, clock, data[7..0], rreq, sclr, wreq) -RETURNS ( empty, full, q[7..0], usedw[5..0]); - ---synthesis_resources = lut 18 M9K 1 reg 20 -SUBDESIGN scfifo_jr21 -( - aclr : input; - clock : input; - data[7..0] : input; - empty : output; - full : output; - q[7..0] : output; - rdreq : input; - usedw[5..0] : output; - wrreq : input; -) -VARIABLE - dpfifo : a_dpfifo_q131; - sclr : NODE; - -BEGIN - dpfifo.aclr = aclr; - dpfifo.clock = clock; - dpfifo.data[] = data[]; - dpfifo.rreq = rdreq; - dpfifo.sclr = sclr; - dpfifo.wreq = wrreq; - empty = dpfifo.empty; - full = dpfifo.full; - q[] = dpfifo.q[]; - sclr = GND; - usedw[] = dpfifo.usedw[]; -END; ---VALID FILE +--scfifo DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTHU=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" +--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION a_dpfifo_q131 (aclr, clock, data[7..0], rreq, sclr, wreq) +RETURNS ( empty, full, q[7..0], usedw[5..0]); + +--synthesis_resources = lut 18 M9K 1 reg 20 +SUBDESIGN scfifo_jr21 +( + aclr : input; + clock : input; + data[7..0] : input; + empty : output; + full : output; + q[7..0] : output; + rdreq : input; + usedw[5..0] : output; + wrreq : input; +) +VARIABLE + dpfifo : a_dpfifo_q131; + sclr : NODE; + +BEGIN + dpfifo.aclr = aclr; + dpfifo.clock = clock; + dpfifo.data[] = data[]; + dpfifo.rreq = rdreq; + dpfifo.sclr = sclr; + dpfifo.wreq = wrreq; + empty = dpfifo.empty; + full = dpfifo.full; + q[] = dpfifo.q[]; + sclr = GND; + usedw[] = dpfifo.usedw[]; +END; +--VALID FILE diff --git a/incremental_db/README b/incremental_db/README index 9f62dcd..6191fbe 100644 --- a/incremental_db/README +++ b/incremental_db/README @@ -1,11 +1,11 @@ -This folder contains data for incremental compilation. - -The compiled_partitions sub-folder contains previous compilation results for each partition. -As long as this folder is preserved, incremental compilation results from earlier compiles -can be re-used. To perform a clean compilation from source files for all partitions, both -the db and incremental_db folder should be removed. - -The imported_partitions sub-folder contains the last imported QXP for each imported partition. -As long as this folder is preserved, imported partitions will be automatically re-imported -when the db or incremental_db/compiled_partitions folders are removed. - +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/incremental_db/compiled_partitions/lights.db_info b/incremental_db/compiled_partitions/lights.db_info index b613d1f..7461abf 100644 --- a/incremental_db/compiled_partitions/lights.db_info +++ b/incremental_db/compiled_partitions/lights.db_info @@ -1,3 +1,3 @@ -Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -Version_Index = 302049280 -Creation_Time = Thu Oct 20 11:14:55 2016 +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Thu Oct 20 11:14:55 2016 diff --git a/lights.bak b/lights.bak index 8468f0c..c7c3a5b 100644 --- a/lights.bak +++ b/lights.bak @@ -1,10 +1,10 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -entity lights is port ( - CLOCK_50 : in std_logic; - KEY : in std_logic_vector(0 downto 0); - SW : in std_logic_vector(7 downto 0); - LEDG : out std_logic_vector(7 downto 0) -); +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity lights is port ( + CLOCK_50 : in std_logic; + KEY : in std_logic_vector(0 downto 0); + SW : in std_logic_vector(7 downto 0); + LEDG : out std_logic_vector(7 downto 0) +); end lights; \ No newline at end of file diff --git a/lights.qpf b/lights.qpf index 1dc6e02..b0e80dc 100644 --- a/lights.qpf +++ b/lights.qpf @@ -1,30 +1,30 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 15:50:27 October 13, 2016 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.0" -DATE = "15:50:27 October 13, 2016" - -# Revisions - -PROJECT_REVISION = "lights" +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:50:27 October 13, 2016 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "15:50:27 October 13, 2016" + +# Revisions + +PROJECT_REVISION = "lights" diff --git a/lights.qsf.bak b/lights.qsf.bak index 845b2e1..2ad331f 100644 --- a/lights.qsf.bak +++ b/lights.qsf.bak @@ -1,56 +1,56 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 15:50:27 October 13, 2016 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# lights_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name TOP_LEVEL_ENTITY lights -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:50:27 OCTOBER 13, 2016" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name QSYS_FILE nios_system.qsys -set_global_assignment -name SOURCE_FILE nios_system.cmp +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:50:27 October 13, 2016 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# lights_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY lights +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:50:27 OCTOBER 13, 2016" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name QSYS_FILE nios_system.qsys +set_global_assignment -name SOURCE_FILE nios_system.cmp set_global_assignment -name VHDL_FILE lights.vhd \ No newline at end of file diff --git a/lights.vhd b/lights.vhd index 183d486..83a1bb7 100644 --- a/lights.vhd +++ b/lights.vhd @@ -1,76 +1,76 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -entity lights is port ( - CLOCK_50 : in std_logic; - KEY : in std_logic_vector(3 downto 0); - SW : in std_logic_vector(17 downto 0); - LEDG : out std_logic_vector(7 downto 0); - LEDR : out std_logic_vector(17 downto 0); - HEX0 : out std_logic_vector(6 downto 0); - HEX1 : out std_logic_vector(6 downto 0); - HEX2 : out std_logic_vector(6 downto 0); - HEX3 : out std_logic_vector(6 downto 0); - HEX4 : out std_logic_vector(6 downto 0); - HEX5 : out std_logic_vector(6 downto 0); - HEX6 : out std_logic_vector(6 downto 0); - HEX7 : out std_logic_vector(6 downto 0); - LCD_RS : out std_logic; - LCD_RW : out std_logic; - LCD_data : out std_logic_vector(7 downto 0); - LCD_EN : out std_logic; - LCD_ON : out std_logic; - LCD_BLON : out std_logic -); -end lights; - -architecture lights_rtl of lights is - component nios_system - port ( - signal clk_clk : in std_logic; - signal reset_reset_n : in std_logic; - signal switches_export : in std_logic_vector(17 downto 0); - signal push_switches_export : in std_logic_vector(2 downto 0); - signal leds_export : out std_logic_vector(7 downto 0); - signal ledrs_export : out std_logic_vector(17 downto 0); - signal hex0_export : out std_logic_vector(6 downto 0); - signal hex1_export : out std_logic_vector(6 downto 0); - signal hex2_export : out std_logic_vector(6 downto 0); - signal hex3_export : out std_logic_vector(6 downto 0); - signal hex4_export : out std_logic_vector(6 downto 0); - signal hex5_export : out std_logic_vector(6 downto 0); - signal hex6_export : out std_logic_vector(6 downto 0); - signal hex7_export : out std_logic_vector(6 downto 0); - signal lcd_16207_0_RS : out std_logic; - signal lcd_16207_0_RW : out std_logic; - signal lcd_16207_0_data : out std_logic_vector(7 downto 0); - signal lcd_16207_0_E : out std_logic; - signal lcd_on_export : out std_logic; - signal lcd_blon_export : out std_logic - ); - end component; -begin - NiosII : nios_system - port map ( - clk_clk => CLOCK_50, - reset_reset_n => KEY(0), - switches_export => SW(17 downto 0), - push_switches_export => KEY(3 downto 1), - leds_export => LEDG(7 downto 0), - ledrs_export => LEDR(17 downto 0), - hex0_export => HEX0(6 downto 0), - hex1_export => HEX1(6 downto 0), - hex2_export => HEX2(6 downto 0), - hex3_export => HEX3(6 downto 0), - hex4_export => HEX4(6 downto 0), - hex5_export => HEX5(6 downto 0), - hex6_export => HEX6(6 downto 0), - hex7_export => HEX7(6 downto 0), - lcd_16207_0_RS => LCD_RS, - lcd_16207_0_RW => LCD_RW, - lcd_16207_0_data => LCD_DATA, - lcd_16207_0_E => LCD_EN, - lcd_on_export => LCD_ON, - lcd_blon_export => LCD_BLON - ); +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity lights is port ( + CLOCK_50 : in std_logic; + KEY : in std_logic_vector(3 downto 0); + SW : in std_logic_vector(17 downto 0); + LEDG : out std_logic_vector(7 downto 0); + LEDR : out std_logic_vector(17 downto 0); + HEX0 : out std_logic_vector(6 downto 0); + HEX1 : out std_logic_vector(6 downto 0); + HEX2 : out std_logic_vector(6 downto 0); + HEX3 : out std_logic_vector(6 downto 0); + HEX4 : out std_logic_vector(6 downto 0); + HEX5 : out std_logic_vector(6 downto 0); + HEX6 : out std_logic_vector(6 downto 0); + HEX7 : out std_logic_vector(6 downto 0); + LCD_RS : out std_logic; + LCD_RW : out std_logic; + LCD_data : out std_logic_vector(7 downto 0); + LCD_EN : out std_logic; + LCD_ON : out std_logic; + LCD_BLON : out std_logic +); +end lights; + +architecture lights_rtl of lights is + component nios_system + port ( + signal clk_clk : in std_logic; + signal reset_reset_n : in std_logic; + signal switches_export : in std_logic_vector(17 downto 0); + signal push_switches_export : in std_logic_vector(2 downto 0); + signal leds_export : out std_logic_vector(7 downto 0); + signal ledrs_export : out std_logic_vector(17 downto 0); + signal hex0_export : out std_logic_vector(6 downto 0); + signal hex1_export : out std_logic_vector(6 downto 0); + signal hex2_export : out std_logic_vector(6 downto 0); + signal hex3_export : out std_logic_vector(6 downto 0); + signal hex4_export : out std_logic_vector(6 downto 0); + signal hex5_export : out std_logic_vector(6 downto 0); + signal hex6_export : out std_logic_vector(6 downto 0); + signal hex7_export : out std_logic_vector(6 downto 0); + signal lcd_16207_0_RS : out std_logic; + signal lcd_16207_0_RW : out std_logic; + signal lcd_16207_0_data : out std_logic_vector(7 downto 0); + signal lcd_16207_0_E : out std_logic; + signal lcd_on_export : out std_logic; + signal lcd_blon_export : out std_logic + ); + end component; +begin + NiosII : nios_system + port map ( + clk_clk => CLOCK_50, + reset_reset_n => KEY(0), + switches_export => SW(17 downto 0), + push_switches_export => KEY(3 downto 1), + leds_export => LEDG(7 downto 0), + ledrs_export => LEDR(17 downto 0), + hex0_export => HEX0(6 downto 0), + hex1_export => HEX1(6 downto 0), + hex2_export => HEX2(6 downto 0), + hex3_export => HEX3(6 downto 0), + hex4_export => HEX4(6 downto 0), + hex5_export => HEX5(6 downto 0), + hex6_export => HEX6(6 downto 0), + hex7_export => HEX7(6 downto 0), + lcd_16207_0_RS => LCD_RS, + lcd_16207_0_RW => LCD_RW, + lcd_16207_0_data => LCD_DATA, + lcd_16207_0_E => LCD_EN, + lcd_on_export => LCD_ON, + lcd_blon_export => LCD_BLON + ); end lights_rtl; \ No newline at end of file diff --git a/lights.vhd.bak b/lights.vhd.bak index 96fea4b..f3d0373 100644 --- a/lights.vhd.bak +++ b/lights.vhd.bak @@ -1,29 +1,29 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; -entity lights is port ( - CLOCK_50 : in std_logic; - KEY : in std_logic_vector(0 downto 0); - SW : in std_logic_vector(7 downto 0); - LEDG : out std_logic_vector(7 downto 0) -); -end lights; - -architecture lights_rtl of lights is - component nios_system - port ( - signal clk_clk : in std_logic; - signal reset_reset_n : in std_logic; - signal switches_export : in std_logic_vector(7 downto 0); - signal leds_export : out std_logic_vector(7 downto 0) - ); - end component; -begin - NiosII : nios_system - port map ( - clk_clk => CLOCK_50, - reset_reset_n => KEY(0), - switches_export => SW(7 downto 0), - leds_export => LEDG(7 downto 0) - ); +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; +entity lights is port ( + CLOCK_50 : in std_logic; + KEY : in std_logic_vector(0 downto 0); + SW : in std_logic_vector(7 downto 0); + LEDG : out std_logic_vector(7 downto 0) +); +end lights; + +architecture lights_rtl of lights is + component nios_system + port ( + signal clk_clk : in std_logic; + signal reset_reset_n : in std_logic; + signal switches_export : in std_logic_vector(7 downto 0); + signal leds_export : out std_logic_vector(7 downto 0) + ); + end component; +begin + NiosII : nios_system + port map ( + clk_clk => CLOCK_50, + reset_reset_n => KEY(0), + switches_export => SW(7 downto 0), + leds_export => LEDG(7 downto 0) + ); end lights_rtl \ No newline at end of file diff --git a/nios_system.bsf b/nios_system.bsf deleted file mode 100644 index dac37b1..0000000 --- a/nios_system.bsf +++ /dev/null @@ -1,248 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 384 792) - (text "nios_system" (rect 155 -1 206 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 776 20 788)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) - (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 160 72)(line_width 1)) - ) - (port - (pt 0 152) - (input) - (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) - (text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8))) - (line (pt 0 152)(pt 160 152)(line_width 1)) - ) - (port - (pt 0 232) - (input) - (text "switches_export[17..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) - (text "switches_export[17..0]" (rect 4 221 136 232)(font "Arial" (font_size 8))) - (line (pt 0 232)(pt 160 232)(line_width 3)) - ) - (port - (pt 0 272) - (input) - (text "push_switches_export[2..0]" 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532)(pt 162 556)(line_width 1)) - (line (pt 161 572)(pt 161 596)(line_width 1)) - (line (pt 162 572)(pt 162 596)(line_width 1)) - (line (pt 161 612)(pt 161 684)(line_width 1)) - (line (pt 162 612)(pt 162 684)(line_width 1)) - (line (pt 161 700)(pt 161 724)(line_width 1)) - (line (pt 162 700)(pt 162 724)(line_width 1)) - (line (pt 161 740)(pt 161 764)(line_width 1)) - (line (pt 162 740)(pt 162 764)(line_width 1)) - (line (pt 160 32)(pt 224 32)(line_width 1)) - (line (pt 224 32)(pt 224 776)(line_width 1)) - (line (pt 160 776)(pt 224 776)(line_width 1)) - (line (pt 160 32)(pt 160 776)(line_width 1)) - (line (pt 0 0)(pt 384 0)(line_width 1)) - (line (pt 384 0)(pt 384 792)(line_width 1)) - (line (pt 0 792)(pt 384 792)(line_width 1)) - (line (pt 0 0)(pt 0 792)(line_width 1)) - ) -) diff --git a/nios_system.cmp b/nios_system.cmp deleted file mode 100644 index e214a8c..0000000 --- a/nios_system.cmp +++ /dev/null @@ -1,25 +0,0 @@ - component nios_system is - port ( - clk_clk : in std_logic := 'X'; -- clk - leds_export : out std_logic_vector(7 downto 0); -- export - reset_reset_n : in std_logic := 'X'; -- reset_n - ledrs_export : out std_logic_vector(17 downto 0); -- export - switches_export : in std_logic_vector(17 downto 0) := (others => 'X'); -- export - push_switches_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export - hex0_export : out std_logic_vector(6 downto 0); -- export - hex1_export : out std_logic_vector(6 downto 0); -- export - hex2_export : out std_logic_vector(6 downto 0); -- export - hex3_export : out std_logic_vector(6 downto 0); -- export - hex4_export : out std_logic_vector(6 downto 0); -- export - hex5_export : out std_logic_vector(6 downto 0); -- export - hex6_export : out std_logic_vector(6 downto 0); -- export - hex7_export : out std_logic_vector(6 downto 0); -- export - lcd_16207_0_RS : out std_logic; -- RS - lcd_16207_0_RW : out std_logic; -- RW - lcd_16207_0_data : inout std_logic_vector(7 downto 0) := (others => 'X'); -- data - lcd_16207_0_E : out std_logic; -- E - lcd_on_export : out std_logic; -- export - lcd_blon_export : out std_logic -- export - ); - end component nios_system; - diff --git a/nios_system.qsys b/nios_system.qsys index 38384f0..da73ace 100644 --- a/nios_system.qsys +++ b/nios_system.qsys @@ -7,393 +7,393 @@ description="" tags="" categories="System" /> - diff --git a/nios_system.sopcinfo b/nios_system.sopcinfo deleted file mode 100644 index 100a9b4..0000000 --- a/nios_system.sopcinfo +++ /dev/null @@ -1,18218 +0,0 @@ - - - - - - - java.lang.Integer - 1482368837 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - CYCLONEIVE - false - true - false - true - - - java.lang.String - EP4CE115F29C7 - false - true - false - true - - - java.lang.Long - -1 - false - true - false - true - - - java.lang.Integer - -1 - false - true - false - true - - - java.lang.Integer - -1 - false - true - false - true - - - java.lang.String - Cyclone IV E - false - true - false - true - - - boolean - false - false - true - true - true - - - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - long - 0 - false - true - false - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - qsys.ui.export_name - clk - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - in_clk - Input - 1 - clk - - - - - - qsys.ui.export_name - reset - - - java.lang.String - - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - java.lang.String - clk_in - false - true - true - true - - - long - 50000000 - false - true - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - true - - clk_out - Output - 1 - clk - - - false - nios2_processor - clk - nios2_processor.clk - - - false - onchip_memory - clk1 - onchip_memory.clk1 - - - false - jtag_uart - clk - jtag_uart.clk - - - false - LEDs - clk - LEDs.clk - - - false - LEDRs - clk - LEDRs.clk - - - false - switches - clk - switches.clk - - - false - push_switches - clk - push_switches.clk - - - false - hex0 - clk - hex0.clk - - - false - hex1 - clk - hex1.clk - - - false - hex2 - clk - hex2.clk - - - false - hex3 - clk - hex3.clk - - - false - hex4 - clk - hex4.clk - - - false - hex5 - clk - hex5.clk - - - false - hex6 - clk - hex6.clk - - - false - hex7 - clk - hex7.clk - - - false - lcd_16207_0 - clk - lcd_16207_0.clk - - - false - lcd_on - clk - lcd_on.clk - - - false - lcd_blon - clk - lcd_blon.clk - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - clk_in_reset - false - true - true - true - - - [Ljava.lang.String; - clk_in_reset - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - NONE - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - reset_n_out - Output - 1 - reset_n - - - - - - - debug.hostConnection - type jtag id 70:34|110:135 - - - embeddedsw.CMacro.BIG_ENDIAN - 0 - - - embeddedsw.CMacro.BREAK_ADDR - 0x00040820 - - - embeddedsw.CMacro.CPU_FREQ - 50000000u - - - embeddedsw.CMacro.CPU_ID_SIZE - 1 - - - embeddedsw.CMacro.CPU_ID_VALUE - 0x00000000 - - - embeddedsw.CMacro.CPU_IMPLEMENTATION - "tiny" - - - embeddedsw.CMacro.DATA_ADDR_WIDTH - 19 - - - embeddedsw.CMacro.DCACHE_LINE_SIZE - 0 - - - embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 - 0 - - - embeddedsw.CMacro.DCACHE_SIZE - 0 - - - embeddedsw.CMacro.EXCEPTION_ADDR - 0x00000020 - - - embeddedsw.CMacro.FLUSHDA_SUPPORTED - - - - embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT - 0 - - - embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT - 0 - - - embeddedsw.CMacro.HARDWARE_MULX_PRESENT - 0 - - - embeddedsw.CMacro.HAS_DEBUG_CORE - 1 - - - embeddedsw.CMacro.HAS_DEBUG_STUB - - - - embeddedsw.CMacro.HAS_JMPI_INSTRUCTION - - - - embeddedsw.CMacro.ICACHE_LINE_SIZE - 0 - - - embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 - 0 - - - embeddedsw.CMacro.ICACHE_SIZE - 0 - - - embeddedsw.CMacro.INST_ADDR_WIDTH - 19 - - - embeddedsw.CMacro.RESET_ADDR - 0x00000000 - - - embeddedsw.configuration.HDLSimCachesCleared - 1 - - - embeddedsw.configuration.breakOffset - 32 - - - embeddedsw.configuration.breakSlave - nios2_processor.jtag_debug_module - - - embeddedsw.configuration.cpuArchitecture - Nios II - - - embeddedsw.configuration.exceptionOffset - 32 - - - embeddedsw.configuration.exceptionSlave - onchip_memory.s1 - - - embeddedsw.configuration.resetOffset - 0 - - - embeddedsw.configuration.resetSlave - onchip_memory.s1 - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - true - false - false - true - true - - - boolean - true - false - true - true - true - - - boolean - true - false - true - false - true - - - boolean - true - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 8 - false - false - true - true - - - int - 8 - false - false - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 32 - false - true - true - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 32 - false - false - true - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - onchip_memory.s1 - false - true - true - true - - - java.lang.String - None - false - false - true - true - - - java.lang.String - onchip_memory.s1 - false - true - true - true - - - java.lang.String - nios2_processor.jtag_debug_module - false - false - true - true - - - int - 32 - false - true - false - true - - - java.lang.String - Internal - false - false - true - true - - - java.lang.String - Automatic - false - true - false - true - - - int - 8 - false - true - false - true - - - java.lang.String - EmbeddedMulFast - false - false - true - true - - - int - 12 - false - false - true - true - - - int - 12 - false - false - true - true - - - int - 4 - false - false - true - true - - - int - 6 - false - false - true - true - - - int - 7 - false - false - true - true - - - int - 16 - false - false - true - true - - - int - 8 - false - false - true - true - - - java.lang.String - Tiny - false - true - true - true - - - int - 4096 - false - false - true - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - None - false - false - true - true - - - java.lang.String - false - false - false - true - true - - - java.lang.String - ram - false - false - true - true - - - java.lang.String - Level1 - false - true - true - true - - - java.lang.String - _128 - false - false - true - true - - - int - 2048 - false - false - true - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - int - 0 - false - false - true - true - - - int - 32 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - java.lang.String - Automatic - false - true - false - true - - - int - 0 - true - true - true - true - - - int - 32 - true - true - true - true - - - int - 264224 - true - true - true - true - - - int - 0 - true - true - true - true - - - java.lang.String - false - true - true - false - true - - - int - 2048 - true - true - false - true - - - int - 32 - true - true - false - true - - - java.lang.String - "synthesis translate_on" - true - true - false - true - - - java.lang.String - "synthesis translate_off" - true - true - false - true - - - int - 19 - false - true - false - true - - - int - 19 - false - true - false - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - false - true - - - java.lang.String - ]]> - false - true - false - true - - - java.lang.String - ]]> - false - true - false - true - - - long - 50000000 - false - true - false - true - - - java.lang.String - CYCLONEIVE - false - true - false - true - - - long - 32 - false - true - false - true - - - java.lang.String - ]]> - false - true - false - true - - - java.lang.String - ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - debug.providesServices - master - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 1 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset_n - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - true - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - d_address - Output - 19 - address - - - d_byteenable - Output - 4 - byteenable - - - d_read - Output - 1 - read - - - d_readdata - Input - 32 - readdata - - - d_waitrequest - Input - 1 - waitrequest - - - d_write - Output - 1 - write - - - d_writedata - Output - 32 - writedata - - - jtag_debug_module_debugaccess_to_roms - Output - 1 - debugaccess - - - false - nios2_processor - jtag_debug_module - nios2_processor.jtag_debug_module - 264192 - 2048 - - - false - onchip_memory - s1 - onchip_memory.s1 - 0 - 204800 - - - false - LEDs - s1 - LEDs.s1 - 266480 - 16 - - - false - jtag_uart - avalon_jtag_slave - jtag_uart.avalon_jtag_slave - 266496 - 8 - - - false - LEDRs - s1 - LEDRs.s1 - 266464 - 16 - - - false - switches - s1 - switches.s1 - 266448 - 16 - - - false - push_switches - s1 - push_switches.s1 - 266432 - 16 - - - false - hex0 - s1 - hex0.s1 - 266416 - 16 - - - false - hex1 - s1 - hex1.s1 - 266400 - 16 - - - false - hex2 - s1 - hex2.s1 - 266384 - 16 - - - false - hex3 - s1 - hex3.s1 - 266368 - 16 - - - false - hex4 - s1 - hex4.s1 - 266352 - 16 - - - false - hex5 - s1 - hex5.s1 - 266336 - 16 - - - false - hex6 - s1 - hex6.s1 - 266320 - 16 - - - false - hex7 - s1 - hex7.s1 - 266304 - 16 - - - false - lcd_16207_0 - control_slave - lcd_16207_0.control_slave - 266288 - 16 - - - false - lcd_on - s1 - lcd_on.s1 - 266256 - 16 - - - false - lcd_blon - s1 - lcd_blon.s1 - 266272 - 16 - - - - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - int - 1 - false - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - SYMBOLS - false - true - true - true - - - boolean - true - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset_n - false - true - true - true - - - int - 8 - false - true - true - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - true - true - - - int - 32 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - true - - i_address - Output - 19 - address - - - i_read - Output - 1 - read - - - i_readdata - Input - 32 - readdata - - - i_waitrequest - Input - 1 - waitrequest - - - false - nios2_processor - jtag_debug_module - nios2_processor.jtag_debug_module - 264192 - 2048 - - - false - onchip_memory - s1 - onchip_memory.s1 - 0 - 204800 - - - - - - com.altera.entityinterfaces.IConnectionPoint - nios2_processor.data_master - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset_n - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - INDIVIDUAL_REQUESTS - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - true - - d_irq - Input - 32 - irq - - - false - jtag_uart - irq - jtag_uart.irq - 5 - - - - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - - false - true - true - true - - - [Ljava.lang.String; - none - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - true - - jtag_debug_module_resetrequest - Output - 1 - reset - - - - - - embeddedsw.configuration.hideDevice - 1 - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - qsys.ui.connect - instruction_master,data_master - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 2048 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset_n - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - false - true - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - jtag_debug_module_address - Input - 9 - address - - - jtag_debug_module_byteenable - Input - 4 - byteenable - - - jtag_debug_module_debugaccess - Input - 1 - debugaccess - - - jtag_debug_module_read - Input - 1 - read - - - jtag_debug_module_readdata - Output - 32 - readdata - - - jtag_debug_module_waitrequest - Output - 1 - waitrequest - - - jtag_debug_module_write - Input - 1 - write - - - jtag_debug_module_writedata - Input - 32 - writedata - - - - - - java.lang.String - - true - true - false - true - - - int - 8 - false - true - false - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - int - 8 - false - true - false - true - - - int - 0 - true - true - false - true - - - boolean - false - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios_custom_instruction - true - - no_ci_readra - Output - 1 - readra - - - - - - - embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR - 0 - - - embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE - 0 - - - embeddedsw.CMacro.CONTENTS_INFO - "" - - - embeddedsw.CMacro.DUAL_PORT - 0 - - - embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE - AUTO - - - embeddedsw.CMacro.INIT_CONTENTS_FILE - nios_system_onchip_memory - - - embeddedsw.CMacro.INIT_MEM_CONTENT - 1 - - - embeddedsw.CMacro.INSTANCE_ID - NONE - - - embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED - 0 - - - embeddedsw.CMacro.RAM_BLOCK_TYPE - AUTO - - - embeddedsw.CMacro.READ_DURING_WRITE_MODE - DONT_CARE - - - embeddedsw.CMacro.SINGLE_CLOCK_OP - 0 - - - embeddedsw.CMacro.SIZE_MULTIPLE - 1 - - - embeddedsw.CMacro.SIZE_VALUE - 204800 - - - embeddedsw.CMacro.WRITABLE - 1 - - - embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR - SIM_DIR - - - embeddedsw.memoryInfo.GENERATE_DAT_SYM - 1 - - - embeddedsw.memoryInfo.GENERATE_HEX - 1 - - - embeddedsw.memoryInfo.HAS_BYTE_LANE - 0 - - - embeddedsw.memoryInfo.HEX_INSTALL_DIR - QPF_DIR - - - embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH - 32 - - - embeddedsw.memoryInfo.MEM_INIT_FILENAME - nios_system_onchip_memory - - - postgeneration.simulation.init_file.param_name - INIT_FILE - - - postgeneration.simulation.init_file.type - MEM_INIT - - - boolean - false - false - true - true - true - - - java.lang.String - AUTO - false - true - true - true - - - int - 32 - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - onchip_mem.hex - false - false - true - true - - - java.lang.String - NONE - false - false - true - true - - - long - 204800 - false - true - true - true - - - java.lang.String - DONT_CARE - false - false - true - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - boolean - false - false - false - true - true - - - int - 1 - false - true - true - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - boolean - true - false - true - true - true - - - java.lang.String - nios_system_onchip_memory - false - true - false - true - - - java.lang.String - CYCLONEIVE - false - true - false - true - - - java.lang.String - ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 - false - true - false - true - - - int - 16 - true - true - false - true - - - java.lang.String - Automatic - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - nios_system_onchip_memory.hex - true - true - false - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 1 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - DYNAMIC - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 204800 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk1 - false - true - true - true - - - java.lang.String - reset1 - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 204800 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - true - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 1 - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 16 - address - - - clken - Input - 1 - clken - - - chipselect - Input - 1 - chipselect - - - write - Input - 1 - write - - - readdata - Output - 32 - readdata - - - writedata - Input - 32 - writedata - - - byteenable - Input - 4 - byteenable - - - - - - java.lang.String - clk1 - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset - Input - 1 - reset - - - reset_req - Input - 1 - reset_req - - - - - - - embeddedsw.CMacro.READ_DEPTH - 64 - - - embeddedsw.CMacro.READ_THRESHOLD - 8 - - - embeddedsw.CMacro.WRITE_DEPTH - 64 - - - embeddedsw.CMacro.WRITE_THRESHOLD - 8 - - - boolean - false - false - true - true - true - - - int - 0 - false - true - false - true - - - int - 64 - false - true - true - true - - - int - 8 - false - true - true - true - - - java.lang.String - - false - false - false - true - - - java.lang.String - NO_INTERACTIVE_WINDOWS - false - true - false - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - true - false - true - - - int - 64 - false - true - true - true - - - int - 8 - false - true - true - true - - - java.lang.String - 2.0 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - rst_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 1 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 2 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - false - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - false - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - false - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - av_chipselect - Input - 1 - chipselect - - - av_address - Input - 1 - address - - - av_read_n - Input - 1 - read_n - - - av_readdata - Output - 32 - readdata - - - av_write_n - Input - 1 - write_n - - - av_writedata - Input - 32 - writedata - - - av_waitrequest - Output - 1 - waitrequest - - - - - - com.altera.entityinterfaces.IConnectionPoint - jtag_uart.avalon_jtag_slave - false - true - true - true - - - java.lang.String - clk - false - true - false - true - - - java.lang.String - reset - false - true - false - true - - - com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme - NONE - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - interrupt - false - - av_irq - Output - 1 - irq - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 8 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 8 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 8 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 18 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 18 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 18 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 18 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 1 - - - embeddedsw.CMacro.HAS_OUT - 0 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - Input - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - false - true - true - - - boolean - false - false - true - true - true - - - long - 0 - false - false - true - true - - - int - 18 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_port - Input - 18 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 3 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 1 - - - embeddedsw.CMacro.HAS_OUT - 0 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - Input - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - false - true - true - - - boolean - false - false - true - true - true - - - long - 0 - false - false - true - true - - - int - 3 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - in_port - Input - 3 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 7 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 7 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 7 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 7 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 7 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 7 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 7 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 7 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 7 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 7 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 7 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 7 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 7 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 7 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 7 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 7 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 7 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 7 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 7 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 7 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 7 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 7 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 7 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 7 - export - - - - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clock - false - - clk - Input - 1 - clk - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 1 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 250 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - true - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 250 - false - true - false - true - - - int - 250 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 250 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Nanoseconds - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 250 - false - true - false - true - - - int - 250 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - begintransfer - Input - 1 - begintransfer - - - read - Input - 1 - read - - - write - Input - 1 - write - - - readdata - Output - 8 - readdata - - - writedata - Input - 8 - writedata - - - address - Input - 2 - address - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - LCD_RS - Output - 1 - export - - - LCD_RW - Output - 1 - export - - - LCD_data - Bidir - 8 - export - - - LCD_E - Output - 1 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 1 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 1 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 1 - export - - - - - - - embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER - 0 - - - embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER - 0 - - - embeddedsw.CMacro.CAPTURE - 0 - - - embeddedsw.CMacro.DATA_WIDTH - 1 - - - embeddedsw.CMacro.DO_TEST_BENCH_WIRING - 0 - - - embeddedsw.CMacro.DRIVEN_SIM_VALUE - 0 - - - embeddedsw.CMacro.EDGE_TYPE - NONE - - - embeddedsw.CMacro.FREQ - 50000000 - - - embeddedsw.CMacro.HAS_IN - 0 - - - embeddedsw.CMacro.HAS_OUT - 1 - - - embeddedsw.CMacro.HAS_TRI - 0 - - - embeddedsw.CMacro.IRQ_TYPE - NONE - - - embeddedsw.CMacro.RESET_VALUE - 0 - - - embeddedsw.dts.compatible - altr,pio-1.0 - - - boolean - false - false - false - true - true - - - boolean - false - false - true - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - Output - false - true - true - true - - - java.lang.String - RISING - false - false - true - true - - - boolean - false - false - false - true - true - - - java.lang.String - LEVEL - false - false - true - true - - - long - 0 - false - true - true - true - - - boolean - false - false - false - true - true - - - long - 0 - false - false - true - true - - - int - 1 - false - true - true - true - - - long - 50000000 - false - true - false - true - - - boolean - false - true - true - false - true - - - boolean - true - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - java.lang.String - NONE - true - true - false - true - - - boolean - false - true - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - - - boolean - false - false - true - false - true - - - java.lang.String - - false - true - false - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.Boolean - true - true - true - false - true - - - java.lang.Long - 50000000 - true - true - false - true - - clock - false - - clk - Input - 1 - clk - - - - - - java.lang.String - clk - false - true - true - true - - - com.altera.sopcmodel.reset.Reset$Edges - DEASSERT - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - reset - false - - reset_n - Input - 1 - reset_n - - - - - - embeddedsw.configuration.isFlash - 0 - - - embeddedsw.configuration.isMemoryDevice - 0 - - - embeddedsw.configuration.isNonVolatileStorage - 0 - - - embeddedsw.configuration.isPrintableDevice - 0 - - - com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment - NATIVE - false - true - false - true - - - int - 0 - false - true - false - true - - - java.math.BigInteger - 4 - true - true - false - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.lang.String - clk - false - true - true - true - - - java.lang.String - reset - false - true - true - true - - - int - 8 - false - true - true - true - - - com.altera.entityinterfaces.IConnectionPoint - - false - true - false - true - - - boolean - false - false - true - true - true - - - com.altera.sopcmodel.avalon.EAddrBurstUnits - WORDS - false - true - true - true - - - boolean - false - false - true - false - true - - - java.math.BigInteger - 0 - false - true - true - true - - - int - 0 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - true - true - - - int - 0 - false - false - true - true - - - int - 0 - false - false - false - true - - - int - 1 - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - int - 1 - false - true - false - true - - - int - 1 - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - true - true - - - com.altera.sopcmodel.avalon.TimingUnits - Cycles - false - true - true - true - - - boolean - false - false - true - false - true - - - boolean - false - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - false - true - - - int - 0 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - avalon - false - - address - Input - 2 - address - - - write_n - Input - 1 - write_n - - - writedata - Input - 32 - writedata - - - chipselect - Input - 1 - chipselect - - - readdata - Output - 32 - readdata - - - - - - java.lang.String - - false - true - true - true - - - java.lang.String - - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - conduit - false - - out_port - Output - 1 - export - - - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00040800 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - instruction_master - nios2_processor - jtag_debug_module - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00040800 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - nios2_processor - jtag_debug_module - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - nios2_processor - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - onchip_memory - clk1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - nios2_processor - reset_n - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - onchip_memory - reset1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - nios2_processor - reset_n - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - onchip_memory - reset1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - instruction_master - onchip_memory - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x0000 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - onchip_memory - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - jtag_uart - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - jtag_uart - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - jtag_uart - clk - - - - int - 5 - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - d_irq - jtag_uart - irq - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - LEDs - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - LEDs - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - LEDs - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000410f0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - LEDs - s1 - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041100 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - jtag_uart - avalon_jtag_slave - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - LEDRs - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - LEDRs - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000410e0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - LEDRs - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - LEDRs - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - switches - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - switches - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - switches - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000410d0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - switches - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - push_switches - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - push_switches - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000410c0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - push_switches - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - push_switches - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - hex0 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - hex0 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000410b0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - hex0 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - hex0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - hex1 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - hex1 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x000410a0 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - hex1 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - hex1 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - hex2 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - hex2 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041090 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - hex2 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - hex2 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - hex3 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - hex3 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041080 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - hex3 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - hex3 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - hex4 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - hex4 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041070 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - hex4 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - hex4 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - hex5 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - hex5 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041060 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - hex5 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - hex5 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - hex6 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - hex6 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041050 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - hex6 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - hex6 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - hex7 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - hex7 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041040 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - hex7 - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - hex7 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - lcd_16207_0 - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - lcd_16207_0 - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - lcd_16207_0 - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041030 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - lcd_16207_0 - control_slave - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - lcd_on - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk - lcd_blon - clk - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - lcd_on - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - clk_0 - clk_reset - lcd_blon - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041010 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - lcd_on - s1 - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - lcd_on - reset - - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - jtag_debug_module_reset - lcd_blon - reset - - - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x00041020 - false - true - true - true - - - boolean - false - false - true - true - true - - - java.lang.String - UNKNOWN - false - true - true - true - - - boolean - false - false - true - true - true - - nios2_processor - data_master - lcd_blon - s1 - - - 1 - altera_avalon_onchip_memory2 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - On-Chip Memory (RAM or ROM) - 13.0.1.99.2 - - - 15 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 13.0 - - - 1 - altera_avalon_jtag_uart - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - JTAG UART - 13.0.1.99.2 - - - 36 - reset - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Reset Connection - 13.0 - - - 18 - avalon_slave - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave - 13.0 - - - 1 - interrupt_receiver - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Receiver - 13.0 - - - 18 - clock - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Clock Connection - 13.0 - - - 14 - altera_avalon_pio - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - PIO (Parallel I/O) - 13.0.1.99.2 - - - 1 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 13.0 - - - 1 - nios_custom_instruction_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Custom Instruction Master - 13.0 - - - 1 - altera_nios2_qsys - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Nios II Processor - 13.0 - - - 1 - reset_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output - 13.0 - - - 1 - interrupt_sender - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender - 13.0 - - - 1 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 13.0 - - - 1 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Clock Source - 13.0 - - - 1 - altera_avalon_lcd_16207 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera Avalon LCD 16207 - 13.0.1.99.2 - - - 2 - avalon_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Master - 13.0 - - - 1 - reset_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output - 13.0 - - - 1 - interrupt - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Interrupt Connection - 13.0 - - - 18 - clock_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input - 13.0 - - - 1 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 13.0 - - - 18 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 13.0 - - - 20 - avalon - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Connection - 13.0 - - 13.0sp1 232 - - diff --git a/nios_system/synthesis/submodules/nios_system_id_router_003.sv b/nios_system/synthesis/submodules/nios_system_id_router_003.sv index 7cfdd0c..5eb343c 100644 --- a/nios_system/synthesis/submodules/nios_system_id_router_003.sv +++ b/nios_system/synthesis/submodules/nios_system_id_router_003.sv @@ -1,217 +1,217 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_003_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 0 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router_003 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_003_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 0 ) begin - src_channel = 18'b1; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_003_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router_003 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_003_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 18'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_lcd.v b/nios_system/synthesis/submodules/nios_system_lcd.v index 942f142..18c2d15 100644 --- a/nios_system/synthesis/submodules/nios_system_lcd.v +++ b/nios_system/synthesis/submodules/nios_system_lcd.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd ( - // inputs: - address, - begintransfer, - clk, - read, - reset_n, - write, - writedata, - - // outputs: - LCD_E, - LCD_RS, - LCD_RW, - LCD_data, - readdata - ) -; - - output LCD_E; - output LCD_RS; - output LCD_RW; - inout [ 7: 0] LCD_data; - output [ 7: 0] readdata; - input [ 1: 0] address; - input begintransfer; - input clk; - input read; - input reset_n; - input write; - input [ 7: 0] writedata; - - wire LCD_E; - wire LCD_RS; - wire LCD_RW; - wire [ 7: 0] LCD_data; - wire [ 7: 0] readdata; - assign LCD_RW = address[0]; - assign LCD_RS = address[1]; - assign LCD_E = read | write; - assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; - assign readdata = LCD_data; - //control_slave, which is an e_avalon_slave - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd ( + // inputs: + address, + begintransfer, + clk, + read, + reset_n, + write, + writedata, + + // outputs: + LCD_E, + LCD_RS, + LCD_RW, + LCD_data, + readdata + ) +; + + output LCD_E; + output LCD_RS; + output LCD_RW; + inout [ 7: 0] LCD_data; + output [ 7: 0] readdata; + input [ 1: 0] address; + input begintransfer; + input clk; + input read; + input reset_n; + input write; + input [ 7: 0] writedata; + + wire LCD_E; + wire LCD_RS; + wire LCD_RW; + wire [ 7: 0] LCD_data; + wire [ 7: 0] readdata; + assign LCD_RW = address[0]; + assign LCD_RS = address[1]; + assign LCD_E = read | write; + assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; + assign readdata = LCD_data; + //control_slave, which is an e_avalon_slave + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_lcd_E.v b/nios_system/synthesis/submodules/nios_system_lcd_E.v index 0d9a8b1..c5680d0 100644 --- a/nios_system/synthesis/submodules/nios_system_lcd_E.v +++ b/nios_system/synthesis/submodules/nios_system_lcd_E.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_E ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg data_out; - wire out_port; - wire read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {1 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_E ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_pio_0.v b/nios_system/synthesis/submodules/nios_system_pio_0.v index 4f92a98..9cd2e61 100644 --- a/nios_system/synthesis/submodules/nios_system_pio_0.v +++ b/nios_system/synthesis/submodules/nios_system_pio_0.v @@ -1,58 +1,58 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_pio_0 ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 17: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 17: 0] data_in; - wire [ 17: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_pio_0 ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 17: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 17: 0] data_in; + wire [ 17: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv index f34687d..44c4d45 100644 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux.sv @@ -1,116 +1,116 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 2 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 2; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - - assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv index a362586..755ac9e 100644 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_003.sv @@ -1,101 +1,101 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux_003 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 1 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux_003 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 1; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - - assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux_003 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux_003 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/nios_system_generation.rpt b/nios_system_generation.rpt deleted file mode 100644 index b559a41..0000000 --- a/nios_system_generation.rpt +++ /dev/null @@ -1,319 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex7 -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_on -Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_blon -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex7 -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_on -Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_blon -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 39 modules, 155 connections -Info: merlin_domain_transform: After transform: 78 modules, 423 connections -Info: merlin_router_transform: After transform: 98 modules, 503 connections -Info: reset_adaptation_transform: After transform: 99 modules, 390 connections -Info: merlin_network_to_switch_transform: After transform: 138 modules, 470 connections -Info: merlin_mm_transform: After transform: 138 modules, 470 connections -Info: merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.22 10:06:19 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.22 10:06:19 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.22 10:06:20 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.22 10:06:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.22 10:06:20 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.22 10:06:20 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.22 10:06:20 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.22 10:06:20 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.22 10:06:20 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.22 10:06:21 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.22 10:06:21 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.22 10:06:23 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info: lcd_on: Starting RTL generation for module 'nios_system_lcd_on' -Info: lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] -Info: lcd_on: Done RTL generation for module 'nios_system_lcd_on' -Info: lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 28 modules, 155 files, 4086283 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/output_files/lights.asm.rpt b/output_files/lights.asm.rpt deleted file mode 100644 index 3c1b293..0000000 --- a/output_files/lights.asm.rpt +++ /dev/null @@ -1,127 +0,0 @@ -Assembler report for lights -Thu Dec 22 10:08:41 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Encrypted IP Cores Summary - 5. Assembler Generated Files - 6. Assembler Device Options: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Dec 22 10:08:41 2016 ; -; Revision Name ; lights ; -; Top-level Entity Name ; lights ; -; Family ; Cyclone IV E ; -; Device ; EP4CE115F29C7 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; On ; On ; -; Use configuration device ; Off ; Off ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Enable OCT_DONE ; Off ; Off ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+------------------------------------------------+ -; Assembler Encrypted IP Cores Summary ; -+--------+------------------------+--------------+ -; Vendor ; IP Core Name ; License Type ; -+--------+------------------------+--------------+ -; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ; -; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ; -+--------+------------------------+--------------+ - - -+--------------------------------------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------------------------------------+ -; File Name ; -+--------------------------------------------------------------------------+ -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof ; -+--------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------+ -; Assembler Device Options: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof ; -+----------------+-----------------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------------------------------------+ -; Device ; EP4CE115F29C7 ; -; JTAG usercode ; 0x0079E234 ; -; Checksum ; 0x0079E234 ; -+----------------+-----------------------------------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit Assembler - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Dec 22 10:08:34 2016 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights -Info (115031): Writing out detailed assembly data for power analysis -Info (115030): Assembler is generating device programming files -Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 481 megabytes - Info: Processing ended: Thu Dec 22 10:08:41 2016 - Info: Elapsed time: 00:00:07 - Info: Total CPU time (on all processors): 00:00:07 - - diff --git a/output_files/lights.cdf b/output_files/lights.cdf index 2adeddc..8cd075f 100644 --- a/output_files/lights.cdf +++ b/output_files/lights.cdf @@ -1,13 +1,13 @@ -/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ -JedecChain; - FileRevision(JESD32A); - DefaultMfr(6E); - - P ActionCode(Cfg) - Device PartName(EP4CE115F29) Path("C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/") File("lights.sof") MfrSpec(OpMask(1)); - -ChainEnd; - -AlteraBegin; - ChainType(JTAG); -AlteraEnd; +/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EP4CE115F29) Path("C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/") File("lights.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/output_files/lights.fit.rpt b/output_files/lights.fit.rpt deleted file mode 100644 index 0fee99a..0000000 --- a/output_files/lights.fit.rpt +++ /dev/null @@ -1,11511 +0,0 @@ -Fitter report for lights -Thu Dec 22 10:08:30 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. I/O Assignment Warnings - 6. Fitter Netlist Optimizations - 7. Ignored Assignments - 8. Incremental Compilation Preservation Summary - 9. Incremental Compilation Partition Settings - 10. Incremental Compilation Placement Preservation - 11. Pin-Out File - 12. Fitter Resource Usage Summary - 13. Fitter Partition Statistics - 14. Input Pins - 15. Output Pins - 16. Dual Purpose and Dedicated Pins - 17. I/O Bank Usage - 18. All Package Pins - 19. Fitter Resource Utilization by Entity - 20. Delay Chain Summary - 21. Pad To Core Delay Chain Fanout - 22. Control Signals - 23. Global & Other Fast Signals - 24. Non-Global High Fan-Out Signals - 25. Fitter RAM Summary - 26. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM - 27. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM - 28. |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM - 29. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM - 30. Other Routing Usage Summary - 31. LAB Logic Elements - 32. LAB-wide Signals - 33. LAB Signals Sourced - 34. LAB Signals Sourced Out - 35. LAB Distinct Inputs - 36. I/O Rules Summary - 37. I/O Rules Details - 38. I/O Rules Matrix - 39. Fitter Device Options - 40. Operating Settings and Conditions - 41. Fitter Messages - 42. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+--------------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Thu Dec 22 10:08:30 2016 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; lights ; -; Top-level Entity Name ; lights ; -; Family ; Cyclone IV E ; -; Device ; EP4CE115F29C7 ; -; Timing Models ; Final ; -; Total logic elements ; 2,234 / 114,480 ( 2 % ) ; -; Total combinational functions ; 2,060 / 114,480 ( 2 % ) ; -; Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; -; Total registers ; 1204 ; -; Total pins ; 118 / 529 ( 22 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; -; Total PLLs ; 0 / 4 ( 0 % ) ; -+------------------------------------+-------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Device ; EP4CE115F29C7 ; ; -; Nominal Core Supply Voltage ; 1.2V ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Auto Merge PLLs ; On ; On ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Perform Clocking Topology Analysis During Routing ; Off ; Off ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Optimize Hold Timing ; All Paths ; All Paths ; -; Optimize Multi-Corner Timing ; On ; On ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; SSN Optimization ; Off ; Off ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; Normal ; Normal ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; -; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; -; Treat Bidirectional Pin as Output Pin ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Register Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; -; Synchronizer Identification ; Off ; Off ; -; Enable Beneficial Skew Optimization ; On ; On ; -; Optimize Design for Metastability ; On ; On ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+----------------------------------------------------+ -; I/O Assignment Warnings ; -+-------------+--------------------------------------+ -; Pin Name ; Reason ; -+-------------+--------------------------------------+ -; LEDG[0] ; Missing drive strength and slew rate ; -; LEDG[1] ; Missing drive strength and slew rate ; -; LEDG[2] ; Missing drive strength and slew rate ; -; LEDG[3] ; Missing drive strength and slew rate ; -; LEDG[4] ; Missing drive strength and slew rate ; -; LEDG[5] ; Missing drive strength and slew rate ; -; LEDG[6] ; Missing drive strength and slew rate ; -; LEDG[7] ; Missing drive strength and slew rate ; -; LEDR[0] ; Missing drive strength and slew rate ; -; LEDR[1] ; Missing drive strength and slew rate ; -; LEDR[2] ; Missing drive strength and slew rate ; -; LEDR[3] ; Missing drive strength and slew rate ; -; LEDR[4] ; Missing drive strength and slew rate ; -; LEDR[5] ; Missing drive strength and slew rate ; -; LEDR[6] ; Missing drive strength and slew rate ; -; LEDR[7] ; Missing drive strength and slew rate ; -; LEDR[8] ; Missing drive strength and slew rate ; -; LEDR[9] ; Missing drive strength and slew rate ; -; LEDR[10] ; Missing drive strength and slew rate ; -; LEDR[11] ; Missing drive strength and slew rate ; -; LEDR[12] ; Missing drive strength and slew rate ; -; LEDR[13] ; Missing drive strength and slew rate ; -; LEDR[14] ; Missing drive strength and slew rate ; -; LEDR[15] ; Missing drive strength and slew rate ; -; LEDR[16] ; Missing drive strength and slew rate ; -; LEDR[17] ; Missing drive strength and slew rate ; -; HEX0[0] ; Missing drive strength and slew rate ; -; HEX0[1] ; Missing drive strength and slew rate ; -; HEX0[2] ; Missing drive strength and slew rate ; -; HEX0[3] ; Missing drive strength and slew rate ; -; HEX0[4] ; Missing drive strength and slew rate ; -; HEX0[5] ; Missing drive strength and slew rate ; -; HEX0[6] ; Missing drive strength and slew rate ; -; HEX1[0] ; Missing drive strength and slew rate ; -; HEX1[1] ; Missing drive strength and slew rate ; -; HEX1[2] ; Missing drive strength and slew rate ; -; HEX1[3] ; Missing drive strength and slew rate ; -; HEX1[4] ; Missing drive strength and slew rate ; -; HEX1[5] ; Missing drive strength and slew rate ; -; HEX1[6] ; Missing drive strength and slew rate ; -; HEX2[0] ; Missing drive strength and slew rate ; -; HEX2[1] ; Missing drive strength and slew rate ; -; HEX2[2] ; Missing drive strength and slew rate ; -; HEX2[3] ; Missing drive strength and slew rate ; -; HEX2[4] ; Missing drive strength and slew rate ; -; HEX2[5] ; Missing drive strength and slew rate ; -; HEX2[6] ; Missing drive strength and slew rate ; -; HEX3[0] ; Missing drive strength and slew rate ; -; HEX3[1] ; Missing drive strength and slew rate ; -; HEX3[2] ; Missing drive strength ; -; HEX3[3] ; Missing drive strength ; -; HEX3[4] ; Missing drive strength ; -; HEX3[5] ; Missing drive strength ; -; HEX3[6] ; Missing drive strength ; -; HEX4[0] ; Missing drive strength ; -; HEX4[1] ; Missing drive strength ; -; HEX4[2] ; Missing drive strength ; -; HEX4[3] ; Missing drive strength ; -; HEX4[4] ; Missing drive strength ; -; HEX4[5] ; Missing drive strength ; -; HEX4[6] ; Missing drive strength ; -; HEX5[0] ; Missing drive strength ; -; HEX5[1] ; Missing drive strength ; -; HEX5[2] ; Missing drive strength ; -; HEX5[3] ; Missing drive strength ; -; HEX5[4] ; Missing drive strength ; -; HEX5[5] ; Missing drive strength ; -; HEX5[6] ; Missing drive strength ; -; HEX6[0] ; Missing drive strength ; -; HEX6[1] ; Missing drive strength ; -; HEX6[2] ; Missing drive strength ; -; HEX6[3] ; Missing drive strength ; -; HEX6[4] ; Missing drive strength ; -; HEX6[5] ; Missing drive strength ; -; HEX6[6] ; Missing drive strength ; -; HEX7[0] ; Missing drive strength ; -; HEX7[1] ; Missing drive strength ; -; HEX7[2] ; Missing drive strength ; -; HEX7[3] ; Missing drive strength ; -; HEX7[4] ; Missing drive strength ; -; HEX7[5] ; Missing drive strength ; -; HEX7[6] ; Missing drive strength ; -; LCD_RS ; Missing drive strength ; -; LCD_RW ; Missing drive strength ; -; LCD_data[0] ; Missing drive strength ; -; LCD_data[1] ; Missing drive strength ; -; LCD_data[2] ; Missing drive strength ; -; LCD_data[3] ; Missing drive strength ; -; LCD_data[4] ; Missing drive strength ; -; LCD_data[5] ; Missing drive strength ; -; LCD_data[6] ; Missing drive strength ; -; LCD_data[7] ; Missing drive strength ; -; LCD_EN ; Missing drive strength ; -; LCD_ON ; Missing drive strength ; -; LCD_BLON ; Missing drive strength ; -+-------------+--------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Netlist Optimizations ; -+-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ -; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; -+-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[0] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[1] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[2] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[3] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[4] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[5] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[6] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[7] ; PORTBDATAOUT ; ; -+-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Ignored Assignments ; -+--------------+----------------+--------------+------------------+---------------+----------------+ -; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; -+--------------+----------------+--------------+------------------+---------------+----------------+ -; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ; -; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ; -; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ; -; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ; -; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ; -; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ; -; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ; -; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ; -; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ; -; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ; -; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ; -; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ; -; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ; -; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ; -; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ; -; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ; -; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ; -; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ; -; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ; -; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ; -; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ; -; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ; -; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ; -; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ; -; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ; -; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ; -; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ; -; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ; -; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ; -; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ; -; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ; -; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ; -; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ; -; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ; -; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ; -; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ; -; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ; -; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ; -; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ; -; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ; -; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ; -; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ; -; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ; -; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ; -; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ; -; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ; -; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ; -; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ; -; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ; -; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ; -; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ; -; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ; -; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ; -; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ; -; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ; -; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ; -; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ; -; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ; -; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ; -; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ; -; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ; -; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ; -; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ; -; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ; -; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ; -; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ; -; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ; -; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ; -; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ; -; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ; -; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ; -; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ; -; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ; -; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ; -; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ; -; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ; -; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ; -; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ; -; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ; -; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ; -; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ; -; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ; -; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ; -; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ; -; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ; -; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ; -; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ; -; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ; -; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ; -; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ; -; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ; -; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ; -; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ; -; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ; -; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ; -; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ; -; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ; -; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ; -; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ; -; Location ; ; ; OTG_DACK_N[0] ; PIN_C4 ; QSF Assignment ; -; Location ; ; ; OTG_DACK_N[1] ; PIN_D4 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ; -; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ; -; Location ; ; ; OTG_DREQ[1] ; PIN_B4 ; QSF Assignment ; -; Location ; ; ; OTG_FSPEED ; PIN_C6 ; QSF Assignment ; -; Location ; ; ; OTG_INT[0] ; PIN_A6 ; QSF Assignment ; -; Location ; ; ; OTG_INT[1] ; PIN_D5 ; QSF Assignment ; -; Location ; ; ; OTG_LSPEED ; PIN_B6 ; QSF Assignment ; -; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ; -; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ; -; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ; -; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ; -; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ; -; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ; -; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ; -; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ; -; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ; -; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ; -; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ; -; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ; -; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ; -; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ; -; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ; -; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ; -; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ; -; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ; -; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ; -; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ; -; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ; -; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ; -; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ; -; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ; -; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ; -; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ; -; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ; -; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ; -; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ; -; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ; -; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ; -; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ; -; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ; -; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ; -; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ; -; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ; -; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ; -; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ; -; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ; -; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ; -; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ; -; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ; -; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ; -; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ; -; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ; -; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ; -; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ; -; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ; -; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ; -; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ; -; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ; -; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ; -; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ; -; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ; -; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ; -; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ; -; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ; -; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ; -; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ; -; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ; -; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ; -; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ; -; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ; -; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ; -; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ; -; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ; -; I/O Standard ; ; ; AUD_ADCDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_ADCLRCK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_BCLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_DACDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_DACLRCK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_XCK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; CLOCK2_50 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; CLOCK3_50 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_BA[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_BA[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CAS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CKE ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQM[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQM[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQM[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQM[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[22] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[23] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[24] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[25] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[26] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[27] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[28] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[29] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[30] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[31] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_RAS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EEP_I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EEP_I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_GTX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_INT_N ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_LINK100 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_MDC ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_MDIO ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RST_N ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_COL ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_CRS ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DATA[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DATA[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DATA[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DATA[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DV ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_ER ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_DATA[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_DATA[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_DATA[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_DATA[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_EN ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_ER ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_GTX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_INT_N ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_LINK100 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_MDC ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_MDIO ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RST_N ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_COL ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_CRS ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DATA[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DATA[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DATA[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DATA[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DV ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_ER ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_DATA[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_DATA[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_DATA[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_DATA[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_EN ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_ER ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENETCLK_25 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[22] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_CE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_OE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_RST_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_RY ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_WE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_WP_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[22] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[23] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[24] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[25] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[26] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[27] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[28] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[29] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[30] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[31] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[32] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[33] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[34] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[35] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN0 ; 3.0-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN_N1 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN_N2 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN_P1 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN_P2 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT0 ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT_N1 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT_N2 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT_P1 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT_P2 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_D[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_D[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_D[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_D[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[0] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[10] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[11] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[12] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[13] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[14] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[15] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[16] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[1] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[2] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[3] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[4] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[5] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[6] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[7] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[8] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[9] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[0] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[10] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[11] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[12] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[13] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[14] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[15] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[16] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[1] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[2] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[3] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[4] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[5] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[6] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[7] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[8] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[9] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[0] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[10] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[11] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[12] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[13] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[14] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[15] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[16] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[1] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[2] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[3] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[4] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[5] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[6] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[7] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[8] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[9] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[0] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[10] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[11] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[12] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[13] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[14] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[15] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[16] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[1] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[2] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[3] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[4] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[5] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[6] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[7] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[8] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[9] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; IRDA_RXD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LEDG[8] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; OTG_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_CS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DACK_N[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DACK_N[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DREQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DREQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_FSPEED ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_INT[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_INT[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_LSPEED ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_RD_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_RST_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_WR_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_CLK2 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_DAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_DAT2 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_CMD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_WP_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SMA_CLKIN ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SMA_CLKOUT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_CE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_LB_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_OE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_UB_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_CLK27 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_HS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_RESET_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_VS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_CTS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_RTS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_RXD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_TXD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_BLANK_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_HS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_SYNC_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_VS ; 3.3-V LVTTL ; QSF Assignment ; -+--------------+----------------+--------------+------------------+---------------+----------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+---------------------+------------------------+ -; Type ; Value ; -+---------------------+------------------------+ -; Placement (by node) ; ; -; -- Requested ; 0 / 3864 ( 0.00 % ) ; -; -- Achieved ; 0 / 3864 ( 0.00 % ) ; -; ; ; -; Routing (by net) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+---------------------+------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -; sld_hub:auto_hub ; Auto-generated ; Post-Synthesis ; N/A ; Post-Synthesis ; N/A ; sld_hub:auto_hub ; -; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ - - -+------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 3599 ; 0 ; N/A ; Source File ; -; sld_hub:auto_hub ; 255 ; 0 ; N/A ; Post-Synthesis ; -; hard_block:auto_generated_inst ; 10 ; 0 ; N/A ; Source File ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.pin. - - -+------------------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+--------------------------------+ -; Resource ; Usage ; -+---------------------------------------------+--------------------------------+ -; Total logic elements ; 2,234 / 114,480 ( 2 % ) ; -; -- Combinational with no register ; 1030 ; -; -- Register only ; 174 ; -; -- Combinational with a register ; 1030 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1077 ; -; -- 3 input functions ; 678 ; -; -- <=2 input functions ; 305 ; -; -- Register only ; 174 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 1913 ; -; -- arithmetic mode ; 147 ; -; ; ; -; Total registers* ; 1,204 / 117,053 ( 1 % ) ; -; -- Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; -; -- I/O registers ; 0 / 2,573 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 160 / 7,155 ( 2 % ) ; -; Virtual pins ; 0 ; -; I/O pins ; 118 / 529 ( 22 % ) ; -; -- Clock pins ; 1 / 7 ( 14 % ) ; -; -- Dedicated input pins ; 3 / 9 ( 33 % ) ; -; ; ; -; Global signals ; 4 ; -; M9Ks ; 205 / 432 ( 47 % ) ; -; Total block memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; -; Total block memory implementation bits ; 1,889,280 / 3,981,312 ( 47 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; -; PLLs ; 0 / 4 ( 0 % ) ; -; Global clocks ; 4 / 20 ( 20 % ) ; -; JTAGs ; 1 / 1 ( 100 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 2% / 2% / 2% ; -; Peak interconnect usage (total/H/V) ; 20% / 19% / 22% ; -; Maximum fan-out ; 1229 ; -; Highest non-global fan-out ; 204 ; -; Total fan-out ; 15183 ; -; Average fan-out ; 3.96 ; -+---------------------------------------------+--------------------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Partition Statistics ; -+---------------------------------------------+-------------------------+------------------------+--------------------------------+ -; Statistic ; Top ; sld_hub:auto_hub ; hard_block:auto_generated_inst ; -+---------------------------------------------+-------------------------+------------------------+--------------------------------+ -; Difficulty Clustering Region ; Low ; Low ; Low ; -; ; ; ; ; -; Total logic elements ; 2062 / 114480 ( 2 % ) ; 172 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ; -; -- Combinational with no register ; 955 ; 75 ; 0 ; -; -- Register only ; 160 ; 14 ; 0 ; -; -- Combinational with a register ; 947 ; 83 ; 0 ; -; ; ; ; ; -; Logic element usage by number of LUT inputs ; ; ; ; -; -- 4 input functions ; 1007 ; 70 ; 0 ; -; -- 3 input functions ; 632 ; 46 ; 0 ; -; -- <=2 input functions ; 263 ; 42 ; 0 ; -; -- Register only ; 160 ; 14 ; 0 ; -; ; ; ; ; -; Logic elements by mode ; ; ; ; -; -- normal mode ; 1763 ; 150 ; 0 ; -; -- arithmetic mode ; 139 ; 8 ; 0 ; -; ; ; ; ; -; Total registers ; 1107 ; 97 ; 0 ; -; -- Dedicated logic registers ; 1107 / 114480 ( < 1 % ) ; 97 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ; -; ; ; ; ; -; Total LABs: partially or completely used ; 147 / 7155 ( 2 % ) ; 15 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ; -; ; ; ; ; -; Virtual pins ; 0 ; 0 ; 0 ; -; I/O pins ; 118 ; 0 ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ; -; Total memory bits ; 1649664 ; 0 ; 0 ; -; Total RAM block bits ; 1889280 ; 0 ; 0 ; -; JTAG ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; -; M9K ; 205 / 432 ( 47 % ) ; 0 / 432 ( 0 % ) ; 0 / 432 ( 0 % ) ; -; Clock control block ; 4 / 24 ( 16 % ) ; 0 / 24 ( 0 % ) ; 0 / 24 ( 0 % ) ; -; ; ; ; ; -; Connections ; ; ; ; -; -- Input Connections ; 268 ; 141 ; 0 ; -; -- Registered Input Connections ; 131 ; 106 ; 0 ; -; -- Output Connections ; 236 ; 173 ; 0 ; -; -- Registered Output Connections ; 4 ; 172 ; 0 ; -; ; ; ; ; -; Internal Connections ; ; ; ; -; -- Total Connections ; 14498 ; 1016 ; 5 ; -; -- Registered Connections ; 4720 ; 708 ; 0 ; -; ; ; ; ; -; External Connections ; ; ; ; -; -- Top ; 192 ; 312 ; 0 ; -; -- sld_hub:auto_hub ; 312 ; 2 ; 0 ; -; -- hard_block:auto_generated_inst ; 0 ; 0 ; 0 ; -; ; ; ; ; -; Partition Interface ; ; ; ; -; -- Input Ports ; 63 ; 23 ; 0 ; -; -- Output Ports ; 102 ; 40 ; 0 ; -; -- Bidir Ports ; 0 ; 0 ; 0 ; -; ; ; ; ; -; Registered Ports ; ; ; ; -; -- Registered Input Ports ; 0 ; 3 ; 0 ; -; -- Registered Output Ports ; 0 ; 29 ; 0 ; -; ; ; ; ; -; Port Connectivity ; ; ; ; -; -- Input Ports driven by GND ; 0 ; 9 ; 0 ; -; -- Output Ports driven by GND ; 0 ; 1 ; 0 ; -; -- Input Ports driven by VCC ; 0 ; 0 ; 0 ; -; -- Output Ports driven by VCC ; 0 ; 0 ; 0 ; -; -- Input Ports with no Source ; 0 ; 1 ; 0 ; -; -- Output Ports with no Source ; 0 ; 0 ; 0 ; -; -- Input Ports with no Fanout ; 0 ; 2 ; 0 ; -; -- Output Ports with no Fanout ; 0 ; 26 ; 0 ; -+---------------------------------------------+-------------------------+------------------------+--------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; -+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; CLOCK_50 ; Y2 ; 2 ; 0 ; 36 ; 14 ; 1229 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; KEY[2] ; N21 ; 6 ; 115 ; 42 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; KEY[3] ; R24 ; 5 ; 115 ; 35 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[10] ; AC24 ; 5 ; 115 ; 4 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[11] ; AB24 ; 5 ; 115 ; 5 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[12] ; AB23 ; 5 ; 115 ; 7 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[13] ; AA24 ; 5 ; 115 ; 9 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[14] ; AA23 ; 5 ; 115 ; 10 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[15] ; AA22 ; 5 ; 115 ; 6 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[16] ; Y24 ; 5 ; 115 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[17] ; Y23 ; 5 ; 115 ; 14 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[9] ; AB25 ; 5 ; 115 ; 16 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; HEX0[0] ; G18 ; 7 ; 69 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[1] ; F22 ; 7 ; 107 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[2] ; E17 ; 7 ; 67 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[3] ; L26 ; 6 ; 115 ; 50 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[4] ; L25 ; 6 ; 115 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[5] ; J22 ; 6 ; 115 ; 67 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[6] ; H22 ; 6 ; 115 ; 69 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[0] ; M24 ; 6 ; 115 ; 41 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[1] ; Y22 ; 5 ; 115 ; 30 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[2] ; W21 ; 5 ; 115 ; 25 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[3] ; W22 ; 5 ; 115 ; 30 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[4] ; W25 ; 5 ; 115 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[5] ; U23 ; 5 ; 115 ; 22 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[6] ; U24 ; 5 ; 115 ; 28 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[0] ; AA25 ; 5 ; 115 ; 17 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[1] ; AA26 ; 5 ; 115 ; 16 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[2] ; Y25 ; 5 ; 115 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[3] ; W26 ; 5 ; 115 ; 19 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[4] ; Y26 ; 5 ; 115 ; 18 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[5] ; W27 ; 5 ; 115 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[6] ; W28 ; 5 ; 115 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX3[0] ; V21 ; 5 ; 115 ; 25 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX3[1] ; U21 ; 5 ; 115 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX3[2] ; AB20 ; 4 ; 100 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX3[3] ; AA21 ; 4 ; 111 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX3[4] ; AD24 ; 4 ; 105 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX3[5] ; AF23 ; 4 ; 105 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX3[6] ; Y19 ; 4 ; 105 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[0] ; AB19 ; 4 ; 98 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[1] ; AA19 ; 4 ; 107 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[2] ; AG21 ; 4 ; 74 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[3] ; AH21 ; 4 ; 74 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[4] ; AE19 ; 4 ; 83 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[5] ; AF19 ; 4 ; 83 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[6] ; AE18 ; 4 ; 79 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[0] ; AD18 ; 4 ; 85 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[1] ; AC18 ; 4 ; 87 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[2] ; AB18 ; 4 ; 98 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[3] ; AH19 ; 4 ; 72 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[4] ; AG19 ; 4 ; 72 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[5] ; AF18 ; 4 ; 79 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[6] ; AH18 ; 4 ; 69 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[0] ; AA17 ; 4 ; 89 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[1] ; AB16 ; 4 ; 65 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[2] ; AA16 ; 4 ; 65 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[3] ; AB17 ; 4 ; 89 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[4] ; AB15 ; 4 ; 67 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[5] ; AA15 ; 4 ; 67 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[6] ; AC17 ; 4 ; 74 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[0] ; AD17 ; 4 ; 74 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[1] ; AE17 ; 4 ; 67 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[2] ; AG17 ; 4 ; 62 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[3] ; AH17 ; 4 ; 62 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[4] ; AF17 ; 4 ; 67 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[5] ; AG18 ; 4 ; 69 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[6] ; AA14 ; 3 ; 54 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_BLON ; L6 ; 1 ; 0 ; 47 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_EN ; L4 ; 1 ; 0 ; 52 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_ON ; L5 ; 1 ; 0 ; 58 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_RS ; M2 ; 1 ; 0 ; 44 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_RW ; M1 ; 1 ; 0 ; 44 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[0] ; L3 ; 1 ; 0 ; 52 ; 14 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[1] ; L1 ; 1 ; 0 ; 44 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[2] ; L2 ; 1 ; 0 ; 44 ; 0 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[3] ; K7 ; 1 ; 0 ; 49 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[4] ; K1 ; 1 ; 0 ; 54 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[5] ; K2 ; 1 ; 0 ; 55 ; 21 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[6] ; M3 ; 1 ; 0 ; 51 ; 14 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[7] ; M5 ; 1 ; 0 ; 47 ; 0 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[1] ; E22 ; 7 ; 111 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[2] ; E25 ; 7 ; 83 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[3] ; E24 ; 7 ; 85 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[4] ; H21 ; 7 ; 72 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[5] ; G20 ; 7 ; 74 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[6] ; G22 ; 7 ; 72 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[7] ; G21 ; 7 ; 74 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[10] ; J15 ; 7 ; 60 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[11] ; H16 ; 7 ; 65 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[12] ; J16 ; 7 ; 65 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[13] ; H17 ; 7 ; 67 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[14] ; F15 ; 7 ; 58 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[15] ; G15 ; 7 ; 65 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[16] ; G16 ; 7 ; 67 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[17] ; H15 ; 7 ; 60 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[7] ; H19 ; 7 ; 72 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[8] ; J17 ; 7 ; 69 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[9] ; G17 ; 7 ; 83 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------+ -; Dual Purpose and Dedicated Pins ; -+----------+-----------------------------+--------------------------+-------------------------+---------------------------+ -; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; -+----------+-----------------------------+--------------------------+-------------------------+---------------------------+ -; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; -; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; -; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; -; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; -; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; -; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; -; P7 ; TDI ; - ; altera_reserved_tdi ; JTAG Pin ; -; P5 ; TCK ; - ; altera_reserved_tck ; JTAG Pin ; -; P8 ; TMS ; - ; altera_reserved_tms ; JTAG Pin ; -; P6 ; TDO ; - ; altera_reserved_tdo ; JTAG Pin ; -; R8 ; nCE ; - ; - ; Dedicated Programming Pin ; -; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; -; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; -; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; -; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; -; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; -; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; -+----------+-----------------------------+--------------------------+-------------------------+---------------------------+ - - -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 17 / 56 ( 30 % ) ; 3.3V ; -- ; -; 2 ; 1 / 63 ( 2 % ) ; 3.3V ; -- ; -; 3 ; 1 / 73 ( 1 % ) ; 3.3V ; -- ; -; 4 ; 32 / 71 ( 45 % ) ; 3.3V ; -- ; -; 5 ; 34 / 65 ( 52 % ) ; 2.5V ; -- ; -; 6 ; 9 / 58 ( 16 % ) ; 2.5V ; -- ; -; 7 ; 29 / 72 ( 40 % ) ; 2.5V ; -- ; -; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ; -+----------+------------------+---------------+--------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AA1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; -; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA14 ; 191 ; 3 ; HEX7[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA15 ; 213 ; 4 ; HEX6[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA16 ; 211 ; 4 ; HEX6[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA17 ; 241 ; 4 ; HEX6[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA18 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AA19 ; 264 ; 4 ; HEX4[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; -; AA21 ; 269 ; 4 ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA22 ; 275 ; 5 ; SW[15] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA23 ; 280 ; 5 ; SW[14] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA24 ; 279 ; 5 ; SW[13] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA25 ; 294 ; 5 ; HEX2[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA26 ; 293 ; 5 ; HEX2[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB15 ; 214 ; 4 ; HEX6[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB16 ; 212 ; 4 ; HEX6[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB17 ; 242 ; 4 ; HEX6[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB18 ; 254 ; 4 ; HEX5[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB19 ; 253 ; 4 ; HEX4[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB20 ; 257 ; 4 ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB23 ; 276 ; 5 ; SW[12] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB24 ; 274 ; 5 ; SW[11] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB25 ; 292 ; 5 ; SW[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC17 ; 221 ; 4 ; HEX6[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AC18 ; 240 ; 4 ; HEX5[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC24 ; 273 ; 5 ; SW[10] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD17 ; 222 ; 4 ; HEX7[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AD18 ; 237 ; 4 ; HEX5[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD24 ; 260 ; 4 ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE17 ; 215 ; 4 ; HEX7[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AE18 ; 225 ; 4 ; HEX4[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AE19 ; 231 ; 4 ; HEX4[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF17 ; 216 ; 4 ; HEX7[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AF18 ; 226 ; 4 ; HEX5[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AF19 ; 232 ; 4 ; HEX4[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF23 ; 262 ; 4 ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG17 ; 207 ; 4 ; HEX7[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AG18 ; 217 ; 4 ; HEX7[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AG19 ; 219 ; 4 ; HEX5[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG21 ; 223 ; 4 ; HEX4[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AH2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AH16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH17 ; 208 ; 4 ; HEX7[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AH18 ; 218 ; 4 ; HEX5[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AH19 ; 220 ; 4 ; HEX5[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AH20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH21 ; 224 ; 4 ; HEX4[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH24 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH27 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; B1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E17 ; 456 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E22 ; 403 ; 7 ; LEDG[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E24 ; 433 ; 7 ; LEDG[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E25 ; 434 ; 7 ; LEDG[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F15 ; 466 ; 7 ; LEDR[14] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F22 ; 409 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; G15 ; 457 ; 7 ; LEDR[15] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G16 ; 453 ; 7 ; LEDR[16] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G17 ; 437 ; 7 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G18 ; 452 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G20 ; 444 ; 7 ; LEDG[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G21 ; 445 ; 7 ; LEDG[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G22 ; 449 ; 7 ; LEDG[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; -; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H15 ; 464 ; 7 ; LEDR[17] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H16 ; 459 ; 7 ; LEDR[11] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H17 ; 454 ; 7 ; LEDR[13] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; H19 ; 446 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; -; H21 ; 448 ; 7 ; LEDG[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H22 ; 399 ; 6 ; HEX0[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J15 ; 465 ; 7 ; LEDR[10] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; J16 ; 458 ; 7 ; LEDR[12] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; J17 ; 450 ; 7 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J22 ; 394 ; 6 ; HEX0[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; K1 ; 28 ; 1 ; LCD_data[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K2 ; 27 ; 1 ; LCD_data[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K7 ; 38 ; 1 ; LCD_data[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L1 ; 49 ; 1 ; LCD_data[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L2 ; 48 ; 1 ; LCD_data[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L3 ; 32 ; 1 ; LCD_data[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L4 ; 31 ; 1 ; LCD_EN ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L5 ; 21 ; 1 ; LCD_ON ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L6 ; 43 ; 1 ; LCD_BLON ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L25 ; 369 ; 6 ; HEX0[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; L26 ; 363 ; 6 ; HEX0[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M1 ; 51 ; 1 ; LCD_RW ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M2 ; 50 ; 1 ; LCD_RS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M3 ; 34 ; 1 ; LCD_data[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M5 ; 41 ; 1 ; LCD_data[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; -; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; M24 ; 347 ; 6 ; HEX1[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N21 ; 348 ; 6 ; KEY[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; P5 ; 59 ; 1 ; altera_reserved_tck ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; -; P6 ; 61 ; 1 ; altera_reserved_tdo ; output ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; -; P7 ; 58 ; 1 ; altera_reserved_tdi ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; -; P8 ; 60 ; 1 ; altera_reserved_tms ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; -; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; -; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R24 ; 330 ; 5 ; KEY[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U21 ; 319 ; 5 ; HEX3[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U23 ; 305 ; 5 ; HEX1[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U24 ; 316 ; 5 ; HEX1[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V21 ; 311 ; 5 ; HEX3[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W21 ; 310 ; 5 ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W22 ; 321 ; 5 ; HEX1[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W25 ; 300 ; 5 ; HEX1[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W26 ; 299 ; 5 ; HEX2[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W27 ; 301 ; 5 ; HEX2[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W28 ; 302 ; 5 ; HEX2[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; Y2 ; 65 ; 2 ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y19 ; 263 ; 4 ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y22 ; 320 ; 5 ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y23 ; 288 ; 5 ; SW[17] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y24 ; 287 ; 5 ; SW[16] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y25 ; 298 ; 5 ; HEX2[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y26 ; 297 ; 5 ; HEX2[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; |lights ; 2234 (1) ; 1204 (0) ; 0 (0) ; 1649664 ; 205 ; 0 ; 0 ; 0 ; 118 ; 0 ; 1030 (1) ; 174 (0) ; 1030 (0) ; |lights ; work ; -; |nios_system:NiosII| ; 2061 (0) ; 1107 (0) ; 0 (0) ; 1649664 ; 205 ; 0 ; 0 ; 0 ; 0 ; 0 ; 954 (0) ; 160 (0) ; 947 (0) ; |lights|nios_system:NiosII ; work ; -; |altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 10 (10) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 5 (5) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_translator:nios2_processor_data_master_translator| ; 9 (9) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_translator:nios2_processor_instruction_master_translator| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex0_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex1_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex2_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex3_s1_translator| ; 12 (12) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex4_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex5_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex6_s1_translator| ; 12 (12) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex7_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator| ; 23 (23) ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 23 (23) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_16207_0_control_slave_translator| ; 22 (22) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 15 (15) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_blon_s1_translator| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_on_s1_translator| ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:ledrs_s1_translator| ; 24 (24) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 21 (21) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:leds_s1_translator| ; 13 (13) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 11 (11) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator| ; 33 (33) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 33 (33) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:onchip_memory_s1_translator| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:push_switches_s1_translator| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:switches_s1_translator| ; 24 (24) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 21 (21) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_reset_controller:rst_controller| ; 10 (7) ; 9 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 7 (5) ; 3 (2) ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller ; altera_reserved_qsys_nios_system ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 1 (1) ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reserved_qsys_nios_system ; -; |nios_system_LEDRs:ledrs| ; 38 (38) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 18 (18) ; 18 (18) ; |lights|nios_system:NiosII|nios_system_LEDRs:ledrs ; altera_reserved_qsys_nios_system ; -; |nios_system_LEDs:leds| ; 19 (19) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 8 (8) ; 8 (8) ; |lights|nios_system:NiosII|nios_system_LEDs:leds ; altera_reserved_qsys_nios_system ; -; |nios_system_addr_router:addr_router| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_addr_router:addr_router ; altera_reserved_qsys_nios_system ; -; |nios_system_addr_router_001:addr_router_001| ; 30 (30) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:cmd_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_mux:cmd_xbar_mux_001| ; 61 (58) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (41) ; 1 (0) ; 18 (15) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 ; altera_reserved_qsys_nios_system ; -; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_mux:cmd_xbar_mux| ; 55 (52) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (3) ; 1 (0) ; 50 (47) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux ; altera_reserved_qsys_nios_system ; -; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex0| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex0 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex1| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex1 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex2| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex2 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex3| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex3 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex4| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex4 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex5| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex5 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex6| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex6 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex7| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex7 ; altera_reserved_qsys_nios_system ; -; |nios_system_jtag_uart:jtag_uart| ; 157 (39) ; 104 (13) ; 0 (0) ; 1024 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 43 (16) ; 17 (2) ; 97 (20) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart ; altera_reserved_qsys_nios_system ; -; |alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic| ; 68 (68) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 15 (15) ; 37 (37) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic ; work ; -; |nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r ; altera_reserved_qsys_nios_system ; -; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; work ; -; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; work ; -; |a_dpfifo_q131:dpfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; -; |a_fefifo_7cf:fifo_state| ; 14 (8) ; 8 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 8 (2) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; -; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; -; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; -; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; -; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; -; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; -; |nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w ; altera_reserved_qsys_nios_system ; -; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; work ; -; |scfifo_jr21:auto_generated| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ; work ; -; |a_dpfifo_q131:dpfifo| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; -; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 8 (2) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; -; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; -; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; -; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; -; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; -; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; -; |nios_system_lcd_16207_0:lcd_16207_0| ; 12 (12) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 8 (8) ; |lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 ; altera_reserved_qsys_nios_system ; -; |nios_system_lcd_on:lcd_blon| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon ; altera_reserved_qsys_nios_system ; -; |nios_system_lcd_on:lcd_on| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_on ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor:nios2_processor| ; 1040 (658) ; 576 (306) ; 0 (0) ; 10240 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 440 (328) ; 51 (5) ; 549 (326) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci| ; 381 (81) ; 269 (80) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (1) ; 46 (1) ; 223 (79) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper| ; 139 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 43 (0) ; 43 (0) ; 53 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk| ; 50 (46) ; 49 (45) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 39 (37) ; 10 (8) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer3| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; work ; -; |altera_std_synchronizer:the_altera_std_synchronizer4| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; work ; -; |nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck| ; 87 (83) ; 47 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 4 (0) ; 43 (43) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; work ; -; |altera_std_synchronizer:the_altera_std_synchronizer2| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; work ; -; |sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; work ; -; |nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg| ; 9 (9) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug| ; 11 (9) ; 9 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 10 (9) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; work ; -; |nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem| ; 112 (112) ; 49 (49) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (62) ; 1 (1) ; 49 (49) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; work ; -; |altsyncram_4891:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; work ; -; |nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; work ; -; |altsyncram_0rh1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; work ; -; |nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; work ; -; |altsyncram_1rh1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; work ; -; |nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench ; altera_reserved_qsys_nios_system ; -; |nios_system_onchip_memory:onchip_memory| ; 171 (1) ; 3 (0) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 168 (1) ; 0 (0) ; 3 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 170 (0) ; 3 (0) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 167 (0) ; 0 (0) ; 3 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; work ; -; |altsyncram_4ed1:auto_generated| ; 170 (3) ; 3 (3) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 167 (0) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; work ; -; |decode_qsa:decode3| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 ; work ; -; |mux_nob:mux2| ; 160 (160) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 160 (160) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 ; work ; -; |nios_system_push_switches:push_switches| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_push_switches:push_switches ; altera_reserved_qsys_nios_system ; -; |nios_system_rsp_xbar_mux:rsp_xbar_mux| ; 11 (11) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux ; altera_reserved_qsys_nios_system ; -; |nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 113 (113) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 89 (89) ; 0 (0) ; 24 (24) ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_switches:switches| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 18 (18) ; |lights|nios_system:NiosII|nios_system_switches:switches ; altera_reserved_qsys_nios_system ; -; |sld_hub:auto_hub| ; 172 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 75 (1) ; 14 (0) ; 83 (0) ; |lights|sld_hub:auto_hub ; work ; -; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 171 (126) ; 97 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (57) ; 14 (14) ; 83 (58) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; work ; -; |sld_rom_sr:hub_info_reg| ; 25 (25) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 9 (9) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; work ; -; |sld_shadow_jsm:shadow_jsm| ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 19 (19) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; work ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+---------------------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+-------------+----------+---------------+---------------+-----------------------+-----+------+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; -+-------------+----------+---------------+---------------+-----------------------+-----+------+ -; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[13] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[14] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[15] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[16] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[17] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_RS ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_RW ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_EN ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_ON ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_BLON ; Output ; -- ; -- ; -- ; -- ; -- ; -; CLOCK_50 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; KEY[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; KEY[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; KEY[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[8] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[9] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[10] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[12] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[13] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[14] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[15] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[16] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[17] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -+-------------+----------+---------------+---------------+-----------------------+-----+------+ - - -+-----------------------------------------------------------------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+-----------------------------------------------------------------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+-----------------------------------------------------------------------------------+-------------------+---------+ -; CLOCK_50 ; ; ; -; SW[0] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[0] ; 0 ; 6 ; -; KEY[1] ; ; ; -; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[0] ; 0 ; 6 ; -; SW[1] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[1] ; 0 ; 6 ; -; KEY[2] ; ; ; -; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[1] ; 0 ; 6 ; -; SW[2] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[2] ; 0 ; 6 ; -; KEY[3] ; ; ; -; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[2] ; 0 ; 6 ; -; SW[3] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[3] ; 1 ; 6 ; -; SW[4] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[4] ; 1 ; 6 ; -; SW[5] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[5] ; 1 ; 6 ; -; SW[6] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[6] ; 0 ; 6 ; -; SW[7] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[7] ; 0 ; 6 ; -; SW[8] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[8] ; 0 ; 6 ; -; SW[9] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[9] ; 1 ; 6 ; -; SW[10] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[10] ; 0 ; 6 ; -; SW[11] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[11] ; 0 ; 6 ; -; SW[12] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[12] ; 0 ; 6 ; -; SW[13] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[13] ; 1 ; 6 ; -; SW[14] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[14] ; 0 ; 6 ; -; SW[15] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[15] ; 0 ; 6 ; -; SW[16] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[16] ; 0 ; 6 ; -; SW[17] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[17] ; 0 ; 6 ; -; KEY[0] ; ; ; -; - nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; 1 ; 6 ; -+-----------------------------------------------------------------------------------+-------------------+---------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ -; CLOCK_50 ; PIN_Y2 ; 1227 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; -; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y37_N0 ; 183 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; -; altera_internal_jtag~TMSUTAP ; JTAG_X1_Y37_N0 ; 21 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; LCCOMB_X58_Y39_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; LCCOMB_X59_Y35_N4 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~23 ; LCCOMB_X60_Y35_N6 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X55_Y38_N0 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK14 ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; FF_X57_Y48_N9 ; 791 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; FF_X57_Y48_N5 ; 204 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~1 ; LCCOMB_X59_Y28_N10 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_LEDs:leds|always0~2 ; LCCOMB_X62_Y33_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; LCCOMB_X59_Y39_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~1 ; LCCOMB_X59_Y39_N18 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~2 ; LCCOMB_X58_Y36_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|update_grant~1 ; LCCOMB_X58_Y36_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex0|always0~1 ; LCCOMB_X63_Y33_N24 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex1|always0~1 ; LCCOMB_X60_Y28_N8 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex2|always0~1 ; LCCOMB_X63_Y28_N18 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex3|always0~1 ; LCCOMB_X63_Y29_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex4|always0~1 ; LCCOMB_X60_Y29_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex5|always0~1 ; LCCOMB_X61_Y29_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex6|always0~1 ; LCCOMB_X60_Y29_N12 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex7|always0~1 ; LCCOMB_X61_Y28_N0 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|r_ena~0 ; LCCOMB_X67_Y36_N28 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0]~4 ; LCCOMB_X63_Y36_N28 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1]~0 ; LCCOMB_X65_Y36_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled~1 ; LCCOMB_X63_Y36_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~2 ; LCCOMB_X61_Y34_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_wr ; FF_X65_Y34_N27 ; 15 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF~2 ; LCCOMB_X61_Y33_N2 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; LCCOMB_X61_Y34_N14 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; LCCOMB_X63_Y34_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val~0 ; LCCOMB_X67_Y36_N0 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|read_0 ; FF_X61_Y34_N31 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|wr_rfifo ; LCCOMB_X62_Y34_N28 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[4] ; FF_X57_Y35_N3 ; 41 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_result~26 ; LCCOMB_X55_Y29_N0 ; 49 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_new_inst ; FF_X53_Y30_N15 ; 42 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_valid ; FF_X53_Y33_N13 ; 25 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_sel_nxt.10~0 ; LCCOMB_X57_Y32_N2 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_valid~0 ; LCCOMB_X59_Y35_N26 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_hi_imm16 ; FF_X53_Y29_N11 ; 17 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot ; FF_X55_Y30_N11 ; 22 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~31 ; LCCOMB_X55_Y34_N18 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_hi~0 ; LCCOMB_X53_Y30_N20 ; 15 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[2] ; FF_X57_Y33_N11 ; 131 ; Output enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren ; LCCOMB_X57_Y38_N20 ; 2 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie_inst_nxt~2 ; LCCOMB_X57_Y32_N16 ; 15 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_valid ; FF_X53_Y33_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4]~0 ; LCCOMB_X57_Y30_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data_en~0 ; LCCOMB_X57_Y31_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~1 ; LCCOMB_X57_Y30_N26 ; 30 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[8] ; FF_X56_Y36_N9 ; 36 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jxuir ; FF_X65_Y37_N23 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a ; LCCOMB_X58_Y38_N18 ; 15 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; LCCOMB_X61_Y38_N8 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_b ; LCCOMB_X59_Y38_N18 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_no_action_break_a~0 ; LCCOMB_X61_Y38_N18 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|update_jdo_strobe ; FF_X58_Y38_N29 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2]~13 ; LCCOMB_X63_Y36_N8 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34]~21 ; LCCOMB_X62_Y36_N4 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36]~29 ; LCCOMB_X62_Y36_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_sdr~0 ; LCCOMB_X65_Y37_N18 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_uir~0 ; LCCOMB_X65_Y37_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; LCCOMB_X56_Y38_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0]~9 ; LCCOMB_X58_Y38_N8 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_wr_en ; LCCOMB_X57_Y38_N30 ; 2 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1849w[3] ; LCCOMB_X58_Y32_N28 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1866w[3] ; LCCOMB_X58_Y32_N16 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1876w[3] ; LCCOMB_X58_Y32_N10 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1886w[3] ; LCCOMB_X58_Y32_N14 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1896w[3] ; LCCOMB_X58_Y32_N20 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1906w[3] ; LCCOMB_X58_Y32_N24 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1916w[3] ; LCCOMB_X58_Y32_N26 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X68_Y37_N15 ; 71 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; LCCOMB_X69_Y35_N0 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; LCCOMB_X69_Y35_N10 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; LCCOMB_X70_Y34_N4 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; LCCOMB_X66_Y34_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; LCCOMB_X66_Y34_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~4 ; LCCOMB_X67_Y34_N14 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~11 ; LCCOMB_X67_Y34_N16 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~4 ; LCCOMB_X66_Y34_N14 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~10 ; LCCOMB_X69_Y35_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; LCCOMB_X69_Y35_N28 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; LCCOMB_X68_Y36_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; LCCOMB_X68_Y36_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; LCCOMB_X68_Y34_N28 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~19 ; LCCOMB_X65_Y37_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; LCCOMB_X66_Y37_N28 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; LCCOMB_X66_Y37_N30 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X68_Y37_N25 ; 15 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; FF_X65_Y35_N9 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; FF_X68_Y37_N5 ; 40 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; FF_X68_Y37_N27 ; 46 ; Sync. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; FF_X68_Y37_N19 ; 14 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; LCCOMB_X65_Y35_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; FF_X66_Y35_N1 ; 32 ; Async. clear ; no ; -- ; -- ; -- ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+--------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+--------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; CLOCK_50 ; PIN_Y2 ; 1227 ; 0 ; Global Clock ; GCLK4 ; -- ; -; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y37_N0 ; 183 ; 0 ; Global Clock ; GCLK2 ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X55_Y38_N0 ; 3 ; 0 ; Global Clock ; GCLK14 ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; FF_X57_Y48_N9 ; 791 ; 0 ; Global Clock ; GCLK11 ; -- ; -+--------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; Name ; Fan-Out ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; 204 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[48] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[47] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[46] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[45] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[44] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[43] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[42] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[41] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[40] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[39] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[38] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[50] ; 192 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[49] ; 192 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[2] ; 131 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[1] ; 112 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[0] ; 112 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[3] ; 111 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; 71 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_no_action_break_a~0 ; 64 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; 58 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; 51 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[35] ; 50 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[34] ; 50 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[33] ; 50 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[32] ; 50 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_result~26 ; 49 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; 46 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_access ; 46 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; 42 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_new_inst ; 42 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[4] ; 41 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; 40 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|update_jdo_strobe ; 39 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_sdr~0 ; 39 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|read_latency_shift_reg[0] ; 38 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[8] ; 36 ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; 35 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_ld ; 35 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_valid~0 ; 34 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_b ; 33 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_aligning_data ; 33 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001|src0_valid ; 33 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_logic_op[0] ; 33 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1896w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1906w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1886w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1849w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1876w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1866w[3] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0]~9 ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_rd_d1 ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[36] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[37] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15]~0 ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[2] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot_right ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~31 ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_use_imm ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_logic_op[1] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|readdata~0 ; 31 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~1 ; 30 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux|src1_valid ; 30 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~24 ; 29 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|uav_write~0 ; 29 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[6] ; 29 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[5] ; 28 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001|src1_valid ; 27 ; -; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|read_latency_shift_reg[0] ; 27 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; 26 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench|d_write ; 26 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; 25 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_valid ; 25 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[14] ; 24 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|write~0 ; 24 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|write_accepted ; 24 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; 23 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|read_latency_shift_reg[0] ; 23 ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|read_latency_shift_reg[0] ; 23 ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; 23 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[2] ; 22 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot ; 22 ; -; altera_internal_jtag~TMSUTAP ; 21 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0]~4 ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15] ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[12] ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[3] ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_logic ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_sub ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28]~19 ; 20 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_valid ; 20 ; -; altera_internal_jtag~TDIUTAP ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28]~20 ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[21] ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[16] ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[1] ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[4] ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34]~21 ; 18 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[0] ; 18 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[0] ; 18 ; -; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~1 ; 18 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[0] ; 18 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~30 ; 17 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_hi_imm16 ; 17 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_br_cmp ; 17 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_read ; 17 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_wr ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr~19 ; 16 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|read_0 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_fill_bit~1 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_sel_nxt.10~0 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_jmp_direct ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_lo~0 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[5] ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_rdctl_inst ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[1] ; 16 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie_inst_nxt~2 ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_hi~0 ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[11] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[6] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[5] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[4] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[3] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[2] ; 15 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; 14 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; 14 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; 14 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|wr_rfifo ; 14 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[13] ; 14 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|read_accepted ; 14 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~2 ; 14 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; 13 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2]~13 ; 13 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~5 ; 13 ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|read_latency_shift_reg[0] ; 13 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|read_latency_shift_reg[0] ; 13 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; 12 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal8~0 ; 12 ; -; nios_system:NiosII|nios_system_LEDs:leds|always0~1 ; 12 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val~0 ; 11 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; 11 ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 11 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; 10 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal133~0 ; 10 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|waitrequest ; 10 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; 9 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; 9 ; -; ~GND ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_fill_bit~0 ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_ld_signed ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; 9 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[6] ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[8] ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[7] ; 9 ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 9 ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 9 ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; 9 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal9~0 ; 9 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; 8 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1]~0 ; 8 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~2 ; 8 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; 8 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1916w[3] ; 8 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[52] ; 8 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[53] ; 8 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[51] ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data_en~0 ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4]~0 ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~0 ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_retaddr~0 ; 8 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal16~1 ; 8 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|read_latency_shift_reg[0] ; 8 ; -; nios_system:NiosII|nios_system_LEDs:leds|always0~2 ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[8] ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[7] ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~31 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~30 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~29 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~28 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~27 ; 7 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~26 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~25 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~24 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~23 ; 7 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~22 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~21 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~20 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~19 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~18 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~17 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~16 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~15 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~14 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~13 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~12 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~11 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~10 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~9 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~8 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~7 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~6 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~5 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~4 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~3 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~2 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~1 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~0 ; 7 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|wren~0 ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[35] ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_break ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_exception ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|write ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|i_read ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_cdr ; 7 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[0] ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex7|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex6|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex5|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~4 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex4|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex3|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex2|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex1|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex0|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[7] ; 7 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~1 ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; 6 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; 6 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; 6 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|t_ena~reg0 ; 6 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[0] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|Equal0~0 ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[2] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[3] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[4] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_b_is_dst~1 ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_valid ; 6 ; -; nios_system:NiosII|nios_system_lcd_on:lcd_blon|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_lcd_on:lcd_on|always0~0 ; 6 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|read_latency_shift_reg[0] ; 6 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|read_latency_shift_reg[0] ; 6 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~23 ; 6 ; -; nios_system:NiosII|nios_system_hex0:hex6|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_hex0:hex5|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_hex0:hex3|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_LEDs:leds|always0~0 ; 6 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|uav_read~0 ; 6 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[4] ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~10 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|clear_signal ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~4 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]~1 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~11 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~4 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_proc~0 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal11~0 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled~1 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~1 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~0 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_result[1]~5 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_result[0]~4 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3]~0 ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate~0 ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift~6 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[34] ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[17] ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~5 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_req~0 ; 5 ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|cp_valid ; 5 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator|read_accepted ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0]~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1]~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1]~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1]~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex7|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex4|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex2|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex1|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex0|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~1 ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[5] ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~19 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]~5 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~0 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~3 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|m0_write~2 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~2 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[30] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[20] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[21] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[22] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[23] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[24] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[25] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[26] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[27] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[28] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[29] ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[19] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_align_cycle[0] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_getting_data~13 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux|src0_valid ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_uir~0 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|update_grant~1 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~1 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|local_read~1 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux|src0_valid~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|WideOr1 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001|src1_valid~0 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux|src1_valid~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0]~0 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[17] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[18] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[19] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[20] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_shift_logical~0 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_br_nxt~0 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~4 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~3 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0]~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1]~0 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|Mux37~0 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal0~2 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|m0_write~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[4] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_waitrequest_generated~2 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[0] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[2] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[3] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal4~2 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~3 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[10] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal2~2 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonARegAddrInc[8]~16 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[2] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[3] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[4] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[5] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[6] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[7] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[0] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[6] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[7] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[8] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[9] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[10] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[11] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[12] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[13] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[14] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[15] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[16] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[17] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[18] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[4] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[2] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[3] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[13] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[14] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[9] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[10] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[11] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[12] ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~5 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~10 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~3 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~0 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_logic~9 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF~2 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[24] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[22] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[23] ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write1 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift~11 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_error ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest~1 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[18] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[19] ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst2 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|r_ena1 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[25] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_ocireg~0 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[26] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[27] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[28] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[29] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[30] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[31] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_wrctl_inst ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_single_step_mode ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[20] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[21] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[5] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_bstatus_reg ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_estatus_reg ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[31] ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid0 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|t_dav ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|ir[0] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|ir[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|enable_action_strobe ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_align_cycle[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_implicit_dst_retaddr~0 ; 3 ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|av_readdatavalid~0 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|read ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|WideOr1 ; 3 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001|src0_valid~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|nios_system_addr_router:addr_router|Equal0~1 ; 3 ; -; nios_system:NiosII|nios_system_addr_router:addr_router|Equal0~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[3] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[22] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[10] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_force_src2_zero ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~2 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|av_waitrequest~2 ; 3 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|write_accepted~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal7~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_getting_data~12 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[5] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[6] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[8] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[10] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[11] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[12] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[13] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[14] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[15] ; 3 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal3~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[17] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[16] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[14] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[13] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[12] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[11] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[8] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; 3 ; -; nios_system:NiosII|nios_system_lcd_on:lcd_blon|data_out ; 3 ; -; nios_system:NiosII|nios_system_lcd_on:lcd_on|data_out ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[24] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[25] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[26] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[27] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[28] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[23] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[29] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[22] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[30] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[21] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[31] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[30] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[19] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[20] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[21] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[22] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[23] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[24] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[25] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[26] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[27] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[28] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[29] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[20] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[0] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|jtag_break ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[19] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[4] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[5] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[6] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[8] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[10] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[11] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[12] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[13] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[14] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[2] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[0] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[6] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[5] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[8] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[13] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[14] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[10] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[11] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[12] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[16] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[17] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[18] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[16] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[17] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[18] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[4] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[2] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[3] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[3] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[2] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[16] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[17] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[5] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~10 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg_proc~0 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~0 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~1 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~0 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~2 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~1 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_wr_dst_reg~4 ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~2 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal4~3 ; 2 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|src_channel[1]~9 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[13] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[9] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[11] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[10] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[12] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[15] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[14] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[7] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[23] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[24] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[25] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[26] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[27] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[28] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[30] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[31] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|resetlatch ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[16] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[17] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[21] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[22] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[10] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[7] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[15] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[14] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[13] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[11] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|always2~0 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate1 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write2 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[19] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[20] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[30]~34 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[20]~33 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[21]~32 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[22]~31 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[23]~30 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[24]~29 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[25]~28 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[26]~27 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[27]~26 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[28]~25 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[29]~24 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[31]~23 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[4] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[2] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[1] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[4] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[2] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[1] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36]~29 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[16] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[19]~22 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_go ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[7] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|rvalid ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[6] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|woverflow ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[4] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ac ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|t_pause~reg0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[23] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read1 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid0~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|always1~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|avalon_ram_wr~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_rd ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_rd ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[7]~7 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[7] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[6]~6 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[5]~5 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[4]~4 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[4] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[3]~3 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[2]~2 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[2] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[1]~1 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[0]~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_wr_en ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|debugaccess ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_wr ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[4] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[2] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jxuir ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[32] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[33] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[18] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[19] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[20] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[21] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[2] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[22] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_fill_bit~0 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[31]~95 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[31] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[30]~92 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[30] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[29]~89 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[29] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[28]~86 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[28] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[27]~83 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[27] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[2] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_readdata[8]~0 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|pause_irq ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_readdata[9] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AE ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_crst ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg_nxt~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|break_on_reset ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_wrctl_status~0 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[26]~80 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[26] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[25]~77 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[25] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[24]~74 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[24] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[23]~71 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[23] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_wrctl_bstatus~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_src1[31] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_src2[31] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_invert_arith_src_msb ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[30]~32 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[1]~31 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[19]~30 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[20]~29 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[21]~28 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[22]~27 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[23]~26 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[24]~25 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[25]~24 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[26]~23 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[27]~22 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[28]~21 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[29]~20 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[31]~19 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[31] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[0]~18 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_compare_op[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_compare_op[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[2]~6 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[4]~5 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3]~4 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[1]~3 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[0]~1 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state~1 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[7] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[9] ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|grant[0]~1 ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|grant[0]~1 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[17]~68 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[17] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[18]~65 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[18] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[19]~62 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[19] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[20]~59 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[20] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[21]~56 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[21] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[18]~21 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[22]~53 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[22] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[10]~50 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[10] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[6]~47 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[6] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[8]~44 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~3 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~2 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_no_crst_nxt[16]~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_jmp_direct~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_stall~5 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_aligning_data_nxt~1 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_waiting_for_data_nxt~0 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[7]~41 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[7] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_force_src2_zero~3 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_break~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~4 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[9]~38 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[9] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[15]~35 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[15] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[16]~32 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[16] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[14]~29 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[14] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[5]~26 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[5] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[12]~23 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[12] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[13]~20 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[13] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[11]~17 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[11] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[2]~14 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[2] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[0]~11 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[0] ; 2 ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter RAM Summary ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ -; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; no ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X64_Y32_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X64_Y34_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 256 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 8192 ; 256 ; 32 ; -- ; -- ; 8192 ; 1 ; nios_system_nios2_processor_ociram_default_contents.mif ; M9K_X51_Y37_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; nios_system_nios2_processor_rf_ram_a.mif ; M9K_X51_Y33_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; nios_system_nios2_processor_rf_ram_b.mif ; M9K_X51_Y34_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 51200 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1638400 ; 51200 ; 32 ; -- ; -- ; 1638400 ; 200 ; nios_system_onchip_memory.hex ; M9K_X37_Y40_N0, M9K_X37_Y37_N0, M9K_X37_Y33_N0, M9K_X15_Y40_N0, M9K_X51_Y41_N0, M9K_X37_Y41_N0, M9K_X37_Y48_N0, M9K_X37_Y52_N0, M9K_X37_Y36_N0, M9K_X37_Y44_N0, M9K_X37_Y42_N0, M9K_X37_Y45_N0, M9K_X51_Y16_N0, M9K_X51_Y15_N0, M9K_X51_Y31_N0, M9K_X37_Y23_N0, M9K_X51_Y28_N0, M9K_X51_Y35_N0, M9K_X15_Y28_N0, M9K_X78_Y25_N0, M9K_X51_Y22_N0, M9K_X37_Y28_N0, M9K_X78_Y21_N0, M9K_X51_Y32_N0, M9K_X64_Y20_N0, M9K_X15_Y30_N0, M9K_X37_Y20_N0, M9K_X37_Y22_N0, M9K_X15_Y24_N0, M9K_X37_Y21_N0, M9K_X51_Y36_N0, M9K_X37_Y25_N0, M9K_X51_Y18_N0, M9K_X37_Y18_N0, M9K_X78_Y24_N0, M9K_X37_Y24_N0, M9K_X78_Y18_N0, M9K_X51_Y27_N0, M9K_X37_Y19_N0, M9K_X51_Y12_N0, M9K_X51_Y14_N0, M9K_X78_Y23_N0, M9K_X78_Y26_N0, M9K_X78_Y16_N0, M9K_X78_Y19_N0, M9K_X64_Y14_N0, M9K_X64_Y19_N0, M9K_X64_Y25_N0, M9K_X51_Y29_N0, M9K_X37_Y31_N0, M9K_X64_Y21_N0, M9K_X78_Y15_N0, M9K_X64_Y15_N0, M9K_X78_Y22_N0, M9K_X51_Y24_N0, M9K_X78_Y17_N0, M9K_X64_Y16_N0, M9K_X64_Y52_N0, M9K_X51_Y21_N0, M9K_X37_Y29_N0, M9K_X51_Y52_N0, M9K_X51_Y17_N0, M9K_X64_Y17_N0, M9K_X51_Y26_N0, M9K_X51_Y30_N0, M9K_X37_Y27_N0, M9K_X37_Y30_N0, M9K_X51_Y25_N0, M9K_X51_Y40_N0, M9K_X51_Y23_N0, M9K_X51_Y20_N0, M9K_X51_Y13_N0, M9K_X64_Y24_N0, M9K_X37_Y26_N0, M9K_X64_Y28_N0, M9K_X51_Y19_N0, M9K_X37_Y58_N0, M9K_X51_Y59_N0, M9K_X51_Y46_N0, M9K_X37_Y59_N0, M9K_X37_Y46_N0, M9K_X78_Y50_N0, M9K_X78_Y20_N0, M9K_X64_Y18_N0, M9K_X51_Y42_N0, M9K_X51_Y43_N0, M9K_X51_Y38_N0, M9K_X64_Y22_N0, M9K_X51_Y63_N0, M9K_X51_Y61_N0, M9K_X51_Y57_N0, M9K_X51_Y60_N0, M9K_X51_Y45_N0, M9K_X51_Y39_N0, M9K_X78_Y63_N0, M9K_X15_Y49_N0, M9K_X51_Y48_N0, M9K_X37_Y47_N0, M9K_X37_Y51_N0, M9K_X37_Y50_N0, M9K_X51_Y50_N0, M9K_X64_Y47_N0, M9K_X78_Y45_N0, M9K_X78_Y52_N0, M9K_X37_Y53_N0, M9K_X78_Y48_N0, M9K_X51_Y54_N0, M9K_X64_Y51_N0, M9K_X64_Y55_N0, M9K_X64_Y56_N0, M9K_X64_Y49_N0, M9K_X64_Y50_N0, M9K_X64_Y54_N0, M9K_X51_Y47_N0, M9K_X78_Y31_N0, M9K_X51_Y53_N0, M9K_X78_Y54_N0, M9K_X64_Y44_N0, M9K_X78_Y32_N0, M9K_X37_Y49_N0, M9K_X51_Y64_N0, M9K_X37_Y56_N0, M9K_X37_Y60_N0, M9K_X37_Y38_N0, M9K_X37_Y61_N0, M9K_X64_Y43_N0, M9K_X78_Y61_N0, M9K_X78_Y41_N0, M9K_X78_Y59_N0, M9K_X78_Y44_N0, M9K_X78_Y39_N0, M9K_X64_Y42_N0, M9K_X78_Y42_N0, M9K_X64_Y36_N0, M9K_X64_Y53_N0, M9K_X78_Y43_N0, M9K_X64_Y57_N0, M9K_X64_Y64_N0, M9K_X64_Y62_N0, M9K_X37_Y57_N0, M9K_X51_Y44_N0, M9K_X37_Y43_N0, M9K_X64_Y39_N0, M9K_X51_Y58_N0, M9K_X37_Y39_N0, M9K_X64_Y26_N0, M9K_X37_Y32_N0, M9K_X37_Y34_N0, M9K_X37_Y35_N0, M9K_X64_Y23_N0, M9K_X51_Y55_N0, M9K_X51_Y56_N0, M9K_X78_Y49_N0, M9K_X37_Y55_N0, M9K_X104_Y38_N0, M9K_X64_Y38_N0, M9K_X78_Y46_N0, M9K_X64_Y48_N0, M9K_X64_Y37_N0, M9K_X64_Y33_N0, M9K_X78_Y29_N0, M9K_X78_Y28_N0, M9K_X64_Y41_N0, M9K_X64_Y60_N0, M9K_X64_Y63_N0, M9K_X78_Y56_N0, M9K_X78_Y37_N0, M9K_X78_Y40_N0, M9K_X64_Y61_N0, M9K_X78_Y38_N0, M9K_X64_Y35_N0, M9K_X64_Y30_N0, M9K_X78_Y33_N0, M9K_X64_Y31_N0, M9K_X78_Y34_N0, M9K_X78_Y36_N0, M9K_X104_Y41_N0, M9K_X78_Y53_N0, M9K_X78_Y55_N0, M9K_X78_Y35_N0, M9K_X64_Y40_N0, M9K_X78_Y57_N0, M9K_X104_Y39_N0, M9K_X64_Y29_N0, M9K_X64_Y27_N0, M9K_X78_Y30_N0, M9K_X78_Y27_N0, M9K_X104_Y32_N0, M9K_X64_Y58_N0, M9K_X64_Y59_N0, M9K_X64_Y45_N0, M9K_X64_Y46_N0, M9K_X51_Y49_N0, M9K_X37_Y54_N0, M9K_X51_Y65_N0, M9K_X51_Y62_N0, M9K_X78_Y51_N0, M9K_X78_Y47_N0, M9K_X51_Y51_N0, M9K_X78_Y62_N0 ; Don't care ; Old data ; Old data ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ -Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. - - -RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; -+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;8;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;16;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;24;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; - - -RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; -+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;8;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;16;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; 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- - -RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 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-;144;(01110000101101011011100001111110) (-387116768) (1890957438) (70B5B87E) ;(00101010001010101110110110001010) (917599316) (707456394) (2A2AED8A) ;(11111001011011001100100010000001) (-644633577) (-110311295) (-6-9-3-3-7-7-15) ;(00000010000110110100100111100001) (206644741) (35342817) (21B49E1) ;(10000110100100010110000000001101) (-691066819) (-2037293043) (-7-9-6-14-9-15-15-3) ;(10110100010111100001110100010010) (797122292) (-1268900590) (-4-11-10-1-14-2-14-14) ;(01100100110110010110010001001110) (-1976188828) (1691968590) (64D9644E) ;(01001000011011001011101011111001) (-1114348277) (1215085305) (486CBAF9) ; -;152;(00111000011010101100111100100000) (-1557387152) (946523936) (386ACF20) ;(00001101000100111000010011010100) (1504702324) (219382996) (D1384D4) ;(01100010010001010101111101110111) (2073773919) (1648713591) (62455F77) ;(10000110011011111101111000100000) (-701569796) (-2039488992) (-7-9-90-2-1-140) ;(00000000011011111110110011101100) (33766354) (7335148) (6FECEC) ;(10010100111010000100010100010100) (1136715590) (-1796717292) (-6-11-1-7-11-10-14-12) ;(01111011101010111100001100110011) (910290519) (2074854195) (7BABC333) ;(10101111101010101000010001000101) (122207975) (-1347779515) (-50-5-5-7-11-11-11) ; -;160;(10110001000101110101111000111010) (475362942) (-1323868614) (-4-14-14-8-10-1-12-6) ;(11100000100011011110011000101001) (560552569) (-527571415) (-1-15-7-2-1-9-13-7) ;(01111111000100101010010100101101) (1262071511) (2131928365) (7F12A52D) ;(00001110001100100010100100001001) (1614424411) (238168329) (E322909) ;(00011000011110000100110111000110) (-1258920590) (410537414) (18784DC6) ;(10110010001110111100110000100000) (586451908) (-1304703968) (-4-13-12-4-3-3-140) ;(00100110011011001001111000110100) (338149768) (644652596) (266C9E34) ;(11001000010101111110101011110011) (1837922177) (-933762317) (-3-7-10-8-1-50-13) ; -;168;(00101010111000111011000101100100) (975763248) (719565156) (2AE3B164) ;(00000011100010101100111100101010) (342547452) (59428650) (38ACF2A) ;(11000001101010111100011000001101) (964899829) (-1045707251) (-3-14-5-4-3-9-15-3) ;(10001010111101111000011110111101) (-59623159) (-1963489347) (-7-50-8-7-8-4-3) ;(00000100001101110010001110101001) (415621651) (70722473) (43723A9) ;(11000011011111001001010100101101) (1149269269) (-1015245523) (-3-12-8-3-6-10-13-3) ;(01101001001110100011011000011111) (-1326017907) (1765422623) (693A361F) ;(11011010010010111000111010011001) (-260103251) (-632582503) (-2-5-11-4-7-1-6-7) ; -;176;(11111011100011111101101100010000) (-434022360) (-74458352) (-4-70-2-4-150) ;(01001101011000110110010111110010) (-616820886) (1298359794) (4D6365F2) ;(01110001001000110101100011101001) (-331796593) (1898141929) (712358E9) ;(10000101110110101110000011111010) (-768766462) (-2049253126) (-7-10-2-5-1-150-6) ;(01111110100000101010010000011000) (1198071086) (2122490904) (7E82A418) ;(11010011010010010011011101101000) (-1160576934) (-750176408) (-2-12-11-6-12-8-9-8) ;(01110011100111000110010111101100) (-95388190) (1939629548) (739C65EC) ;(01110011101101100110101100011001) (-86985513) (1941334809) (73B66B19) ; -;184;(00100010000101000010100000010110) (-89943270) (571746326) (22142816) ;(11111111010010011000001100100010) (-55476336) (-11959518) (-11-6-7-12-13-14) ;(00110010011001100100100101011110) (1936477240) (845564254) (3266495E) ;(11100010011011101000001000010100) (750690542) (-496074220) (-1-13-9-1-7-13-14-12) ;(11001000110001000111000100110001) (1873227275) (-926650063) (-3-7-3-11-8-14-12-15) ;(01100110000001111001001111011000) (-1840739214) (1711772632) (660793D8) ;(01101000100111111000110101101001) (-1394744393) (1755286889) (689F8D69) ;(11111010101011100011010000001011) (-524345765) (-89246709) (-5-5-1-12-11-15-5) ; -;192;(00110111010100011000101110100111) (-1865628945) (928091047) (37518BA7) ;(11110010100001100101111111100101) (-1536320033) (-226074651) (-13-7-9-100-1-11) ;(00011011101101000100111100111101) (-939919821) (464801597) (1BB44F3D) ;(00111011110011100100010011000101) (-1226492287) (1003373765) (3BCE44C5) ;(10101111111100101101000110001000) (144256478) (-1343041144) (-500-13-2-14-7-8) ;(10011000010101000100001011011010) (1689714498) (-1739308326) (-6-7-10-11-11-13-2-6) ;(10000101101110110101100010111101) (-778672559) (-2051319619) (-7-10-4-4-10-7-4-3) ;(00001100010100110001001101011101) (1424611535) (206771037) (C53135D) ; -;200;(01001001010111111000000010111100) (-1019783374) (1230995644) (495F80BC) ;(10000101001111001001010111011100) (-818214100) (-2059627044) (-7-10-12-3-6-10-2-4) ;(11011101111010010011011111110001) (89423279) (-571918351) (-2-2-1-6-12-80-15) ;(01000001100011111001010001010010) (-2003771526) (1099928658) (418F9452) ;(01110110011010010110010000011100) (189811090) (1986618396) (7669641C) ;(00001110011101010010010000110100) (1635222064) (242558004) (E752434) ;(10110000111111100001011110100111) (447119517) (-1325525081) (-4-150-1-14-8-5-9) ;(11010001101111101001101110001000) (-1325294874) (-776037496) (-2-14-4-1-6-4-7-8) ; -;208;(11001111101111111110101101110110) (-1725044916) (-809505930) (-30-40-1-4-8-10) ;(10000000101101001000101000010001) (-1280221813) (-2135651823) (-7-15-4-11-7-5-14-15) ;(10010011001001111100011010011110) (976416402) (-1826109794) (-6-12-13-8-3-9-6-2) ;(10111110110010100101101010001000) (2032161078) (-1094034808) (-4-1-3-5-10-5-7-8) ;(11100111000111010100001010001111) (1224430735) (-417512817) (-1-8-14-2-11-13-7-1) ;(10110011000110001101001001110101) (675857035) (-1290218891) (-4-12-14-7-2-13-8-11) ;(01010110111111101010001101011110) (530037888) (1459528542) (56FEA35E) ;(00010100000011001101011010111101) (-1891814021) (336385725) (140CD6BD) ; -;216;(10111000110010010011011111001110) (1431939586) (-1194772530) (-4-7-3-6-12-8-3-2) ;(01010100000011101110101000110110) (256081418) (1410263606) (540EEA36) ;(11101110010110001111110001111111) (2143365695) (-296158081) (-1-1-10-70-3-8-1) ;(01010110000101011100001110001001) (457857963) (1444266889) (5615C389) ;(01000110011010010010101011010000) (-1515258328) (1181297360) (46692AD0) ;(01011100011100010011111001010001) (1286753473) (1550925393) (5C713E51) ;(01101011101010010101111101100000) (-1090193404) (1806262112) (6BA95F60) ;(00001110000101100110011100110010) (1605463462) (236349234) (E166732) ; -;224;(10101100000011100100100111110101) (-226849365) (-1408349707) (-5-3-15-1-11-60-11) ;(11001001101001011110101001110110) (1963521980) (-911873418) (-3-6-5-10-1-5-8-10) ;(00000101101100000100110110000110) (554046606) (95440262) (5B04D86) ;(10110010100110101100011100010010) (616249292) (-1298479342) (-4-13-6-5-3-8-14-14) ;(01001110001101000100010010010011) (-532441425) (1312048275) (4E344493) ;(11010100010111101101111001001000) (-1055253374) (-731980216) (-2-11-10-1-2-1-11-8) ;(00111101101001111110010000100110) (-1038172546) (1034413094) (3DA7E426) ;(01001101011010101000100100110111) (-614979181) (1298827575) (4D6A8937) ; -;232;(10011001101101011001101111010100) (1819988890) (-1716151340) (-6-6-4-10-6-4-2-12) ;(00011111100010100101011101010001) (-552513775) (529160017) (1F8A5751) ;(10001011000001111110011001001110) (-33563718) (-1962416562) (-7-4-15-8-1-9-11-2) ;(10110100110111001101010010010110) (836858096) (-1260596074) (-4-11-2-3-2-11-6-10) ;(01000010111110000100111111100110) (-1871435902) (1123569638) (42F84FE6) ;(11110001110101011001010100101111) (-1612465321) (-237660881) (-14-2-10-6-10-13-1) ;(10100010111001011010010000101101) (-1358972075) (-1562008531) (-5-13-1-10-5-11-13-3) ;(00010101101100011010111100010110) (-1740639870) (363966230) (15B1AF16) ; -;240;(00010110100000000001001010111100) (-1654956022) (377492156) (168012BC) ;(00101110001001110110011000010010) (1316695726) (774333970) (2E276612) ;(10001001100100010011111010101010) (-191089582) (-1986969942) (-7-6-6-14-12-1-5-6) ;(11000110000001111010000110100010) (1413877456) (-972578398) (-3-9-15-8-5-14-5-14) ;(11111101100010110101010001001101) (-235125663) (-41200563) (-2-7-4-10-11-11-3) ;(10101110110000110001101001010011) (30320993) (-1362945453) (-5-1-3-12-14-5-10-13) ;(00100101111110010101100010101101) (281286959) (637098157) (25F958AD) ;(00110110010110010000001111101100) (-1963732838) (911803372) (365903EC) ; -;248;(00010100011101100001100001100101) (-1859553151) (343283813) (14761865) ;(01010110100011001100001000111011) (495657425) (1452065339) (568CC23B) ;(10110000001110000110001100000101) (385767275) (-1338481915) (-4-15-12-7-9-12-15-11) ;(11111011100111101011110110001010) (-430241166) (-73482870) (-4-6-1-4-2-7-6) ;(10100010010110010001000111010100) (-1404083406) (-1571221036) (-5-13-10-6-14-14-2-12) ;(10000000011011100011111110111011) (-1301889161) (-2140258373) (-7-15-9-1-120-4-5) ;(10011101111100110101001001100100) (-2055642986) (-1644998044) (-6-20-12-10-13-9-12) ;(11010110001010110011100000010100) (-870176458) (-701810668) (-2-9-13-4-12-7-14-12) ; - - -+-------------------------------------------------------+ -; Other Routing Usage Summary ; -+-----------------------------+-------------------------+ -; Other Routing Resource Type ; Usage ; -+-----------------------------+-------------------------+ -; Block interconnects ; 6,699 / 342,891 ( 2 % ) ; -; C16 interconnects ; 370 / 10,120 ( 4 % ) ; -; C4 interconnects ; 4,207 / 209,544 ( 2 % ) ; -; Direct links ; 319 / 342,891 ( < 1 % ) ; -; Global clocks ; 4 / 20 ( 20 % ) ; -; Local interconnects ; 1,216 / 119,088 ( 1 % ) ; -; R24 interconnects ; 466 / 9,963 ( 5 % ) ; -; R4 interconnects ; 4,336 / 289,782 ( 1 % ) ; -+-----------------------------+-------------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB Logic Elements ; -+---------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 13.96) ; Number of LABs (Total = 160) ; -+---------------------------------------------+-------------------------------+ -; 1 ; 1 ; -; 2 ; 4 ; -; 3 ; 1 ; -; 4 ; 1 ; -; 5 ; 1 ; -; 6 ; 4 ; -; 7 ; 1 ; -; 8 ; 2 ; -; 9 ; 3 ; -; 10 ; 2 ; -; 11 ; 4 ; -; 12 ; 7 ; -; 13 ; 4 ; -; 14 ; 16 ; -; 15 ; 29 ; -; 16 ; 80 ; -+---------------------------------------------+-------------------------------+ - - -+--------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 2.25) ; Number of LABs (Total = 160) ; -+------------------------------------+-------------------------------+ -; 1 Async. clear ; 113 ; -; 1 Clock ; 136 ; -; 1 Clock enable ; 58 ; -; 1 Sync. clear ; 6 ; -; 1 Sync. load ; 28 ; -; 2 Async. clears ; 2 ; -; 2 Clock enables ; 10 ; -; 2 Clocks ; 7 ; -+------------------------------------+-------------------------------+ - - -+------------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 21.06) ; Number of LABs (Total = 160) ; -+----------------------------------------------+-------------------------------+ -; 0 ; 1 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 2 ; -; 5 ; 2 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 1 ; -; 10 ; 1 ; -; 11 ; 3 ; -; 12 ; 3 ; -; 13 ; 1 ; -; 14 ; 2 ; -; 15 ; 4 ; -; 16 ; 16 ; -; 17 ; 6 ; -; 18 ; 6 ; -; 19 ; 5 ; -; 20 ; 12 ; -; 21 ; 7 ; -; 22 ; 8 ; -; 23 ; 10 ; -; 24 ; 12 ; -; 25 ; 18 ; -; 26 ; 8 ; -; 27 ; 11 ; -; 28 ; 9 ; -; 29 ; 3 ; -; 30 ; 1 ; -; 31 ; 1 ; -; 32 ; 5 ; -+----------------------------------------------+-------------------------------+ - - -+---------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 8.65) ; Number of LABs (Total = 160) ; -+-------------------------------------------------+-------------------------------+ -; 0 ; 1 ; -; 1 ; 1 ; -; 2 ; 7 ; -; 3 ; 5 ; -; 4 ; 24 ; -; 5 ; 6 ; -; 6 ; 16 ; -; 7 ; 10 ; -; 8 ; 15 ; -; 9 ; 10 ; -; 10 ; 14 ; -; 11 ; 7 ; -; 12 ; 11 ; -; 13 ; 7 ; -; 14 ; 10 ; -; 15 ; 2 ; -; 16 ; 10 ; -; 17 ; 1 ; -; 18 ; 0 ; -; 19 ; 0 ; -; 20 ; 0 ; -; 21 ; 2 ; -; 22 ; 0 ; -; 23 ; 1 ; -+-------------------------------------------------+-------------------------------+ - - -+------------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 18.74) ; Number of LABs (Total = 160) ; -+----------------------------------------------+-------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 1 ; -; 3 ; 3 ; -; 4 ; 2 ; -; 5 ; 5 ; -; 6 ; 2 ; -; 7 ; 4 ; -; 8 ; 0 ; -; 9 ; 3 ; -; 10 ; 2 ; -; 11 ; 4 ; -; 12 ; 5 ; -; 13 ; 5 ; -; 14 ; 6 ; -; 15 ; 7 ; -; 16 ; 6 ; -; 17 ; 6 ; -; 18 ; 14 ; -; 19 ; 9 ; -; 20 ; 7 ; -; 21 ; 10 ; -; 22 ; 5 ; -; 23 ; 5 ; -; 24 ; 6 ; -; 25 ; 7 ; -; 26 ; 12 ; -; 27 ; 7 ; -; 28 ; 3 ; -; 29 ; 3 ; -; 30 ; 2 ; -; 31 ; 2 ; -; 32 ; 0 ; -; 33 ; 4 ; -; 34 ; 2 ; -+----------------------------------------------+-------------------------------+ - - -+------------------------------------------+ -; I/O Rules Summary ; -+----------------------------------+-------+ -; I/O Rules Statistic ; Total ; -+----------------------------------+-------+ -; Total I/O Rules ; 30 ; -; Number of I/O Rules Passed ; 12 ; -; Number of I/O Rules Failed ; 0 ; -; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 18 ; -+----------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Details ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; -; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; -; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; -; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; -; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; -; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; -; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; -; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Matrix ; -+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; -+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Total Pass ; 118 ; 0 ; 118 ; 0 ; 0 ; 122 ; 118 ; 0 ; 122 ; 122 ; 0 ; 49 ; 0 ; 0 ; 31 ; 0 ; 49 ; 31 ; 0 ; 0 ; 0 ; 49 ; 0 ; 0 ; 0 ; 0 ; 0 ; 122 ; 0 ; 0 ; -; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 4 ; 122 ; 4 ; 122 ; 122 ; 0 ; 4 ; 122 ; 0 ; 0 ; 122 ; 73 ; 122 ; 122 ; 91 ; 122 ; 73 ; 91 ; 122 ; 122 ; 122 ; 73 ; 122 ; 122 ; 122 ; 122 ; 122 ; 0 ; 122 ; 122 ; -; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; LEDG[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_RS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_RW ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_EN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_ON ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_BLON ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; KEY[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; KEY[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; altera_reserved_tms ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; altera_reserved_tck ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; altera_reserved_tdi ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; altera_reserved_tdo ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ - - -+---------------------------------------------------------------------------------------------+ -; Fitter Device Options ; -+------------------------------------------------------------------+--------------------------+ -; Option ; Setting ; -+------------------------------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; Enable open drain on CRC_ERROR pin ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; -; Configuration Voltage Level ; Auto ; -; Force Configuration Voltage Level ; Off ; -; nCEO ; As output driving ground ; -; Data[0] ; As input tri-stated ; -; Data[1]/ASDO ; As input tri-stated ; -; Data[7..2] ; Unreserved ; -; FLASH_nCE/nCSO ; As input tri-stated ; -; Other Active Parallel pins ; Unreserved ; -; DCLK ; As output driving ground ; -; Base pin-out file on sameframe device ; Off ; -+------------------------------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 �C ; -; High Junction Temperature ; 85 �C ; -+---------------------------+--------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (119006): Selected device EP4CE115F29C7 for design "lights" -Info (21077): Core supply voltage is 1.2V -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. -Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info (176445): Device EP4CE40F29C7 is compatible - Info (176445): Device EP4CE40F29I7 is compatible - Info (176445): Device EP4CE30F29C7 is compatible - Info (176445): Device EP4CE30F29I7 is compatible - Info (176445): Device EP4CE55F29C7 is compatible - Info (176445): Device EP4CE55F29I7 is compatible - Info (176445): Device EP4CE75F29C7 is compatible - Info (176445): Device EP4CE75F29I7 is compatible - Info (176445): Device EP4CE115F29I7 is compatible -Info (169124): Fitter converted 5 user pins into dedicated programming pins - Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4 - Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 - Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3 - Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7 - Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28 -Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. -Info (332164): Evaluating HDL-embedded SDC commands - Info (332165): Entity alt_jtag_atlantic - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] - Info (332165): Entity altera_std_synchronizer - Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] - Info (332165): Entity sld_jtag_hub - Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz - Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} -Critical Warning (332012): Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. -Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) -Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements -Info (332111): Found 1 clocks - Info (332111): Period Clock Name - Info (332111): ======== ============ - Info (332111): 100.000 altera_reserved_tck -Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 -Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock -Info (176353): Automatically promoted node nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock - Info (176356): Following destination nodes may be non-global or may not use global or regional clocks - Info (176357): Destination node nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 - Info (176357): Destination node nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren - Info (176357): Destination node nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 -Info (176353): Automatically promoted node nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock -Info (176233): Starting register packing -Info (176235): Finished register packing - Extra Info (176218): Packed 8 registers into blocks of type EC -Warning (15709): Ignored I/O standard assignments to the following nodes - Warning (15710): Ignored I/O standard assignment to node "AUD_ADCDAT" - Warning (15710): Ignored I/O standard assignment to node "AUD_ADCLRCK" - Warning (15710): Ignored I/O standard assignment to node "AUD_BCLK" - Warning (15710): Ignored I/O standard assignment to node "AUD_DACDAT" - Warning (15710): Ignored I/O standard assignment to node "AUD_DACLRCK" - Warning (15710): Ignored I/O standard assignment to node "AUD_XCK" - Warning (15710): Ignored I/O standard assignment to node "CLOCK2_50" - Warning (15710): Ignored I/O standard assignment to node "CLOCK3_50" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[10]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[11]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[12]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[2]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[3]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[4]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[5]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[6]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[7]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[8]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[9]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_BA[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_BA[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CAS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CKE" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CLK" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[2]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[3]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[10]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[11]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[12]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[13]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[14]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[15]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[16]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[17]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[18]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[19]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[20]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[21]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[22]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[23]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[24]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[25]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[26]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[27]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[28]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[29]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[2]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[30]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[31]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[3]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[4]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[5]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[6]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[7]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[8]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[9]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_RAS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_WE_N" - Warning (15710): Ignored I/O standard assignment to node "EEP_I2C_SCLK" - Warning (15710): Ignored I/O standard assignment to node "EEP_I2C_SDAT" - Warning (15710): Ignored I/O standard assignment to node "ENET0_GTX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET0_INT_N" - Warning (15710): Ignored I/O standard assignment to node "ENET0_LINK100" - Warning (15710): Ignored I/O standard assignment to node "ENET0_MDC" - Warning (15710): Ignored I/O standard assignment to node "ENET0_MDIO" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RST_N" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_COL" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_CRS" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DV" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_ER" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_EN" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_ER" - Warning (15710): Ignored I/O standard assignment to node "ENET1_GTX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET1_INT_N" - Warning (15710): Ignored I/O standard assignment to node "ENET1_LINK100" - Warning (15710): Ignored I/O standard assignment to node "ENET1_MDC" - Warning (15710): Ignored I/O standard assignment to node "ENET1_MDIO" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RST_N" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_COL" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_CRS" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DV" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_ER" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_EN" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_ER" - Warning (15710): Ignored I/O standard assignment to node "ENETCLK_25" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[0]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[1]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[2]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[3]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[4]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[5]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[6]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[10]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[11]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[12]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[13]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[14]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[15]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[16]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[17]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[18]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[19]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[20]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[21]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[22]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[2]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[3]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[4]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[5]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[6]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[7]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[8]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[9]" - Warning (15710): Ignored I/O standard assignment to node "FL_CE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[0]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[1]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[2]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[3]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[4]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[5]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[6]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[7]" - Warning (15710): Ignored I/O standard assignment to node "FL_OE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_RST_N" - Warning (15710): Ignored I/O standard assignment to node "FL_RY" - Warning (15710): Ignored I/O standard assignment to node "FL_WE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_WP_N" - Warning (15710): Ignored I/O standard assignment to node "GPIO[0]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[10]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[11]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[12]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[13]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[14]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[15]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[16]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[17]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[18]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[19]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[1]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[20]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[21]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[22]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[23]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[24]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[25]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[26]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[27]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[28]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[29]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[2]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[30]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[31]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[32]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[33]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[34]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[35]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[3]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[4]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[5]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[6]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[7]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[8]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[9]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN0" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_N1" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_N2" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_P1" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_P2" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT0" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_N1" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_N2" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_P1" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_P2" - Warning (15710): Ignored I/O standard assignment to node "HSMC_D[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_D[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_D[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_D[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[10]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[11]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[12]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[13]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[14]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[15]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[16]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[4]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[5]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[6]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[7]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[8]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[9]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[10]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[11]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[12]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[13]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[14]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[15]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[16]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[4]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[5]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[6]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[7]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[8]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[9]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[10]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[11]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[12]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[13]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[14]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[15]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[16]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[4]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[5]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[6]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[7]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[8]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[9]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[10]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[11]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[12]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[13]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[14]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[15]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[16]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[4]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[5]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[6]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[7]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[8]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[9]" - Warning (15710): Ignored I/O standard assignment to node "I2C_SCLK" - Warning (15710): Ignored I/O standard assignment to node "I2C_SDAT" - Warning (15710): Ignored I/O standard assignment to node "IRDA_RXD" - Warning (15710): Ignored I/O standard assignment to node "LEDG[8]" - Warning (15710): Ignored I/O standard assignment to node "OTG_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_CS_N" - Warning (15710): Ignored I/O standard assignment to node "OTG_DACK_N[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DACK_N[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[10]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[11]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[12]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[13]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[14]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[15]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[4]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[5]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[6]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[7]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[8]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[9]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DREQ[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DREQ[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_FSPEED" - Warning (15710): Ignored I/O standard assignment to node "OTG_INT[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_INT[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_LSPEED" - Warning (15710): Ignored I/O standard assignment to node "OTG_RD_N" - Warning (15710): Ignored I/O standard assignment to node "OTG_RST_N" - Warning (15710): Ignored I/O standard assignment to node "OTG_WR_N" - Warning (15710): Ignored I/O standard assignment to node "PS2_CLK" - Warning (15710): Ignored I/O standard assignment to node "PS2_CLK2" - Warning (15710): Ignored I/O standard assignment to node "PS2_DAT" - Warning (15710): Ignored I/O standard assignment to node "PS2_DAT2" - Warning (15710): Ignored I/O standard assignment to node "SD_CLK" - Warning (15710): Ignored I/O standard assignment to node "SD_CMD" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT[0]" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT[1]" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT[2]" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT[3]" - Warning (15710): Ignored I/O standard assignment to node "SD_WP_N" - Warning (15710): Ignored I/O standard assignment to node "SMA_CLKIN" - Warning (15710): Ignored I/O standard assignment to node "SMA_CLKOUT" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[10]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[11]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[12]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[13]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[14]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[15]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[16]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[17]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[18]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[19]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[2]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[3]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[4]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[5]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[6]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[7]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[8]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[9]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_CE_N" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[0]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[10]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[11]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[12]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[13]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[14]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[15]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[1]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[2]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[3]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[4]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[5]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[6]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[7]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[8]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[9]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_LB_N" - Warning (15710): Ignored I/O standard assignment to node "SRAM_OE_N" - Warning (15710): Ignored I/O standard assignment to node "SRAM_UB_N" - Warning (15710): Ignored I/O standard assignment to node "SRAM_WE_N" - Warning (15710): Ignored I/O standard assignment to node "TD_CLK27" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[4]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[5]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[6]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[7]" - Warning (15710): Ignored I/O standard assignment to node "TD_HS" - Warning (15710): Ignored I/O standard assignment to node "TD_RESET_N" - Warning (15710): Ignored I/O standard assignment to node "TD_VS" - Warning (15710): Ignored I/O standard assignment to node "UART_CTS" - Warning (15710): Ignored I/O standard assignment to node "UART_RTS" - Warning (15710): Ignored I/O standard assignment to node "UART_RXD" - Warning (15710): Ignored I/O standard assignment to node "UART_TXD" - Warning (15710): Ignored I/O standard assignment to node "VGA_BLANK_N" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[0]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[1]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[2]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[3]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[4]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[5]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[6]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[7]" - Warning (15710): Ignored I/O standard assignment to node "VGA_CLK" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[0]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[1]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[2]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[3]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[4]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[5]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[6]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[7]" - Warning (15710): Ignored I/O standard assignment to node "VGA_HS" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[0]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[1]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[2]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[3]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[4]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[5]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[6]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[7]" - Warning (15710): Ignored I/O standard assignment to node "VGA_SYNC_N" - Warning (15710): Ignored I/O standard assignment to node "VGA_VS" -Warning (15705): Ignored locations or region assignments to the following nodes - Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design - Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design - Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design - Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DACK_N[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DACK_N[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DREQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_FSPEED" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_INT[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_INT[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_LSPEED" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design - Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:08 -Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02 -Info (170191): Fitter placement operations beginning -Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 -Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 2% of the available device resources - Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X46_Y24 to location X57_Y36 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:04 -Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info (170201): Optimizations that may affect the design's routability were skipped - Info (170200): Optimizations that may affect the design's timing were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds. -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03 -Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Warning (169177): 9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. - Info (169178): Pin LCD_data[0] uses I/O standard 3.3-V LVTTL at L3 - Info (169178): Pin LCD_data[1] uses I/O standard 3.3-V LVTTL at L1 - Info (169178): Pin LCD_data[2] uses I/O standard 3.3-V LVTTL at L2 - Info (169178): Pin LCD_data[3] uses I/O standard 3.3-V LVTTL at K7 - Info (169178): Pin LCD_data[4] uses I/O standard 3.3-V LVTTL at K1 - Info (169178): Pin LCD_data[5] uses I/O standard 3.3-V LVTTL at K2 - Info (169178): Pin LCD_data[6] uses I/O standard 3.3-V LVTTL at M3 - Info (169178): Pin LCD_data[7] uses I/O standard 3.3-V LVTTL at M5 - Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2 -Info (144001): Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg -Info: Quartus II 64-Bit Fitter was successful. 0 errors, 827 warnings - Info: Peak virtual memory: 1017 megabytes - Info: Processing ended: Thu Dec 22 10:08:33 2016 - Info: Elapsed time: 00:00:39 - Info: Total CPU time (on all processors): 00:00:38 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg. - - diff --git a/output_files/lights.flow.rpt b/output_files/lights.flow.rpt deleted file mode 100644 index 4a97568..0000000 --- a/output_files/lights.flow.rpt +++ /dev/null @@ -1,123 +0,0 @@ -Flow report for lights -Thu Dec 22 10:08:48 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - 8. Flow Messages - 9. Flow Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+--------------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Thu Dec 22 10:08:41 2016 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; lights ; -; Top-level Entity Name ; lights ; -; Family ; Cyclone IV E ; -; Device ; EP4CE115F29C7 ; -; Timing Models ; Final ; -; Total logic elements ; 2,234 / 114,480 ( 2 % ) ; -; Total combinational functions ; 2,060 / 114,480 ( 2 % ) ; -; Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; -; Total registers ; 1204 ; -; Total pins ; 118 / 529 ( 22 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; -; Total PLLs ; 0 / 4 ( 0 % ) ; -+------------------------------------+-------------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 12/22/2016 10:07:13 ; -; Main task ; Compilation ; -; Revision Name ; lights ; -+-------------------+---------------------+ - - -+------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+-------------------------------------+---------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+-------------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 224508679122295.148236883301196 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -+-------------------------------------+---------------------------------+---------------+-------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:38 ; 1.0 ; 657 MB ; 00:00:35 ; -; Fitter ; 00:00:36 ; 1.0 ; 1017 MB ; 00:00:35 ; -; Assembler ; 00:00:07 ; 1.0 ; 481 MB ; 00:00:07 ; -; TimeQuest Timing Analyzer ; 00:00:06 ; 1.0 ; 605 MB ; 00:00:06 ; -; Total ; 00:01:27 ; -- ; -- ; 00:01:23 ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; -; Fitter ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; -; Assembler ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; -; TimeQuest Timing Analyzer ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; -+---------------------------+------------------+-----------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off lights -c lights -quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights -quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights -quartus_sta lights -c lights - - - diff --git a/output_files/lights.map.rpt b/output_files/lights.map.rpt deleted file mode 100644 index 4e13598..0000000 --- a/output_files/lights.map.rpt +++ /dev/null @@ -1,7187 +0,0 @@ -Analysis & Synthesis report for lights -Thu Dec 22 10:07:53 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Parallel Compilation - 5. Analysis & Synthesis Source Files Read - 6. Analysis & Synthesis Resource Usage Summary - 7. Analysis & Synthesis Resource Utilization by Entity - 8. Analysis & Synthesis RAM Summary - 9. State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize - 10. Registers Protected by Synthesis - 11. Registers Removed During Synthesis - 12. Removed Registers Triggering Further Register Optimizations - 13. General Register Statistics - 14. Inverted Register Statistics - 15. Multiplexer Restructuring Statistics (Restructuring Performed) - 16. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated - 17. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated - 18. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer - 19. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated - 20. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 - 21. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 - 22. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 - 23. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 - 24. Source assignments for nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated - 25. Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 - 26. Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 - 27. Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller - 28. Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 - 29. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux - 30. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 - 31. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux - 32. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 - 33. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 - 34. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 - 35. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 - 36. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 - 37. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 - 38. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 - 39. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 - 40. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 - 41. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 - 42. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 - 43. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 - 44. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 - 45. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 - 46. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 - 47. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 - 48. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 - 49. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a - 50. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram - 51. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b - 52. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram - 53. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer - 54. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram - 55. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram - 56. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 - 57. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 - 58. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 - 59. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 - 60. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy - 61. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory - 62. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram - 63. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo - 64. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo - 65. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator - 66. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator - 67. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator - 68. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator - 69. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator - 70. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator - 71. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator - 72. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator - 73. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator - 74. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator - 75. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator - 76. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator - 77. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator - 78. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator - 79. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator - 80. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator - 81. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator - 82. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator - 83. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator - 84. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator - 85. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent - 86. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent - 87. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent - 88. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor - 89. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo - 90. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent - 91. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor - 92. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo - 93. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent - 94. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor - 95. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo - 96. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent - 97. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor - 98. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo - 99. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent -100. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -101. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -102. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent -103. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -104. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -105. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent -106. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -107. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -108. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent -109. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -110. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -111. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent -112. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -113. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -114. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent -115. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -116. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -117. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent -118. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -119. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -120. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent -121. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -122. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -123. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent -124. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -125. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -126. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent -127. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -128. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -129. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent -130. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -131. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -132. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent -133. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -134. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo -135. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent -136. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -137. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -138. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent -139. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -140. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -141. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode -142. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode -143. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode -144. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode -145. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode -146. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode -147. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode -148. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode -149. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode -150. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode -151. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode -152. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode -153. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode -154. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode -155. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode -156. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode -157. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode -158. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode -159. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode -160. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode -161. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller -162. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -163. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb -164. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -165. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb -166. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -167. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb -168. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -169. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb -170. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -171. altsyncram Parameter Settings by Entity Instance -172. scfifo Parameter Settings by Entity Instance -173. Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -174. Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -175. Port Connectivity Checks: "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -176. Port Connectivity Checks: "nios_system:NiosII|altera_reset_controller:rst_controller" -177. Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" -178. Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" -179. Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" -180. Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" -181. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -182. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent" -183. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -184. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent" -185. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" -186. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent" -187. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -188. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent" -189. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -190. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent" -191. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -192. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent" -193. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -194. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent" -195. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -196. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent" -197. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -198. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent" -199. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -200. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent" -201. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -202. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent" -203. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -204. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent" -205. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -206. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent" -207. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -208. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent" -209. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" -210. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent" -211. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -212. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent" -213. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -214. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent" -215. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -216. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -217. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" -218. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -219. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator" -220. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator" -221. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" -222. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator" -223. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator" -224. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator" -225. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator" -226. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator" -227. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator" -228. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator" -229. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator" -230. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator" -231. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator" -232. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator" -233. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" -234. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" -235. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" -236. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" -237. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" -238. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" -239. Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" -240. Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" -241. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" -242. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4" -243. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3" -244. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" -245. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" -246. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" -247. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" -248. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" -249. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" -250. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" -251. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" -252. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" -253. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" -254. Port Connectivity Checks: "nios_system:NiosII" -255. Elapsed Time Per Partition -256. Analysis & Synthesis Messages -257. Analysis & Synthesis Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+--------------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Dec 22 10:07:53 2016 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; lights ; -; Top-level Entity Name ; lights ; -; Family ; Cyclone IV E ; -; Total logic elements ; 2,331 ; -; Total combinational functions ; 2,056 ; -; Dedicated logic registers ; 1,212 ; -; Total registers ; 1212 ; -; Total pins ; 118 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 1,649,664 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+-------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP4CE115F29C7 ; ; -; Top-level entity name ; lights ; lights ; -; Family name ; Cyclone IV E ; Cyclone IV GX ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; Parallel Synthesis ; On ; On ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto DSP Block Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM Block Balancing ; On ; On ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; On ; On ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Pre-Mapping Resynthesis Optimization ; Off ; Off ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -; Resource Aware Inference For Block RAM ; On ; On ; -; Synthesis Seed ; 1 ; 1 ; -+----------------------------------------------------------------------------+--------------------+--------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; lights.vhd ; yes ; User VHDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd ; ; -; nios_system/synthesis/nios_system.v ; yes ; User Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v ; ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v ; altera_reserved_qsys_nios_system ; -; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ; ; -; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; -; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc ; ; -; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; -; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ; -; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; -; altrom.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altrom.inc ; ; -; altram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altram.inc ; ; -; altdpram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc ; ; -; db/altsyncram_0rh1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf ; ; -; db/altsyncram_1rh1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf ; ; -; altera_std_synchronizer.v ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v ; ; -; db/altsyncram_4891.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf ; ; -; sld_virtual_jtag_basic.v ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v ; ; -; db/altsyncram_4ed1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf ; ; -; db/decode_qsa.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf ; ; -; db/mux_nob.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf ; ; -; scfifo.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf ; ; -; a_regfifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_regfifo.inc ; ; -; a_dpfifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_dpfifo.inc ; ; -; a_i2fifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_i2fifo.inc ; ; -; a_fffifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_fffifo.inc ; ; -; a_f2fifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_f2fifo.inc ; ; -; db/scfifo_jr21.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf ; ; -; db/a_dpfifo_q131.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf ; ; -; db/a_fefifo_7cf.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf ; ; -; db/cntr_do7.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf ; ; -; db/dpram_nl21.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf ; ; -; db/altsyncram_r1m1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf ; ; -; db/cntr_1ob.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf ; ; -; alt_jtag_atlantic.v ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v ; ; -; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd ; ; -; sld_jtag_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd ; ; -; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ; -+---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ - - -+--------------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+----------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------+ -; Estimated Total logic elements ; 2,331 ; -; ; ; -; Total combinational functions ; 2056 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1077 ; -; -- 3 input functions ; 678 ; -; -- <=2 input functions ; 301 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 1909 ; -; -- arithmetic mode ; 147 ; -; ; ; -; Total registers ; 1212 ; -; -- Dedicated logic registers ; 1212 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 118 ; -; Total memory bits ; 1649664 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Maximum fan-out node ; CLOCK_50~input ; -; Maximum fan-out ; 1365 ; -; Total fan-out ; 16737 ; -; Average fan-out ; 4.35 ; -+---------------------------------------------+----------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; |lights ; 2056 (1) ; 1212 (0) ; 1649664 ; 0 ; 0 ; 0 ; 118 ; 0 ; |lights ; work ; -; |nios_system:NiosII| ; 1897 (0) ; 1115 (0) ; 1649664 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII ; work ; -; |altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 8 (8) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_translator:nios2_processor_data_master_translator| ; 9 (9) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_translator:nios2_processor_instruction_master_translator| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex0_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex1_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex2_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex3_s1_translator| ; 5 (5) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex4_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex5_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex6_s1_translator| ; 5 (5) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex7_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator| ; 9 (9) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_16207_0_control_slave_translator| ; 14 (14) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_blon_s1_translator| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_on_s1_translator| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:ledrs_s1_translator| ; 6 (6) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:leds_s1_translator| ; 5 (5) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator| ; 1 (1) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:onchip_memory_s1_translator| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:push_switches_s1_translator| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:switches_s1_translator| ; 6 (6) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_reset_controller:rst_controller| ; 2 (2) ; 9 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller ; altera_reserved_qsys_nios_system ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reserved_qsys_nios_system ; -; |nios_system_LEDRs:ledrs| ; 20 (20) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_LEDRs:ledrs ; altera_reserved_qsys_nios_system ; -; |nios_system_LEDs:leds| ; 11 (11) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_LEDs:leds ; altera_reserved_qsys_nios_system ; -; |nios_system_addr_router:addr_router| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_addr_router:addr_router ; altera_reserved_qsys_nios_system ; -; |nios_system_addr_router_001:addr_router_001| ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:cmd_xbar_demux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_mux:cmd_xbar_mux_001| ; 60 (56) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 ; altera_reserved_qsys_nios_system ; -; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_mux:cmd_xbar_mux| ; 54 (50) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux ; altera_reserved_qsys_nios_system ; -; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex0| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex0 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex1| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex1 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex2| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex2 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex3| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex3 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex4| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex4 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex5| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex5 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex6| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex6 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex7| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex7 ; altera_reserved_qsys_nios_system ; -; |nios_system_jtag_uart:jtag_uart| ; 140 (36) ; 112 (13) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart ; altera_reserved_qsys_nios_system ; -; |alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic| ; 53 (53) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic ; work ; -; |nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r ; altera_reserved_qsys_nios_system ; -; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; work ; -; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; work ; -; |a_dpfifo_q131:dpfifo| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; -; |a_fefifo_7cf:fifo_state| ; 14 (8) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; -; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; -; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; -; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; -; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; -; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; -; |nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w ; altera_reserved_qsys_nios_system ; -; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; work ; -; |scfifo_jr21:auto_generated| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ; work ; -; |a_dpfifo_q131:dpfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; -; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; -; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; -; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; -; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; -; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; -; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; -; |nios_system_lcd_16207_0:lcd_16207_0| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 ; altera_reserved_qsys_nios_system ; -; |nios_system_lcd_on:lcd_blon| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon ; altera_reserved_qsys_nios_system ; -; |nios_system_lcd_on:lcd_on| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_on ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor:nios2_processor| ; 929 (643) ; 576 (306) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci| ; 286 (34) ; 269 (80) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper| ; 92 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk| ; 6 (6) ; 49 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer3| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; work ; -; |altera_std_synchronizer:the_altera_std_synchronizer4| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; work ; -; |nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck| ; 82 (82) ; 47 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer1| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; work ; -; |altera_std_synchronizer:the_altera_std_synchronizer2| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; work ; -; |sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; work ; -; |nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg| ; 8 (8) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break| ; 32 (32) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug| ; 9 (8) ; 9 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer| ; 1 (1) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; work ; -; |nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem| ; 111 (111) ; 49 (49) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; work ; -; |altsyncram_4891:auto_generated| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; work ; -; |nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; work ; -; |altsyncram_0rh1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; work ; -; |nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; work ; -; |altsyncram_1rh1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; work ; -; |nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench ; altera_reserved_qsys_nios_system ; -; |nios_system_onchip_memory:onchip_memory| ; 168 (1) ; 3 (0) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 167 (0) ; 3 (0) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; work ; -; |altsyncram_4ed1:auto_generated| ; 167 (0) ; 3 (3) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; work ; -; |decode_qsa:decode3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 ; work ; -; |mux_nob:mux2| ; 160 (160) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 ; work ; -; |nios_system_push_switches:push_switches| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_push_switches:push_switches ; altera_reserved_qsys_nios_system ; -; |nios_system_rsp_xbar_mux:rsp_xbar_mux| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux ; altera_reserved_qsys_nios_system ; -; |nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_switches:switches| ; 18 (18) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_switches:switches ; altera_reserved_qsys_nios_system ; -; |sld_hub:auto_hub| ; 158 (1) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub ; work ; -; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 157 (115) ; 97 (69) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; work ; -; |sld_rom_sr:hub_info_reg| ; 25 (25) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; work ; -; |sld_shadow_jsm:shadow_jsm| ; 17 (17) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; work ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis RAM Summary ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ -; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 256 ; 32 ; -- ; -- ; 8192 ; nios_system_nios2_processor_ociram_default_contents.mif ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; nios_system_nios2_processor_rf_ram_a.mif ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; nios_system_nios2_processor_rf_ram_b.mif ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 51200 ; 32 ; -- ; -- ; 1638400 ; nios_system_onchip_memory.hex ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ - - -Encoding Type: One-Hot -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize ; -+------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Name ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000 ; -+------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DRsize.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DRsize.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; DRsize.010 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; DRsize.011 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; DRsize.100 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; DRsize.101 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Registers Protected by Synthesis ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ -; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[2] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[7] ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[1] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[2] ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[3] ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[4] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[5] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[6] ; yes ; yes ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Registers Removed During Synthesis ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Register name ; Reason for Removal ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|locked[0,1] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|locked[0,1] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|av_readdata_pre[18..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|av_readdata_pre[11,23..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|av_readdata_pre[8..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[3..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_switches:switches|readdata[18..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[0..4,6..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ipending_reg[0..4,6..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_custom ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im|trc_im_addr[0..6] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im|trc_wrap ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto1 ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto0 ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk|xbrk_break ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[3..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[18..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[1..4,6..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst1 ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; Merged with nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[22] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[23] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[23] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[24] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[24] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[25] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[25] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[7] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[7] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[27] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[27] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[28] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[28] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[29] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[29] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[30] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[30] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[31] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[31] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[0] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[0] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[1] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[1] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[2] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[2] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[3] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[3] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[4] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[4] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[6] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[6] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[8] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[8] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[9] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[9] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[10] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[10] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[11] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[11] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[12] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[12] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[13] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[13] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[14] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[14] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[15] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[15] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[26] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[26] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[16] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[16] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[17] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[17] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[18] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[18] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[19] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[19] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[20] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[20] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[21] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigger_state ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigbrktype ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_early_rst ; Merged with nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|share_count[0] ; Lost fanout ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|share_count[0] ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~3 ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~4 ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~5 ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.101 ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.011 ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.001 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.001 ; Stuck at GND due to stuck port data_in ; -; Total Number of Removed Registers = 975 ; ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Removed Registers Triggering Further Register Optimizations ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Register name ; Reason for Removal ; Registers Removed due to This Register ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break, ; -; ; due to stuck port data_in ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigbrktype ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[12] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[12] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[11] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[11] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[10] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[10] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[9] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[9] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[8] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[8] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[7] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[7] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[6] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[6] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[5] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[5] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[4] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[4] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[3] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[3] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[31] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[31] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[30] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[30] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[29] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[29] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[28] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[28] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[27] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[27] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[26] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[26] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[25] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[25] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[24] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[24] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[23] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[23] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[22] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[22] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[21] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[21] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[20] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[20] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[19] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[19] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[18] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[18] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[31] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[31] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[30] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[30] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[29] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[29] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[28] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[28] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[27] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[27] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[26] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[26] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[25] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[25] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[24] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[24] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[23] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[23] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[22] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[22] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[21] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[21] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[20] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[20] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[19] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[19] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[18] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[18] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[17] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[17] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[16] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[16] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[15] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[15] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[14] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[14] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[13] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[13] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[12] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[12] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[11] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[11] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[10] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[10] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[9] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[9] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[8] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[8] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[7] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[7] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[6] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[6] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[4] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[4] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[3] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[3] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[2] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[2] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[1] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[1] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto1 ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigger_state ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[31] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[31] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[30] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[30] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[29] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[29] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[28] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[28] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[27] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[27] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[26] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[26] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[25] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[25] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[24] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[24] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[23] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[23] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[22] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[22] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[21] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[21] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[20] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[20] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[19] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[19] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[18] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[18] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[17] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[17] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[16] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[16] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[15] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[15] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[14] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[14] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[13] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[13] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~3 ; Lost Fanouts ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.101 ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 1212 ; -; Number of registers using Synchronous Clear ; 69 ; -; Number of registers using Synchronous Load ; 166 ; -; Number of registers using Asynchronous Clear ; 885 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 476 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Inverted Register Statistics ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; Inverted Register ; Fan out ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; 801 ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; 23 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest ; 7 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_chain[1] ; 2 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; 228 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|i_read ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; 11 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[2] ; 1 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; 9 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|t_dav ; 3 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[1] ; 1 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst2 ; 3 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[0] ; 1 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 1 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; 1 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ; -; Total number of inverted registers = 22 ; ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0] ; -; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[12] ; -; 3:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[27] ; -; 3:1 ; 17 bits ; 34 LEs ; 34 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[12] ; -; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[12] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; -; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15] ; -; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4] ; -; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte2_data[2] ; -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|readdata[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[1] ; -; 4:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[10] ; -; 4:1 ; 15 bits ; 30 LEs ; 30 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[20] ; -; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; -; 4:1 ; 23 bits ; 46 LEs ; 46 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[15] ; -; 4:1 ; 9 bits ; 18 LEs ; 18 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[31] ; -; 6:1 ; 2 bits ; 8 LEs ; 2 LEs ; 6 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; -; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; -; 6:1 ; 13 bits ; 52 LEs ; 26 LEs ; 26 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; -; 6:1 ; 16 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; -; 5:1 ; 13 bits ; 39 LEs ; 39 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28] ; -; 4:1 ; 17 bits ; 34 LEs ; 34 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[10] ; -; 4:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[2] ; -; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|break_readreg[15] ; -; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[3] ; -; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; -; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; -; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[18] ; -; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[19] ; -; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; -; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; -; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; -; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; -; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; -; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; -; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; -; 8:1 ; 5 bits ; 25 LEs ; 10 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; -; 34:1 ; 4 bits ; 88 LEs ; 60 LEs ; 28 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 28:1 ; 4 bits ; 72 LEs ; 48 LEs ; 24 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller ; -+-------------------+-------+------+-----------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+-----------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[2] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+-----------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+-------------------+-------+------+------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; -+-----------------+-------+------+----------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+----------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+----------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; -+-----------------+-------+------+----------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+----------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+----------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; -+-----------------+-------+------+--------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+--------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+--------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; lpm_file ; nios_system_nios2_processor_rf_ram_a.mif ; String ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; DUAL_PORT ; Untyped ; -; WIDTH_A ; 32 ; Signed Integer ; -; WIDTHAD_A ; 5 ; Signed Integer ; -; NUMWORDS_A ; 32 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 32 ; Signed Integer ; -; WIDTHAD_B ; 5 ; Signed Integer ; -; NUMWORDS_B ; 32 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK0 ; Untyped ; -; ADDRESS_REG_B ; CLOCK0 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Untyped ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; nios_system_nios2_processor_rf_ram_a.mif ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; CBXI_PARAMETER ; altsyncram_0rh1 ; Untyped ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; lpm_file ; nios_system_nios2_processor_rf_ram_b.mif ; String ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; DUAL_PORT ; Untyped ; -; WIDTH_A ; 32 ; Signed Integer ; -; WIDTHAD_A ; 5 ; Signed Integer ; -; NUMWORDS_A ; 32 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 32 ; Signed Integer ; -; WIDTHAD_B ; 5 ; Signed Integer ; -; NUMWORDS_B ; 32 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK0 ; Untyped ; -; ADDRESS_REG_B ; CLOCK0 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Untyped ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; nios_system_nios2_processor_rf_ram_b.mif ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; CBXI_PARAMETER ; altsyncram_1rh1 ; Untyped ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; -+----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; lpm_file ; nios_system_nios2_processor_ociram_default_contents.mif ; String ; -+----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; -+------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; SINGLE_PORT ; Untyped ; -; WIDTH_A ; 32 ; Signed Integer ; -; WIDTHAD_A ; 8 ; Signed Integer ; -; NUMWORDS_A ; 256 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 1 ; Untyped ; -; WIDTHAD_B ; 1 ; Untyped ; -; NUMWORDS_B ; 1 ; Untyped ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; nios_system_nios2_processor_ociram_default_contents.mif ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; CBXI_PARAMETER ; altsyncram_4891 ; Untyped ; -+------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sld_mfg_id ; 70 ; Signed Integer ; -; sld_type_id ; 34 ; Signed Integer ; -; sld_version ; 3 ; Signed Integer ; -; sld_instance_index ; 0 ; Signed Integer ; -; sld_auto_instance_index ; YES ; String ; -; sld_ir_width ; 2 ; Signed Integer ; -; sld_sim_n_scan ; 0 ; Signed Integer ; -; sld_sim_action ; ; String ; -; sld_sim_total_length ; 0 ; Signed Integer ; -; lpm_type ; sld_virtual_jtag_basic ; String ; -; lpm_hint ; UNUSED ; String ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; -+----------------+-------------------------------+--------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------------------------+--------------------------------------------------------+ -; INIT_FILE ; nios_system_onchip_memory.hex ; String ; -+----------------+-------------------------------+--------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; -+------------------------------------+-------------------------------+--------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-------------------------------+--------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; SINGLE_PORT ; Untyped ; -; WIDTH_A ; 32 ; Signed Integer ; -; WIDTHAD_A ; 16 ; Signed Integer ; -; NUMWORDS_A ; 51200 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 1 ; Untyped ; -; WIDTHAD_B ; 1 ; Untyped ; -; NUMWORDS_B ; 1 ; Untyped ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Signed Integer ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; nios_system_onchip_memory.hex ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 51200 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; CBXI_PARAMETER ; altsyncram_4ed1 ; Untyped ; -+------------------------------------+-------------------------------+--------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; lpm_width ; 8 ; Signed Integer ; -; LPM_NUMWORDS ; 64 ; Signed Integer ; -; LPM_WIDTHU ; 6 ; Signed Integer ; -; LPM_SHOWAHEAD ; OFF ; Untyped ; -; UNDERFLOW_CHECKING ; OFF ; Untyped ; -; OVERFLOW_CHECKING ; OFF ; Untyped ; -; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; -; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; -; ALMOST_FULL_VALUE ; 0 ; Untyped ; -; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; -; USE_EAB ; ON ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; -; CBXI_PARAMETER ; scfifo_jr21 ; Untyped ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; lpm_width ; 8 ; Signed Integer ; -; LPM_NUMWORDS ; 64 ; Signed Integer ; -; LPM_WIDTHU ; 6 ; Signed Integer ; -; LPM_SHOWAHEAD ; OFF ; Untyped ; -; UNDERFLOW_CHECKING ; OFF ; Untyped ; -; OVERFLOW_CHECKING ; OFF ; Untyped ; -; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; -; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; -; ALMOST_FULL_VALUE ; 0 ; Untyped ; -; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; -; USE_EAB ; ON ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; -; CBXI_PARAMETER ; scfifo_jr21 ; Untyped ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 19 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; USE_BURSTCOUNT ; 0 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WRITE ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 1 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 19 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; USE_BURSTCOUNT ; 0 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WRITE ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 1 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 9 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 16 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 1 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 1 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; -+--------------------------------+-------+---------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+---------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+---------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 8 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 13 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 13 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 13 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 13 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; -+--------------------------------+-------+----------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+----------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+----------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 75 ; Signed Integer ; -; PKT_QOS_L ; 75 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 73 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 73 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 72 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 72 ; Signed Integer ; -; PKT_CACHE_H ; 93 ; Signed Integer ; -; PKT_CACHE_L ; 90 ; Signed Integer ; -; PKT_THREAD_ID_H ; 86 ; Signed Integer ; -; PKT_THREAD_ID_L ; 86 ; Signed Integer ; -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 71 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 70 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 60 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; -; BURSTWRAP_VALUE ; 3 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 3 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 19 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 5 ; Signed Integer ; -; PKT_DEST_ID_W ; 5 ; Signed Integer ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 75 ; Signed Integer ; -; PKT_QOS_L ; 75 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 73 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 73 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 72 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 72 ; Signed Integer ; -; PKT_CACHE_H ; 93 ; Signed Integer ; -; PKT_CACHE_L ; 90 ; Signed Integer ; -; PKT_THREAD_ID_H ; 86 ; Signed Integer ; -; PKT_THREAD_ID_L ; 86 ; Signed Integer ; -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 71 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 70 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 60 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 0 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; -; BURSTWRAP_VALUE ; 7 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 3 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 19 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 5 ; Signed Integer ; -; PKT_DEST_ID_W ; 5 ; Signed Integer ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 15 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 15 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 1 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 1 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller ; -+-------------------------+----------+-------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+----------+-------------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 2 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 1 ; Signed Integer ; -+-------------------------+----------+-------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 1 ; Unsigned Binary ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; -+----------------+-------------+-----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------+-----------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; round-robin ; String ; -; PIPELINE ; 1 ; Signed Integer ; -+----------------+-------------+-----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; -+----------------+-------------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------+---------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; round-robin ; String ; -; PIPELINE ; 1 ; Signed Integer ; -+----------------+-------------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb ; -+----------------+--------+----------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+----------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+----------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb ; -+----------------+--------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 18 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 36 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; altsyncram Parameter Settings by Entity Instance ; -+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Name ; Value ; -+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Number of entity instances ; 4 ; -; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; DUAL_PORT ; -; -- WIDTH_A ; 32 ; -; -- NUMWORDS_A ; 32 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 32 ; -; -- NUMWORDS_B ; 32 ; -; -- ADDRESS_REG_B ; CLOCK0 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; DUAL_PORT ; -; -- WIDTH_A ; 32 ; -; -- NUMWORDS_A ; 32 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 32 ; -; -- NUMWORDS_B ; 32 ; -; -- ADDRESS_REG_B ; CLOCK0 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; SINGLE_PORT ; -; -- WIDTH_A ; 32 ; -; -- NUMWORDS_A ; 256 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 1 ; -; -- NUMWORDS_B ; 1 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; SINGLE_PORT ; -; -- WIDTH_A ; 32 ; -; -- NUMWORDS_A ; 51200 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 1 ; -; -- NUMWORDS_B ; 1 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; scfifo Parameter Settings by Entity Instance ; -+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Name ; Value ; -+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Number of entity instances ; 2 ; -; Entity Instance ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; -; -- FIFO Type ; Single Clock ; -; -- lpm_width ; 8 ; -; -- LPM_NUMWORDS ; 64 ; -; -- LPM_SHOWAHEAD ; OFF ; -; -- USE_EAB ; ON ; -; Entity Instance ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; -; -- FIFO Type ; Single Clock ; -; -- lpm_width ; 8 ; -; -- LPM_NUMWORDS ; 64 ; -; -- LPM_SHOWAHEAD ; OFF ; -; -- USE_EAB ; ON ; -+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; b[35..1] ; Input ; Info ; Stuck at GND ; -; b[0] ; Input ; Info ; Stuck at VCC ; -; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; b[3..1] ; Input ; Info ; Stuck at GND ; -; b[0] ; Input ; Info ; Stuck at VCC ; -; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ -; b[3..2] ; Input ; Info ; Stuck at GND ; -+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_reset_controller:rst_controller" ; -+------------+-------+----------+-------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+-------+----------+-------------------------------------------------------+ -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -+------------+-------+----------+-------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+-------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+-------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+-------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" ; -+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator" ; -+--------------------------+--------+----------+-------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator" ; -+--------------------------+--------+----------+-----------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-----------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-----------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" ; -+--------------------------+--------+----------+---------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------------------------+ -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator" ; -+--------------------------+--------+----------+------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+------------------------------------------------------------+ -; av_write ; Output ; Info ; Explicitly unconnected ; -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_writedata ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator" ; -+--------------------------+--------+----------+-------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-------------------------------------------------------+ -; av_write ; Output ; Info ; Explicitly unconnected ; -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_writedata ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator" ; -+--------------------------+--------+----------+----------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+----------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+----------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" ; -+--------------------------+--------+----------+-----------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-----------------------------------------------------------------------+ -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-----------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" ; -+--------------------------+--------+----------+------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+------------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" ; -+--------------------------+--------+----------+-----------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-----------------------------------------------------------------------------+ -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" ; -+--------------------------+--------+----------+------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+------------------------------------------------------------------------+ -; av_burstcount ; Input ; Info ; Stuck at VCC ; -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_readdatavalid ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponserequest ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+--------------------------+--------+----------+------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" ; -+--------------------------+--------+----------+-------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-------------------------------------------------------------------------------+ -; av_burstcount ; Input ; Info ; Stuck at VCC ; -; av_byteenable ; Input ; Info ; Stuck at VCC ; -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_readdatavalid ; Output ; Info ; Explicitly unconnected ; -; av_write ; Input ; Info ; Stuck at GND ; -; av_writedata ; Input ; Info ; Stuck at GND ; -; av_lock ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponserequest ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+--------------------------+--------+----------+-------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" ; -+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; raw_tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; tdi ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; rti ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; shift ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; update ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; usr1 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; clr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; ena ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; ir_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; tdo ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; irq ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; ir_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_cdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_sdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_udr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" ; -+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; dataavailable ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; readyfordata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; virtual_state_e1dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; virtual_state_pdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; virtual_state_e2dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; virtual_state_cir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; tms ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_tlr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sdrs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_cdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e1dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_pdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e2dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_udr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sirs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_cir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e1ir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_pir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e2ir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_uir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4" ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; reset_n ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3" ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; reset_n ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" ; -+---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; clkx2 ; Input ; Info ; Stuck at GND ; -; tr_clk ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; tr_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; fifowp_inc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; td_mode ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; jdo ; Input ; Warning ; Input port expression (38 bits) is wider than the input port (16 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; dbrk_trigout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; xbrk_trigout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; debugreq ; Input ; Info ; Stuck at GND ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ -; oci_ienable[31..6] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; oci_ienable[4..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" ; -+-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; F_pcb[1..0] ; Input ; Info ; Stuck at GND ; -; i_address[1..0] ; Input ; Info ; Stuck at GND ; -+-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" ; -+--------------+--------+----------+---------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+---------------------------------------------------------+ -; no_ci_readra ; Output ; Info ; Explicitly unconnected ; -+--------------+--------+----------+---------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII" ; -+------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ -; lcd_16207_0_data ; Bidir ; Critical Warning ; Port on prototype, e.g. VHDL component, declared as "Output" but port on entity declared as "Bidir" ; -+------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ - - -+---------------------------------+ -; Elapsed Time Per Partition ; -+------------------+--------------+ -; Partition Name ; Elapsed Time ; -+------------------+--------------+ -; Top ; 00:00:07 ; -; sld_hub:auto_hub ; 00:00:00 ; -+------------------+--------------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit Analysis & Synthesis - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Dec 22 10:07:13 2016 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (12248): Elaborating Qsys system entity "nios_system.qsys" -Info (12250): 2016.12.22.10:07:14 Progress: Loading qsys_tutorial/nios_system.qsys -Info (12250): 2016.12.22.10:07:14 Progress: Reading input file -Info (12250): 2016.12.22.10:07:14 Progress: Adding clk_0 [clock_source 13.0] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module clk_0 -Info (12250): 2016.12.22.10:07:15 Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module nios2_processor -Info (12250): 2016.12.22.10:07:15 Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module onchip_memory -Info (12250): 2016.12.22.10:07:15 Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module jtag_uart -Info (12250): 2016.12.22.10:07:15 Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module LEDs -Info (12250): 2016.12.22.10:07:15 Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module LEDRs -Info (12250): 2016.12.22.10:07:15 Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module switches -Info (12250): 2016.12.22.10:07:15 Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module push_switches -Info (12250): 2016.12.22.10:07:15 Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex0 -Info (12250): 2016.12.22.10:07:15 Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex1 -Info (12250): 2016.12.22.10:07:15 Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex2 -Info (12250): 2016.12.22.10:07:15 Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex3 -Info (12250): 2016.12.22.10:07:15 Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex4 -Info (12250): 2016.12.22.10:07:15 Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex5 -Info (12250): 2016.12.22.10:07:15 Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module hex6 -Info (12250): 2016.12.22.10:07:16 Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module hex7 -Info (12250): 2016.12.22.10:07:16 Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module lcd_16207_0 -Info (12250): 2016.12.22.10:07:16 Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module lcd_on -Info (12250): 2016.12.22.10:07:16 Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module lcd_blon -Info (12250): 2016.12.22.10:07:16 Progress: Building connections -Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing connections -Info (12250): 2016.12.22.10:07:16 Progress: Validating -Info (12250): 2016.12.22.10:07:16 Progress: Done reading input file -Info (12250): Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info (12250): Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info (12250): Nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info (12250): Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections -Info (12250): No custom instruction connections, skipping transform -Info (12250): Merlin_translator_transform: After transform: 39 modules, 155 connections -Info (12250): Merlin_domain_transform: After transform: 78 modules, 423 connections -Info (12250): Merlin_router_transform: After transform: 98 modules, 503 connections -Info (12250): Reset_adaptation_transform: After transform: 99 modules, 390 connections -Info (12250): Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections -Info (12250): Merlin_mm_transform: After transform: 138 modules, 470 connections -Info (12250): Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info (12250): Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info (12250): Nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Starting Nios II generation -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Checking for plaintext license. -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Plaintext license not found. -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e. -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings -Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Creating all objects for CPU -Info (12250): Nios2_processor: # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects -Info (12250): Nios2_processor: # 2016.12.22 10:07:24 (*) Creating plain-text RTL -Info (12250): Nios2_processor: # 2016.12.22 10:07:26 (*) Done Nios II generation -Info (12250): Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info (12250): Nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info (12250): Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info (12250): Onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info (12250): Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info (12250): Onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info (12250): Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info (12250): Jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info (12250): Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info (12250): Jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info (12250): LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info (12250): LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info (12250): LEDs: Done RTL generation for module 'nios_system_LEDs' -Info (12250): LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info (12250): LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info (12250): LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info (12250): LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info (12250): LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info (12250): Switches: Starting RTL generation for module 'nios_system_switches' -Info (12250): Switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info (12250): Switches: Done RTL generation for module 'nios_system_switches' -Info (12250): Switches: "nios_system" instantiated altera_avalon_pio "switches" -Info (12250): Push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info (12250): Push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info (12250): Push_switches: Done RTL generation for module 'nios_system_push_switches' -Info (12250): Push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info (12250): Hex0: Starting RTL generation for module 'nios_system_hex0' -Info (12250): Hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info (12250): Hex0: Done RTL generation for module 'nios_system_hex0' -Info (12250): Hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info (12250): Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info (12250): Lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info (12250): Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info (12250): Lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info (12250): Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' -Info (12250): Lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] -Info (12250): Lcd_on: Done RTL generation for module 'nios_system_lcd_on' -Info (12250): Lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" -Info (12250): Nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info (12250): Nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info (12250): Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info (12250): Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info (12250): Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info (12250): Addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info (12250): Addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info (12250): Id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info (12250): Id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info (12250): Rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info (12250): Cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info (12250): Cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info (12250): Cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info (12250): Rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info (12250): Rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info (12250): Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv -Info (12250): Rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info (12250): Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv -Info (12250): Irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info (12250): Nios_system: Done nios_system" with 28 modules, 155 files, 4086283 bytes -Info (12249): Finished elaborating Qsys system entity "nios_system.qsys" -Info (12021): Found 2 design units, including 1 entities, in source file lights.vhd - Info (12022): Found design unit 1: lights-lights_rtl - Info (12023): Found entity 1: lights -Info (12021): Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v - Info (12023): Found entity 1: nios_system -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v - Info (12023): Found entity 1: nios_system -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v - Info (12023): Found entity 1: altera_avalon_sc_fifo -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv - Info (12023): Found entity 1: altera_merlin_arbitrator - Info (12023): Found entity 2: altera_merlin_arb_adder -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv - Info (12023): Found entity 1: altera_merlin_burst_uncompressor -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv - Info (12023): Found entity 1: altera_merlin_master_agent -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv - Info (12023): Found entity 1: altera_merlin_master_translator -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv - Info (12023): Found entity 1: altera_merlin_slave_agent -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv - Info (12023): Found entity 1: altera_merlin_slave_translator -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v - Info (12023): Found entity 1: altera_reset_controller -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v - Info (12023): Found entity 1: altera_reset_synchronizer -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v - Info (12023): Found entity 1: nios_system_LEDRs -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v - Info (12023): Found entity 1: nios_system_LEDs -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv - Info (12023): Found entity 1: nios_system_addr_router_default_decode - Info (12023): Found entity 2: nios_system_addr_router -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv - Info (12023): Found entity 1: nios_system_addr_router_001_default_decode - Info (12023): Found entity 2: nios_system_addr_router_001 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv - Info (12023): Found entity 1: nios_system_cmd_xbar_demux -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv - Info (12023): Found entity 1: nios_system_cmd_xbar_demux_001 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv - Info (12023): Found entity 1: nios_system_cmd_xbar_mux -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v - Info (12023): Found entity 1: nios_system_hex0 -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv - Info (12023): Found entity 1: nios_system_id_router_default_decode - Info (12023): Found entity 2: nios_system_id_router -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv - Info (12023): Found entity 1: nios_system_id_router_002_default_decode - Info (12023): Found entity 2: nios_system_id_router_002 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv - Info (12023): Found entity 1: nios_system_irq_mapper -Info (12021): Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v - Info (12023): Found entity 1: nios_system_jtag_uart_sim_scfifo_w - Info (12023): Found entity 2: nios_system_jtag_uart_scfifo_w - Info (12023): Found entity 3: nios_system_jtag_uart_sim_scfifo_r - Info (12023): Found entity 4: nios_system_jtag_uart_scfifo_r - Info (12023): Found entity 5: nios_system_jtag_uart -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v - Info (12023): Found entity 1: nios_system_lcd_16207_0 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v - Info (12023): Found entity 1: nios_system_lcd_on -Info (12021): Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v - Info (12023): Found entity 1: nios_system_nios2_processor_register_bank_a_module - Info (12023): Found entity 2: nios_system_nios2_processor_register_bank_b_module - Info (12023): Found entity 3: nios_system_nios2_processor_nios2_oci_debug - Info (12023): Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module - Info (12023): Found entity 5: nios_system_nios2_processor_nios2_ocimem - Info (12023): Found entity 6: nios_system_nios2_processor_nios2_avalon_reg - Info (12023): Found entity 7: nios_system_nios2_processor_nios2_oci_break - Info (12023): Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk - Info (12023): Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk - Info (12023): Found entity 10: nios_system_nios2_processor_nios2_oci_itrace - Info (12023): Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode - Info (12023): Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace - Info (12023): Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count - Info (12023): Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc - Info (12023): Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc - Info (12023): Found entity 16: nios_system_nios2_processor_nios2_oci_fifo - Info (12023): Found entity 17: nios_system_nios2_processor_nios2_oci_pib - Info (12023): Found entity 18: nios_system_nios2_processor_nios2_oci_im - Info (12023): Found entity 19: nios_system_nios2_processor_nios2_performance_monitors - Info (12023): Found entity 20: nios_system_nios2_processor_nios2_oci - Info (12023): Found entity 21: nios_system_nios2_processor -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v - Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v - Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v - Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v - Info (12023): Found entity 1: nios_system_nios2_processor_oci_test_bench -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v - Info (12023): Found entity 1: nios_system_nios2_processor_test_bench -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v - Info (12023): Found entity 1: nios_system_onchip_memory -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v - Info (12023): Found entity 1: nios_system_push_switches -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv - Info (12023): Found entity 1: nios_system_rsp_xbar_demux_002 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv - Info (12023): Found entity 1: nios_system_rsp_xbar_mux -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv - Info (12023): Found entity 1: nios_system_rsp_xbar_mux_001 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v - Info (12023): Found entity 1: nios_system_switches -Info (12127): Elaborating entity "lights" for the top level hierarchy -Info (12128): Elaborating entity "nios_system" for hierarchy "nios_system:NiosII" -Info (12128): Elaborating entity "nios_system_nios2_processor" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" -Info (12128): Elaborating entity "nios_system_nios2_processor_test_bench" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" -Info (12128): Elaborating entity "nios_system_nios2_processor_register_bank_a_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a" -Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" with the following parameter: - Info (12134): Parameter "address_reg_b" = "CLOCK0" - Info (12134): Parameter "init_file" = "nios_system_nios2_processor_rf_ram_a.mif" - Info (12134): Parameter "maximum_depth" = "0" - Info (12134): Parameter "numwords_a" = "32" - Info (12134): Parameter "numwords_b" = "32" - Info (12134): Parameter "operation_mode" = "DUAL_PORT" - Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" - Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" - Info (12134): Parameter "width_a" = "32" - Info (12134): Parameter "width_b" = "32" - Info (12134): Parameter "widthad_a" = "5" - Info (12134): Parameter "widthad_b" = "5" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf - Info (12023): Found entity 1: altsyncram_0rh1 -Info (12128): Elaborating entity "altsyncram_0rh1" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated" -Info (12128): Elaborating entity "nios_system_nios2_processor_register_bank_b_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b" -Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" with the following parameter: - Info (12134): Parameter "address_reg_b" = "CLOCK0" - Info (12134): Parameter "init_file" = "nios_system_nios2_processor_rf_ram_b.mif" - Info (12134): Parameter "maximum_depth" = "0" - Info (12134): Parameter "numwords_a" = "32" - Info (12134): Parameter "numwords_b" = "32" - Info (12134): Parameter "operation_mode" = "DUAL_PORT" - Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" - Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" - Info (12134): Parameter "width_a" = "32" - Info (12134): Parameter "width_b" = "32" - Info (12134): Parameter "widthad_a" = "5" - Info (12134): Parameter "widthad_b" = "5" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf - Info (12023): Found entity 1: altsyncram_1rh1 -Info (12128): Elaborating entity "altsyncram_1rh1" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_debug" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" -Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: - Info (12134): Parameter "depth" = "2" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_ocimem" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem" -Info (12128): Elaborating entity "nios_system_nios2_processor_ociram_sp_ram_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram" -Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" with the following parameter: - Info (12134): Parameter "init_file" = "nios_system_nios2_processor_ociram_default_contents.mif" - Info (12134): Parameter "maximum_depth" = "0" - Info (12134): Parameter "numwords_a" = "256" - Info (12134): Parameter "operation_mode" = "SINGLE_PORT" - Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "width_a" = "32" - Info (12134): Parameter "width_byteena_a" = "4" - Info (12134): Parameter "widthad_a" = "8" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf - Info (12023): Found entity 1: altsyncram_4891 -Info (12128): Elaborating entity "altsyncram_4891" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_avalon_reg" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_break" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_xbrk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_dbrk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_itrace" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_dtrace" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_td_mode" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifo" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_compute_tm_count" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifowp_inc" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifocount_inc" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" -Info (12128): Elaborating entity "nios_system_nios2_processor_oci_test_bench" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench" -Warning (12158): Entity "nios_system_nios2_processor_oci_test_bench" contains only dangling pins -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_pib" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_im" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im" -Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_wrapper" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper" -Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_tck" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck" -Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_sysclk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk" -Info (12128): Elaborating entity "sld_virtual_jtag_basic" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" with the following parameter: - Info (12134): Parameter "sld_auto_instance_index" = "YES" - Info (12134): Parameter "sld_instance_index" = "0" - Info (12134): Parameter "sld_ir_width" = "2" - Info (12134): Parameter "sld_mfg_id" = "70" - Info (12134): Parameter "sld_sim_action" = "" - Info (12134): Parameter "sld_sim_n_scan" = "0" - Info (12134): Parameter "sld_sim_total_length" = "0" - Info (12134): Parameter "sld_type_id" = "34" - Info (12134): Parameter "sld_version" = "3" -Info (12128): Elaborating entity "sld_virtual_jtag_impl" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" -Info (12131): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" -Info (12128): Elaborating entity "nios_system_onchip_memory" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory" -Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" with the following parameter: - Info (12134): Parameter "byte_size" = "8" - Info (12134): Parameter "init_file" = "nios_system_onchip_memory.hex" - Info (12134): Parameter "lpm_type" = "altsyncram" - Info (12134): Parameter "maximum_depth" = "51200" - Info (12134): Parameter "numwords_a" = "51200" - Info (12134): Parameter "operation_mode" = "SINGLE_PORT" - Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" - Info (12134): Parameter "width_a" = "32" - Info (12134): Parameter "width_byteena_a" = "4" - Info (12134): Parameter "widthad_a" = "16" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf - Info (12023): Found entity 1: altsyncram_4ed1 -Info (12128): Elaborating entity "altsyncram_4ed1" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated" -Info (12021): Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf - Info (12023): Found entity 1: decode_qsa -Info (12128): Elaborating entity "decode_qsa" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3" -Info (12021): Found 1 design units, including 1 entities, in source file db/mux_nob.tdf - Info (12023): Found entity 1: mux_nob -Info (12128): Elaborating entity "mux_nob" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2" -Info (12128): Elaborating entity "nios_system_jtag_uart" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" -Info (12128): Elaborating entity "nios_system_jtag_uart_scfifo_w" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w" -Info (12128): Elaborating entity "scfifo" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" with the following parameter: - Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO" - Info (12134): Parameter "lpm_numwords" = "64" - Info (12134): Parameter "lpm_showahead" = "OFF" - Info (12134): Parameter "lpm_type" = "scfifo" - Info (12134): Parameter "lpm_width" = "8" - Info (12134): Parameter "lpm_widthu" = "6" - Info (12134): Parameter "overflow_checking" = "OFF" - Info (12134): Parameter "underflow_checking" = "OFF" - Info (12134): Parameter "use_eab" = "ON" -Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf - Info (12023): Found entity 1: scfifo_jr21 -Info (12128): Elaborating entity "scfifo_jr21" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated" -Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf - Info (12023): Found entity 1: a_dpfifo_q131 -Info (12128): Elaborating entity "a_dpfifo_q131" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo" -Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf - Info (12023): Found entity 1: a_fefifo_7cf -Info (12128): Elaborating entity "a_fefifo_7cf" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state" -Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf - Info (12023): Found entity 1: cntr_do7 -Info (12128): Elaborating entity "cntr_do7" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw" -Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf - Info (12023): Found entity 1: dpram_nl21 -Info (12128): Elaborating entity "dpram_nl21" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf - Info (12023): Found entity 1: altsyncram_r1m1 -Info (12128): Elaborating entity "altsyncram_r1m1" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1" -Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf - Info (12023): Found entity 1: cntr_1ob -Info (12128): Elaborating entity "cntr_1ob" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count" -Info (12128): Elaborating entity "nios_system_jtag_uart_scfifo_r" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r" -Info (12128): Elaborating entity "alt_jtag_atlantic" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" with the following parameter: - Info (12134): Parameter "INSTANCE_ID" = "0" - Info (12134): Parameter "LOG2_RXFIFO_DEPTH" = "6" - Info (12134): Parameter "LOG2_TXFIFO_DEPTH" = "6" - Info (12134): Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES" -Info (12128): Elaborating entity "nios_system_LEDs" for hierarchy "nios_system:NiosII|nios_system_LEDs:leds" -Info (12128): Elaborating entity "nios_system_LEDRs" for hierarchy "nios_system:NiosII|nios_system_LEDRs:ledrs" -Info (12128): Elaborating entity "nios_system_switches" for hierarchy "nios_system:NiosII|nios_system_switches:switches" -Info (12128): Elaborating entity "nios_system_push_switches" for hierarchy "nios_system:NiosII|nios_system_push_switches:push_switches" -Info (12128): Elaborating entity "nios_system_hex0" for hierarchy "nios_system:NiosII|nios_system_hex0:hex0" -Info (12128): Elaborating entity "nios_system_lcd_16207_0" for hierarchy "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0" -Info (12128): Elaborating entity "nios_system_lcd_on" for hierarchy "nios_system:NiosII|nios_system_lcd_on:lcd_on" -Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" -Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" -Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" -Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor" -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info (12128): Elaborating entity "nios_system_addr_router" for hierarchy "nios_system:NiosII|nios_system_addr_router:addr_router" -Info (12128): Elaborating entity "nios_system_addr_router_default_decode" for hierarchy "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" -Info (12128): Elaborating entity "nios_system_addr_router_001" for hierarchy "nios_system:NiosII|nios_system_addr_router_001:addr_router_001" -Info (12128): Elaborating entity "nios_system_addr_router_001_default_decode" for hierarchy "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" -Info (12128): Elaborating entity "nios_system_id_router" for hierarchy "nios_system:NiosII|nios_system_id_router:id_router" -Info (12128): Elaborating entity "nios_system_id_router_default_decode" for hierarchy "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" -Info (12128): Elaborating entity "nios_system_id_router_002" for hierarchy "nios_system:NiosII|nios_system_id_router_002:id_router_002" -Info (12128): Elaborating entity "nios_system_id_router_002_default_decode" for hierarchy "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" -Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "nios_system:NiosII|altera_reset_controller:rst_controller" -Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" -Info (12128): Elaborating entity "nios_system_cmd_xbar_demux" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux" -Info (12128): Elaborating entity "nios_system_cmd_xbar_demux_001" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001" -Info (12128): Elaborating entity "nios_system_cmd_xbar_mux" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux" -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb" -Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -Info (12128): Elaborating entity "nios_system_rsp_xbar_demux_002" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002" -Info (12128): Elaborating entity "nios_system_rsp_xbar_mux" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux" -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb" -Info (12128): Elaborating entity "nios_system_rsp_xbar_mux_001" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001" -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb" -Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -Info (12128): Elaborating entity "nios_system_irq_mapper" for hierarchy "nios_system:NiosII|nios_system_irq_mapper:irq_mapper" -Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder -Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[0]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[0]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[1]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[1]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[2]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[2]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[3]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[3]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[4]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[4]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[5]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[5]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[6]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[6]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[7]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[7]" into an OR gate -Info (13000): Registers with preset signals will power-up high -Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back -Info (286031): Timing-Driven Synthesis is running on partition "Top" -Info (17049): 166 registers lost all their fanouts during netlist optimizations. -Info (13000): Registers with preset signals will power-up high -Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back -Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "sld_hub:auto_hub|receive[0][0]" is stuck at GND -Info (286031): Timing-Driven Synthesis is running on partition "sld_hub:auto_hub" -Info (144001): Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg -Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" - Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 2878 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 26 input pins - Info (21059): Implemented 96 output pins - Info (21061): Implemented 2419 logic cells - Info (21064): Implemented 336 RAM segments -Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 150 warnings - Info: Peak virtual memory: 657 megabytes - Info: Processing ended: Thu Dec 22 10:07:53 2016 - Info: Elapsed time: 00:00:40 - Info: Total CPU time (on all processors): 00:00:36 - - -+------------------------------------------+ -; Analysis & Synthesis Suppressed Messages ; -+------------------------------------------+ -The suppressed messages can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg. - - diff --git a/output_files/lights.sta.rpt b/output_files/lights.sta.rpt deleted file mode 100644 index 4872c07..0000000 --- a/output_files/lights.sta.rpt +++ /dev/null @@ -1,2976 +0,0 @@ -TimeQuest Timing Analyzer report for lights -Thu Dec 22 10:08:48 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. TimeQuest Timing Analyzer Summary - 3. Parallel Compilation - 4. Clocks - 5. Slow 1200mV 85C Model Fmax Summary - 6. Timing Closure Recommendations - 7. Slow 1200mV 85C Model Setup Summary - 8. Slow 1200mV 85C Model Hold Summary - 9. Slow 1200mV 85C Model Recovery Summary - 10. Slow 1200mV 85C Model Removal Summary - 11. Slow 1200mV 85C Model Minimum Pulse Width Summary - 12. Slow 1200mV 85C Model Setup: 'altera_reserved_tck' - 13. Slow 1200mV 85C Model Hold: 'altera_reserved_tck' - 14. Slow 1200mV 85C Model Recovery: 'altera_reserved_tck' - 15. Slow 1200mV 85C Model Removal: 'altera_reserved_tck' - 16. Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck' - 17. Setup Times - 18. Hold Times - 19. Clock to Output Times - 20. Minimum Clock to Output Times - 21. MTBF Summary - 22. Synchronizer Summary - 23. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years - 24. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years - 25. Slow 1200mV 0C Model Fmax Summary - 26. Slow 1200mV 0C Model Setup Summary - 27. Slow 1200mV 0C Model Hold Summary - 28. Slow 1200mV 0C Model Recovery Summary - 29. Slow 1200mV 0C Model Removal Summary - 30. Slow 1200mV 0C Model Minimum Pulse Width Summary - 31. Slow 1200mV 0C Model Setup: 'altera_reserved_tck' - 32. Slow 1200mV 0C Model Hold: 'altera_reserved_tck' - 33. Slow 1200mV 0C Model Recovery: 'altera_reserved_tck' - 34. Slow 1200mV 0C Model Removal: 'altera_reserved_tck' - 35. Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' - 36. Setup Times - 37. Hold Times - 38. Clock to Output Times - 39. Minimum Clock to Output Times - 40. MTBF Summary - 41. Synchronizer Summary - 42. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years - 43. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years - 44. Fast 1200mV 0C Model Setup Summary - 45. Fast 1200mV 0C Model Hold Summary - 46. Fast 1200mV 0C Model Recovery Summary - 47. Fast 1200mV 0C Model Removal Summary - 48. Fast 1200mV 0C Model Minimum Pulse Width Summary - 49. Fast 1200mV 0C Model Setup: 'altera_reserved_tck' - 50. Fast 1200mV 0C Model Hold: 'altera_reserved_tck' - 51. Fast 1200mV 0C Model Recovery: 'altera_reserved_tck' - 52. Fast 1200mV 0C Model Removal: 'altera_reserved_tck' - 53. Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' - 54. Setup Times - 55. Hold Times - 56. Clock to Output Times - 57. Minimum Clock to Output Times - 58. MTBF Summary - 59. Synchronizer Summary - 60. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years - 61. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years - 62. Multicorner Timing Analysis Summary - 63. Setup Times - 64. Hold Times - 65. Clock to Output Times - 66. Minimum Clock to Output Times - 67. Board Trace Model Assignments - 68. Input Transition Times - 69. Signal Integrity Metrics (Slow 1200mv 0c Model) - 70. Signal Integrity Metrics (Slow 1200mv 85c Model) - 71. Signal Integrity Metrics (Fast 1200mv 0c Model) - 72. Setup Transfers - 73. Hold Transfers - 74. Recovery Transfers - 75. Removal Transfers - 76. Report TCCS - 77. Report RSKM - 78. Unconstrained Paths - 79. TimeQuest Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+----------------------------------------------------------------------------------------+ -; TimeQuest Timing Analyzer Summary ; -+--------------------+-------------------------------------------------------------------+ -; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; -; Revision Name ; lights ; -; Device Family ; Cyclone IV E ; -; Device Name ; EP4CE115F29C7 ; -; Timing Models ; Final ; -; Delay Model ; Combined ; -; Rise/Fall Delays ; Enabled ; -+--------------------+-------------------------------------------------------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ -; altera_reserved_tck ; Base ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; ; ; ; ; ; ; ; ; ; ; { altera_reserved_tck } ; -+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ - - -+-----------------------------------------------------------+ -; Slow 1200mV 85C Model Fmax Summary ; -+------------+-----------------+---------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+---------------------+------+ -; 149.52 MHz ; 149.52 MHz ; altera_reserved_tck ; ; -+------------+-----------------+---------------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - ----------------------------------- -; Timing Closure Recommendations ; ----------------------------------- -HTML report is unavailable in plain text report export. - - -+----------------------------------------------+ -; Slow 1200mV 85C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 46.656 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 1200mV 85C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.401 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Slow 1200mV 85C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 47.591 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 1200mV 85C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 1.180 ; 0.000 ; -+---------------------+-------+---------------+ - - -+---------------------------------------------------+ -; Slow 1200mV 85C Model Minimum Pulse Width Summary ; -+---------------------+--------+--------------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+--------------------+ -; altera_reserved_tck ; 49.555 ; 0.000 ; -+---------------------+--------+--------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Setup: 'altera_reserved_tck' ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 46.656 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.150 ; 3.512 ; -; 46.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.152 ; 3.380 ; -; 46.911 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.150 ; 3.257 ; -; 47.218 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 2.940 ; -; 47.221 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.150 ; 2.947 ; -; 47.294 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.138 ; 2.862 ; -; 47.377 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 2.781 ; -; 47.378 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.154 ; 2.794 ; -; 47.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.151 ; 2.640 ; -; 47.549 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.141 ; 2.610 ; -; 47.560 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.151 ; 2.609 ; -; 47.658 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.151 ; 2.511 ; -; 47.742 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.151 ; 2.427 ; -; 47.866 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.154 ; 2.306 ; -; 47.965 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.153 ; 2.206 ; -; 48.251 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.153 ; 1.920 ; -; 48.617 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 1.541 ; -; 48.849 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.116 ; 1.285 ; -; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; -; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; -; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; -; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; -; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; -; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; -; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; -; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; -; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; -; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; -; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; -; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; -; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; -; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; -; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; -; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; -; 94.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.108 ; 5.611 ; -; 94.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.108 ; 5.611 ; -; 94.377 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.108 ; 5.533 ; -; 94.377 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.108 ; 5.533 ; -; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; -; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; -; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; -; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; -; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; -; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; -; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; -; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; -; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; -; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; -; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; -; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; -; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; -; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; -; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; -; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; -; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; -; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; -; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; -; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; -; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; -; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; -; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; -; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; -; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; -; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; -; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; -; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; -; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; -; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; -; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; -; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; -; 94.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 5.113 ; -; 94.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 5.113 ; -; 94.853 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 5.095 ; -; 94.853 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 5.095 ; -; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; -; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; -; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; -; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; -; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; -; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; -; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; -; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; -; 94.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.992 ; -; 94.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.992 ; -; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; -; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; -; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; -; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; -; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; -; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; -; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; -; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; -; 95.052 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.893 ; -; 95.052 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.893 ; -; 95.111 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.834 ; -; 95.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.732 ; -; 95.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.701 ; -; 95.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.701 ; -; 95.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.701 ; -; 95.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.701 ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Hold: 'altera_reserved_tck' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 0.401 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; -; 0.404 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.407 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.674 ; -; 0.407 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.674 ; -; 0.407 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.674 ; -; 0.407 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.674 ; -; 0.419 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.686 ; -; 0.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.694 ; -; 0.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.694 ; -; 0.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.694 ; -; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; -; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; -; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; -; 0.428 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; -; 0.428 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 0.696 ; -; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; -; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; -; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; -; 0.429 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.696 ; -; 0.429 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.696 ; -; 0.429 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.696 ; -; 0.429 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.696 ; -; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; -; 0.430 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; -; 0.430 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; -; 0.430 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; -; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; -; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; -; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; -; 0.434 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.701 ; -; 0.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.702 ; -; 0.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.702 ; -; 0.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.702 ; -; 0.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.702 ; -; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; -; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; -; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; -; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; -; 0.436 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; -; 0.436 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; -; 0.437 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.704 ; -; 0.437 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.704 ; -; 0.437 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.704 ; -; 0.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.710 ; -; 0.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.710 ; -; 0.444 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.711 ; -; 0.450 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.717 ; -; 0.450 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.717 ; -; 0.451 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.718 ; -; 0.451 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.718 ; -; 0.451 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.718 ; -; 0.451 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.718 ; -; 0.452 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.719 ; -; 0.453 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.720 ; -; 0.488 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.755 ; -; 0.552 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.819 ; -; 0.553 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.820 ; -; 0.560 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.827 ; -; 0.561 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.828 ; -; 0.561 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.828 ; -; 0.564 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.831 ; -; 0.573 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.840 ; -; 0.574 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.841 ; -; 0.574 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.841 ; -; 0.574 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.841 ; -; 0.576 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.843 ; -; 0.577 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.844 ; -; 0.577 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.844 ; -; 0.592 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.859 ; -; 0.599 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.866 ; -; 0.599 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 0.867 ; -; 0.599 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.866 ; -; 0.599 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.866 ; -; 0.601 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.868 ; -; 0.601 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.868 ; -; 0.602 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.869 ; -; 0.605 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.872 ; -; 0.607 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.874 ; -; 0.612 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.879 ; -; 0.616 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.883 ; -; 0.622 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.889 ; -; 0.622 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.889 ; -; 0.628 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.895 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Recovery: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 47.591 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 2.567 ; -; 47.694 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 2.464 ; -; 48.594 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.156 ; 1.580 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; -; 97.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.091 ; 2.745 ; -; 97.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.091 ; 2.745 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; -; 97.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.274 ; -; 97.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.274 ; -; 97.690 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.091 ; 2.237 ; -; 97.690 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.091 ; 2.237 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; -; 97.711 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.119 ; 2.188 ; -; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; -; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; -; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; -; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; -; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; -; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; -; 97.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.094 ; 2.134 ; -; 97.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.094 ; 2.134 ; -; 97.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.094 ; 2.134 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; -; 98.045 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 1.883 ; -; 98.045 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 1.883 ; -; 98.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.580 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Removal: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 1.180 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 1.448 ; -; 1.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.120 ; 1.746 ; -; 1.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.120 ; 1.746 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; -; 1.705 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.116 ; 2.007 ; -; 1.705 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.116 ; 2.007 ; -; 1.705 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.116 ; 2.007 ; -; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; -; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; -; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; -; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; -; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; -; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; -; 1.759 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.091 ; 2.036 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; -; 1.794 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.127 ; 2.107 ; -; 1.794 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.127 ; 2.107 ; -; 1.795 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.119 ; 2.100 ; -; 1.795 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.119 ; 2.100 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; -; 2.296 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.119 ; 2.601 ; -; 2.296 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.119 ; 2.601 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; -; 50.944 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.318 ; 1.448 ; -; 51.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.350 ; 2.335 ; -; 51.875 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.351 ; 2.412 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck' ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.555 ; 49.775 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; -; 49.557 ; 49.777 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.559 ; 49.779 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; -; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; -; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; -; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; -; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; -; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; -; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; -; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; -; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Setup Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 4.797 ; 5.038 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 9.083 ; 9.211 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Hold Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; -1.132 ; -1.407 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -2.605 ; -2.801 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 13.944 ; 14.539 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 11.553 ; 12.146 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - ----------------- -; MTBF Summary ; ----------------- -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 2 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 -Worst Case Available Settling Time: 197.069 ns - -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 - - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Synchronizer Summary ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ - - -Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 197.069 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.147 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 97.922 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 197.289 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.147 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 98.142 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -+-----------------------------------------------------------+ -; Slow 1200mV 0C Model Fmax Summary ; -+------------+-----------------+---------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+---------------------+------+ -; 169.03 MHz ; 169.03 MHz ; altera_reserved_tck ; ; -+------------+-----------------+---------------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+----------------------------------------------+ -; Slow 1200mV 0C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 47.042 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 1200mV 0C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.353 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Slow 1200mV 0C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 47.930 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 1200mV 0C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 1.082 ; 0.000 ; -+---------------------+-------+---------------+ - - -+--------------------------------------------------+ -; Slow 1200mV 0C Model Minimum Pulse Width Summary ; -+---------------------+--------+-------------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+-------------------+ -; altera_reserved_tck ; 49.489 ; 0.000 ; -+---------------------+--------+-------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Setup: 'altera_reserved_tck' ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 47.042 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.228 ; 3.205 ; -; 47.180 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.231 ; 3.070 ; -; 47.288 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.229 ; 2.960 ; -; 47.505 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.230 ; 2.744 ; -; 47.543 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.221 ; 2.697 ; -; 47.662 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.221 ; 2.578 ; -; 47.667 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.219 ; 2.571 ; -; 47.720 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.232 ; 2.531 ; -; 47.826 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.220 ; 2.413 ; -; 47.838 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.228 ; 2.409 ; -; 47.904 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.229 ; 2.344 ; -; 47.976 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.228 ; 2.271 ; -; 48.062 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.228 ; 2.185 ; -; 48.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.232 ; 2.072 ; -; 48.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.231 ; 2.004 ; -; 48.501 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.231 ; 1.749 ; -; 48.833 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.222 ; 1.408 ; -; 49.052 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.198 ; 1.165 ; -; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; -; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; -; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; -; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; -; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; -; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; -; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; -; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; -; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; -; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; -; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; -; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; -; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; -; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; -; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; -; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; -; 94.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.118 ; -; 94.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.118 ; -; 94.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.023 ; -; 94.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.023 ; -; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; -; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; -; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; -; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; -; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; -; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; -; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; -; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; -; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; -; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; -; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; -; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; -; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; -; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; -; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; -; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; -; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; -; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; -; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; -; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; -; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; -; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; -; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; -; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; -; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; -; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; -; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; -; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; -; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; -; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; -; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; -; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; -; 95.285 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.672 ; -; 95.285 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.672 ; -; 95.322 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.635 ; -; 95.322 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.635 ; -; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; -; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; -; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; -; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; -; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; -; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; -; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; -; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; -; 95.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.559 ; -; 95.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.559 ; -; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; -; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; -; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; -; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; -; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; -; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; -; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; -; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; -; 95.492 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 4.461 ; -; 95.492 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 4.461 ; -; 95.541 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 4.414 ; -; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; -; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; -; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; -; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; -; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'altera_reserved_tck' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.355 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.071 ; 0.597 ; -; 0.364 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; -; 0.364 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; -; 0.364 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; -; 0.365 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.608 ; -; 0.379 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.622 ; -; 0.386 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.630 ; -; 0.386 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.629 ; -; 0.387 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.630 ; -; 0.387 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.631 ; -; 0.394 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.638 ; -; 0.394 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.638 ; -; 0.395 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.638 ; -; 0.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.638 ; -; 0.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.638 ; -; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.640 ; -; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; -; 0.396 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; -; 0.396 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; -; 0.396 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.640 ; -; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.640 ; -; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; -; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; -; 0.397 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.640 ; -; 0.397 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.640 ; -; 0.398 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.641 ; -; 0.398 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.641 ; -; 0.398 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.641 ; -; 0.401 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.645 ; -; 0.401 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.644 ; -; 0.401 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.644 ; -; 0.401 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.645 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.646 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.646 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.645 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.645 ; -; 0.403 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; -; 0.403 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; -; 0.403 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; -; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; -; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; -; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; -; 0.403 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; -; 0.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.652 ; -; 0.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.652 ; -; 0.416 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.659 ; -; 0.416 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.659 ; -; 0.416 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.659 ; -; 0.416 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.659 ; -; 0.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.660 ; -; 0.417 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.660 ; -; 0.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.661 ; -; 0.418 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.661 ; -; 0.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.693 ; -; 0.507 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.750 ; -; 0.507 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.751 ; -; 0.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.755 ; -; 0.513 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.757 ; -; 0.514 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.758 ; -; 0.514 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.758 ; -; 0.526 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.769 ; -; 0.526 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.769 ; -; 0.526 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.770 ; -; 0.527 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.770 ; -; 0.528 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.772 ; -; 0.530 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.773 ; -; 0.534 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.777 ; -; 0.547 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.790 ; -; 0.547 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.791 ; -; 0.548 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.791 ; -; 0.548 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.792 ; -; 0.549 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.793 ; -; 0.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.794 ; -; 0.553 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.796 ; -; 0.554 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.797 ; -; 0.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.799 ; -; 0.557 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.801 ; -; 0.561 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.804 ; -; 0.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.805 ; -; 0.569 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.812 ; -; 0.569 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.812 ; -; 0.574 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.818 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Recovery: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 47.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.222 ; 2.311 ; -; 48.002 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.221 ; 2.238 ; -; 48.832 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.233 ; 1.420 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; -; 97.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.497 ; -; 97.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.497 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; -; 97.873 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.067 ; -; 97.873 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.067 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; -; 97.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.047 ; -; 97.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.047 ; -; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.107 ; 2.000 ; -; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; -; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; -; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; -; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; -; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; -; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; -; 98.018 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 1.919 ; -; 98.018 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 1.919 ; -; 98.018 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 1.919 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; -; 98.244 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.695 ; -; 98.244 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.695 ; -; 98.528 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.420 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Removal: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 1.082 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.326 ; -; 1.321 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.599 ; -; 1.321 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.599 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; -; 1.565 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.104 ; 1.840 ; -; 1.565 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.104 ; 1.840 ; -; 1.565 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.104 ; 1.840 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; -; 1.598 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 1.848 ; -; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; -; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; -; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; -; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; -; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; -; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; -; 1.617 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.895 ; -; 1.617 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.895 ; -; 1.653 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.114 ; 1.938 ; -; 1.653 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.114 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; -; 2.088 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 2.365 ; -; 2.088 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 2.365 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; -; 50.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.383 ; 1.326 ; -; 51.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.413 ; 2.116 ; -; 51.629 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.414 ; 2.214 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.489 ; 49.707 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; -; 49.490 ; 49.708 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; -; 49.490 ; 49.708 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; -; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.100 ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; -; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Setup Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 4.588 ; 4.953 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 8.807 ; 8.972 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Hold Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; -1.136 ; -1.533 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -2.650 ; -2.955 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 12.999 ; 13.411 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 10.643 ; 11.056 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - ----------------- -; MTBF Summary ; ----------------- -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 2 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 -Worst Case Available Settling Time: 197.362 ns - -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 - - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Synchronizer Summary ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ - - -Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 197.362 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.235 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 98.127 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 197.556 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.237 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 98.319 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -+----------------------------------------------+ -; Fast 1200mV 0C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 48.710 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Fast 1200mV 0C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.178 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Fast 1200mV 0C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 49.091 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Fast 1200mV 0C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.560 ; 0.000 ; -+---------------------+-------+---------------+ - - -+--------------------------------------------------+ -; Fast 1200mV 0C Model Minimum Pulse Width Summary ; -+---------------------+--------+-------------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+-------------------+ -; altera_reserved_tck ; 49.301 ; 0.000 ; -+---------------------+--------+-------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Setup: 'altera_reserved_tck' ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 48.710 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.437 ; 1.734 ; -; 48.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.440 ; 1.677 ; -; 48.832 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.437 ; 1.612 ; -; 48.931 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.439 ; 1.515 ; -; 48.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 1.488 ; -; 49.013 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.431 ; 1.425 ; -; 49.048 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 1.392 ; -; 49.082 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.442 ; 1.367 ; -; 49.116 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.434 ; 1.325 ; -; 49.160 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.438 ; 1.285 ; -; 49.174 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.439 ; 1.272 ; -; 49.212 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.438 ; 1.233 ; -; 49.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.438 ; 1.178 ; -; 49.342 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.442 ; 1.107 ; -; 49.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.441 ; 1.036 ; -; 49.561 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.441 ; 0.887 ; -; 49.660 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 0.780 ; -; 49.775 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.417 ; 0.649 ; -; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; -; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; -; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; -; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; -; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; -; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; -; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; -; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; -; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; -; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; -; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; -; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; -; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; -; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; -; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; -; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; -; 97.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.803 ; -; 97.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.803 ; -; 97.143 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.804 ; -; 97.143 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.804 ; -; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; -; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; -; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; -; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; -; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; -; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; -; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; -; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; -; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; -; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; -; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; -; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; -; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; -; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; -; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; -; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; -; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; -; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; -; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; -; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; -; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; -; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; -; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; -; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; -; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; -; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; -; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; -; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; -; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; -; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; -; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; -; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; -; 97.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.535 ; -; 97.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.535 ; -; 97.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.529 ; -; 97.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.529 ; -; 97.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.039 ; 2.499 ; -; 97.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.039 ; 2.499 ; -; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; -; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; -; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; -; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; -; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; -; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; -; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; -; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; -; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; -; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; -; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; -; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; -; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; -; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; -; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; -; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; -; 97.518 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.452 ; -; 97.518 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.452 ; -; 97.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.039 ; 2.401 ; -; 97.590 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.380 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.045 ; 2.367 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.045 ; 2.367 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.045 ; 2.367 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.045 ; 2.367 ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Hold: 'altera_reserved_tck' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 0.178 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.045 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.182 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; -; 0.187 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; -; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; -; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; -; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; -; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.189 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.315 ; -; 0.189 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.315 ; -; 0.189 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.315 ; -; 0.189 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.315 ; -; 0.190 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; -; 0.190 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; -; 0.190 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; -; 0.190 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; -; 0.190 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; -; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; -; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; -; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; -; 0.191 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; -; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.192 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.192 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.192 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.319 ; -; 0.193 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.319 ; -; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.319 ; -; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.322 ; -; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.322 ; -; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.322 ; -; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.322 ; -; 0.199 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; -; 0.199 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; -; 0.199 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; -; 0.199 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; -; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.326 ; -; 0.200 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.326 ; -; 0.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.327 ; -; 0.203 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.328 ; -; 0.206 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.332 ; -; 0.219 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.345 ; -; 0.247 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.373 ; -; 0.248 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.374 ; -; 0.252 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.378 ; -; 0.252 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.378 ; -; 0.252 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.378 ; -; 0.253 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.379 ; -; 0.257 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.383 ; -; 0.257 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.382 ; -; 0.258 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.384 ; -; 0.258 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.383 ; -; 0.258 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.384 ; -; 0.259 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.384 ; -; 0.260 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.386 ; -; 0.260 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.386 ; -; 0.260 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.386 ; -; 0.261 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.387 ; -; 0.261 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.387 ; -; 0.262 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.388 ; -; 0.262 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.387 ; -; 0.263 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.389 ; -; 0.263 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.388 ; -; 0.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.390 ; -; 0.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.390 ; -; 0.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.393 ; -; 0.268 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.393 ; -; 0.271 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.397 ; -; 0.272 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.398 ; -; 0.273 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.399 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Recovery: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 49.091 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 1.349 ; -; 49.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 1.267 ; -; 49.671 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.443 ; 0.779 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; -; 98.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.447 ; -; 98.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.447 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; -; 98.783 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.043 ; 1.181 ; -; 98.783 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.043 ; 1.181 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; -; 98.808 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.153 ; -; 98.808 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.153 ; -; 98.812 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 1.127 ; -; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; -; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; -; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; -; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; -; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; -; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; -; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.050 ; 1.105 ; -; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.050 ; 1.105 ; -; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.050 ; 1.105 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; -; 99.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 0.956 ; -; 99.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 0.956 ; -; 99.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.779 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Removal: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 0.560 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.043 ; 0.687 ; -; 0.686 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.837 ; -; 0.686 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.837 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; -; 0.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.064 ; 0.964 ; -; 0.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.064 ; 0.964 ; -; 0.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.064 ; 0.964 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; -; 0.828 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.980 ; -; 0.828 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.980 ; -; 0.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.046 ; 0.960 ; -; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; -; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; -; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; -; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; -; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; -; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; -; 0.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.071 ; 1.012 ; -; 0.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.071 ; 1.012 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; -; 1.098 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 1.248 ; -; 1.098 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 1.248 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; -; 50.069 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.534 ; 0.687 ; -; 50.466 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.554 ; 1.104 ; -; 50.520 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.555 ; 1.159 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.301 ; 49.517 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; -; 49.302 ; 49.518 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.303 ; 49.519 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.100 ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Setup Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 2.198 ; 2.498 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 3.853 ; 4.252 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Hold Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; -0.427 ; -0.731 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -0.933 ; -1.275 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 7.464 ; 8.013 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 6.241 ; 6.786 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - ----------------- -; MTBF Summary ; ----------------- -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 2 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 -Worst Case Available Settling Time: 198.608 ns - -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 - - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Synchronizer Summary ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ - - -Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 198.608 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.592 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 99.016 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 198.706 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.593 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 99.113 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -+----------------------------------------------------------------------------------+ -; Multicorner Timing Analysis Summary ; -+----------------------+--------+-------+----------+---------+---------------------+ -; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; -+----------------------+--------+-------+----------+---------+---------------------+ -; Worst-case Slack ; 46.656 ; 0.178 ; 47.591 ; 0.560 ; 49.301 ; -; altera_reserved_tck ; 46.656 ; 0.178 ; 47.591 ; 0.560 ; 49.301 ; -; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -; altera_reserved_tck ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; -+----------------------+--------+-------+----------+---------+---------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Setup Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 4.797 ; 5.038 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 9.083 ; 9.211 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Hold Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; -0.427 ; -0.731 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -0.933 ; -1.275 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 13.944 ; 14.539 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 6.241 ; 6.786 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Board Trace Model Assignments ; -+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; -+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_RS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_RW ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_EN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_ON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_BLON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; altera_reserved_tdo ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ - - -+----------------------------------------------------------------------------+ -; Input Transition Times ; -+-------------------------+--------------+-----------------+-----------------+ -; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; -+-------------------------+--------------+-----------------+-----------------+ -; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; KEY[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; KEY[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ; -; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; altera_reserved_tms ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; altera_reserved_tck ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; altera_reserved_tdi ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -+-------------------------+--------------+-----------------+-----------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1200mv 0c Model) ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; -; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; -; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; -; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; -; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; -; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; -; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; -; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; -; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; -; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; -; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; -; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 4.33e-08 V ; 3.11 V ; -0.0128 V ; 0.235 V ; 0.229 V ; 6.79e-10 s ; 1.6e-09 s ; Yes ; Yes ; 3.08 V ; 4.33e-08 V ; 3.11 V ; -0.0128 V ; 0.235 V ; 0.229 V ; 6.79e-10 s ; 1.6e-09 s ; Yes ; Yes ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.149 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.149 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; -; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1200mv 85c Model) ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; -; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; -; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; -; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; -; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; -; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; -; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; -; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; -; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; -; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; -; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; -; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.02e-06 V ; 3.09 V ; -0.00287 V ; 0.055 V ; 0.123 V ; 8.59e-10 s ; 2.03e-09 s ; Yes ; Yes ; 3.08 V ; 5.02e-06 V ; 3.09 V ; -0.00287 V ; 0.055 V ; 0.123 V ; 8.59e-10 s ; 2.03e-09 s ; Yes ; Yes ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; -; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Fast 1200mv 0c Model) ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; -; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; -; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; -; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; -; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; -; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; -; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; -; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; -; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; -; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; -; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; -; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 4.9e-07 V ; 3.52 V ; -0.0234 V ; 0.372 V ; 0.263 V ; 5.16e-10 s ; 1.44e-09 s ; No ; No ; 3.46 V ; 4.9e-07 V ; 3.52 V ; -0.0234 V ; 0.372 V ; 0.263 V ; 5.16e-10 s ; 1.44e-09 s ; No ; No ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; -; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+---------------------------------------------------------------------------------------+ -; Setup Transfers ; -+---------------------+---------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+----------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 1728 ; 0 ; 32 ; 2 ; -+---------------------+---------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+---------------------------------------------------------------------------------------+ -; Hold Transfers ; -+---------------------+---------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+----------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 1728 ; 0 ; 32 ; 2 ; -+---------------------+---------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+---------------------------------------------------------------------------------------+ -; Recovery Transfers ; -+---------------------+---------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+----------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 81 ; 0 ; 3 ; 0 ; -+---------------------+---------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+---------------------------------------------------------------------------------------+ -; Removal Transfers ; -+---------------------+---------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+----------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 81 ; 0 ; 3 ; 0 ; -+---------------------+---------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 1 ; 1 ; -; Unconstrained Input Ports ; 24 ; 24 ; -; Unconstrained Input Port Paths ; 90 ; 90 ; -; Unconstrained Output Ports ; 96 ; 96 ; -; Unconstrained Output Port Paths ; 129 ; 129 ; -+---------------------------------+-------+------+ - - -+------------------------------------+ -; TimeQuest Timing Analyzer Messages ; -+------------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Thu Dec 22 10:08:42 2016 -Info: Command: quartus_sta lights -c lights -Info: qsta_default_script.tcl version: #1 -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (21077): Core supply voltage is 1.2V -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (332164): Evaluating HDL-embedded SDC commands - Info (332165): Entity alt_jtag_atlantic - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] - Info (332165): Entity altera_std_synchronizer - Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] - Info (332165): Entity sld_jtag_hub - Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz - Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} -Critical Warning (332012): Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. -Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) -Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Info: Analyzing Slow 1200mV 85C Model -Info (332146): Worst-case setup slack is 46.656 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 46.656 0.000 altera_reserved_tck -Info (332146): Worst-case hold slack is 0.401 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 0.401 0.000 altera_reserved_tck -Info (332146): Worst-case recovery slack is 47.591 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 47.591 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 1.180 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 1.180 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 49.555 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 49.555 0.000 altera_reserved_tck -Info (332114): Report Metastability: Found 2 synchronizer chains. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 2 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 - Info (332114): Worst Case Available Settling Time: 197.069 ns - Info (332114): - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 -Info: Analyzing Slow 1200mV 0C Model -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. -Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) -Info (332146): Worst-case setup slack is 47.042 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 47.042 0.000 altera_reserved_tck -Info (332146): Worst-case hold slack is 0.353 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 0.353 0.000 altera_reserved_tck -Info (332146): Worst-case recovery slack is 47.930 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 47.930 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 1.082 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 1.082 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 49.489 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 49.489 0.000 altera_reserved_tck -Info (332114): Report Metastability: Found 2 synchronizer chains. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 2 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 - Info (332114): Worst Case Available Settling Time: 197.362 ns - Info (332114): - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 -Info: Analyzing Fast 1200mV 0C Model -Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. -Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) -Info (332146): Worst-case setup slack is 48.710 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 48.710 0.000 altera_reserved_tck -Info (332146): Worst-case hold slack is 0.178 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 0.178 0.000 altera_reserved_tck -Info (332146): Worst-case recovery slack is 49.091 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 49.091 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 0.560 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 0.560 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 49.301 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 49.301 0.000 altera_reserved_tck -Info (332114): Report Metastability: Found 2 synchronizer chains. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 2 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 - Info (332114): Worst Case Available Settling Time: 198.608 ns - Info (332114): - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings - Info: Peak virtual memory: 605 megabytes - Info: Processing ended: Thu Dec 22 10:08:48 2016 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:06 - - diff --git a/software/qsys_tutorial_lcd4/.cproject b/software/qsys_tutorial_lcd4/.cproject index a59f7ce..32f327b 100644 --- a/software/qsys_tutorial_lcd4/.cproject +++ b/software/qsys_tutorial_lcd4/.cproject @@ -1,508 +1,508 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - make - - mem_init_install - true - false - false - - - make - - mem_init_generate - true - false - false - - - make - - help - true - false - false - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + mem_init_install + true + false + false + + + make + + mem_init_generate + true + false + false + + + make + + help + true + false + false + + + + diff --git a/software/qsys_tutorial_lcd4/.project b/software/qsys_tutorial_lcd4/.project index 24528eb..9112c8d 100644 --- a/software/qsys_tutorial_lcd4/.project +++ b/software/qsys_tutorial_lcd4/.project @@ -1,96 +1,96 @@ - - - qsys_tutorial_lcd4 - - - - - - com.altera.sbtgui.project.makefileBuilder - - - - - com.altera.sbtgui.project.makefileBuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc://qsys_tutorial_lcd4} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.core.ccnature - com.altera.sbtgui.project.SBTGUINature - com.altera.sbtgui.project.SBTGUIAppNature - com.altera.sbtgui.project.SBTGUIManagedNature - - + + + qsys_tutorial_lcd4 + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://qsys_tutorial_lcd4} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/software/qsys_tutorial_lcd4/Makefile b/software/qsys_tutorial_lcd4/Makefile index d7d8325..aa1c4b3 100644 --- a/software/qsys_tutorial_lcd4/Makefile +++ b/software/qsys_tutorial_lcd4/Makefile @@ -1,1097 +1,1097 @@ -#------------------------------------------------------------------------------ -# VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS -#------------------------------------------------------------------------------ - -# List of include directories for -I compiler option (-I added when used). -# Includes the BSP. -ALT_INCLUDE_DIRS := - -# List of library directories for -L linker option (-L added when used). -# Includes the BSP. -ALT_LIBRARY_DIRS := - -# List of library names for -l linker option (-l added when used). -# Includes the BSP. -ALT_LIBRARY_NAMES := - -# List of library names for -msys-lib linker option (-msys-lib added when used). -# These are libraries that might be located in the BSP and depend on the BSP -# library, or vice versa -ALT_BSP_DEP_LIBRARY_NAMES := - -# List of dependencies for the linker. This is usually the full pathname -# of each library (*.a) file. -# Includes the BSP. -ALT_LDDEPS := - -# List of root library directories that support running make to build them. -# Includes the BSP and any ALT libraries. -MAKEABLE_LIBRARY_ROOT_DIRS := - -# Generic flags passed to the compiler for different types of input files. -ALT_CFLAGS := -ALT_CXXFLAGS := -ALT_CPPFLAGS := -ALT_ASFLAGS := -ALT_LDFLAGS := - - -#------------------------------------------------------------------------------ -# The adjust-path macro -# -# If COMSPEC/ComSpec is defined, Make is launched from Windows through -# Cygwin. The adjust-path macro converts absolute windows paths into -# unix style paths (Example: c:/dir -> /c/dir). This will ensture -# paths are readable by GNU Make. -# -# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no -# adjustment is necessary -# -#------------------------------------------------------------------------------ - -ifndef COMSPEC -ifdef ComSpec -COMSPEC = $(ComSpec) -endif # ComSpec -endif # COMSPEC - -ifdef COMSPEC # if Windows OS - -ifeq ($(MAKE_VERSION),3.81) -# -# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows -# -# Example Usage: -# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb -# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb -# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb -# - -# -# adjust-path -# - converts back slash characters into forward slashes -# - if input arg ($1) is an empty string then return the empty string -# - if input arg ($1) does not contain the string ":/", then return input arg -# - using sed, convert mixed path [c:/...] into mingw path [/c/...] -define adjust-path -$(strip \ -$(if $1,\ -$(if $(findstring :/,$(subst \,/,$1)),\ -$(shell echo $(subst \,/,$1) | sed -e 's,^$[a-zA-Z]$:/,/\1/,'),\ -$(subst \,/,$1)))) -endef - -# -# adjust-path-mixed -# - converts back slash characters into forward slashes -# - if input arg ($1) is an empty string then return the empty string -# - if input arg ($1) does not begin with a forward slash '/' char, then -# return input arg -# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] -# into a mixed path [c:/...] -define adjust-path-mixed -$(strip \ -$(if $1,\ -$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ -$(subst \,/,$1),\ -$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/$[a-zA-Z]$/,\1:/,' -e 's,^/$[a-zA-Z]$/,\1:/,')))) -endef - -else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) -# -# adjust-path for Cygwin Gnu Make -# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb -# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb -# -adjust-path = $(if $1,$(shell cygpath -u "$1"),) -adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),) -endif - -else # !COMSPEC - -adjust-path = $1 -adjust-path-mixed = $1 - -endif # COMSPEC - - -#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -# GENERATED SETTINGS START v -#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv - -#START GENERATED -ACTIVE_BUILD_CONFIG := default -BUILD_CONFIGS := default - -# The following TYPE comment allows tools to identify the 'type' of target this -# makefile is associated with. -# TYPE: APP_MAKEFILE - -# This following VERSION comment indicates the version of the tool used to -# generate this makefile. A makefile variable is provided for VERSION as well. -# ACDS_VERSION: 13.0sp1 -ACDS_VERSION := 13.0sp1 - -# This following BUILD_NUMBER comment indicates the build number of the tool -# used to generate this makefile. -# BUILD_NUMBER: 232 - +#------------------------------------------------------------------------------ +# VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS +#------------------------------------------------------------------------------ + +# List of include directories for -I compiler option (-I added when used). +# Includes the BSP. +ALT_INCLUDE_DIRS := + +# List of library directories for -L linker option (-L added when used). +# Includes the BSP. +ALT_LIBRARY_DIRS := + +# List of library names for -l linker option (-l added when used). +# Includes the BSP. +ALT_LIBRARY_NAMES := + +# List of library names for -msys-lib linker option (-msys-lib added when used). +# These are libraries that might be located in the BSP and depend on the BSP +# library, or vice versa +ALT_BSP_DEP_LIBRARY_NAMES := + +# List of dependencies for the linker. This is usually the full pathname +# of each library (*.a) file. +# Includes the BSP. +ALT_LDDEPS := + +# List of root library directories that support running make to build them. +# Includes the BSP and any ALT libraries. +MAKEABLE_LIBRARY_ROOT_DIRS := + +# Generic flags passed to the compiler for different types of input files. +ALT_CFLAGS := +ALT_CXXFLAGS := +ALT_CPPFLAGS := +ALT_ASFLAGS := +ALT_LDFLAGS := + + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC/ComSpec is defined, Make is launched from Windows through +# Cygwin. The adjust-path macro converts absolute windows paths into +# unix style paths (Example: c:/dir -> /c/dir). This will ensture +# paths are readable by GNU Make. +# +# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no +# adjustment is necessary +# +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # COMSPEC + +ifdef COMSPEC # if Windows OS + +ifeq ($(MAKE_VERSION),3.81) +# +# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows +# +# Example Usage: +# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb +# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb +# + +# +# adjust-path +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not contain the string ":/", then return input arg +# - using sed, convert mixed path [c:/...] into mingw path [/c/...] +define adjust-path +$(strip \ +$(if $1,\ +$(if $(findstring :/,$(subst \,/,$1)),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^$[a-zA-Z]$:/,/\1/,'),\ +$(subst \,/,$1)))) +endef + +# +# adjust-path-mixed +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not begin with a forward slash '/' char, then +# return input arg +# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] +# into a mixed path [c:/...] +define adjust-path-mixed +$(strip \ +$(if $1,\ +$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ +$(subst \,/,$1),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/$[a-zA-Z]$/,\1:/,' -e 's,^/$[a-zA-Z]$/,\1:/,')))) +endef + +else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) +# +# adjust-path for Cygwin Gnu Make +# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb +# +adjust-path = $(if $1,$(shell cygpath -u "$1"),) +adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),) +endif + +else # !COMSPEC + +adjust-path = $1 +adjust-path-mixed = $1 + +endif # COMSPEC + + +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv +# GENERATED SETTINGS START v +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv + +#START GENERATED +ACTIVE_BUILD_CONFIG := default +BUILD_CONFIGS := default + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: APP_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + # Define path to the application ELF. # It may be used by the makefile fragments so is defined before including them. -# -ELF := qsys_tutorial_lcd4.elf - -# Paths to C, C++, and assembly source files. -C_SRCS += LCD.c -C_SRCS += hello_world_small.c -C_SRCS += hex_encoder.c -C_SRCS += hex_out.c -C_SRCS += input_int.c -C_SRCS += inst_decoder.c -C_SRCS += sys_memory.c -C_SRCS += sys_register.c -C_SRCS += sys_except.c -C_SRCS += lcd_out.c -C_SRCS += sys_debug.c -C_SRCS += sys_prog.c -CXX_SRCS := -ASM_SRCS := - - +# +ELF := qsys_tutorial_lcd4.elf + +# Paths to C, C++, and assembly source files. +C_SRCS += LCD.c +C_SRCS += hello_world_small.c +C_SRCS += hex_encoder.c +C_SRCS += hex_out.c +C_SRCS += input_int.c +C_SRCS += inst_decoder.c +C_SRCS += sys_memory.c +C_SRCS += sys_register.c +C_SRCS += sys_except.c +C_SRCS += lcd_out.c +C_SRCS += sys_debug.c +C_SRCS += sys_prog.c +CXX_SRCS := +ASM_SRCS := + + # Path to root of object file tree. -OBJ_ROOT_DIR := obj - +OBJ_ROOT_DIR := obj + # Options to control objdump. -CREATE_OBJDUMP := 1 -OBJDUMP_INCLUDE_SOURCE := 1 -OBJDUMP_FULL_CONTENTS := 0 - +CREATE_OBJDUMP := 1 +OBJDUMP_INCLUDE_SOURCE := 1 +OBJDUMP_FULL_CONTENTS := 0 + # Options to enable/disable optional files. -CREATE_ELF_DERIVED_FILES := 0 -CREATE_LINKER_MAP := 1 - -# Common arguments for ALT_CFLAGSs -APP_CFLAGS_DEFINED_SYMBOLS := -APP_CFLAGS_UNDEFINED_SYMBOLS := -APP_CFLAGS_OPTIMIZATION := -O0 -APP_CFLAGS_DEBUG_LEVEL := -g -APP_CFLAGS_WARNINGS := -Wall -APP_CFLAGS_USER_FLAGS := - -APP_ASFLAGS_USER := -APP_LDFLAGS_USER := - +CREATE_ELF_DERIVED_FILES := 0 +CREATE_LINKER_MAP := 1 + +# Common arguments for ALT_CFLAGSs +APP_CFLAGS_DEFINED_SYMBOLS := +APP_CFLAGS_UNDEFINED_SYMBOLS := +APP_CFLAGS_OPTIMIZATION := -O0 +APP_CFLAGS_DEBUG_LEVEL := -g +APP_CFLAGS_WARNINGS := -Wall +APP_CFLAGS_USER_FLAGS := + +APP_ASFLAGS_USER := +APP_LDFLAGS_USER := + # Linker options that have default values assigned later if not # assigned here. -LINKER_SCRIPT := -CRT0 := -SYS_LIB := - -# Define path to the root of the BSP. -BSP_ROOT_DIR := ../qsys_tutorial_lcd4_bsp/ - -# List of application specific include directories, library directories and library names -APP_INCLUDE_DIRS := -APP_LIBRARY_DIRS := -APP_LIBRARY_NAMES := - -# Pre- and post- processor settings. -BUILD_PRE_PROCESS := -BUILD_POST_PROCESS := - -QUARTUS_PROJECT_DIR := ../../ - - -#END GENERATED - -#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -# GENERATED SETTINGS END ^ -#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - -#------------------------------------------------------------------------------ -# DEFAULT TARGET -#------------------------------------------------------------------------------ - -# Define the variable used to echo output if not already defined. -ifeq ($(ECHO),) -ECHO := echo -endif - -# Put "all" rule before included makefile fragments because they may -# define rules and we don't want one of those to become the default rule. -.PHONY : all - -all: - @$(ECHO) [$(APP_NAME) build complete] - -all : build_pre_process libs app build_post_process - - -#------------------------------------------------------------------------------ -# VARIABLES DEPENDENT ON GENERATED CONTENT -#------------------------------------------------------------------------------ - -# Define object file directory per build configuration -CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG) - -ifeq ($(BSP_ROOT_DIR),) -$(error Edit Makefile and provide a value for BSP_ROOT_DIR) -endif - -ifeq ($(wildcard $(BSP_ROOT_DIR)),) -$(error BSP directory does not exist: $(BSP_ROOT_DIR)) -endif - -# Define absolute path to the root of the BSP. -ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) - -# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before -# including each makefile fragment so that it knows the path to itself. -BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk -ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) -include $(BSP_INCLUDE_FILE) -# C2H will need this to touch the BSP public.mk and avoid the sopc file -# out-of-date error during a BSP make -ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk - - -ifneq ($(WARNING.SMALL_STACK_SIZE),) -# This WARNING is here to protect you from unknowingly using a very small stack -# If the warning is set, increase your stack size or enable the BSP small stack -# setting to eliminate the warning -$(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) -endif - - -# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF -# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. -ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) -ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) -endif - -# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to -# download_elf target -ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) -GMON_OUT_FILENAME := gmon.out -WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME) -endif - -# Name of ELF application. -APP_NAME := $(basename $(ELF)) - -# Set to defaults if variables not already defined in settings. -ifeq ($(LINKER_SCRIPT),) -LINKER_SCRIPT := $(BSP_LINKER_SCRIPT) -endif -ifeq ($(CRT0),) -CRT0 := $(BSP_CRT0) -endif -ifeq ($(SYS_LIB),) -SYS_LIB := $(BSP_SYS_LIB) -endif - -OBJDUMP_NAME := $(APP_NAME).objdump -OBJDUMP_FLAGS := --disassemble --syms --all-header -ifeq ($(OBJDUMP_INCLUDE_SOURCE),1) -OBJDUMP_FLAGS += --source -endif -ifeq ($(OBJDUMP_FULL_CONTENTS),1) -OBJDUMP_FLAGS += --full-contents -endif - -# Create list of linker dependencies (*.a files). -APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS) - -# Take lists and add required prefixes. -APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) -ASM_INC_PREFIX := -Wa,-I -APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) -APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS)) -APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS)) - -ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) - -# -# Avoid Nios II GCC 3.X options. -# - -# Detect if small newlib C library is requested. -# If yes, remove the -msmallc option because it is -# now handled by other means. -ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),) - ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS)) - ALT_C_LIBRARY := smallc -else - ALT_C_LIBRARY := c -endif - -# Put each BSP dependent library in a group to avoid circular dependencies. -APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group) - -else # !AVOID_NIOS2_GCC3_OPTIONS - -# -# Use Nios II GCC 3.X options. -# -APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES)) - -endif # !AVOID_NIOS2_GCC3_OPTIONS - -# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker. -APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \ - $(APP_CFLAGS_UNDEFINED_SYMBOLS) \ - $(APP_CFLAGS_OPTIMIZATION) \ - $(APP_CFLAGS_DEBUG_LEVEL) \ - $(APP_CFLAGS_WARNINGS) \ - $(APP_CFLAGS_USER_FLAGS) \ - $(ALT_CFLAGS) \ - $(CFLAGS) - -# Arguments only for the C++ compiler. -APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS) - -# Arguments only for the C preprocessor. -# Prefix each include directory with -I. -APP_CPPFLAGS := $(APP_INC_DIRS) \ - $(ALT_CPPFLAGS) \ - $(CPPFLAGS) - -# Arguments only for the assembler. -APP_ASFLAGS := $(APP_ASM_INC_DIRS) \ - $(ALT_ASFLAGS) \ - $(APP_ASFLAGS_USER) \ - $(ASFLAGS) - -# Arguments only for the linker. -APP_LDFLAGS := $(APP_LDFLAGS_USER) - -ifneq ($(LINKER_SCRIPT),) -APP_LDFLAGS += -T'$(LINKER_SCRIPT)' -endif - -ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) - -# Avoid Nios II GCC 3.x options. -ifneq ($(CRT0),) -APP_LDFLAGS += $(CRT0) -endif - -# The equivalent of the -msys-lib option is provided -# by the GROUP() command in the linker script. -# Note this means the SYS_LIB variable is now ignored. - -else # !AVOID_NIOS2_GCC3_OPTIONS - -# Use Nios II GCC 3.x options. -ifneq ($(CRT0),) -APP_LDFLAGS += -msys-crt0='$(CRT0)' -endif -ifneq ($(SYS_LIB),) -APP_LDFLAGS += -msys-lib=$(SYS_LIB) -endif - -endif # !AVOID_NIOS2_GCC3_OPTIONS - -APP_LDFLAGS += \ - $(APP_LIB_DIRS) \ - $(ALT_LDFLAGS) \ - $(LDFLAGS) - -LINKER_MAP_NAME := $(APP_NAME).map -ifeq ($(CREATE_LINKER_MAP), 1) -APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) -endif - -# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the -# mem_init_install target of the mem_init.mk (located in the associated BSP) -# to know how to copy memory initialization files (e.g. .dat, .hex) into -# directories required for Quartus compilation or RTL simulation. - -# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory -# initialization files into your Quartus project directory. This is required -# to provide the initial memory contents of FPGA memories that can be -# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used -# for VHDL simulation of on-chip memories. - -# Defining SOPC_NAME causes the mem_init_install target to copy memory -# initialization files into your RTL simulation directory. This is required -# to provide the initial memory contents of all memories that can be -# initialized by RTL simulation. This variable should be set to the same name -# as your SOPC Builder system name. For example, if you have a system called -# "foo.sopc", this variable should be set to "foo". - -# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. -ifeq ($(SOPC_NAME),) -ifneq ($(QUARTUS_PROJECT_DIR),) -SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) -endif -endif - -# Defining JDI_FILE is required to specify the JTAG Debug Information File -# path. This file is generated by Quartus, and is needed along with the -# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU -# systems. For multi-CPU systems, the processor instance ID is used to select -# from multiple CPU's during ELF download. - -# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during -# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then -# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be -# multiple .sopcinfo files in a Quartus project. -ifeq ($(JDI_FILE),) -ifneq ($(QUARTUS_PROJECT_DIR),) -JDI_FILE := $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi) -endif -endif - -# Path to root runtime directory used for hdl simulation -RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime - - - -#------------------------------------------------------------------------------ -# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT -#------------------------------------------------------------------------------ -# mem_init.mk is a generated makefile fragment. This file defines all targets -# used to generate HDL initialization simulation files and pre-initialized -# onchip memory files. -MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk -include $(MEM_INIT_FILE) - -# Create list of object files to be built using the list of source files. -# The source file hierarchy is preserved in the object tree. -# The supported file extensions are: -# -# .c - for C files -# .cxx .cc .cpp - for C++ files -# .S .s - for assembler files -# -# Handle source files specified by --src-dir & --src-rdir differently, to -# save some processing time in calling the adjust-path macro. - -OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS))) -OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS))) -OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS))) -OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS))) -OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS))) -OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS))) - -OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \ - $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS)) - -SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS))) -SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS))) -SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS))) -SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS))) -SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS))) -SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS))) - -SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ - $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \ - $(SDIR_OBJ_LIST_SS)) - -# Relative-pathed objects that being with "../" are handled differently. -# -# Regular objects are created as -# $(CONFIG_OBJ_DIR)//.o -# where the path structure is maintained under the obj directory. This -# applies for both absolute and relative paths; in the absolute path -# case this means the entire source path will be recreated under the obj -# directory. This is done to allow two source files with the same name -# to be included as part of the project. -# -# Note: On Cygwin, the path recreated under the obj directory will be -# the cygpath -u output path. -# -# Relative-path objects that begin with "../" cause problems under this -# scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object -# files anywhere in the system, creating clutter and polluting the source tree. -# As such, their paths are flattened - the object file created will be -# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with -# "../" in the beginning cannot have the same name in the project. VPATH -# will be set for these sources to allow make to relocate the source file -# via %.o rules. -# -# The following lines separate the object list into the flatten and regular -# lists, and then handles them as appropriate. - -FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST)) -FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST))) - -REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST)) -REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST)) -REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST)) -REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST)) -REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST)) -REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST)) -REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST)) - -FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST)) -FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST))) - -REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST)) -REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST)) -REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST)) -REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST)) -REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST)) -REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST)) -REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST)) - -VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST))) - -APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\ - $(REGULAR_SDIR_OBJ_LIST_C) \ - $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s))) - -APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\ - $(REGULAR_SDIR_OBJ_LIST_CPP) \ - $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s))) - -APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\ - $(REGULAR_SDIR_OBJ_LIST_CXX) \ - $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s))) - -APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\ - $(REGULAR_SDIR_OBJ_LIST_CC) \ - $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s))) - -APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\ - $(REGULAR_SDIR_OBJ_LIST_S) \ - $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s))) - -APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\ - $(REGULAR_SDIR_OBJ_LIST_SS) \ - $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s))) - -APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \ - $(APP_OBJS_S) $(APP_OBJS_SS) \ - $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS) - -# Add any extra user-provided object files. -APP_OBJS += $(OBJS) - -# Create list of dependancy files for each object file. -APP_DEPS := $(APP_OBJS:.o=.d) - -# Patch the Elf file with system specific information - -# Patch the Elf with the name of the sopc system -ifneq ($(SOPC_NAME),) -ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME) -endif - -# Patch the Elf with the absolute path to the Quartus Project Directory -ifneq ($(QUARTUS_PROJECT_DIR),) -ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd)) -ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)" -endif - -# Patch the Elf and download args with the JDI_FILE if specified -ifneq ($(wildcard $(JDI_FILE)),) -ELF_PATCH_FLAG += --jdi $(JDI_FILE) -DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE) -endif - -# Patch the Elf with the SOPCINFO_FILE if specified -ifneq ($(wildcard $(SOPCINFO_FILE)),) -ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) -endif - -# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. -# This is not needed if you only have one cable. -ifneq ($(DOWNLOAD_CABLE),) -DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' -endif - - -#------------------------------------------------------------------------------ -# BUILD PRE/POST PROCESS -#------------------------------------------------------------------------------ -build_pre_process : - $(BUILD_PRE_PROCESS) - -build_post_process : - $(BUILD_POST_PROCESS) - -.PHONY: build_pre_process build_post_process - - -#------------------------------------------------------------------------------ -# TOOLS -#------------------------------------------------------------------------------ - -# -# Set tool default variables if not already defined. -# If these are defined, they would typically be defined in an -# included makefile fragment. -# -ifeq ($(DEFAULT_CROSS_COMPILE),) -DEFAULT_CROSS_COMPILE := nios2-elf- -endif - -ifeq ($(DEFAULT_STACK_REPORT),) -DEFAULT_STACKREPORT := nios2-stackreport -endif - -ifeq ($(DEFAULT_DOWNLOAD),) -DEFAULT_DOWNLOAD := nios2-download -endif - -ifeq ($(DEFAULT_FLASHPROG),) -DEFAULT_FLASHPROG := nios2-flash-programmer -endif - -ifeq ($(DEFAULT_ELFPATCH),) -DEFAULT_ELFPATCH := nios2-elf-insert -endif - -ifeq ($(DEFAULT_RM),) -DEFAULT_RM := rm -f -endif - -ifeq ($(DEFAULT_CP),) -DEFAULT_CP := cp -f -endif - -ifeq ($(DEFAULT_MKDIR),) -DEFAULT_MKDIR := mkdir -p -endif - -# -# Set tool variables to defaults if not already defined. -# If these are defined, they would typically be defined by a -# setting in the generated portion of this makefile. -# -ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE) -endif - -ifeq ($(origin CC),default) -CC := $(CROSS_COMPILE)gcc -xc -endif - -ifeq ($(origin CXX),default) -CXX := $(CROSS_COMPILE)gcc -xc++ -endif - -ifeq ($(origin AS),default) -AS := $(CROSS_COMPILE)gcc -endif - -ifeq ($(origin AR),default) -AR := $(CROSS_COMPILE)ar -endif - -ifeq ($(origin LD),default) -LD := $(CROSS_COMPILE)g++ -endif - -ifeq ($(origin NM),default) -NM := $(CROSS_COMPILE)nm -endif - -ifeq ($(origin RM),default) -RM := $(DEFAULT_RM) -endif - -ifeq ($(origin CP),default) -CP := $(DEFAULT_CP) -endif - -ifeq ($(OBJDUMP),) -OBJDUMP := $(CROSS_COMPILE)objdump -endif - -ifeq ($(OBJCOPY),) -OBJCOPY := $(CROSS_COMPILE)objcopy -endif - -ifeq ($(STACKREPORT),) -ifeq ($(CROSS_COMPILE),nios2-elf-) -STACKREPORT := $(DEFAULT_STACKREPORT) -else -DISABLE_STACKREPORT := 1 -endif -endif - -ifeq ($(DOWNLOAD),) -DOWNLOAD := $(DEFAULT_DOWNLOAD) -endif - -ifeq ($(FLASHPROG),) -FLASHPROG := $(DEFAULT_FLASHPROG) -endif - -ifeq ($(ELFPATCH),) -ELFPATCH := $(DEFAULT_ELFPATCH) -endif - -ifeq ($(MKDIR),) -MKDIR := $(DEFAULT_MKDIR) -endif - -#------------------------------------------------------------------------------ -# PATTERN RULES TO BUILD OBJECTS -#------------------------------------------------------------------------------ - -define compile.c -@$(ECHO) Info: Compiling $< to $@ -@$(MKDIR) $(@D) -$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< -$(CC_POST_PROCESS) -endef - -define compile.cpp -@$(ECHO) Info: Compiling $< to $@ -@$(MKDIR) $(@D) -$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< -$(CXX_POST_PROCESS) -endef - -# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS -ifeq ($(AS),$(patsubst %as,%,$(AS))) -COMMA := , -APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS)))) -endif - -define compile.s -@$(ECHO) Info: Assembling $< to $@ -@$(MKDIR) $(@D) -$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< -$(AS_POST_PROCESS) -endef - -ifeq ($(MAKE_VERSION),3.81) -.SECONDEXPANSION: - -$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) - $(compile.c) - -$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp) - $(compile.cpp) - -$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc) - $(compile.cpp) - -$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx) - $(compile.cpp) - -$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S) - $(compile.s) - -$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s) - $(compile.s) - -endif # MAKE_VERSION != 3.81 - -$(CONFIG_OBJ_DIR)/%.o: %.c - $(compile.c) - -$(CONFIG_OBJ_DIR)/%.o: %.cpp - $(compile.cpp) - -$(CONFIG_OBJ_DIR)/%.o: %.cc - $(compile.cpp) - -$(CONFIG_OBJ_DIR)/%.o: %.cxx - $(compile.cpp) - -$(CONFIG_OBJ_DIR)/%.o: %.S - $(compile.s) - -$(CONFIG_OBJ_DIR)/%.o: %.s - $(compile.s) - - -#------------------------------------------------------------------------------ -# PATTERN RULES TO INTERMEDIATE FILES -#------------------------------------------------------------------------------ - -$(CONFIG_OBJ_DIR)/%.s: %.c - @$(ECHO) Info: Compiling $< to $@ - @$(MKDIR) $(@D) - $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< - -$(CONFIG_OBJ_DIR)/%.s: %.cpp - @$(ECHO) Info: Compiling $< to $@ - @$(MKDIR) $(@D) - $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< - -$(CONFIG_OBJ_DIR)/%.s: %.cc - @$(ECHO) Info: Compiling $< to $@ - @$(MKDIR) $(@D) - $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< - -$(CONFIG_OBJ_DIR)/%.s: %.cxx - @$(ECHO) Info: Compiling $< to $@ - @$(MKDIR) $(@D) - $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< - -$(CONFIG_OBJ_DIR)/%.i: %.c - @$(ECHO) Info: Compiling $< to $@ - @$(MKDIR) $(@D) - $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< - -$(CONFIG_OBJ_DIR)/%.i: %.cpp - @$(ECHO) Info: Compiling $< to $@ - @$(MKDIR) $(@D) - $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< - -$(CONFIG_OBJ_DIR)/%.i: %.cc - @$(ECHO) Info: Compiling $< to $@ - @$(MKDIR) $(@D) - $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< - -$(CONFIG_OBJ_DIR)/%.i: %.cxx - @$(ECHO) Info: Compiling $< to $@ - @$(MKDIR) $(@D) - $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< - - -#------------------------------------------------------------------------------ -# TARGET RULES -#------------------------------------------------------------------------------ - -.PHONY : help -help : - @$(ECHO) "Summary of Makefile targets" - @$(ECHO) " Build targets:" - @$(ECHO) " all (default) - Application and all libraries (including BSP)" - @$(ECHO) " bsp - Just the BSP" - @$(ECHO) " libs - All libraries (including BSP)" - @$(ECHO) " flash - All flash files" - @$(ECHO) " mem_init_generate - All memory initialization files" -ifeq ($(QSYS),1) - @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" - @$(ECHO) " --> Use the mem_init_generate target and then" - @$(ECHO) " add the generated meminit.qip file to your" - @$(ECHO) " Quartus II Project." -else # if QSYS != 1 - @$(ECHO) " mem_init_install - Copy memory initialization files to Quartus II project" -endif # QSYS == 1 - @$(ECHO) - @$(ECHO) " Clean targets:" - @$(ECHO) " clean_all - Application and all libraries (including BSP)" - @$(ECHO) " clean - Just the application" - @$(ECHO) " clean_bsp - Just the BSP" - @$(ECHO) " clean_libs - All libraries (including BSP)" - @$(ECHO) - @$(ECHO) " Run targets:" - @$(ECHO) " download-elf - Download and run your elf executable" - @$(ECHO) " program-flash - Program flash contents to the board" - -# Handy rule to skip making libraries and just make application. -.PHONY : app -app : $(ELF) - -ifeq ($(CREATE_OBJDUMP), 1) -app : $(OBJDUMP_NAME) -endif - -ifeq ($(CREATE_ELF_DERIVED_FILES),1) -app : elf_derived_files -endif - -.PHONY: elf_derived_files -elf_derived_files: default_mem_init - -# Handy rule for making just the BSP. -.PHONY : bsp -bsp : - @$(ECHO) Info: Building $(BSP_ROOT_DIR) - @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) - - -# Make sure all makeable libraries (including the BSP) are up-to-date. -LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) - -.PHONY : libs -libs : $(LIB_TARGETS) - -ifneq ($(strip $(LIB_TARGETS)),) -$(LIB_TARGETS): %-recurs-make-lib: - @$(ECHO) Info: Building $* - $(MAKE) --no-print-directory -C $* -endif - -ifneq ($(strip $(APP_LDDEPS)),) -$(APP_LDDEPS): libs - @true -endif - -# Rules to force your project to rebuild or relink -# .force_relink file will cause any application that depends on this project to relink -# .force_rebuild file will cause this project to rebuild object files -# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files - -FORCE_RELINK_DEP := .force_relink -FORCE_REBUILD_DEP := .force_rebuild -FORCE_REBUILD_ALL_DEP := .force_rebuild_all -FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) - -$(FORCE_REBUILD_DEP_LIST): - -$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS))) - -$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS))) - - -# Clean just the application. -.PHONY : clean -ifeq ($(CREATE_ELF_DERIVED_FILES),1) -clean : clean_elf_derived_files -endif - -clean : - @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) - @$(ECHO) [$(APP_NAME) clean complete] - -# Clean just the BSP. -.PHONY : clean_bsp -clean_bsp : - @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR) - @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean - -# Clean all makeable libraries including the BSP. -LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) - -.PHONY : clean_libs -clean_libs : $(LIB_CLEAN_TARGETS) - -ifneq ($(strip $(LIB_CLEAN_TARGETS)),) -$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib: - @$(ECHO) Info: Cleaning $* - $(MAKE) --no-print-directory -C $* clean -endif - -.PHONY: clean_elf_derived_files -clean_elf_derived_files: mem_init_clean - -# Clean application and all makeable libraries including the BSP. -.PHONY : clean_all -clean_all : clean mem_init_clean clean_libs - -# Include the dependency files unless the make goal is performing a clean -# of the application. -ifneq ($(firstword $(MAKECMDGOALS)),clean) -ifneq ($(firstword $(MAKECMDGOALS)),clean_all) --include $(APP_DEPS) -endif -endif - -.PHONY : download-elf -download-elf : $(ELF) - @if [ "$(DOWNLOAD)" = "none" ]; \ - then \ - $(ECHO) Downloading $(ELF) not supported; \ - else \ - $(ECHO) Info: Downloading $(ELF); \ - $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ - fi - -# Delete the target of a rule if it has changed and its commands exit -# with a nonzero exit status. -.DELETE_ON_ERROR: - -# Rules for flash programming commands -PROGRAM_FLASH_SUFFIX := -program -PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES)) - -.PHONY : program-flash -program-flash : $(PROGRAM_FLASH_TARGET) - -.PHONY : $(PROGRAM_FLASH_TARGET) -$(PROGRAM_FLASH_TARGET) : flash - @if [ "$(FLASHPROG)" = "none" ]; \ - then \ - $(ECHO) Programming flash not supported; \ - else \ - $(ECHO) Info: Programming $(basename $@).flash; \ - if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \ - then \ - $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ - $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ - else \ - $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ - $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ - fi \ - fi - - -# Rules for simulating with an HDL Simulator [QSYS only] -ifeq ($(QSYS),1) -IP_MAKE_SIMSCRIPT := ip-make-simscript - -ifeq ($(VSIM),) -VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim" -ifeq ($(ENABLE_VSIM_GUI),1) -VSIM := $(VSIM_EXE) -gui -else -VSIM := $(VSIM_EXE) -c -endif # ENABLE_VSIM_GUI == 1 -endif # VSIM not set - -ifeq ($(SPD),) -ifneq ($(ABS_QUARTUS_PROJECT_DIR),) -ifneq ($(SOPC_NAME),) -SPD := $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd -endif # SOPC_NAME set -endif # ABS_QUARTUS_PROJECT_DIR set -endif # SPD == empty string - -ifeq ($(MSIM_SCRIPT),) -SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim -MSIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/msim_setup.tcl -endif # MSIM_SCRIPT == empty string - -ifeq ($(MAKE_VERSION),3.81) -ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE)) -else -ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE) -endif - -$(MSIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE) -ifeq ($(SPD),) - $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set) -endif - @$(MKDIR) $(SIM_SCRIPT_DIR) - $(IP_MAKE_SIMSCRIPT) --spd=$(SPD) --spd=$(MEM_INIT_DESCRIPTOR_FILE) --output-directory=$(SIM_SCRIPT_DIR) - -VSIM_COMMAND = \ - cd $(dir $(MSIM_SCRIPT)) && \ - $(VSIM) -do "do $(notdir $(MSIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)" - -.PHONY: sim -sim: $(MSIM_SCRIPT) mem_init_generate -ifeq ($(MSIM_SCRIPT),) - $(error MSIM_SCRIPT not set) -endif - $(VSIM_COMMAND) - -endif # QSYS == 1 - - -#------------------------------------------------------------------------------ -# ELF TARGET RULE -#------------------------------------------------------------------------------ -# Rule for constructing the executable elf file. -$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS) - @$(ECHO) Info: Linking $@ - $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS) -ifneq ($(DISABLE_ELFPATCH),1) - $(ELFPATCH) $@ $(ELF_PATCH_FLAG) -endif -ifneq ($(DISABLE_STACKREPORT),1) - @bash -c "$(STACKREPORT) $@" -endif - -$(OBJDUMP_NAME) : $(ELF) - @$(ECHO) Info: Creating $@ - $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@ - -# Rule for printing the name of the elf file -.PHONY: print-elf-name -print-elf-name: - @$(ECHO) $(ELF) - - +LINKER_SCRIPT := +CRT0 := +SYS_LIB := + +# Define path to the root of the BSP. +BSP_ROOT_DIR := ../qsys_tutorial_lcd4_bsp/ + +# List of application specific include directories, library directories and library names +APP_INCLUDE_DIRS := +APP_LIBRARY_DIRS := +APP_LIBRARY_NAMES := + +# Pre- and post- processor settings. +BUILD_PRE_PROCESS := +BUILD_POST_PROCESS := + +QUARTUS_PROJECT_DIR := ../../ + + +#END GENERATED + +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +# GENERATED SETTINGS END ^ +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +#------------------------------------------------------------------------------ + +# Define the variable used to echo output if not already defined. +ifeq ($(ECHO),) +ECHO := echo +endif + +# Put "all" rule before included makefile fragments because they may +# define rules and we don't want one of those to become the default rule. +.PHONY : all + +all: + @$(ECHO) [$(APP_NAME) build complete] + +all : build_pre_process libs app build_post_process + + +#------------------------------------------------------------------------------ +# VARIABLES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ + +# Define object file directory per build configuration +CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG) + +ifeq ($(BSP_ROOT_DIR),) +$(error Edit Makefile and provide a value for BSP_ROOT_DIR) +endif + +ifeq ($(wildcard $(BSP_ROOT_DIR)),) +$(error BSP directory does not exist: $(BSP_ROOT_DIR)) +endif + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) + +# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before +# including each makefile fragment so that it knows the path to itself. +BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk +ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) +include $(BSP_INCLUDE_FILE) +# C2H will need this to touch the BSP public.mk and avoid the sopc file +# out-of-date error during a BSP make +ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk + + +ifneq ($(WARNING.SMALL_STACK_SIZE),) +# This WARNING is here to protect you from unknowingly using a very small stack +# If the warning is set, increase your stack size or enable the BSP small stack +# setting to eliminate the warning +$(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) +endif + + +# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF +# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. +ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) +ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) +endif + +# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to +# download_elf target +ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) +GMON_OUT_FILENAME := gmon.out +WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME) +endif + +# Name of ELF application. +APP_NAME := $(basename $(ELF)) + +# Set to defaults if variables not already defined in settings. +ifeq ($(LINKER_SCRIPT),) +LINKER_SCRIPT := $(BSP_LINKER_SCRIPT) +endif +ifeq ($(CRT0),) +CRT0 := $(BSP_CRT0) +endif +ifeq ($(SYS_LIB),) +SYS_LIB := $(BSP_SYS_LIB) +endif + +OBJDUMP_NAME := $(APP_NAME).objdump +OBJDUMP_FLAGS := --disassemble --syms --all-header +ifeq ($(OBJDUMP_INCLUDE_SOURCE),1) +OBJDUMP_FLAGS += --source +endif +ifeq ($(OBJDUMP_FULL_CONTENTS),1) +OBJDUMP_FLAGS += --full-contents +endif + +# Create list of linker dependencies (*.a files). +APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS) + +# Take lists and add required prefixes. +APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +ASM_INC_PREFIX := -Wa,-I +APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS)) +APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS)) + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# +# Avoid Nios II GCC 3.X options. +# + +# Detect if small newlib C library is requested. +# If yes, remove the -msmallc option because it is +# now handled by other means. +ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),) + ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS)) + ALT_C_LIBRARY := smallc +else + ALT_C_LIBRARY := c +endif + +# Put each BSP dependent library in a group to avoid circular dependencies. +APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group) + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# +# Use Nios II GCC 3.X options. +# +APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES)) + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker. +APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \ + $(APP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(APP_CFLAGS_OPTIMIZATION) \ + $(APP_CFLAGS_DEBUG_LEVEL) \ + $(APP_CFLAGS_WARNINGS) \ + $(APP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Arguments only for the C++ compiler. +APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS) + +# Arguments only for the C preprocessor. +# Prefix each include directory with -I. +APP_CPPFLAGS := $(APP_INC_DIRS) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Arguments only for the assembler. +APP_ASFLAGS := $(APP_ASM_INC_DIRS) \ + $(ALT_ASFLAGS) \ + $(APP_ASFLAGS_USER) \ + $(ASFLAGS) + +# Arguments only for the linker. +APP_LDFLAGS := $(APP_LDFLAGS_USER) + +ifneq ($(LINKER_SCRIPT),) +APP_LDFLAGS += -T'$(LINKER_SCRIPT)' +endif + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# Avoid Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += $(CRT0) +endif + +# The equivalent of the -msys-lib option is provided +# by the GROUP() command in the linker script. +# Note this means the SYS_LIB variable is now ignored. + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# Use Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += -msys-crt0='$(CRT0)' +endif +ifneq ($(SYS_LIB),) +APP_LDFLAGS += -msys-lib=$(SYS_LIB) +endif + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +APP_LDFLAGS += \ + $(APP_LIB_DIRS) \ + $(ALT_LDFLAGS) \ + $(LDFLAGS) + +LINKER_MAP_NAME := $(APP_NAME).map +ifeq ($(CREATE_LINKER_MAP), 1) +APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) +endif + +# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the +# mem_init_install target of the mem_init.mk (located in the associated BSP) +# to know how to copy memory initialization files (e.g. .dat, .hex) into +# directories required for Quartus compilation or RTL simulation. + +# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory +# initialization files into your Quartus project directory. This is required +# to provide the initial memory contents of FPGA memories that can be +# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used +# for VHDL simulation of on-chip memories. + +# Defining SOPC_NAME causes the mem_init_install target to copy memory +# initialization files into your RTL simulation directory. This is required +# to provide the initial memory contents of all memories that can be +# initialized by RTL simulation. This variable should be set to the same name +# as your SOPC Builder system name. For example, if you have a system called +# "foo.sopc", this variable should be set to "foo". + +# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. +ifeq ($(SOPC_NAME),) +ifneq ($(QUARTUS_PROJECT_DIR),) +SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) +endif +endif + +# Defining JDI_FILE is required to specify the JTAG Debug Information File +# path. This file is generated by Quartus, and is needed along with the +# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU +# systems. For multi-CPU systems, the processor instance ID is used to select +# from multiple CPU's during ELF download. + +# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during +# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then +# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be +# multiple .sopcinfo files in a Quartus project. +ifeq ($(JDI_FILE),) +ifneq ($(QUARTUS_PROJECT_DIR),) +JDI_FILE := $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi) +endif +endif + +# Path to root runtime directory used for hdl simulation +RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime + + + +#------------------------------------------------------------------------------ +# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ +# mem_init.mk is a generated makefile fragment. This file defines all targets +# used to generate HDL initialization simulation files and pre-initialized +# onchip memory files. +MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk +include $(MEM_INIT_FILE) + +# Create list of object files to be built using the list of source files. +# The source file hierarchy is preserved in the object tree. +# The supported file extensions are: +# +# .c - for C files +# .cxx .cc .cpp - for C++ files +# .S .s - for assembler files +# +# Handle source files specified by --src-dir & --src-rdir differently, to +# save some processing time in calling the adjust-path macro. + +OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS))) +OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS))) +OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS))) +OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS))) +OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS))) +OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS))) + +OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \ + $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS)) + +SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS))) +SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS))) +SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS))) + +SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ + $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \ + $(SDIR_OBJ_LIST_SS)) + +# Relative-pathed objects that being with "../" are handled differently. +# +# Regular objects are created as +# $(CONFIG_OBJ_DIR)//.o +# where the path structure is maintained under the obj directory. This +# applies for both absolute and relative paths; in the absolute path +# case this means the entire source path will be recreated under the obj +# directory. This is done to allow two source files with the same name +# to be included as part of the project. +# +# Note: On Cygwin, the path recreated under the obj directory will be +# the cygpath -u output path. +# +# Relative-path objects that begin with "../" cause problems under this +# scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object +# files anywhere in the system, creating clutter and polluting the source tree. +# As such, their paths are flattened - the object file created will be +# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with +# "../" in the beginning cannot have the same name in the project. VPATH +# will be set for these sources to allow make to relocate the source file +# via %.o rules. +# +# The following lines separate the object list into the flatten and regular +# lists, and then handles them as appropriate. + +FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST)) +FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST))) + +REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST)) +REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST)) + +FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST)) +FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST))) + +REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST)) + +VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST))) + +APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_C) \ + $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s))) + +APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CPP) \ + $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s))) + +APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CXX) \ + $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s))) + +APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CC) \ + $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s))) + +APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_S) \ + $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s))) + +APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_SS) \ + $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s))) + +APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \ + $(APP_OBJS_S) $(APP_OBJS_SS) \ + $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS) + +# Add any extra user-provided object files. +APP_OBJS += $(OBJS) + +# Create list of dependancy files for each object file. +APP_DEPS := $(APP_OBJS:.o=.d) + +# Patch the Elf file with system specific information + +# Patch the Elf with the name of the sopc system +ifneq ($(SOPC_NAME),) +ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME) +endif + +# Patch the Elf with the absolute path to the Quartus Project Directory +ifneq ($(QUARTUS_PROJECT_DIR),) +ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd)) +ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)" +endif + +# Patch the Elf and download args with the JDI_FILE if specified +ifneq ($(wildcard $(JDI_FILE)),) +ELF_PATCH_FLAG += --jdi $(JDI_FILE) +DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE) +endif + +# Patch the Elf with the SOPCINFO_FILE if specified +ifneq ($(wildcard $(SOPCINFO_FILE)),) +ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) +endif + +# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. +# This is not needed if you only have one cable. +ifneq ($(DOWNLOAD_CABLE),) +DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' +endif + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +# +# Set tool default variables if not already defined. +# If these are defined, they would typically be defined in an +# included makefile fragment. +# +ifeq ($(DEFAULT_CROSS_COMPILE),) +DEFAULT_CROSS_COMPILE := nios2-elf- +endif + +ifeq ($(DEFAULT_STACK_REPORT),) +DEFAULT_STACKREPORT := nios2-stackreport +endif + +ifeq ($(DEFAULT_DOWNLOAD),) +DEFAULT_DOWNLOAD := nios2-download +endif + +ifeq ($(DEFAULT_FLASHPROG),) +DEFAULT_FLASHPROG := nios2-flash-programmer +endif + +ifeq ($(DEFAULT_ELFPATCH),) +DEFAULT_ELFPATCH := nios2-elf-insert +endif + +ifeq ($(DEFAULT_RM),) +DEFAULT_RM := rm -f +endif + +ifeq ($(DEFAULT_CP),) +DEFAULT_CP := cp -f +endif + +ifeq ($(DEFAULT_MKDIR),) +DEFAULT_MKDIR := mkdir -p +endif + +# +# Set tool variables to defaults if not already defined. +# If these are defined, they would typically be defined by a +# setting in the generated portion of this makefile. +# +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE) +endif + +ifeq ($(origin CC),default) +CC := $(CROSS_COMPILE)gcc -xc +endif + +ifeq ($(origin CXX),default) +CXX := $(CROSS_COMPILE)gcc -xc++ +endif + +ifeq ($(origin AS),default) +AS := $(CROSS_COMPILE)gcc +endif + +ifeq ($(origin AR),default) +AR := $(CROSS_COMPILE)ar +endif + +ifeq ($(origin LD),default) +LD := $(CROSS_COMPILE)g++ +endif + +ifeq ($(origin NM),default) +NM := $(CROSS_COMPILE)nm +endif + +ifeq ($(origin RM),default) +RM := $(DEFAULT_RM) +endif + +ifeq ($(origin CP),default) +CP := $(DEFAULT_CP) +endif + +ifeq ($(OBJDUMP),) +OBJDUMP := $(CROSS_COMPILE)objdump +endif + +ifeq ($(OBJCOPY),) +OBJCOPY := $(CROSS_COMPILE)objcopy +endif + +ifeq ($(STACKREPORT),) +ifeq ($(CROSS_COMPILE),nios2-elf-) +STACKREPORT := $(DEFAULT_STACKREPORT) +else +DISABLE_STACKREPORT := 1 +endif +endif + +ifeq ($(DOWNLOAD),) +DOWNLOAD := $(DEFAULT_DOWNLOAD) +endif + +ifeq ($(FLASHPROG),) +FLASHPROG := $(DEFAULT_FLASHPROG) +endif + +ifeq ($(ELFPATCH),) +ELFPATCH := $(DEFAULT_ELFPATCH) +endif + +ifeq ($(MKDIR),) +MKDIR := $(DEFAULT_MKDIR) +endif + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ + +define compile.c +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< +$(CC_POST_PROCESS) +endef + +define compile.cpp +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< +$(CXX_POST_PROCESS) +endef + +# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS +ifeq ($(AS),$(patsubst %as,%,$(AS))) +COMMA := , +APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS)))) +endif + +define compile.s +@$(ECHO) Info: Assembling $< to $@ +@$(MKDIR) $(@D) +$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< +$(AS_POST_PROCESS) +endef + +ifeq ($(MAKE_VERSION),3.81) +.SECONDEXPANSION: + +$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) + $(compile.c) + +$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp) + $(compile.cpp) + +$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc) + $(compile.cpp) + +$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx) + $(compile.cpp) + +$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S) + $(compile.s) + +$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s) + $(compile.s) + +endif # MAKE_VERSION != 3.81 + +$(CONFIG_OBJ_DIR)/%.o: %.c + $(compile.c) + +$(CONFIG_OBJ_DIR)/%.o: %.cpp + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cc + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cxx + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.S + $(compile.s) + +$(CONFIG_OBJ_DIR)/%.o: %.s + $(compile.s) + + +#------------------------------------------------------------------------------ +# PATTERN RULES TO INTERMEDIATE FILES +#------------------------------------------------------------------------------ + +$(CONFIG_OBJ_DIR)/%.s: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + + +#------------------------------------------------------------------------------ +# TARGET RULES +#------------------------------------------------------------------------------ + +.PHONY : help +help : + @$(ECHO) "Summary of Makefile targets" + @$(ECHO) " Build targets:" + @$(ECHO) " all (default) - Application and all libraries (including BSP)" + @$(ECHO) " bsp - Just the BSP" + @$(ECHO) " libs - All libraries (including BSP)" + @$(ECHO) " flash - All flash files" + @$(ECHO) " mem_init_generate - All memory initialization files" +ifeq ($(QSYS),1) + @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" + @$(ECHO) " --> Use the mem_init_generate target and then" + @$(ECHO) " add the generated meminit.qip file to your" + @$(ECHO) " Quartus II Project." +else # if QSYS != 1 + @$(ECHO) " mem_init_install - Copy memory initialization files to Quartus II project" +endif # QSYS == 1 + @$(ECHO) + @$(ECHO) " Clean targets:" + @$(ECHO) " clean_all - Application and all libraries (including BSP)" + @$(ECHO) " clean - Just the application" + @$(ECHO) " clean_bsp - Just the BSP" + @$(ECHO) " clean_libs - All libraries (including BSP)" + @$(ECHO) + @$(ECHO) " Run targets:" + @$(ECHO) " download-elf - Download and run your elf executable" + @$(ECHO) " program-flash - Program flash contents to the board" + +# Handy rule to skip making libraries and just make application. +.PHONY : app +app : $(ELF) + +ifeq ($(CREATE_OBJDUMP), 1) +app : $(OBJDUMP_NAME) +endif + +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +app : elf_derived_files +endif + +.PHONY: elf_derived_files +elf_derived_files: default_mem_init + +# Handy rule for making just the BSP. +.PHONY : bsp +bsp : + @$(ECHO) Info: Building $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) + + +# Make sure all makeable libraries (including the BSP) are up-to-date. +LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : libs +libs : $(LIB_TARGETS) + +ifneq ($(strip $(LIB_TARGETS)),) +$(LIB_TARGETS): %-recurs-make-lib: + @$(ECHO) Info: Building $* + $(MAKE) --no-print-directory -C $* +endif + +ifneq ($(strip $(APP_LDDEPS)),) +$(APP_LDDEPS): libs + @true +endif + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS))) + +$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS))) + + +# Clean just the application. +.PHONY : clean +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +clean : clean_elf_derived_files +endif + +clean : + @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) + @$(ECHO) [$(APP_NAME) clean complete] + +# Clean just the BSP. +.PHONY : clean_bsp +clean_bsp : + @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean + +# Clean all makeable libraries including the BSP. +LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : clean_libs +clean_libs : $(LIB_CLEAN_TARGETS) + +ifneq ($(strip $(LIB_CLEAN_TARGETS)),) +$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib: + @$(ECHO) Info: Cleaning $* + $(MAKE) --no-print-directory -C $* clean +endif + +.PHONY: clean_elf_derived_files +clean_elf_derived_files: mem_init_clean + +# Clean application and all makeable libraries including the BSP. +.PHONY : clean_all +clean_all : clean mem_init_clean clean_libs + +# Include the dependency files unless the make goal is performing a clean +# of the application. +ifneq ($(firstword $(MAKECMDGOALS)),clean) +ifneq ($(firstword $(MAKECMDGOALS)),clean_all) +-include $(APP_DEPS) +endif +endif + +.PHONY : download-elf +download-elf : $(ELF) + @if [ "$(DOWNLOAD)" = "none" ]; \ + then \ + $(ECHO) Downloading $(ELF) not supported; \ + else \ + $(ECHO) Info: Downloading $(ELF); \ + $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ + fi + +# Delete the target of a rule if it has changed and its commands exit +# with a nonzero exit status. +.DELETE_ON_ERROR: + +# Rules for flash programming commands +PROGRAM_FLASH_SUFFIX := -program +PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES)) + +.PHONY : program-flash +program-flash : $(PROGRAM_FLASH_TARGET) + +.PHONY : $(PROGRAM_FLASH_TARGET) +$(PROGRAM_FLASH_TARGET) : flash + @if [ "$(FLASHPROG)" = "none" ]; \ + then \ + $(ECHO) Programming flash not supported; \ + else \ + $(ECHO) Info: Programming $(basename $@).flash; \ + if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \ + then \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + else \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + fi \ + fi + + +# Rules for simulating with an HDL Simulator [QSYS only] +ifeq ($(QSYS),1) +IP_MAKE_SIMSCRIPT := ip-make-simscript + +ifeq ($(VSIM),) +VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim" +ifeq ($(ENABLE_VSIM_GUI),1) +VSIM := $(VSIM_EXE) -gui +else +VSIM := $(VSIM_EXE) -c +endif # ENABLE_VSIM_GUI == 1 +endif # VSIM not set + +ifeq ($(SPD),) +ifneq ($(ABS_QUARTUS_PROJECT_DIR),) +ifneq ($(SOPC_NAME),) +SPD := $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd +endif # SOPC_NAME set +endif # ABS_QUARTUS_PROJECT_DIR set +endif # SPD == empty string + +ifeq ($(MSIM_SCRIPT),) +SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim +MSIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/msim_setup.tcl +endif # MSIM_SCRIPT == empty string + +ifeq ($(MAKE_VERSION),3.81) +ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE)) +else +ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE) +endif + +$(MSIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE) +ifeq ($(SPD),) + $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set) +endif + @$(MKDIR) $(SIM_SCRIPT_DIR) + $(IP_MAKE_SIMSCRIPT) --spd=$(SPD) --spd=$(MEM_INIT_DESCRIPTOR_FILE) --output-directory=$(SIM_SCRIPT_DIR) + +VSIM_COMMAND = \ + cd $(dir $(MSIM_SCRIPT)) && \ + $(VSIM) -do "do $(notdir $(MSIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)" + +.PHONY: sim +sim: $(MSIM_SCRIPT) mem_init_generate +ifeq ($(MSIM_SCRIPT),) + $(error MSIM_SCRIPT not set) +endif + $(VSIM_COMMAND) + +endif # QSYS == 1 + + +#------------------------------------------------------------------------------ +# ELF TARGET RULE +#------------------------------------------------------------------------------ +# Rule for constructing the executable elf file. +$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS) + @$(ECHO) Info: Linking $@ + $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS) +ifneq ($(DISABLE_ELFPATCH),1) + $(ELFPATCH) $@ $(ELF_PATCH_FLAG) +endif +ifneq ($(DISABLE_STACKREPORT),1) + @bash -c "$(STACKREPORT) $@" +endif + +$(OBJDUMP_NAME) : $(ELF) + @$(ECHO) Info: Creating $@ + $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@ + +# Rule for printing the name of the elf file +.PHONY: print-elf-name +print-elf-name: + @$(ECHO) $(ELF) + + diff --git a/software/qsys_tutorial_lcd4/create-this-app b/software/qsys_tutorial_lcd4/create-this-app index dcd4608..a71c979 100644 --- a/software/qsys_tutorial_lcd4/create-this-app +++ b/software/qsys_tutorial_lcd4/create-this-app @@ -1,114 +1,114 @@ -#!/bin/bash -# -# This script creates the hello_world application in this directory. - - -BSP_DIR=../qsys_tutorial_lcd4_bsp -QUARTUS_PROJECT_DIR=../../ -NIOS2_APP_GEN_ARGS="--elf-name qsys_tutorial_lcd4.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_world.c" - - -# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set. -# This variable is required for the command line tools to execute correctly. -if [ -z "${SOPC_KIT_NIOS2}" ] -then - echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set! - exit 1 -fi - - -# Also make sure that the APP has not been created already. Check for -# existence of Makefile in the app directory -if [ -f ./Makefile ] -then - echo Application has already been created! Delete Makefile if you want to create a new application makefile - exit 1 -fi - - -# We are selecting hal_default bsp because it supports this application. -# Check to see if the hal_default has already been generated by checking for -# existence of the public.mk file. If not, we need to run -# create-this-bsp file to generate the bsp. -if [ ! -f ${BSP_DIR}/public.mk ]; then - # Since BSP doesn't exist, create the BSP - # Pass any command line arguments passed to this script to the BSP. - pushd ${BSP_DIR} >> /dev/null - ./create-this-bsp "$@" || { - echo "create-this-bsp failed" - exit 1 - } - popd >> /dev/null -fi - - -# Don't run make if create-this-app script is called with --no-make arg -SKIP_MAKE= -while [ $# -gt 0 ] -do - case "$1" in - --no-make) - SKIP_MAKE=1 - ;; - esac - shift -done - - -# Now we also need to go copy the sources for this application to the -# local directory. -find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || { - echo "failed during copying example source files" - exit 1 -} - -find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || { - echo "failed copying readme file" -} - -if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" ] -then - cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" . || { - echo "failed during copying project support files" - exit 1 - } -fi - -chmod -R +w . || { - echo "failed during changing file permissions" - exit 1 -} - -cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}" - -echo "create-this-app: Running \"${cmd}\"" -$cmd || { - echo "nios2-app-generate-makefile failed" - exit 1 -} - -if [ -z "$SKIP_MAKE" ]; then - cmd="make" - - echo "create-this-app: Running \"$cmd\"" - $cmd || { - echo "make failed" - exit 1 - } - - echo - echo "To download and run the application:" - echo " 1. Make sure the board is connected to the system." - echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design." - echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell." - echo " 4. Run 'make download-elf' from the application directory." - echo - echo "To debug the application:" - echo " Import the project into Nios II Software Build Tools for Eclipse." - echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information." - echo - echo -e "" -fi - - -exit 0 +#!/bin/bash +# +# This script creates the hello_world application in this directory. + + +BSP_DIR=../qsys_tutorial_lcd4_bsp +QUARTUS_PROJECT_DIR=../../ +NIOS2_APP_GEN_ARGS="--elf-name qsys_tutorial_lcd4.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_world.c" + + +# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set. +# This variable is required for the command line tools to execute correctly. +if [ -z "${SOPC_KIT_NIOS2}" ] +then + echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set! + exit 1 +fi + + +# Also make sure that the APP has not been created already. Check for +# existence of Makefile in the app directory +if [ -f ./Makefile ] +then + echo Application has already been created! Delete Makefile if you want to create a new application makefile + exit 1 +fi + + +# We are selecting hal_default bsp because it supports this application. +# Check to see if the hal_default has already been generated by checking for +# existence of the public.mk file. If not, we need to run +# create-this-bsp file to generate the bsp. +if [ ! -f ${BSP_DIR}/public.mk ]; then + # Since BSP doesn't exist, create the BSP + # Pass any command line arguments passed to this script to the BSP. + pushd ${BSP_DIR} >> /dev/null + ./create-this-bsp "$@" || { + echo "create-this-bsp failed" + exit 1 + } + popd >> /dev/null +fi + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + esac + shift +done + + +# Now we also need to go copy the sources for this application to the +# local directory. +find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || { + echo "failed during copying example source files" + exit 1 +} + +find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || { + echo "failed copying readme file" +} + +if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" ] +then + cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" . || { + echo "failed during copying project support files" + exit 1 + } +fi + +chmod -R +w . || { + echo "failed during changing file permissions" + exit 1 +} + +cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}" + +echo "create-this-app: Running \"${cmd}\"" +$cmd || { + echo "nios2-app-generate-makefile failed" + exit 1 +} + +if [ -z "$SKIP_MAKE" ]; then + cmd="make" + + echo "create-this-app: Running \"$cmd\"" + $cmd || { + echo "make failed" + exit 1 + } + + echo + echo "To download and run the application:" + echo " 1. Make sure the board is connected to the system." + echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design." + echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell." + echo " 4. Run 'make download-elf' from the application directory." + echo + echo "To debug the application:" + echo " Import the project into Nios II Software Build Tools for Eclipse." + echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information." + echo + echo -e "" +fi + + +exit 0 diff --git a/software/qsys_tutorial_lcd4/hex_encoder.c b/software/qsys_tutorial_lcd4/hex_encoder.c index ab4eca0..9639775 100644 --- a/software/qsys_tutorial_lcd4/hex_encoder.c +++ b/software/qsys_tutorial_lcd4/hex_encoder.c @@ -1,205 +1,205 @@ -/* - * hex_encoder.c - * - * Created on: 2016/11/17 - * Author: takayun - */ - -#include "hex_encoder.h" -#include - -void encodeNumHex(int hex_i, int num) { - char encoded = 0; - switch (num) { - case 0: - encoded = (char)0x40; // 100 0000 - break; - case 1: - encoded = (char)0xF9; // 111 1001 - break; - case 2: - encoded = (char)0x24; // 010 0100 - break; - case 3: - encoded = (char)0x30; // 011 0000 - break; - case 4: - encoded = (char)0x19; // 001 1001 - break; - case 5: - encoded = (char)0x12; // 001 0010 - break; - case 6: - encoded = (char)0x02; // 000 0010 - break; - case 7: - encoded = (char)0x58; // 101 1000 - break; - case 8: - encoded = (char)0x00; // 000 0000 - break; - case 9: - encoded = (char)0x10; // 001 0000 - break; - default: - encoded = 0; - break; - } - - switch (hex_i) { - case 0: - *hex0 = encoded; - break; - case 1: - *hex1 = encoded; - break; - case 2: - *hex2 = encoded; - break; - case 3: - *hex3 = encoded; - break; - case 4: - *hex4 = encoded; - break; - case 5: - *hex5 = encoded; - break; - case 6: - *hex6 = encoded; - break; - case 7: - *hex7 = encoded; - break; - default: - break; - } -} - -void encodeLatHex(int hex_i, char c) { - char encoded = 0; - - if (isdigit(c)) { - encodeNumHex(hex_i, c-'0'); - return; - } - - switch (c) { - case ' ': - encoded = (char)0xFF; // 111 1111 - break; - case '-': - encoded = (char)0x3F; // 011 1111 - break; - case 'a': - encoded = (char)0x08; // 000 1000 - break; - case 'b': - encoded = (char)0x03; // 000 0011 - break; - case 'c': - encoded = (char)0x27; // 010 0111 - break; - case 'd': - encoded = (char)0x21; // 010 0001 - break; - case 'e': - encoded = (char)0x06; // 000 0110 - break; - case 'f': - encoded = (char)0x0E; // 000 1110 - break; - case 'g': - encoded = (char)0x42; // 100 0010 - break; - case 'h': - encoded = (char)0x0B; // 000 1011 - break; - case 'i': - encoded = (char)0xFB; // 111 1011 - break; - case 'j': - encoded = (char)0x61; // 110 0001 - break; - case 'k': - encoded = (char)0x0A; // 000 1010 - break; - case 'l': - encoded = (char)0x47; // 100 0111 - break; - case 'm': - encoded = (char)0x48; // 100 1000 - break; - case 'n': - encoded = (char)0x2B; // 010 1011 - break; - case 'o': - encoded = (char)0x23; // 010 0011 - break; - case 'p': - encoded = (char)0x0C; // 000 1100 - break; - case 'q': - encoded = (char)0x04; // 000 0100 - break; - case 'r': - encoded = (char)0x2F; // 010 1111 - break; - case 's': - encoded = (char)0x13; // 001 0011 - break; - case 't': - encoded = (char)0x07; // 000 0111 - break; - case 'u': - encoded = (char)0x63; // 110 0011 - break; - case 'v': - encoded = (char)0x41; // 100 0001 - break; - case 'w': - encoded = (char)0x01; // 000 0001 - break; - case 'x': - encoded = (char)0x09; // 000 1001 - break; - case 'y': - encoded = (char)0x11; // 001 0001 - break; - case 'z': - encoded = (char)0x64; // 110 0100 - break; - default: - encoded = 0; - break; - } - - switch (hex_i) { - case 0: - *hex0 = encoded; - break; - case 1: - *hex1 = encoded; - break; - case 2: - *hex2 = encoded; - break; - case 3: - *hex3 = encoded; - break; - case 4: - *hex4 = encoded; - break; - case 5: - *hex5 = encoded; - break; - case 6: - *hex6 = encoded; - break; - case 7: - *hex7 = encoded; - break; - default: - break; - } -} +/* + * hex_encoder.c + * + * Created on: 2016/11/17 + * Author: takayun + */ + +#include "hex_encoder.h" +#include + +void encodeNumHex(int hex_i, int num) { + char encoded = 0; + switch (num) { + case 0: + encoded = (char)0x40; // 100 0000 + break; + case 1: + encoded = (char)0xF9; // 111 1001 + break; + case 2: + encoded = (char)0x24; // 010 0100 + break; + case 3: + encoded = (char)0x30; // 011 0000 + break; + case 4: + encoded = (char)0x19; // 001 1001 + break; + case 5: + encoded = (char)0x12; // 001 0010 + break; + case 6: + encoded = (char)0x02; // 000 0010 + break; + case 7: + encoded = (char)0x58; // 101 1000 + break; + case 8: + encoded = (char)0x00; // 000 0000 + break; + case 9: + encoded = (char)0x10; // 001 0000 + break; + default: + encoded = 0; + break; + } + + switch (hex_i) { + case 0: + *hex0 = encoded; + break; + case 1: + *hex1 = encoded; + break; + case 2: + *hex2 = encoded; + break; + case 3: + *hex3 = encoded; + break; + case 4: + *hex4 = encoded; + break; + case 5: + *hex5 = encoded; + break; + case 6: + *hex6 = encoded; + break; + case 7: + *hex7 = encoded; + break; + default: + break; + } +} + +void encodeLatHex(int hex_i, char c) { + char encoded = 0; + + if (isdigit(c)) { + encodeNumHex(hex_i, c-'0'); + return; + } + + switch (c) { + case ' ': + encoded = (char)0xFF; // 111 1111 + break; + case '-': + encoded = (char)0x3F; // 011 1111 + break; + case 'a': + encoded = (char)0x08; // 000 1000 + break; + case 'b': + encoded = (char)0x03; // 000 0011 + break; + case 'c': + encoded = (char)0x27; // 010 0111 + break; + case 'd': + encoded = (char)0x21; // 010 0001 + break; + case 'e': + encoded = (char)0x06; // 000 0110 + break; + case 'f': + encoded = (char)0x0E; // 000 1110 + break; + case 'g': + encoded = (char)0x42; // 100 0010 + break; + case 'h': + encoded = (char)0x0B; // 000 1011 + break; + case 'i': + encoded = (char)0xFB; // 111 1011 + break; + case 'j': + encoded = (char)0x61; // 110 0001 + break; + case 'k': + encoded = (char)0x0A; // 000 1010 + break; + case 'l': + encoded = (char)0x47; // 100 0111 + break; + case 'm': + encoded = (char)0x48; // 100 1000 + break; + case 'n': + encoded = (char)0x2B; // 010 1011 + break; + case 'o': + encoded = (char)0x23; // 010 0011 + break; + case 'p': + encoded = (char)0x0C; // 000 1100 + break; + case 'q': + encoded = (char)0x04; // 000 0100 + break; + case 'r': + encoded = (char)0x2F; // 010 1111 + break; + case 's': + encoded = (char)0x13; // 001 0011 + break; + case 't': + encoded = (char)0x07; // 000 0111 + break; + case 'u': + encoded = (char)0x63; // 110 0011 + break; + case 'v': + encoded = (char)0x41; // 100 0001 + break; + case 'w': + encoded = (char)0x01; // 000 0001 + break; + case 'x': + encoded = (char)0x09; // 000 1001 + break; + case 'y': + encoded = (char)0x11; // 001 0001 + break; + case 'z': + encoded = (char)0x64; // 110 0100 + break; + default: + encoded = 0; + break; + } + + switch (hex_i) { + case 0: + *hex0 = encoded; + break; + case 1: + *hex1 = encoded; + break; + case 2: + *hex2 = encoded; + break; + case 3: + *hex3 = encoded; + break; + case 4: + *hex4 = encoded; + break; + case 5: + *hex5 = encoded; + break; + case 6: + *hex6 = encoded; + break; + case 7: + *hex7 = encoded; + break; + default: + break; + } +} diff --git a/software/qsys_tutorial_lcd4/hex_encoder.h b/software/qsys_tutorial_lcd4/hex_encoder.h index 3aa8e67..7909cf8 100644 --- a/software/qsys_tutorial_lcd4/hex_encoder.h +++ b/software/qsys_tutorial_lcd4/hex_encoder.h @@ -1,38 +1,38 @@ -/* - * hex_encoder.h - * - * Created on: 2016/11/17 - * Author: takayun - */ - -#ifndef HEX_ENCODER_H_ -#define HEX_ENCODER_H_ - -#include "system.h" - -/************************************************** - * Defines - **************************************************/ - -#define hex0 (volatile char *) HEX0_BASE -#define hex1 (volatile char *) HEX1_BASE -#define hex2 (volatile char *) HEX2_BASE -#define hex3 (volatile char *) HEX3_BASE -#define hex4 (volatile char *) HEX4_BASE -#define hex5 (volatile char *) HEX5_BASE -#define hex6 (volatile char *) HEX6_BASE -#define hex7 (volatile char *) HEX7_BASE - -/************************************************** - * Variables - **************************************************/ - - -/************************************************** - * Functions - **************************************************/ - -void encodeNumHex(int hex_i, int num); -void encodeLatHex(int hex_i, char c); - -#endif /* HEX_ENCODER_H_ */ +/* + * hex_encoder.h + * + * Created on: 2016/11/17 + * Author: takayun + */ + +#ifndef HEX_ENCODER_H_ +#define HEX_ENCODER_H_ + +#include "system.h" + +/************************************************** + * Defines + **************************************************/ + +#define hex0 (volatile char *) HEX0_BASE +#define hex1 (volatile char *) HEX1_BASE +#define hex2 (volatile char *) HEX2_BASE +#define hex3 (volatile char *) HEX3_BASE +#define hex4 (volatile char *) HEX4_BASE +#define hex5 (volatile char *) HEX5_BASE +#define hex6 (volatile char *) HEX6_BASE +#define hex7 (volatile char *) HEX7_BASE + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void encodeNumHex(int hex_i, int num); +void encodeLatHex(int hex_i, char c); + +#endif /* HEX_ENCODER_H_ */ diff --git a/software/qsys_tutorial_lcd4/hex_out.c b/software/qsys_tutorial_lcd4/hex_out.c index 2995aac..874dbac 100644 --- a/software/qsys_tutorial_lcd4/hex_out.c +++ b/software/qsys_tutorial_lcd4/hex_out.c @@ -1,67 +1,67 @@ -/* - * hex_out.c - * - * Created on: 2016/11/24 - * Author: takayun - */ -#include "hex_out.h" -#include "hex_encoder.h" -#include "sys_except.h" - -void print_block(char * str, unsigned int size, enum BLOCK_N block_i) { - int i; - if (block_i == HEX0_3) { - if (size > 4) panic(); - for (i = 0; i < size; i++) { - encodeLatHex(i,str[size-1-i]); - } - } - else if (block_i == HEX4_5) { - if (size > 2) panic(); - for (i = 0; i < size; i++) { - encodeLatHex(i+4,str[size-1-i]); - } - } - else if (block_i == HEX6_7) { - if (size > 2) panic(); - for (i = 0; i < size; i++) { - encodeLatHex(i+6,str[size-1-i]); - } - } -} - -void clear_block(enum BLOCK_N block_i) { - if (block_i == HEX0_3) { - print_block(" ", 4, HEX0_3); - } - else if (block_i == HEX4_5) { - print_block(" ", 2, HEX4_5); - } - else if (block_i == HEX6_7) { - print_block(" ", 2, HEX6_7); - } -} - -void print_number(char num) { - int i; - char buf[5]; - char val; - for (i = 0; i < 4; i++) { - if (num < 0) { - buf[0] = '-'; - val = -num; - } else { - buf[0] = ' '; - val = num; - } - buf[1] = val/100%10 + '0'; - buf[2] = val/10%10 + '0'; - buf[3] = val%10 + '0'; - } - clear_block(HEX0_3); - print_block(buf, 4, HEX0_3); -} - - - - +/* + * hex_out.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "hex_out.h" +#include "hex_encoder.h" +#include "sys_except.h" + +void print_block(char * str, unsigned int size, enum BLOCK_N block_i) { + int i; + if (block_i == HEX0_3) { + if (size > 4) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i,str[size-1-i]); + } + } + else if (block_i == HEX4_5) { + if (size > 2) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i+4,str[size-1-i]); + } + } + else if (block_i == HEX6_7) { + if (size > 2) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i+6,str[size-1-i]); + } + } +} + +void clear_block(enum BLOCK_N block_i) { + if (block_i == HEX0_3) { + print_block(" ", 4, HEX0_3); + } + else if (block_i == HEX4_5) { + print_block(" ", 2, HEX4_5); + } + else if (block_i == HEX6_7) { + print_block(" ", 2, HEX6_7); + } +} + +void print_number(char num) { + int i; + char buf[5]; + char val; + for (i = 0; i < 4; i++) { + if (num < 0) { + buf[0] = '-'; + val = -num; + } else { + buf[0] = ' '; + val = num; + } + buf[1] = val/100%10 + '0'; + buf[2] = val/10%10 + '0'; + buf[3] = val%10 + '0'; + } + clear_block(HEX0_3); + print_block(buf, 4, HEX0_3); +} + + + + diff --git a/software/qsys_tutorial_lcd4/hex_out.h b/software/qsys_tutorial_lcd4/hex_out.h index 50d6868..99219b5 100644 --- a/software/qsys_tutorial_lcd4/hex_out.h +++ b/software/qsys_tutorial_lcd4/hex_out.h @@ -1,33 +1,33 @@ -/* - * hex_out.h - * - * Created on: 2016/11/24 - * Author: takayun - */ - -#ifndef HEX_IO_H_ -#define HEX_IO_H_ - -/************************************************** - * Defines - **************************************************/ - -enum BLOCK_N { - HEX0_3, HEX4_5, HEX6_7 -}; - -/************************************************** - * Variables - **************************************************/ - - -/************************************************** - * Functions - **************************************************/ - -void print_block(char * str, unsigned int size, enum BLOCK_N block_i); -void clear_block(enum BLOCK_N block_i); -void print_number(char num); - - -#endif /* HEX_IO_H_ */ +/* + * hex_out.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef HEX_IO_H_ +#define HEX_IO_H_ + +/************************************************** + * Defines + **************************************************/ + +enum BLOCK_N { + HEX0_3, HEX4_5, HEX6_7 +}; + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void print_block(char * str, unsigned int size, enum BLOCK_N block_i); +void clear_block(enum BLOCK_N block_i); +void print_number(char num); + + +#endif /* HEX_IO_H_ */ diff --git a/software/qsys_tutorial_lcd4/input_int.c b/software/qsys_tutorial_lcd4/input_int.c index 6897db4..0145286 100644 --- a/software/qsys_tutorial_lcd4/input_int.c +++ b/software/qsys_tutorial_lcd4/input_int.c @@ -1,71 +1,71 @@ -/* - * input_int.c - * - * Created on: 2016/11/24 - * Author: takayun - */ -#include "input_int.h" -#include "sys_register.h" - -unsigned char PUSH_EVENT = PUSH_NONE; - -void in_int() { - push_int(); -} - -static void update_sw_reg(sw_t s) { - global_registers[Ssw_data] = (char)s.data.value; - global_registers[Ssw_inst] = (char)s.splited.instruction_code; - global_registers[Ssw_memi] = (char)s.splited.memory_index; - global_registers[Ssw_regi] = (char)s.splited.register_index; - global_registers[Ssw_psel] = (char)s.splited.program_selecter; - global_registers[Ssw_rw] = (char)s.splited.rw_mode; - global_registers[Ssw_run] = (char)s.splited.run_mode; -} - -enum PushEvent push_decode(char psw) { - int result = PUSH_NONE; - switch(psw) { - case 0x3: - result += PUSH_ANY; - result += PUSH_VALSTR; - break; - case 0x5: - result += PUSH_ANY; - result += PUSH_INSSTR; - break; - case 0x6: - result += PUSH_ANY; - result += PUSH_RUN; - break; - } - return result; -} - -void push_int() { - static unsigned char status = 0; - static enum PushEvent event_code; - volatile sw_t s; - s.sw = *switches; - - switch (status) { - case 0: - PUSH_EVENT = PUSH_NONE; - if (*push_switches != 7) { - event_code = push_decode(*push_switches); - status = 1; - } - update_sw_reg(s); // �X�C�b�`��W�X�^�X�V - break; - case 1: - if (*push_switches == 7) status = 2; - break; - case 2: - PUSH_EVENT = event_code; - status = 0; - break; - default: - status = 0; - break; - } -} +/* + * input_int.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "input_int.h" +#include "sys_register.h" + +unsigned char PUSH_EVENT = PUSH_NONE; + +void in_int() { + push_int(); +} + +static void update_sw_reg(sw_t s) { + global_registers[Ssw_data] = (char)s.data.value; + global_registers[Ssw_inst] = (char)s.splited.instruction_code; + global_registers[Ssw_memi] = (char)s.splited.memory_index; + global_registers[Ssw_regi] = (char)s.splited.register_index; + global_registers[Ssw_psel] = (char)s.splited.program_selecter; + global_registers[Ssw_rw] = (char)s.splited.rw_mode; + global_registers[Ssw_run] = (char)s.splited.run_mode; +} + +enum PushEvent push_decode(char psw) { + int result = PUSH_NONE; + switch(psw) { + case 0x3: + result += PUSH_ANY; + result += PUSH_VALSTR; + break; + case 0x5: + result += PUSH_ANY; + result += PUSH_INSSTR; + break; + case 0x6: + result += PUSH_ANY; + result += PUSH_RUN; + break; + } + return result; +} + +void push_int() { + static unsigned char status = 0; + static enum PushEvent event_code; + volatile sw_t s; + s.sw = *switches; + + switch (status) { + case 0: + PUSH_EVENT = PUSH_NONE; + if (*push_switches != 7) { + event_code = push_decode(*push_switches); + status = 1; + } + update_sw_reg(s); // �X�C�b�`��W�X�^�X�V + break; + case 1: + if (*push_switches == 7) status = 2; + break; + case 2: + PUSH_EVENT = event_code; + status = 0; + break; + default: + status = 0; + break; + } +} diff --git a/software/qsys_tutorial_lcd4/input_int.h b/software/qsys_tutorial_lcd4/input_int.h index 288fc14..e1d0612 100644 --- a/software/qsys_tutorial_lcd4/input_int.h +++ b/software/qsys_tutorial_lcd4/input_int.h @@ -1,62 +1,62 @@ -/* - * input_int.h - * - * Created on: 2016/11/24 - * Author: takayun - */ - -#ifndef SWITCHES_INT_H_ -#define SWITCHES_INT_H_ - -#include "system.h" - -/************************************************** - * Defines - **************************************************/ - -#define switches (volatile int *) SWITCHES_BASE -#define push_switches (volatile char *) PUSH_SWITCHES_BASE - -typedef union { - int sw; - struct { - unsigned int run_mode : 1; - unsigned int rw_mode : 1; - unsigned int program_selecter : 4; - unsigned int memory_index : 4; - unsigned int register_index : 4; - unsigned int instruction_code : 4; - } splited; - struct { - unsigned int : 10; - unsigned int value : 8; - } data; -} sw_t; - -enum PushEvent{ - PUSH_NONE = 1<<0, - PUSH_ANY = 1<<1, - PUSH_VALSTR = 1<<2, - PUSH_INSSTR = 1<<3, - PUSH_RUN = 1<<4 -}; - -/************************************************** - * Variables - **************************************************/ - -extern unsigned char PUSH_EVENT; - -/************************************************** - * Functions - **************************************************/ - -/* Function: in_int - * Sammary: - * �S�Ă̓��͊��荞�݂��s�� - * */ -void in_int(); - -void push_int(); - -#endif /* SWITCHES_INT_H_ */ +/* + * input_int.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SWITCHES_INT_H_ +#define SWITCHES_INT_H_ + +#include "system.h" + +/************************************************** + * Defines + **************************************************/ + +#define switches (volatile int *) SWITCHES_BASE +#define push_switches (volatile char *) PUSH_SWITCHES_BASE + +typedef union { + int sw; + struct { + unsigned int run_mode : 1; + unsigned int rw_mode : 1; + unsigned int program_selecter : 4; + unsigned int memory_index : 4; + unsigned int register_index : 4; + unsigned int instruction_code : 4; + } splited; + struct { + unsigned int : 10; + unsigned int value : 8; + } data; +} sw_t; + +enum PushEvent{ + PUSH_NONE = 1<<0, + PUSH_ANY = 1<<1, + PUSH_VALSTR = 1<<2, + PUSH_INSSTR = 1<<3, + PUSH_RUN = 1<<4 +}; + +/************************************************** + * Variables + **************************************************/ + +extern unsigned char PUSH_EVENT; + +/************************************************** + * Functions + **************************************************/ + +/* Function: in_int + * Sammary: + * �S�Ă̓��͊��荞�݂��s�� + * */ +void in_int(); + +void push_int(); + +#endif /* SWITCHES_INT_H_ */ diff --git a/software/qsys_tutorial_lcd4/lcd_out.c b/software/qsys_tutorial_lcd4/lcd_out.c index a97d5a6..b09a0bb 100644 --- a/software/qsys_tutorial_lcd4/lcd_out.c +++ b/software/qsys_tutorial_lcd4/lcd_out.c @@ -1,29 +1,29 @@ -#include "lcd_out.h" -#include -#include -#include -#include -#include "system.h" -#include "LCD.h" - -// LCD�̏�� -void lcd_init() { - *lcd_on = 1; - *lcd_blon = 1; - LCD_Init(); -} - -// LCD�̃L��b�g��P�s�ڂ̂͂��߂Ɉړ�� -void lcd_caret_reset() { - LCD_Init(); -} - -// LCD�̃L��b�g��Q�s�ڂ̂͂��߂Ɉړ�� -void lcd_caret_reset2() { - LCD_Line2(); -} - -// LCD�ɕ��\�� -void lcd_print(const char *str) { - LCD_Show_Text(str); -} +#include "lcd_out.h" +#include +#include +#include +#include +#include "system.h" +#include "LCD.h" + +// LCD�̏�� +void lcd_init() { + *lcd_on = 1; + *lcd_blon = 1; + LCD_Init(); +} + +// LCD�̃L��b�g��P�s�ڂ̂͂��߂Ɉړ�� +void lcd_caret_reset() { + LCD_Init(); +} + +// LCD�̃L��b�g��Q�s�ڂ̂͂��߂Ɉړ�� +void lcd_caret_reset2() { + LCD_Line2(); +} + +// LCD�ɕ��\�� +void lcd_print(const char *str) { + LCD_Show_Text(str); +} diff --git a/software/qsys_tutorial_lcd4/lcd_out.h b/software/qsys_tutorial_lcd4/lcd_out.h index a1c2cfe..7c51dd4 100644 --- a/software/qsys_tutorial_lcd4/lcd_out.h +++ b/software/qsys_tutorial_lcd4/lcd_out.h @@ -1,28 +1,28 @@ -/* - * lcd_out.h - * - * Created on: 2016/12/02 - * Author: takayun - */ - -#ifndef LCD_OUT_H_ -#define LCD_OUT_H_ - -#include "system.h" - -#define lcd_on (volatile char *) LCD_ON_BASE -#define lcd_blon (volatile char *) LCD_BLON_BASE - -// LCD�̏�� -void lcd_init(); - -// LCD�̃L��b�g��P�s�ڂ̂͂��߂Ɉړ�� -void lcd_caret_reset(); - -// LCD�̃L��b�g��Q�s�ڂ̂͂��߂Ɉړ�� -void lcd_caret_reset2(); - -// LCD�ɕ��\�� -void lcd_print(const char *str); - -#endif /* LCD_OUT_H_ */ +/* + * lcd_out.h + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#ifndef LCD_OUT_H_ +#define LCD_OUT_H_ + +#include "system.h" + +#define lcd_on (volatile char *) LCD_ON_BASE +#define lcd_blon (volatile char *) LCD_BLON_BASE + +// LCD�̏�� +void lcd_init(); + +// LCD�̃L��b�g��P�s�ڂ̂͂��߂Ɉړ�� +void lcd_caret_reset(); + +// LCD�̃L��b�g��Q�s�ڂ̂͂��߂Ɉړ�� +void lcd_caret_reset2(); + +// LCD�ɕ��\�� +void lcd_print(const char *str); + +#endif /* LCD_OUT_H_ */ diff --git a/software/qsys_tutorial_lcd4/readme.txt b/software/qsys_tutorial_lcd4/readme.txt index 7d0742f..a949aa6 100644 --- a/software/qsys_tutorial_lcd4/readme.txt +++ b/software/qsys_tutorial_lcd4/readme.txt @@ -1,26 +1,26 @@ -Readme - Hello World Software Example - -DESCRIPTION: -Simple program that prints "Hello from Nios II" - -The memory footprint of this hosted application is intended to be small (under 100 kbytes) by default -using a standard reference deisgn. - -For an even smaller, reduced footprint version of this template, and an explanation of how -to reduce the memory footprint for a given application, see the -"small_hello_world" template. - - -PERIPHERALS USED: -This example exercises the following peripherals: -- STDOUT device (UART or JTAG UART) - -SOFTWARE SOURCE FILES: -This example includes the following software source files: -- hello_world.c: Everyone needs a Hello World program, right? - -BOARD/HOST REQUIREMENTS: -This example requires only a JTAG connection with a Nios Development board. If -the host communication settings are changed from JTAG UART (default) to use a -conventional UART, a serial cable between board DB-9 connector and the host is -required. +Readme - Hello World Software Example + +DESCRIPTION: +Simple program that prints "Hello from Nios II" + +The memory footprint of this hosted application is intended to be small (under 100 kbytes) by default +using a standard reference deisgn. + +For an even smaller, reduced footprint version of this template, and an explanation of how +to reduce the memory footprint for a given application, see the +"small_hello_world" template. + + +PERIPHERALS USED: +This example exercises the following peripherals: +- STDOUT device (UART or JTAG UART) + +SOFTWARE SOURCE FILES: +This example includes the following software source files: +- hello_world.c: Everyone needs a Hello World program, right? + +BOARD/HOST REQUIREMENTS: +This example requires only a JTAG connection with a Nios Development board. If +the host communication settings are changed from JTAG UART (default) to use a +conventional UART, a serial cable between board DB-9 connector and the host is +required. diff --git a/software/qsys_tutorial_lcd4/sys_debug.c b/software/qsys_tutorial_lcd4/sys_debug.c index 48aa3c2..0a8cf77 100644 --- a/software/qsys_tutorial_lcd4/sys_debug.c +++ b/software/qsys_tutorial_lcd4/sys_debug.c @@ -1,118 +1,118 @@ -/* - * sys_debug.c - * - * Created on: 2016/12/02 - * Author: takayun - */ - -#include "sys_debug.h" -#include -#include "lcd_out.h" -#include - -void display_inst(struct InstRec inst, unsigned int pc) { - char inst_name[INST_NAME_ARRAY_LEN]; // ��ߖ� - char reg_name[REG_NAME_ARRAY_LEN]; // ��W�X�^�� - char buf[17]; - - // ��߂̖��O�̎擾 - convertInstName(inst_name, inst.inst); - // ��W�X�^�̖��O�̎擾 - convertRegName(reg_name, inst.regi); - - lcd_caret_reset(); - sprintf(buf, "PC:0x%02x -> %4s",pc,inst_name); - lcd_print(buf); - lcd_caret_reset2(); - sprintf(buf, "REG:%3s,MEM:0x%1x",reg_name,inst.memi); - lcd_print(buf); -} - -void display_mem(unsigned char memi, char memv) { - char buf[17]; - - lcd_caret_reset(); - sprintf(buf, "MEM:0x%1x",memi); - lcd_print(buf); - lcd_caret_reset2(); - sprintf(buf, "value:%d",memv); - lcd_print(buf); -} - -void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code) { - switch(reg_code) { - case Szero: - sprintf(reg_name, STRING_REG_ZERO); - break; - case Spc: - sprintf(reg_name, STRING_REG_PC); - break; - case Ssp: - sprintf(reg_name, STRING_REG_SP); - break; - case Sgp0: - sprintf(reg_name, STRING_REG_GP0); - break; - case Sgp1: - sprintf(reg_name, STRING_REG_GP1); - break; - case Sacc: - sprintf(reg_name, STRING_REG_ACC); - break; - case Sflg: - sprintf(reg_name, STRING_REG_FLG); - break; - default: - sprintf(reg_name, "non"); - break; - } -} - - -void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code) { - switch(inst_code) { - case INST_END: - sprintf(inst_name, STRING_INST_END); - break; - case INST_JUMP: - sprintf(inst_name, STRING_INST_JUMP); - break; - case INST_OUTPUT: - sprintf(inst_name, STRING_INST_OUTPUT); - break; - case INST_LOAD: - sprintf(inst_name, STRING_INST_LOAD); - break; - case INST_STORE: - sprintf(inst_name, STRING_INST_STORE); - break; - case INST_DELAY: - sprintf(inst_name, STRING_INST_DELAY); - break; - case INST_ADD: - sprintf(inst_name, STRING_INST_ADD); - break; - case INST_COMP: - sprintf(inst_name, STRING_INST_COMP); - break; - case INST_JEQ: - sprintf(inst_name, STRING_INST_JEQ); - break; - case INST_JNE: - sprintf(inst_name, STRING_INST_JNE); - break; - case INST_JIEQ: - sprintf(inst_name, STRING_INST_JIEQ); - break; - case INST_JINE: - sprintf(inst_name, STRING_INST_JINE); - break; - default: - sprintf(inst_name, "NoOp"); - break; - } -} - -void delay10ms(unsigned int s) { - usleep(s*10000); -} +/* + * sys_debug.c + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#include "sys_debug.h" +#include +#include "lcd_out.h" +#include + +void display_inst(struct InstRec inst, unsigned int pc) { + char inst_name[INST_NAME_ARRAY_LEN]; // ��ߖ� + char reg_name[REG_NAME_ARRAY_LEN]; // ��W�X�^�� + char buf[17]; + + // ��߂̖��O�̎擾 + convertInstName(inst_name, inst.inst); + // ��W�X�^�̖��O�̎擾 + convertRegName(reg_name, inst.regi); + + lcd_caret_reset(); + sprintf(buf, "PC:0x%02x -> %4s",pc,inst_name); + lcd_print(buf); + lcd_caret_reset2(); + sprintf(buf, "REG:%3s,MEM:0x%1x",reg_name,inst.memi); + lcd_print(buf); +} + +void display_mem(unsigned char memi, char memv) { + char buf[17]; + + lcd_caret_reset(); + sprintf(buf, "MEM:0x%1x",memi); + lcd_print(buf); + lcd_caret_reset2(); + sprintf(buf, "value:%d",memv); + lcd_print(buf); +} + +void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code) { + switch(reg_code) { + case Szero: + sprintf(reg_name, STRING_REG_ZERO); + break; + case Spc: + sprintf(reg_name, STRING_REG_PC); + break; + case Ssp: + sprintf(reg_name, STRING_REG_SP); + break; + case Sgp0: + sprintf(reg_name, STRING_REG_GP0); + break; + case Sgp1: + sprintf(reg_name, STRING_REG_GP1); + break; + case Sacc: + sprintf(reg_name, STRING_REG_ACC); + break; + case Sflg: + sprintf(reg_name, STRING_REG_FLG); + break; + default: + sprintf(reg_name, "non"); + break; + } +} + + +void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code) { + switch(inst_code) { + case INST_END: + sprintf(inst_name, STRING_INST_END); + break; + case INST_JUMP: + sprintf(inst_name, STRING_INST_JUMP); + break; + case INST_OUTPUT: + sprintf(inst_name, STRING_INST_OUTPUT); + break; + case INST_LOAD: + sprintf(inst_name, STRING_INST_LOAD); + break; + case INST_STORE: + sprintf(inst_name, STRING_INST_STORE); + break; + case INST_DELAY: + sprintf(inst_name, STRING_INST_DELAY); + break; + case INST_ADD: + sprintf(inst_name, STRING_INST_ADD); + break; + case INST_COMP: + sprintf(inst_name, STRING_INST_COMP); + break; + case INST_JEQ: + sprintf(inst_name, STRING_INST_JEQ); + break; + case INST_JNE: + sprintf(inst_name, STRING_INST_JNE); + break; + case INST_JIEQ: + sprintf(inst_name, STRING_INST_JIEQ); + break; + case INST_JINE: + sprintf(inst_name, STRING_INST_JINE); + break; + default: + sprintf(inst_name, "NoOp"); + break; + } +} + +void delay10ms(unsigned int s) { + usleep(s*10000); +} diff --git a/software/qsys_tutorial_lcd4/sys_debug.h b/software/qsys_tutorial_lcd4/sys_debug.h index 751ffa5..dcbba39 100644 --- a/software/qsys_tutorial_lcd4/sys_debug.h +++ b/software/qsys_tutorial_lcd4/sys_debug.h @@ -1,61 +1,61 @@ -/* - * sys_debug.h - * - * Created on: 2016/12/02 - * Author: takayun - */ - -#ifndef SYS_DEBUG_H_ -#define SYS_DEBUG_H_ - -#include "inst_decoder.h" -#include "sys_register.h" - -/************************************************** - * Defines - **************************************************/ - -#define INST_NAME_ARRAY_LEN 5 - -#define STRING_INST_END "END" -#define STRING_INST_JUMP "JUMP" -#define STRING_INST_OUTPUT "OUT" -#define STRING_INST_LOAD "LOAD" -#define STRING_INST_STORE "STOR" -#define STRING_INST_DELAY "DELY" -#define STRING_INST_ADD "ADD" -#define STRING_INST_COMP "COMP" -#define STRING_INST_JEQ "JEQ" -#define STRING_INST_JNE "JNE" -#define STRING_INST_JIEQ "JIEQ" -#define STRING_INST_JINE "JINE" - - -#define REG_NAME_ARRAY_LEN 4 - -#define STRING_REG_ZERO "ZE" -#define STRING_REG_PC "PC" -#define STRING_REG_SP "SP" -#define STRING_REG_GP0 "GP0" -#define STRING_REG_GP1 "GP1" -#define STRING_REG_ACC "ACC" -#define STRING_REG_FLG "FLG" - -/************************************************** - * Variables - **************************************************/ - - -/************************************************** - * Functions - **************************************************/ - -void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code); -void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code); - -void display_inst(struct InstRec inst, unsigned int pc); -void display_mem(unsigned char memi, char memv); - -void delay10ms(unsigned int s); - -#endif /* SYS_DEBUG_H_ */ +/* + * sys_debug.h + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#ifndef SYS_DEBUG_H_ +#define SYS_DEBUG_H_ + +#include "inst_decoder.h" +#include "sys_register.h" + +/************************************************** + * Defines + **************************************************/ + +#define INST_NAME_ARRAY_LEN 5 + +#define STRING_INST_END "END" +#define STRING_INST_JUMP "JUMP" +#define STRING_INST_OUTPUT "OUT" +#define STRING_INST_LOAD "LOAD" +#define STRING_INST_STORE "STOR" +#define STRING_INST_DELAY "DELY" +#define STRING_INST_ADD "ADD" +#define STRING_INST_COMP "COMP" +#define STRING_INST_JEQ "JEQ" +#define STRING_INST_JNE "JNE" +#define STRING_INST_JIEQ "JIEQ" +#define STRING_INST_JINE "JINE" + + +#define REG_NAME_ARRAY_LEN 4 + +#define STRING_REG_ZERO "ZE" +#define STRING_REG_PC "PC" +#define STRING_REG_SP "SP" +#define STRING_REG_GP0 "GP0" +#define STRING_REG_GP1 "GP1" +#define STRING_REG_ACC "ACC" +#define STRING_REG_FLG "FLG" + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code); +void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code); + +void display_inst(struct InstRec inst, unsigned int pc); +void display_mem(unsigned char memi, char memv); + +void delay10ms(unsigned int s); + +#endif /* SYS_DEBUG_H_ */ diff --git a/software/qsys_tutorial_lcd4/sys_except.c b/software/qsys_tutorial_lcd4/sys_except.c index 27c1a74..82420a4 100644 --- a/software/qsys_tutorial_lcd4/sys_except.c +++ b/software/qsys_tutorial_lcd4/sys_except.c @@ -1,14 +1,14 @@ -/* - * sys_except.c - * - * Created on: 2016/11/24 - * Author: takayun - */ -#include "system.h" -#include "hex_out.h" - -void panic() { - clear_block(HEX0_3); - print_block("err ", 4, HEX0_3); -} - +/* + * sys_except.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "system.h" +#include "hex_out.h" + +void panic() { + clear_block(HEX0_3); + print_block("err ", 4, HEX0_3); +} + diff --git a/software/qsys_tutorial_lcd4/sys_except.h b/software/qsys_tutorial_lcd4/sys_except.h index 689c62b..fa6f420 100644 --- a/software/qsys_tutorial_lcd4/sys_except.h +++ b/software/qsys_tutorial_lcd4/sys_except.h @@ -1,13 +1,13 @@ -/* - * sys_except.h - * - * Created on: 2016/11/24 - * Author: takayun - */ - -#ifndef SYSTEM_H_ -#define SYSTEM_H_ - -void panic(); - -#endif /* SYSTEM_H_ */ +/* + * sys_except.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYSTEM_H_ +#define SYSTEM_H_ + +void panic(); + +#endif /* SYSTEM_H_ */ diff --git a/software/qsys_tutorial_lcd4/sys_memory.c b/software/qsys_tutorial_lcd4/sys_memory.c index 372ea9e..71b9d69 100644 --- a/software/qsys_tutorial_lcd4/sys_memory.c +++ b/software/qsys_tutorial_lcd4/sys_memory.c @@ -1,59 +1,59 @@ -/* - * sys_memory.c - * - * Created on: 2016/11/24 - * Author: takayun - */ -#include "system.h" -#include "sys_memory.h" -#include "sys_register.h" -#include "sys_except.h" - -/************************************************** - * Public - **************************************************/ - -// ��̂ǂ̃��(0 < global_current_memory < MEMS_COUNT) -unsigned int global_current_memory = 0; - -/************************************************** - * Private - **************************************************/ - -// ��̕ϐ� -static char memory[MEMS_COUNT][MEM_SIZE]; - -static struct InstRec inst_memory[MEMS_COUNT][MEM_SIZE]; - - -/************************************************** - * Impl - **************************************************/ - -void memory_init() { - int i, j; - for (i = 0; i < MEMS_COUNT; i++) - for (j = 0; j < MEM_SIZE; j++) { - memory[i][j] = 0; - } -} - -void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec){ - inst_memory[global_current_memory][mem_addr] = inst_rec; -} -struct InstRec inst_memory_load(unsigned int mem_addr){ - return inst_memory[global_current_memory][mem_addr]; -} - -char memory_store(unsigned int mem_addr, enum Register reg) { - if (!(mem_addr < MEM_SIZE)) panic(); - memory[global_current_memory][mem_addr] = global_registers[reg]; - return memory[global_current_memory][mem_addr]; -} - -char memory_load(unsigned int mem_addr, enum Register reg) { - if (!(mem_addr < MEM_SIZE)) panic(); - global_registers[reg] = memory[global_current_memory][mem_addr]; - return global_registers[reg]; -} - +/* + * sys_memory.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "system.h" +#include "sys_memory.h" +#include "sys_register.h" +#include "sys_except.h" + +/************************************************** + * Public + **************************************************/ + +// ��̂ǂ̃��(0 < global_current_memory < MEMS_COUNT) +unsigned int global_current_memory = 0; + +/************************************************** + * Private + **************************************************/ + +// ��̕ϐ� +static char memory[MEMS_COUNT][MEM_SIZE]; + +static struct InstRec inst_memory[MEMS_COUNT][MEM_SIZE]; + + +/************************************************** + * Impl + **************************************************/ + +void memory_init() { + int i, j; + for (i = 0; i < MEMS_COUNT; i++) + for (j = 0; j < MEM_SIZE; j++) { + memory[i][j] = 0; + } +} + +void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec){ + inst_memory[global_current_memory][mem_addr] = inst_rec; +} +struct InstRec inst_memory_load(unsigned int mem_addr){ + return inst_memory[global_current_memory][mem_addr]; +} + +char memory_store(unsigned int mem_addr, enum Register reg) { + if (!(mem_addr < MEM_SIZE)) panic(); + memory[global_current_memory][mem_addr] = global_registers[reg]; + return memory[global_current_memory][mem_addr]; +} + +char memory_load(unsigned int mem_addr, enum Register reg) { + if (!(mem_addr < MEM_SIZE)) panic(); + global_registers[reg] = memory[global_current_memory][mem_addr]; + return global_registers[reg]; +} + diff --git a/software/qsys_tutorial_lcd4/sys_memory.h b/software/qsys_tutorial_lcd4/sys_memory.h index f9bce60..f67c9a4 100644 --- a/software/qsys_tutorial_lcd4/sys_memory.h +++ b/software/qsys_tutorial_lcd4/sys_memory.h @@ -1,67 +1,67 @@ -/* - * sys_memory.h - * - * Created on: 2016/11/24 - * Author: takayun - */ - -#ifndef SYS_MEMORY_H_ -#define SYS_MEMORY_H_ - -#include "sys_register.h" -#include "inst_decoder.h" - -/************************************************** - * Defines - **************************************************/ - -// ��̐� -#define MEMS_COUNT 16 - -// 1��̃T�C�Y -#define MEM_SIZE 16 - -/************************************************** - * Variables - **************************************************/ - -extern unsigned int global_current_memory; - -/************************************************** - * Functions - **************************************************/ - -/* Function: memory_init - * Sammary: - * ��(All 0) */ -void memory_init(); - -/* ��ߗp��ɖ��߂̃X�g�A&��[�h */ - -/* Function: memory_store -> char - * Sammary: - * ��̎w��Ԓn�Ɏw�肵��W�X�^��l��i�[�� - * Return: - * ��Ɋi�[��ꂽ�l */ -void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec); -struct InstRec inst_memory_load(unsigned int mem_addr); - - -/* ��-��W�X�^�Ԃ̑�� */ - -/* Function: memory_store -> char - * Sammary: - * ��̎w��Ԓn�Ɏw�肵��W�X�^��l��i�[�� - * Return: - * ��Ɋi�[��ꂽ�l */ -char memory_store(unsigned int mem_addr, enum Register reg); - -/* Function: memory_store -> char - * Sammary: - * �w�肵��W�X�^�Ƀ��̎w��Ԓn��l��i�[�� - * Return: - * ��W�X�^�Ɋi�[��ꂽ�l */ -char memory_load(unsigned int mem_addr, enum Register reg); - - -#endif /* SYS_MEMORY_H_ */ +/* + * sys_memory.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYS_MEMORY_H_ +#define SYS_MEMORY_H_ + +#include "sys_register.h" +#include "inst_decoder.h" + +/************************************************** + * Defines + **************************************************/ + +// ��̐� +#define MEMS_COUNT 16 + +// 1��̃T�C�Y +#define MEM_SIZE 16 + +/************************************************** + * Variables + **************************************************/ + +extern unsigned int global_current_memory; + +/************************************************** + * Functions + **************************************************/ + +/* Function: memory_init + * Sammary: + * ��(All 0) */ +void memory_init(); + +/* ��ߗp��ɖ��߂̃X�g�A&��[�h */ + +/* Function: memory_store -> char + * Sammary: + * ��̎w��Ԓn�Ɏw�肵��W�X�^��l��i�[�� + * Return: + * ��Ɋi�[��ꂽ�l */ +void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec); +struct InstRec inst_memory_load(unsigned int mem_addr); + + +/* ��-��W�X�^�Ԃ̑�� */ + +/* Function: memory_store -> char + * Sammary: + * ��̎w��Ԓn�Ɏw�肵��W�X�^��l��i�[�� + * Return: + * ��Ɋi�[��ꂽ�l */ +char memory_store(unsigned int mem_addr, enum Register reg); + +/* Function: memory_store -> char + * Sammary: + * �w�肵��W�X�^�Ƀ��̎w��Ԓn��l��i�[�� + * Return: + * ��W�X�^�Ɋi�[��ꂽ�l */ +char memory_load(unsigned int mem_addr, enum Register reg); + + +#endif /* SYS_MEMORY_H_ */ diff --git a/software/qsys_tutorial_lcd4/sys_register.c b/software/qsys_tutorial_lcd4/sys_register.c index 84ed485..26ba99b 100644 --- a/software/qsys_tutorial_lcd4/sys_register.c +++ b/software/qsys_tutorial_lcd4/sys_register.c @@ -1,17 +1,17 @@ -/* - * sys_register.c - * - * Created on: 2016/11/24 - * Author: takayun - */ -#include "sys_register.h" - -char global_registers[REG_MAX_COUNT]; - -void registers_init() { - int i; - for (i = 0; i < REG_MAX_COUNT; i++) global_registers[i] = 0; -} - - - +/* + * sys_register.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "sys_register.h" + +char global_registers[REG_MAX_COUNT]; + +void registers_init() { + int i; + for (i = 0; i < REG_MAX_COUNT; i++) global_registers[i] = 0; +} + + + diff --git a/software/qsys_tutorial_lcd4/sys_register.h b/software/qsys_tutorial_lcd4/sys_register.h index 65ad219..2603f26 100644 --- a/software/qsys_tutorial_lcd4/sys_register.h +++ b/software/qsys_tutorial_lcd4/sys_register.h @@ -1,54 +1,54 @@ -/* - * sys_register.h - * - * Created on: 2016/11/24 - * Author: takayun - */ - -#ifndef SYS_REGISTER_H_ -#define SYS_REGISTER_H_ - -/************************************************** - * Defines - **************************************************/ - -// ��W�X�^�̒�` -enum Register { - /* �ʏ�̃��W�X�^ */ - Szero, //�[��W�X�^ - Spc, //�v��O��J�E��^ - Ssp, //�X�^�b�N�|�C��^ - Sgp0, //�ėp��W�X�^0 - Sgp1, //�ėp��W�X�^1 - Sacc, //�A�L��[�^ - Sflg, //�t��O��W�X�^ - /* �X�C�b�`�ǂݏo��p��W�X�^ */ - Ssw_data, //�f�[�^(8bit) - Ssw_inst, //��(4bit) - Ssw_regi, //��W�X�^�ԍ�(4bit) - Ssw_memi, //��Ԓn(4bit) - Ssw_psel, //�v��O��Z��N�^(4bit) - Ssw_rw, //�ǂݏ��[�h(1bit) - Ssw_run, //��s��[�h(1bit) - /* 7�Z�O�p��W�X�^ */ - Sseg, - - /* �z��錾�p */ - REG_MAX_COUNT -}; - -/************************************************** - * Variables - **************************************************/ - -// ��W�X�^�p�̕ϐ� -extern char global_registers[REG_MAX_COUNT]; - -/************************************************** - * Functions - **************************************************/ - -void registers_init(); - - -#endif /* SYS_REGISTER_H_ */ +/* + * sys_register.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYS_REGISTER_H_ +#define SYS_REGISTER_H_ + +/************************************************** + * Defines + **************************************************/ + +// ��W�X�^�̒�` +enum Register { + /* �ʏ�̃��W�X�^ */ + Szero, //�[��W�X�^ + Spc, //�v��O��J�E��^ + Ssp, //�X�^�b�N�|�C��^ + Sgp0, //�ėp��W�X�^0 + Sgp1, //�ėp��W�X�^1 + Sacc, //�A�L��[�^ + Sflg, //�t��O��W�X�^ + /* �X�C�b�`�ǂݏo��p��W�X�^ */ + Ssw_data, //�f�[�^(8bit) + Ssw_inst, //��(4bit) + Ssw_regi, //��W�X�^�ԍ�(4bit) + Ssw_memi, //��Ԓn(4bit) + Ssw_psel, //�v��O��Z��N�^(4bit) + Ssw_rw, //�ǂݏ��[�h(1bit) + Ssw_run, //��s��[�h(1bit) + /* 7�Z�O�p��W�X�^ */ + Sseg, + + /* �z��錾�p */ + REG_MAX_COUNT +}; + +/************************************************** + * Variables + **************************************************/ + +// ��W�X�^�p�̕ϐ� +extern char global_registers[REG_MAX_COUNT]; + +/************************************************** + * Functions + **************************************************/ + +void registers_init(); + + +#endif /* SYS_REGISTER_H_ */ diff --git a/software/qsys_tutorial_lcd4_bsp/.cproject b/software/qsys_tutorial_lcd4_bsp/.cproject index a92ec0f..2927f5c 100644 --- a/software/qsys_tutorial_lcd4_bsp/.cproject +++ b/software/qsys_tutorial_lcd4_bsp/.cproject @@ -1,481 +1,481 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/qsys_tutorial_lcd4_bsp/.project b/software/qsys_tutorial_lcd4_bsp/.project index 8bbece1..0598622 100644 --- a/software/qsys_tutorial_lcd4_bsp/.project +++ b/software/qsys_tutorial_lcd4_bsp/.project @@ -1,85 +1,85 @@ - - - qsys_tutorial_lcd4_bsp - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc://qsys_tutorial_lcd4_bsp} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.core.ccnature - com.altera.sbtgui.project.SBTGUINature - com.altera.sbtgui.project.SBTGUIBspNature - - + + + qsys_tutorial_lcd4_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://qsys_tutorial_lcd4_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/alt_types.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/alt_types.h index d02f171..8eb438f 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/alt_types.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/alt_types.h @@ -1,54 +1,54 @@ -#ifndef __ALT_TYPES_H__ -#define __ALT_TYPES_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/* - * Don't declare these typedefs if this file is included by assembly source. - */ -#ifndef ALT_ASM_SRC -typedef signed char alt_8; -typedef unsigned char alt_u8; -typedef signed short alt_16; -typedef unsigned short alt_u16; -typedef signed long alt_32; -typedef unsigned long alt_u32; -typedef long long alt_64; -typedef unsigned long long alt_u64; -#endif - -#define ALT_INLINE __inline__ -#define ALT_ALWAYS_INLINE __attribute__ ((always_inline)) -#define ALT_WEAK __attribute__((weak)) - -#endif /* __ALT_TYPES_H__ */ +#ifndef __ALT_TYPES_H__ +#define __ALT_TYPES_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Don't declare these typedefs if this file is included by assembly source. + */ +#ifndef ALT_ASM_SRC +typedef signed char alt_8; +typedef unsigned char alt_u8; +typedef signed short alt_16; +typedef unsigned short alt_u16; +typedef signed long alt_32; +typedef unsigned long alt_u32; +typedef long long alt_64; +typedef unsigned long long alt_u64; +#endif + +#define ALT_INLINE __inline__ +#define ALT_ALWAYS_INLINE __attribute__ ((always_inline)) +#define ALT_WEAK __attribute__((weak)) + +#endif /* __ALT_TYPES_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/altera_nios2_qsys_irq.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/altera_nios2_qsys_irq.h index 6629ec9..910c91c 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/altera_nios2_qsys_irq.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/altera_nios2_qsys_irq.h @@ -1,80 +1,80 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * Support for the Nios II internal interrupt controller. - */ - -#ifndef __ALT_NIOS2_QSYS_IRQ_H__ -#define __ALT_NIOS2_QSYS_IRQ_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The macro ALTERA_NIOS2_IRQ_INSTANCE is used by the alt_irq_init() - * function in the auto-generated file alt_sys_init.c to create an - * instance of this interrupt controller device driver state if this - * module contains an interrupt controller. - * Only one instance of a Nios II is allowed so this macro is just empty. - */ - -#define ALTERA_NIOS2_QSYS_IRQ_INSTANCE(name, state) - -/* - * altera_nios2_irq_init() is called by the auto-generated function - * alt_irq_init() once for the Nios II if it contains an interrupt controller. - * The altera_nios2_irq_init() routine is called using the - * ALTERA_NIOS2_IRQ_INIT macro given below. - * - * This function initializes the internal interrupt controller - * so is not called if the Nios II contains an external interrupt - * controller port (because the internal interrupt controller - * is removed if this port is present). - */ - -extern void altera_nios2_qsys_irq_init( void ); - -/* - * The macro ALTERA_NIOS2_IRQ_INIT is used by the alt_irq_init() routine - * in the auto-generated file alt_sys_init.c to initialize an instance - * of the interrupt controller device driver state. - */ - -#define ALTERA_NIOS2_QSYS_IRQ_INIT(name, state) altera_nios2_qsys_irq_init() - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_NIOS2_QSYS_IRQ_H__ */ - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * Support for the Nios II internal interrupt controller. + */ + +#ifndef __ALT_NIOS2_QSYS_IRQ_H__ +#define __ALT_NIOS2_QSYS_IRQ_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The macro ALTERA_NIOS2_IRQ_INSTANCE is used by the alt_irq_init() + * function in the auto-generated file alt_sys_init.c to create an + * instance of this interrupt controller device driver state if this + * module contains an interrupt controller. + * Only one instance of a Nios II is allowed so this macro is just empty. + */ + +#define ALTERA_NIOS2_QSYS_IRQ_INSTANCE(name, state) + +/* + * altera_nios2_irq_init() is called by the auto-generated function + * alt_irq_init() once for the Nios II if it contains an interrupt controller. + * The altera_nios2_irq_init() routine is called using the + * ALTERA_NIOS2_IRQ_INIT macro given below. + * + * This function initializes the internal interrupt controller + * so is not called if the Nios II contains an external interrupt + * controller port (because the internal interrupt controller + * is removed if this port is present). + */ + +extern void altera_nios2_qsys_irq_init( void ); + +/* + * The macro ALTERA_NIOS2_IRQ_INIT is used by the alt_irq_init() routine + * in the auto-generated file alt_sys_init.c to initialize an instance + * of the interrupt controller device driver state. + */ + +#define ALTERA_NIOS2_QSYS_IRQ_INIT(name, state) altera_nios2_qsys_irq_init() + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_NIOS2_QSYS_IRQ_H__ */ + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/io.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/io.h index 362f103..867e87d 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/io.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/io.h @@ -1,81 +1,81 @@ -#ifndef __IO_H__ -#define __IO_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/* IO Header file for Nios II Toolchain */ - -#include "alt_types.h" -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#ifndef SYSTEM_BUS_WIDTH -#error SYSTEM_BUS_WIDTH undefined -#endif - -/* Dynamic bus access functions */ - -#define __IO_CALC_ADDRESS_DYNAMIC(BASE, OFFSET) \ - ((void *)(((alt_u8*)BASE) + (OFFSET))) - -#define IORD_32DIRECT(BASE, OFFSET) \ - __builtin_ldwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) -#define IORD_16DIRECT(BASE, OFFSET) \ - __builtin_ldhuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) -#define IORD_8DIRECT(BASE, OFFSET) \ - __builtin_ldbuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) - -#define IOWR_32DIRECT(BASE, OFFSET, DATA) \ - __builtin_stwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) -#define IOWR_16DIRECT(BASE, OFFSET, DATA) \ - __builtin_sthio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) -#define IOWR_8DIRECT(BASE, OFFSET, DATA) \ - __builtin_stbio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) - -/* Native bus access functions */ - -#define __IO_CALC_ADDRESS_NATIVE(BASE, REGNUM) \ - ((void *)(((alt_u8*)BASE) + ((REGNUM) * (SYSTEM_BUS_WIDTH/8)))) - -#define IORD(BASE, REGNUM) \ - __builtin_ldwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM))) -#define IOWR(BASE, REGNUM, DATA) \ - __builtin_stwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)), (DATA)) - -#ifdef __cplusplus -} -#endif - -#endif /* __IO_H__ */ +#ifndef __IO_H__ +#define __IO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* IO Header file for Nios II Toolchain */ + +#include "alt_types.h" +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#ifndef SYSTEM_BUS_WIDTH +#error SYSTEM_BUS_WIDTH undefined +#endif + +/* Dynamic bus access functions */ + +#define __IO_CALC_ADDRESS_DYNAMIC(BASE, OFFSET) \ + ((void *)(((alt_u8*)BASE) + (OFFSET))) + +#define IORD_32DIRECT(BASE, OFFSET) \ + __builtin_ldwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_16DIRECT(BASE, OFFSET) \ + __builtin_ldhuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_8DIRECT(BASE, OFFSET) \ + __builtin_ldbuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) + +#define IOWR_32DIRECT(BASE, OFFSET, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_16DIRECT(BASE, OFFSET, DATA) \ + __builtin_sthio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_8DIRECT(BASE, OFFSET, DATA) \ + __builtin_stbio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) + +/* Native bus access functions */ + +#define __IO_CALC_ADDRESS_NATIVE(BASE, REGNUM) \ + ((void *)(((alt_u8*)BASE) + ((REGNUM) * (SYSTEM_BUS_WIDTH/8)))) + +#define IORD(BASE, REGNUM) \ + __builtin_ldwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM))) +#define IOWR(BASE, REGNUM, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)), (DATA)) + +#ifdef __cplusplus +} +#endif + +#endif /* __IO_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/nios2.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/nios2.h index 72cefba..eec4e35 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/nios2.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/nios2.h @@ -1,230 +1,230 @@ -#ifndef __NIOS2_H__ -#define __NIOS2_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * This header provides processor specific macros for accessing the Nios2 - * control registers. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Macros for accessing selected processor registers - */ - -#define NIOS2_READ_ET(et) \ - do { __asm ("mov %0, et" : "=r" (et) ); } while (0) - -#define NIOS2_WRITE_ET(et) \ - do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0) - -#define NIOS2_READ_SP(sp) \ - do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0) - -/* - * Macros for useful processor instructions - */ - -#define NIOS2_BREAK() \ - do { __asm volatile ("break"); } while (0) - -#define NIOS2_REPORT_STACK_OVERFLOW() \ - do { __asm volatile("break 3"); } while (0) - -/* - * Macros for accessing the control registers. - */ - -#define NIOS2_READ_STATUS(dest) \ - do { dest = __builtin_rdctl(0); } while (0) - -#define NIOS2_WRITE_STATUS(src) \ - do { __builtin_wrctl(0, src); } while (0) - -#define NIOS2_READ_ESTATUS(dest) \ - do { dest = __builtin_rdctl(1); } while (0) - -#define NIOS2_READ_BSTATUS(dest) \ - do { dest = __builtin_rdctl(2); } while (0) - -#define NIOS2_READ_IENABLE(dest) \ - do { dest = __builtin_rdctl(3); } while (0) - -#define NIOS2_WRITE_IENABLE(src) \ - do { __builtin_wrctl(3, src); } while (0) - -#define NIOS2_READ_IPENDING(dest) \ - do { dest = __builtin_rdctl(4); } while (0) - -#define NIOS2_READ_CPUID(dest) \ - do { dest = __builtin_rdctl(5); } while (0) - - -/* - * Macros for accessing extra exception registers. These - * are always enabled wit the MPU or MMU, and optionally - * with other advanced exception types/ - */ -#define NIOS2_READ_EXCEPTION(dest) \ - do { dest = __builtin_rdctl(7); } while (0) - -#define NIOS2_READ_BADADDR(dest) \ - do { dest = __builtin_rdctl(12); } while (0) - - -/* - * Macros for accessing control registers for MPU - * operation. These should not be used unless the - * MPU is enabled. - * - * The config register may be augmented for future - * enhancements. For now, only MPU support is provided. - */ -/* Config register */ -#define NIOS2_WRITE_CONFIG(src) \ - do { __builtin_wrctl(13, src); } while (0) - -#define NIOS2_READ_CONFIG(dest) \ - do { dest = __builtin_rdctl(13); } while (0) - -/* MPU Base Address Register */ -#define NIOS2_WRITE_MPUBASE(src) \ - do { __builtin_wrctl(14, src); } while (0) - -#define NIOS2_READ_MPUBASE(dest) \ - do { dest = __builtin_rdctl(14); } while (0) - -/* MPU Access Register */ -#define NIOS2_WRITE_MPUACC(src) \ - do { __builtin_wrctl(15, src); } while (0) - -#define NIOS2_READ_MPUACC(dest) \ - do { dest = __builtin_rdctl(15); } while (0) - - -/* - * Nios II control registers that are always present - */ -#define NIOS2_STATUS status -#define NIOS2_ESTATUS estatus -#define NIOS2_BSTATUS bstatus -#define NIOS2_IENABLE ienable -#define NIOS2_IPENDING ipending -#define NIOS2_CPUID cpuid - -/* - * STATUS, BSTATUS, ESTATUS, and SSTATUS fields. - * The presence of fields is a function of the Nios II configuration. - */ -#define NIOS2_STATUS_PIE_MSK (0x00000001) -#define NIOS2_STATUS_PIE_OFST (0) -#define NIOS2_STATUS_U_MSK (0x00000002) -#define NIOS2_STATUS_U_OFST (1) -#define NIOS2_STATUS_EH_MSK (0x00000004) -#define NIOS2_STATUS_EH_OFST (2) -#define NIOS2_STATUS_IH_MSK (0x00000008) -#define NIOS2_STATUS_IH_OFST (3) -#define NIOS2_STATUS_IL_MSK (0x000003f0) -#define NIOS2_STATUS_IL_OFST (4) -#define NIOS2_STATUS_CRS_MSK (0x0000fc00) -#define NIOS2_STATUS_CRS_OFST (10) -#define NIOS2_STATUS_PRS_MSK (0x003f0000) -#define NIOS2_STATUS_PRS_OFST (16) -#define NIOS2_STATUS_NMI_MSK (0x00400000) -#define NIOS2_STATUS_NMI_OFST (22) -#define NIOS2_STATUS_RSIE_MSK (0x00800000) -#define NIOS2_STATUS_RSIE_OFST (23) -#define NIOS2_STATUS_SRS_MSK (0x80000000) -#define NIOS2_STATUS_SRS_OFST (31) - -/* - * Bit masks & offsets available with extra exceptions support - */ - -/* Exception register */ -#define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c) -#define NIOS2_EXCEPTION_REG_CAUSE_OFST (2) - -/* - * Bit masks & offsets for MPU support - * - * All bit-masks are expressed relative to the position - * of the data with a register. To read data that is LSB- - * aligned, the register read data should be masked, then - * right-shifted by the designated "OFST" macro value. The - * opposite should be used for register writes when starting - * with LSB-aligned data. - */ - -/* Config register */ -#define NIOS2_CONFIG_REG_PE_MASK (0x00000001) -#define NIOS2_CONFIG_REG_PE_OFST (0) -#define NIOS2_CONFIG_REG_ANI_MASK (0x00000002) -#define NIOS2_CONFIG_REG_ANI_OFST (1) - -/* MPU Base Address Register */ -#define NIOS2_MPUBASE_D_MASK (0x00000001) -#define NIOS2_MPUBASE_D_OFST (0) -#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) -#define NIOS2_MPUBASE_INDEX_OFST (1) -#define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0) -#define NIOS2_MPUBASE_BASE_ADDR_OFST (6) - -/* MPU Access Register */ -#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) -#define NIOS2_MPUACC_LIMIT_OFST (6) -#define NIOS2_MPUACC_MASK_MASK (0xffffffc0) -#define NIOS2_MPUACC_MASK_OFST (6) -#define NIOS2_MPUACC_C_MASK (0x00000020) -#define NIOS2_MPUACC_C_OFST (5) -#define NIOS2_MPUACC_PERM_MASK (0x0000001c) -#define NIOS2_MPUACC_PERM_OFST (2) -#define NIOS2_MPUACC_RD_MASK (0x00000002) -#define NIOS2_MPUACC_RD_OFST (1) -#define NIOS2_MPUACC_WR_MASK (0x00000001) -#define NIOS2_MPUACC_WR_OFST (0) - -/* - * Number of available IRQs in internal interrupt controller. - */ -#define NIOS2_NIRQ 32 - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NIOS2_H__ */ +#ifndef __NIOS2_H__ +#define __NIOS2_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This header provides processor specific macros for accessing the Nios2 + * control registers. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros for accessing selected processor registers + */ + +#define NIOS2_READ_ET(et) \ + do { __asm ("mov %0, et" : "=r" (et) ); } while (0) + +#define NIOS2_WRITE_ET(et) \ + do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0) + +#define NIOS2_READ_SP(sp) \ + do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0) + +/* + * Macros for useful processor instructions + */ + +#define NIOS2_BREAK() \ + do { __asm volatile ("break"); } while (0) + +#define NIOS2_REPORT_STACK_OVERFLOW() \ + do { __asm volatile("break 3"); } while (0) + +/* + * Macros for accessing the control registers. + */ + +#define NIOS2_READ_STATUS(dest) \ + do { dest = __builtin_rdctl(0); } while (0) + +#define NIOS2_WRITE_STATUS(src) \ + do { __builtin_wrctl(0, src); } while (0) + +#define NIOS2_READ_ESTATUS(dest) \ + do { dest = __builtin_rdctl(1); } while (0) + +#define NIOS2_READ_BSTATUS(dest) \ + do { dest = __builtin_rdctl(2); } while (0) + +#define NIOS2_READ_IENABLE(dest) \ + do { dest = __builtin_rdctl(3); } while (0) + +#define NIOS2_WRITE_IENABLE(src) \ + do { __builtin_wrctl(3, src); } while (0) + +#define NIOS2_READ_IPENDING(dest) \ + do { dest = __builtin_rdctl(4); } while (0) + +#define NIOS2_READ_CPUID(dest) \ + do { dest = __builtin_rdctl(5); } while (0) + + +/* + * Macros for accessing extra exception registers. These + * are always enabled wit the MPU or MMU, and optionally + * with other advanced exception types/ + */ +#define NIOS2_READ_EXCEPTION(dest) \ + do { dest = __builtin_rdctl(7); } while (0) + +#define NIOS2_READ_BADADDR(dest) \ + do { dest = __builtin_rdctl(12); } while (0) + + +/* + * Macros for accessing control registers for MPU + * operation. These should not be used unless the + * MPU is enabled. + * + * The config register may be augmented for future + * enhancements. For now, only MPU support is provided. + */ +/* Config register */ +#define NIOS2_WRITE_CONFIG(src) \ + do { __builtin_wrctl(13, src); } while (0) + +#define NIOS2_READ_CONFIG(dest) \ + do { dest = __builtin_rdctl(13); } while (0) + +/* MPU Base Address Register */ +#define NIOS2_WRITE_MPUBASE(src) \ + do { __builtin_wrctl(14, src); } while (0) + +#define NIOS2_READ_MPUBASE(dest) \ + do { dest = __builtin_rdctl(14); } while (0) + +/* MPU Access Register */ +#define NIOS2_WRITE_MPUACC(src) \ + do { __builtin_wrctl(15, src); } while (0) + +#define NIOS2_READ_MPUACC(dest) \ + do { dest = __builtin_rdctl(15); } while (0) + + +/* + * Nios II control registers that are always present + */ +#define NIOS2_STATUS status +#define NIOS2_ESTATUS estatus +#define NIOS2_BSTATUS bstatus +#define NIOS2_IENABLE ienable +#define NIOS2_IPENDING ipending +#define NIOS2_CPUID cpuid + +/* + * STATUS, BSTATUS, ESTATUS, and SSTATUS fields. + * The presence of fields is a function of the Nios II configuration. + */ +#define NIOS2_STATUS_PIE_MSK (0x00000001) +#define NIOS2_STATUS_PIE_OFST (0) +#define NIOS2_STATUS_U_MSK (0x00000002) +#define NIOS2_STATUS_U_OFST (1) +#define NIOS2_STATUS_EH_MSK (0x00000004) +#define NIOS2_STATUS_EH_OFST (2) +#define NIOS2_STATUS_IH_MSK (0x00000008) +#define NIOS2_STATUS_IH_OFST (3) +#define NIOS2_STATUS_IL_MSK (0x000003f0) +#define NIOS2_STATUS_IL_OFST (4) +#define NIOS2_STATUS_CRS_MSK (0x0000fc00) +#define NIOS2_STATUS_CRS_OFST (10) +#define NIOS2_STATUS_PRS_MSK (0x003f0000) +#define NIOS2_STATUS_PRS_OFST (16) +#define NIOS2_STATUS_NMI_MSK (0x00400000) +#define NIOS2_STATUS_NMI_OFST (22) +#define NIOS2_STATUS_RSIE_MSK (0x00800000) +#define NIOS2_STATUS_RSIE_OFST (23) +#define NIOS2_STATUS_SRS_MSK (0x80000000) +#define NIOS2_STATUS_SRS_OFST (31) + +/* + * Bit masks & offsets available with extra exceptions support + */ + +/* Exception register */ +#define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c) +#define NIOS2_EXCEPTION_REG_CAUSE_OFST (2) + +/* + * Bit masks & offsets for MPU support + * + * All bit-masks are expressed relative to the position + * of the data with a register. To read data that is LSB- + * aligned, the register read data should be masked, then + * right-shifted by the designated "OFST" macro value. The + * opposite should be used for register writes when starting + * with LSB-aligned data. + */ + +/* Config register */ +#define NIOS2_CONFIG_REG_PE_MASK (0x00000001) +#define NIOS2_CONFIG_REG_PE_OFST (0) +#define NIOS2_CONFIG_REG_ANI_MASK (0x00000002) +#define NIOS2_CONFIG_REG_ANI_OFST (1) + +/* MPU Base Address Register */ +#define NIOS2_MPUBASE_D_MASK (0x00000001) +#define NIOS2_MPUBASE_D_OFST (0) +#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) +#define NIOS2_MPUBASE_INDEX_OFST (1) +#define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0) +#define NIOS2_MPUBASE_BASE_ADDR_OFST (6) + +/* MPU Access Register */ +#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) +#define NIOS2_MPUACC_LIMIT_OFST (6) +#define NIOS2_MPUACC_MASK_MASK (0xffffffc0) +#define NIOS2_MPUACC_MASK_OFST (6) +#define NIOS2_MPUACC_C_MASK (0x00000020) +#define NIOS2_MPUACC_C_OFST (5) +#define NIOS2_MPUACC_PERM_MASK (0x0000001c) +#define NIOS2_MPUACC_PERM_OFST (2) +#define NIOS2_MPUACC_RD_MASK (0x00000002) +#define NIOS2_MPUACC_RD_OFST (1) +#define NIOS2_MPUACC_WR_MASK (0x00000001) +#define NIOS2_MPUACC_WR_OFST (0) + +/* + * Number of available IRQs in internal interrupt controller. + */ +#define NIOS2_NIRQ 32 + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NIOS2_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_flag.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_flag.h index b9b4605..86493c2 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_flag.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_flag.h @@ -1,98 +1,98 @@ -#ifndef __ALT_FLAG_H__ -#define __ALT_FLAG_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/* - * This header provides macro definitions that can be used to create and use - * uc/OS-II style event flags. These macros can be used in both a uC/OS-II based - * environment, and a single threaded HAL based environment. - * - * The motivation for these macros is to allow code to be developed which is - * thread safe under uC/OS-II, but incurs no additional overhead when used in a - * single threaded HAL environment. - * - * In the case of a single threaded HAL environment, they compile to - * "do nothing" directives, which ensures they do not contribute to the final - * executable. - * - * The following macros are available: - * - * ALT_FLAG_GRP - Create a flag group instance. - * ALT_EXTERN_FLAG_GRP - Create a reference to an external flag group instance. - * ALT_STATIC_FLAG_GRP - Create a static flag group instance. - * ALT_FLAG_CREATE - Initialise a flag group. - * ALT_FLAG_PEND - Pend on a flag group. - * ALT_FLAG_POST - Set a flag condition. - - * - * Input arguments and return codes are all consistant with the equivalent - * uC/OS-II function. - * - * It's important to be careful in the use of the macros: ALT_FLAG_GRP, - * ALT_EXTERN_FLAG_GRP, and ALT_STATIC_FLAG_GRP. In these three cases the - * semi-colon is included in the macro definition; so, for example, you should - * use: - * - * ALT_FLAG_GRP(mygroup) - * - * not: - * - * ALT_FLAG_GRP(mygroup); - * - * The inclusion of the semi-colon has been necessary to ensure the macros can - * compile with no warnings when used in a single threaded HAL environment. - * - */ - -#include "priv/alt_no_error.h" - -#define ALT_FLAG_GRP(group) -#define ALT_EXTERN_FLAG_GRP(group) -#define ALT_STATIC_FLAG_GRP(group) - -#define ALT_FLAG_CREATE(group, flags) alt_no_error () -#define ALT_FLAG_PEND(group, flags, wait_type, timeout) alt_no_error () -#define ALT_FLAG_POST(group, flags, opt) alt_no_error () - -#ifndef ALT_SINGLE_THREADED -#define ALT_SINGLE_THREADED -#endif - -#endif /* __ALT_FLAG_H__ */ +#ifndef __ALT_FLAG_H__ +#define __ALT_FLAG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides macro definitions that can be used to create and use + * uc/OS-II style event flags. These macros can be used in both a uC/OS-II based + * environment, and a single threaded HAL based environment. + * + * The motivation for these macros is to allow code to be developed which is + * thread safe under uC/OS-II, but incurs no additional overhead when used in a + * single threaded HAL environment. + * + * In the case of a single threaded HAL environment, they compile to + * "do nothing" directives, which ensures they do not contribute to the final + * executable. + * + * The following macros are available: + * + * ALT_FLAG_GRP - Create a flag group instance. + * ALT_EXTERN_FLAG_GRP - Create a reference to an external flag group instance. + * ALT_STATIC_FLAG_GRP - Create a static flag group instance. + * ALT_FLAG_CREATE - Initialise a flag group. + * ALT_FLAG_PEND - Pend on a flag group. + * ALT_FLAG_POST - Set a flag condition. + + * + * Input arguments and return codes are all consistant with the equivalent + * uC/OS-II function. + * + * It's important to be careful in the use of the macros: ALT_FLAG_GRP, + * ALT_EXTERN_FLAG_GRP, and ALT_STATIC_FLAG_GRP. In these three cases the + * semi-colon is included in the macro definition; so, for example, you should + * use: + * + * ALT_FLAG_GRP(mygroup) + * + * not: + * + * ALT_FLAG_GRP(mygroup); + * + * The inclusion of the semi-colon has been necessary to ensure the macros can + * compile with no warnings when used in a single threaded HAL environment. + * + */ + +#include "priv/alt_no_error.h" + +#define ALT_FLAG_GRP(group) +#define ALT_EXTERN_FLAG_GRP(group) +#define ALT_STATIC_FLAG_GRP(group) + +#define ALT_FLAG_CREATE(group, flags) alt_no_error () +#define ALT_FLAG_PEND(group, flags, wait_type, timeout) alt_no_error () +#define ALT_FLAG_POST(group, flags, opt) alt_no_error () + +#ifndef ALT_SINGLE_THREADED +#define ALT_SINGLE_THREADED +#endif + +#endif /* __ALT_FLAG_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_hooks.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_hooks.h index 9054e3f..ba1100e 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_hooks.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_hooks.h @@ -1,61 +1,61 @@ -#ifndef __ALT_HOOKS_H__ -#define __ALT_HOOKS_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/* - * This header provides "do-nothing" macro definitions for operating system - * hooks within the HAL. The O/S component can override these to provide it's - * own implementation. - */ - -#define ALT_OS_TIME_TICK() while(0) -#define ALT_OS_INIT() while(0) -#define ALT_OS_STOP() while(0) - -/* Call from assembly code */ -#define ALT_OS_INT_ENTER_ASM -#define ALT_OS_INT_EXIT_ASM - -/* Call from C code */ -#define ALT_OS_INT_ENTER() while(0) -#define ALT_OS_INT_EXIT() while(0) - - -#endif /* __ALT_HOOKS_H__ */ +#ifndef __ALT_HOOKS_H__ +#define __ALT_HOOKS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides "do-nothing" macro definitions for operating system + * hooks within the HAL. The O/S component can override these to provide it's + * own implementation. + */ + +#define ALT_OS_TIME_TICK() while(0) +#define ALT_OS_INIT() while(0) +#define ALT_OS_STOP() while(0) + +/* Call from assembly code */ +#define ALT_OS_INT_ENTER_ASM +#define ALT_OS_INT_EXIT_ASM + +/* Call from C code */ +#define ALT_OS_INT_ENTER() while(0) +#define ALT_OS_INT_EXIT() while(0) + + +#endif /* __ALT_HOOKS_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_sem.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_sem.h index 753943e..ed0f4a8 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_sem.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_sem.h @@ -1,96 +1,96 @@ -#ifndef __ALT_SEM_H__ -#define __ALT_SEM_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/* - * This header provides macro definitions that can be used to create and use - * semaphores. These macros can be used in both a uC/OS-II based environment, - * and a single threaded HAL based environment. - * - * The motivation for these macros is to allow code to be developed which is - * thread safe under uC/OS-II, but incurs no additional overhead when used in a - * single threaded HAL environment. - * - * In the case of a single threaded HAL environment, they compile to - * "do nothing" directives, which ensures they do not contribute to the final - * executable. - * - * The following macros are available: - * - * ALT_SEM - Create a semaphore instance. - * ALT_EXTERN_SEM - Create a reference to an external semaphore instance. - * ALT_STATIC_SEM - Create a static semaphore instance. - * ALT_SEM_CREATE - Initialise a semaphore. - * ALT_SEM_PEND - Pend on a semaphore. - * ALT_SEM_POST - Increment a semaphore. - * - * Input arguments and return codes are all consistant with the equivalent - * uC/OS-II function. - * - * It's important to be careful in the use of the macros: ALT_SEM, - * ALT_EXTERN_SEM, and ALT_STATIC_SEM. In these three cases the semi-colon is - * included in the macro definition; so, for example, you should use: - * - * ALT_SEM(mysem) - * - * not: - * - * ALT_SEM(mysem); - * - * The inclusion of the semi-colon has been necessary to ensure the macros can - * compile with no warnings when used in a single threaded HAL environment. - * - */ - -#include "priv/alt_no_error.h" - -#define ALT_SEM(sem) -#define ALT_EXTERN_SEM(sem) -#define ALT_STATIC_SEM(sem) - -#define ALT_SEM_CREATE(sem, value) alt_no_error () -#define ALT_SEM_PEND(sem, timeout) alt_no_error () -#define ALT_SEM_POST(sem) alt_no_error () - -#ifndef ALT_SINGLE_THREADED -#define ALT_SINGLE_THREADED -#endif - -#endif /* __ALT_SEM_H__ */ +#ifndef __ALT_SEM_H__ +#define __ALT_SEM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides macro definitions that can be used to create and use + * semaphores. These macros can be used in both a uC/OS-II based environment, + * and a single threaded HAL based environment. + * + * The motivation for these macros is to allow code to be developed which is + * thread safe under uC/OS-II, but incurs no additional overhead when used in a + * single threaded HAL environment. + * + * In the case of a single threaded HAL environment, they compile to + * "do nothing" directives, which ensures they do not contribute to the final + * executable. + * + * The following macros are available: + * + * ALT_SEM - Create a semaphore instance. + * ALT_EXTERN_SEM - Create a reference to an external semaphore instance. + * ALT_STATIC_SEM - Create a static semaphore instance. + * ALT_SEM_CREATE - Initialise a semaphore. + * ALT_SEM_PEND - Pend on a semaphore. + * ALT_SEM_POST - Increment a semaphore. + * + * Input arguments and return codes are all consistant with the equivalent + * uC/OS-II function. + * + * It's important to be careful in the use of the macros: ALT_SEM, + * ALT_EXTERN_SEM, and ALT_STATIC_SEM. In these three cases the semi-colon is + * included in the macro definition; so, for example, you should use: + * + * ALT_SEM(mysem) + * + * not: + * + * ALT_SEM(mysem); + * + * The inclusion of the semi-colon has been necessary to ensure the macros can + * compile with no warnings when used in a single threaded HAL environment. + * + */ + +#include "priv/alt_no_error.h" + +#define ALT_SEM(sem) +#define ALT_EXTERN_SEM(sem) +#define ALT_STATIC_SEM(sem) + +#define ALT_SEM_CREATE(sem, value) alt_no_error () +#define ALT_SEM_PEND(sem, timeout) alt_no_error () +#define ALT_SEM_POST(sem) alt_no_error () + +#ifndef ALT_SINGLE_THREADED +#define ALT_SINGLE_THREADED +#endif + +#endif /* __ALT_SEM_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_syscall.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_syscall.h index 507c6aa..2b1165a 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_syscall.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/os/alt_syscall.h @@ -1,75 +1,75 @@ -#ifndef __ALT_SYSCALL_H__ -#define __ALT_SYSCALL_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * The macros defined in this file are used to provide the function names used - * for the HAL 'UNIX style' interface, e.g. read(), write() etc. - * - * Operating systems which are ported to the HAL can provide their own - * version of this file, which will be used in preference. This allows - * the operating system to provide it's own implementation of the top level - * system calls, while retaining the HAL functions under a different name, - * for example, alt_read(), alt_write() etc. - */ - -#define ALT_CLOSE close -#define ALT_ENVIRON environ -#define ALT_EXECVE execve -#define ALT_EXIT _exit -#define ALT_FCNTL fcntl -#define ALT_FORK fork -#define ALT_FSTAT fstat -#define ALT_GETPID getpid -#define ALT_GETTIMEOFDAY gettimeofday -#define ALT_IOCTL ioctl -#define ALT_ISATTY isatty -#define ALT_KILL kill -#define ALT_LINK link -#define ALT_LSEEK lseek -#define ALT_OPEN open -#define ALT_READ read -#define ALT_RENAME _rename -#define ALT_SBRK sbrk -#define ALT_SETTIMEOFDAY settimeofday -#define ALT_STAT stat -#define ALT_UNLINK unlink -#define ALT_USLEEP usleep -#define ALT_WAIT wait -#define ALT_WRITE write -#define ALT_TIMES times - -/* - * - */ - -#endif /* __ALT_SYSCALL_H__ */ +#ifndef __ALT_SYSCALL_H__ +#define __ALT_SYSCALL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The macros defined in this file are used to provide the function names used + * for the HAL 'UNIX style' interface, e.g. read(), write() etc. + * + * Operating systems which are ported to the HAL can provide their own + * version of this file, which will be used in preference. This allows + * the operating system to provide it's own implementation of the top level + * system calls, while retaining the HAL functions under a different name, + * for example, alt_read(), alt_write() etc. + */ + +#define ALT_CLOSE close +#define ALT_ENVIRON environ +#define ALT_EXECVE execve +#define ALT_EXIT _exit +#define ALT_FCNTL fcntl +#define ALT_FORK fork +#define ALT_FSTAT fstat +#define ALT_GETPID getpid +#define ALT_GETTIMEOFDAY gettimeofday +#define ALT_IOCTL ioctl +#define ALT_ISATTY isatty +#define ALT_KILL kill +#define ALT_LINK link +#define ALT_LSEEK lseek +#define ALT_OPEN open +#define ALT_READ read +#define ALT_RENAME _rename +#define ALT_SBRK sbrk +#define ALT_SETTIMEOFDAY settimeofday +#define ALT_STAT stat +#define ALT_UNLINK unlink +#define ALT_USLEEP usleep +#define ALT_WAIT wait +#define ALT_WRITE write +#define ALT_TIMES times + +/* + * + */ + +#endif /* __ALT_SYSCALL_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_alarm.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_alarm.h index 45d6a0e..ae687bb 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_alarm.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_alarm.h @@ -1,101 +1,101 @@ -#ifndef __ALT_PRIV_ALARM_H__ -#define __ALT_PRIV_ALARM_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "alt_types.h" - -/* - * This header provides the internal defenitions required by the public - * interface alt_alarm.h. These variables and structures are not guaranteed to - * exist in future implementations of the HAL. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * "alt_alarm_s" is a structure type used to maintain lists of alarm callback - * functions. - */ - -struct alt_alarm_s -{ - alt_llist llist; /* linked list */ - alt_u32 time; /* time in system ticks of the callback */ - alt_u32 (*callback) (void* context); /* callback function. The return - * value is the period for the next callback; where - * zero indicates that the alarm should be removed - * from the list. - */ - alt_u8 rollover; /* set when desired alarm time + current time causes - overflow, to prevent premature alarm */ - void* context; /* Argument for the callback */ -}; - -/* - * "_alt_tick_rate" is a global variable used to store the system clock rate - * in ticks per second. This is initialised to zero, which coresponds to there - * being no system clock available. - * - * It is then set to it's final value by the system clock driver through a call - * to alt_sysclk_init(). - */ - -extern alt_u32 _alt_tick_rate; - -/* - * "_alt_nticks" is a global variable which records the elapsed number of - * system clock ticks since the last call to settimeofday() or since reset if - * settimeofday() has not been called. - */ - -extern volatile alt_u32 _alt_nticks; - -/* The list of registered alarms. */ - -extern alt_llist alt_alarm_list; - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_PRIV_ALARM_H__ */ +#ifndef __ALT_PRIV_ALARM_H__ +#define __ALT_PRIV_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required by the public + * interface alt_alarm.h. These variables and structures are not guaranteed to + * exist in future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm_s" is a structure type used to maintain lists of alarm callback + * functions. + */ + +struct alt_alarm_s +{ + alt_llist llist; /* linked list */ + alt_u32 time; /* time in system ticks of the callback */ + alt_u32 (*callback) (void* context); /* callback function. The return + * value is the period for the next callback; where + * zero indicates that the alarm should be removed + * from the list. + */ + alt_u8 rollover; /* set when desired alarm time + current time causes + overflow, to prevent premature alarm */ + void* context; /* Argument for the callback */ +}; + +/* + * "_alt_tick_rate" is a global variable used to store the system clock rate + * in ticks per second. This is initialised to zero, which coresponds to there + * being no system clock available. + * + * It is then set to it's final value by the system clock driver through a call + * to alt_sysclk_init(). + */ + +extern alt_u32 _alt_tick_rate; + +/* + * "_alt_nticks" is a global variable which records the elapsed number of + * system clock ticks since the last call to settimeofday() or since reset if + * settimeofday() has not been called. + */ + +extern volatile alt_u32 _alt_nticks; + +/* The list of registered alarms. */ + +extern alt_llist alt_alarm_list; + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_PRIV_ALARM_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_busy_sleep.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_busy_sleep.h index b1af849..a165e93 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_busy_sleep.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_busy_sleep.h @@ -1,35 +1,35 @@ -#ifndef __ALT_BUSY_SLEEP_H -#define __ALT_BUSY_SLEEP_H - -/* - * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* - * The function alt_busy_sleep provides a busy loop implementation of usleep. - * This is used to provide usleep for the standalone HAL, or when the timer is - * unavailable in uC/OS-II. - */ - -extern unsigned int alt_busy_sleep (unsigned int us); - -#endif /* __ALT_BUSY_SLEEP_H */ +#ifndef __ALT_BUSY_SLEEP_H +#define __ALT_BUSY_SLEEP_H + +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * The function alt_busy_sleep provides a busy loop implementation of usleep. + * This is used to provide usleep for the standalone HAL, or when the timer is + * unavailable in uC/OS-II. + */ + +extern unsigned int alt_busy_sleep (unsigned int us); + +#endif /* __ALT_BUSY_SLEEP_H */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_dev_llist.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_dev_llist.h index 451b063..0ab7a28 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_dev_llist.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_dev_llist.h @@ -1,77 +1,77 @@ -#ifndef __ALT_DEV_LLIST_H__ -#define __ALT_DEV_LLIST_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "sys/alt_llist.h" -#include "alt_types.h" - -/* - * This header provides the internal defenitions required to control file - * access. These variables and functions are not guaranteed to exist in - * future implementations of the HAL. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The alt_dev_llist is an internal structure used to form a common base - * class for all device types. The use of this structure allows common code - * to be used to manipulate the various device lists. - */ - -typedef struct { - alt_llist llist; - const char* name; -} alt_dev_llist; - -/* - * - */ - -extern int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list); - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_DEV_LLIST_H__ */ +#ifndef __ALT_DEV_LLIST_H__ +#define __ALT_DEV_LLIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_llist.h" +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The alt_dev_llist is an internal structure used to form a common base + * class for all device types. The use of this structure allows common code + * to be used to manipulate the various device lists. + */ + +typedef struct { + alt_llist llist; + const char* name; +} alt_dev_llist; + +/* + * + */ + +extern int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_LLIST_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_exception_handler_registry.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_exception_handler_registry.h index c6905fa..4502ea7 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_exception_handler_registry.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_exception_handler_registry.h @@ -1,39 +1,39 @@ -#ifndef __ALT_EXCEPTION_HANDLER_REGISTRY_H__ -#define __ALT_EXCEPTION_HANDLER_REGISTRY_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ -#include "sys/alt_exceptions.h" - -/* Function pointer to exception callback routine */ -extern alt_exception_result (*alt_instruction_exception_handler) - (alt_exception_cause, alt_u32, alt_u32); - -#endif /* __ALT_EXCEPTION_HANDLER_REGISTRY_H__ */ +#ifndef __ALT_EXCEPTION_HANDLER_REGISTRY_H__ +#define __ALT_EXCEPTION_HANDLER_REGISTRY_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "sys/alt_exceptions.h" + +/* Function pointer to exception callback routine */ +extern alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32); + +#endif /* __ALT_EXCEPTION_HANDLER_REGISTRY_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_file.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_file.h index 2c3e843..94007a6 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_file.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_file.h @@ -1,179 +1,179 @@ -#ifndef __ALT_FILE_H__ -#define __ALT_FILE_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "sys/alt_dev.h" -#include "sys/alt_llist.h" -#include "os/alt_sem.h" - -#include "alt_types.h" - -/* - * This header provides the internal defenitions required to control file - * access. These variables and functions are not guaranteed to exist in - * future implementations of the HAL. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The function alt_find_dev() is used to search the device list "list" to - * locate a device named "name". If a match is found, then a pointer to the - * device is returned, otherwise NULL is returned. - */ - -extern alt_dev* alt_find_dev (const char* name, alt_llist* list); - -/* - * alt_find_file() is used to search the list of registered file systems to - * find the filesystem that the file named "name" belongs to. If a match is - * found, then a pointer to the filesystems alt_dev structure is returned, - * otherwise NULL is returned. - * - * Note that a match does not indicate that the file exists, only that a - * filesystem exists that is registered for a partition that could contain - * the file. The filesystems open() function would need to be called in order - * to determine if the file exists. - */ - -extern alt_dev* alt_find_file (const char* name); - -/* - * alt_get_fd() is used to allocate a file descriptor for the device or - * filesystem "dev". A negative return value indicates an error, otherwise the - * return value is the index of the file descriptor within the file descriptor - * pool. - */ - -extern int alt_get_fd (alt_dev* dev); - -/* - * alt_release_fd() is called to free the file descriptor with index "fd". - */ - -extern void alt_release_fd (int fd); - -/* - * alt_fd_lock() is called by ioctl() to mark the file descriptor "fd" as - * being open for exclusive access. Subsequent calls to open() for the device - * associated with "fd" will fail. A device is unlocked by either calling - * close() for "fd", or by an alternate call to ioctl() (see ioctl.c for - * details). - */ - -extern int alt_fd_lock (alt_fd* fd); - -/* - * alt_fd_unlock() is called by ioctl() to unlock a descriptor previously - * locked by a call to alt_fd_lock(). - */ - -extern int alt_fd_unlock (alt_fd* fd); - -/* - * "alt_fd_list" is the pool of file descriptors. - */ - -extern alt_fd alt_fd_list[]; - -/* - * flags used by alt_fd. - * - * ALT_FD_EXCL is used to mark a file descriptor as locked for exclusive - * access, i.e. further calls to open() for the associated device should - * fail. - * - * ALT_FD_DEV marks a dile descriptor as belonging to a device as oposed to a - * filesystem. - */ - -#define ALT_FD_EXCL 0x80000000 -#define ALT_FD_DEV 0x40000000 - -#define ALT_FD_FLAGS_MASK (ALT_FD_EXCL | ALT_FD_DEV) - -/* - * "alt_dev_list" is the head of the linked list of registered devices. - */ - -extern alt_llist alt_dev_list; - -/* - * "alt_fs_list" is the head of the linked list of registered filesystems. - */ - -extern alt_llist alt_fs_list; - -/* - * "alt_fd_list_lock" is a semaphore used to ensure that access to the pool - * of file descriptors is thread safe. - */ - -ALT_EXTERN_SEM(alt_fd_list_lock) - -/* - * "alt_max_fd" is a 'high water mark'. It indicates the highest file - * descriptor allocated. Use of this can save searching the entire pool - * for active file descriptors, which helps avoid contention on access - * to the file descriptor pool. - */ - -extern alt_32 alt_max_fd; - -/* - * alt_io_redirect() is called at startup to redirect stdout, stdin, and - * stderr to the devices named in the input arguments. By default these streams - * are directed at /dev/null, and are then redirected using this function once - * all of the devices have been registered within the system. - */ - -extern void alt_io_redirect(const char* stdout_dev, - const char* stdin_dev, - const char* stderr_dev); - - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_FILE_H__ */ +#ifndef __ALT_FILE_H__ +#define __ALT_FILE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "sys/alt_llist.h" +#include "os/alt_sem.h" + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_find_dev() is used to search the device list "list" to + * locate a device named "name". If a match is found, then a pointer to the + * device is returned, otherwise NULL is returned. + */ + +extern alt_dev* alt_find_dev (const char* name, alt_llist* list); + +/* + * alt_find_file() is used to search the list of registered file systems to + * find the filesystem that the file named "name" belongs to. If a match is + * found, then a pointer to the filesystems alt_dev structure is returned, + * otherwise NULL is returned. + * + * Note that a match does not indicate that the file exists, only that a + * filesystem exists that is registered for a partition that could contain + * the file. The filesystems open() function would need to be called in order + * to determine if the file exists. + */ + +extern alt_dev* alt_find_file (const char* name); + +/* + * alt_get_fd() is used to allocate a file descriptor for the device or + * filesystem "dev". A negative return value indicates an error, otherwise the + * return value is the index of the file descriptor within the file descriptor + * pool. + */ + +extern int alt_get_fd (alt_dev* dev); + +/* + * alt_release_fd() is called to free the file descriptor with index "fd". + */ + +extern void alt_release_fd (int fd); + +/* + * alt_fd_lock() is called by ioctl() to mark the file descriptor "fd" as + * being open for exclusive access. Subsequent calls to open() for the device + * associated with "fd" will fail. A device is unlocked by either calling + * close() for "fd", or by an alternate call to ioctl() (see ioctl.c for + * details). + */ + +extern int alt_fd_lock (alt_fd* fd); + +/* + * alt_fd_unlock() is called by ioctl() to unlock a descriptor previously + * locked by a call to alt_fd_lock(). + */ + +extern int alt_fd_unlock (alt_fd* fd); + +/* + * "alt_fd_list" is the pool of file descriptors. + */ + +extern alt_fd alt_fd_list[]; + +/* + * flags used by alt_fd. + * + * ALT_FD_EXCL is used to mark a file descriptor as locked for exclusive + * access, i.e. further calls to open() for the associated device should + * fail. + * + * ALT_FD_DEV marks a dile descriptor as belonging to a device as oposed to a + * filesystem. + */ + +#define ALT_FD_EXCL 0x80000000 +#define ALT_FD_DEV 0x40000000 + +#define ALT_FD_FLAGS_MASK (ALT_FD_EXCL | ALT_FD_DEV) + +/* + * "alt_dev_list" is the head of the linked list of registered devices. + */ + +extern alt_llist alt_dev_list; + +/* + * "alt_fs_list" is the head of the linked list of registered filesystems. + */ + +extern alt_llist alt_fs_list; + +/* + * "alt_fd_list_lock" is a semaphore used to ensure that access to the pool + * of file descriptors is thread safe. + */ + +ALT_EXTERN_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is a 'high water mark'. It indicates the highest file + * descriptor allocated. Use of this can save searching the entire pool + * for active file descriptors, which helps avoid contention on access + * to the file descriptor pool. + */ + +extern alt_32 alt_max_fd; + +/* + * alt_io_redirect() is called at startup to redirect stdout, stdin, and + * stderr to the devices named in the input arguments. By default these streams + * are directed at /dev/null, and are then redirected using this function once + * all of the devices have been registered within the system. + */ + +extern void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FILE_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_iic_isr_register.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_iic_isr_register.h index a0cb01c..6c53c86 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_iic_isr_register.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_iic_isr_register.h @@ -1,39 +1,39 @@ -#ifndef __ALT_IIC_ISR_REGISTER_H_ -#define __ALT_IIC_ISR_REGISTER_H_ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ -#include "alt_types.h" -#include "sys/alt_irq.h" - -extern int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, - void *isr_context, void *flags); - -#endif /* __ALT_IIC_ISR_REGISTER_H_ */ +#ifndef __ALT_IIC_ISR_REGISTER_H_ +#define __ALT_IIC_ISR_REGISTER_H_ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "sys/alt_irq.h" + +extern int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags); + +#endif /* __ALT_IIC_ISR_REGISTER_H_ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_irq_table.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_irq_table.h index 694ef06..5b4a787 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_irq_table.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_irq_table.h @@ -1,59 +1,59 @@ -#ifndef __ALT_IRQ_TABLE_H__ -#define __ALT_IRQ_TABLE_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/* - * Definition of a table describing each interrupt handler. The index into - * the array is the interrupt id associated with the handler. - * - * When an interrupt occurs, the associated handler is called with - * the argument stored in the context member. - * - * The table is physically created in alt_irq_handler.c - */ -extern struct ALT_IRQ_HANDLER -{ -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - void (*handler)(void*); -#else - void (*handler)(void*, alt_u32); -#endif - void *context; -} alt_irq[ALT_NIRQ]; - -#endif +#ifndef __ALT_IRQ_TABLE_H__ +#define __ALT_IRQ_TABLE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definition of a table describing each interrupt handler. The index into + * the array is the interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + * + * The table is physically created in alt_irq_handler.c + */ +extern struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +#endif diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_legacy_irq.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_legacy_irq.h index c7aec02..0e19af2 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_legacy_irq.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_legacy_irq.h @@ -1,158 +1,158 @@ -#ifndef __ALT_LEGACY_IRQ_H__ -#define __ALT_LEGACY_IRQ_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * This file provides prototypes and inline implementations of certain routines - * used by the legacy interrupt API. Do not include this in your driver or - * application source files, use "sys/alt_irq.h" instead to access the proper - * public API. - */ - -#include -#include "system.h" - -#ifndef NIOS2_EIC_PRESENT - -#include "nios2.h" -#include "alt_types.h" - -#include "sys/alt_irq.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * alt_irq_register() can be used to register an interrupt handler. If the - * function is succesful, then the requested interrupt will be enabled upon - * return. - */ -extern int alt_irq_register (alt_u32 id, - void* context, - alt_isr_func handler); - -/* - * alt_irq_disable() disables the individual interrupt indicated by "id". - */ -static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) -{ - alt_irq_context status; - extern volatile alt_u32 alt_irq_active; - - status = alt_irq_disable_all (); - - alt_irq_active &= ~(1 << id); - NIOS2_WRITE_IENABLE (alt_irq_active); - - alt_irq_enable_all(status); - - return 0; -} - -/* - * alt_irq_enable() enables the individual interrupt indicated by "id". - */ -static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) -{ - alt_irq_context status; - extern volatile alt_u32 alt_irq_active; - - status = alt_irq_disable_all (); - - alt_irq_active |= (1 << id); - NIOS2_WRITE_IENABLE (alt_irq_active); - - alt_irq_enable_all(status); - - return 0; -} - -#ifndef ALT_EXCEPTION_STACK -/* - * alt_irq_initerruptable() should only be called from within an ISR. It is used - * to allow higer priority interrupts to interrupt the current ISR. The input - * argument, "priority", is the priority, i.e. interrupt number of the current - * interrupt. - * - * If this function is called, then the ISR is required to make a call to - * alt_irq_non_interruptible() before returning. The input argument to - * alt_irq_non_interruptible() is the return value from alt_irq_interruptible(). - * - * Care should be taken when using this pair of functions, since they increasing - * the system overhead associated with interrupt handling. - * - * If you are using an exception stack then nested interrupts won't work, so - * these functions are not available in that case. - */ -static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_interruptible (alt_u32 priority) -{ - extern volatile alt_u32 alt_priority_mask; - extern volatile alt_u32 alt_irq_active; - - alt_u32 old_priority; - - old_priority = alt_priority_mask; - alt_priority_mask = (1 << priority) - 1; - - NIOS2_WRITE_IENABLE (alt_irq_active & alt_priority_mask); - - NIOS2_WRITE_STATUS (1); - - return old_priority; -} - -/* - * See Comments above for alt_irq_interruptible() for an explanation of the use of this - * function. - */ -static ALT_INLINE void ALT_ALWAYS_INLINE alt_irq_non_interruptible (alt_u32 mask) -{ - extern volatile alt_u32 alt_priority_mask; - extern volatile alt_u32 alt_irq_active; - - NIOS2_WRITE_STATUS (0); - - alt_priority_mask = mask; - - NIOS2_WRITE_IENABLE (mask & alt_irq_active); -} -#endif /* ALT_EXCEPTION_STACK */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* NIOS2_EIC_PRESENT */ - -#endif /* __ALT_LEGACY_IRQ_H__ */ +#ifndef __ALT_LEGACY_IRQ_H__ +#define __ALT_LEGACY_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides prototypes and inline implementations of certain routines + * used by the legacy interrupt API. Do not include this in your driver or + * application source files, use "sys/alt_irq.h" instead to access the proper + * public API. + */ + +#include +#include "system.h" + +#ifndef NIOS2_EIC_PRESENT + +#include "nios2.h" +#include "alt_types.h" + +#include "sys/alt_irq.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_irq_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler); + +/* + * alt_irq_disable() disables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active &= ~(1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +/* + * alt_irq_enable() enables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active |= (1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +#ifndef ALT_EXCEPTION_STACK +/* + * alt_irq_initerruptable() should only be called from within an ISR. It is used + * to allow higer priority interrupts to interrupt the current ISR. The input + * argument, "priority", is the priority, i.e. interrupt number of the current + * interrupt. + * + * If this function is called, then the ISR is required to make a call to + * alt_irq_non_interruptible() before returning. The input argument to + * alt_irq_non_interruptible() is the return value from alt_irq_interruptible(). + * + * Care should be taken when using this pair of functions, since they increasing + * the system overhead associated with interrupt handling. + * + * If you are using an exception stack then nested interrupts won't work, so + * these functions are not available in that case. + */ +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_interruptible (alt_u32 priority) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + alt_u32 old_priority; + + old_priority = alt_priority_mask; + alt_priority_mask = (1 << priority) - 1; + + NIOS2_WRITE_IENABLE (alt_irq_active & alt_priority_mask); + + NIOS2_WRITE_STATUS (1); + + return old_priority; +} + +/* + * See Comments above for alt_irq_interruptible() for an explanation of the use of this + * function. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE alt_irq_non_interruptible (alt_u32 mask) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + NIOS2_WRITE_STATUS (0); + + alt_priority_mask = mask; + + NIOS2_WRITE_IENABLE (mask & alt_irq_active); +} +#endif /* ALT_EXCEPTION_STACK */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* NIOS2_EIC_PRESENT */ + +#endif /* __ALT_LEGACY_IRQ_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_no_error.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_no_error.h index 6143fc9..06a036c 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_no_error.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/alt_no_error.h @@ -1,77 +1,77 @@ -#ifndef __ALT_NO_ERROR_H__ -#define __ALT_NO_ERROR_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "alt_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * alt_no_error() is a dummy function used by alt_sem.h and alt_flag.h. It - * substitutes for functions that have a return code by creating a function - * that always returns zero. - * - * This may seem a little obscure, but what happens is that the compiler can - * then optomise away the call to this function, and any code written which - * handles the error path (i.e. non zero return values). - * - * This allows code to be written which correctly use the uC/OS-II semaphore - * and flag utilities, without the use of those utilities impacting on - * excutables built for a single threaded HAL environment. - * - * This function is considered to be part of the internal implementation of - * the HAL, and should not be called directly by application code or device - * drivers. It is not guaranteed to be preserved in future versions of the - * HAL. - */ - -static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void) -{ - return 0; -} - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_NO_ERROR_H__ */ +#ifndef __ALT_NO_ERROR_H__ +#define __ALT_NO_ERROR_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_no_error() is a dummy function used by alt_sem.h and alt_flag.h. It + * substitutes for functions that have a return code by creating a function + * that always returns zero. + * + * This may seem a little obscure, but what happens is that the compiler can + * then optomise away the call to this function, and any code written which + * handles the error path (i.e. non zero return values). + * + * This allows code to be written which correctly use the uC/OS-II semaphore + * and flag utilities, without the use of those utilities impacting on + * excutables built for a single threaded HAL environment. + * + * This function is considered to be part of the internal implementation of + * the HAL, and should not be called directly by application code or device + * drivers. It is not guaranteed to be preserved in future versions of the + * HAL. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void) +{ + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_NO_ERROR_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/nios2_gmon_data.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/nios2_gmon_data.h index 3f43f12..4bc058d 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/nios2_gmon_data.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/priv/nios2_gmon_data.h @@ -1,47 +1,47 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ -#ifndef NIOS2_GMON_DATA_H -#define NIOS2_GMON_DATA_H - -#define GMON_DATA_SIG 0 -#define GMON_DATA_WORDS 1 -#define GMON_DATA_PROFILE_DATA 2 -#define GMON_DATA_PROFILE_LOWPC 3 -#define GMON_DATA_PROFILE_HIGHPC 4 -#define GMON_DATA_PROFILE_BUCKET 5 -#define GMON_DATA_PROFILE_RATE 6 -#define GMON_DATA_MCOUNT_START 7 -#define GMON_DATA_MCOUNT_LIMIT 8 - -#define GMON_DATA_SIZE 9 - -extern unsigned int alt_gmon_data[GMON_DATA_SIZE]; - -#endif +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#ifndef NIOS2_GMON_DATA_H +#define NIOS2_GMON_DATA_H + +#define GMON_DATA_SIG 0 +#define GMON_DATA_WORDS 1 +#define GMON_DATA_PROFILE_DATA 2 +#define GMON_DATA_PROFILE_LOWPC 3 +#define GMON_DATA_PROFILE_HIGHPC 4 +#define GMON_DATA_PROFILE_BUCKET 5 +#define GMON_DATA_PROFILE_RATE 6 +#define GMON_DATA_MCOUNT_START 7 +#define GMON_DATA_MCOUNT_LIMIT 8 + +#define GMON_DATA_SIZE 9 + +extern unsigned int alt_gmon_data[GMON_DATA_SIZE]; + +#endif diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_alarm.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_alarm.h index 68a2f5d..9093080 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_alarm.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_alarm.h @@ -1,126 +1,126 @@ -#ifndef __ALT_ALARM_H__ -#define __ALT_ALARM_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "alt_llist.h" -#include "alt_types.h" - -#include "priv/alt_alarm.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * "alt_alarm" is a structure type used by applications to register an alarm - * callback function. An instance of this type must be passed as an input - * argument to alt_alarm_start(). The user is not responsible for initialising - * the contents of the instance. This is done by alt_alarm_start(). - */ - -typedef struct alt_alarm_s alt_alarm; - -/* - * alt_alarm_start() can be called by an application/driver in order to register - * a function for periodic callback at the system clock frequency. Be aware that - * this callback is likely to occur in interrupt context. - */ - -extern int alt_alarm_start (alt_alarm* the_alarm, - alt_u32 nticks, - alt_u32 (*callback) (void* context), - void* context); - -/* - * alt_alarm_stop() is used to unregister a callback. Alternatively the callback - * can return zero to unregister. - */ - -extern void alt_alarm_stop (alt_alarm* the_alarm); - -/* - * Obtain the system clock rate in ticks/s. - */ - -static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) -{ - return _alt_tick_rate; -} - -/* - * alt_sysclk_init() is intended to be only used by the system clock driver - * in order to initialise the value of the clock frequency. - */ - -static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) -{ - if (! _alt_tick_rate) - { - _alt_tick_rate = nticks; - return 0; - } - else - { - return -1; - } -} - -/* - * alt_nticks() returns the elapsed number of system clock ticks since reset. - */ - -static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) -{ - return _alt_nticks; -} - -/* - * alt_tick() should only be called by the system clock driver. This is used - * to notify the system that the system timer period has expired. - */ - -extern void alt_tick (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_ALARM_H__ */ +#ifndef __ALT_ALARM_H__ +#define __ALT_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_llist.h" +#include "alt_types.h" + +#include "priv/alt_alarm.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm" is a structure type used by applications to register an alarm + * callback function. An instance of this type must be passed as an input + * argument to alt_alarm_start(). The user is not responsible for initialising + * the contents of the instance. This is done by alt_alarm_start(). + */ + +typedef struct alt_alarm_s alt_alarm; + +/* + * alt_alarm_start() can be called by an application/driver in order to register + * a function for periodic callback at the system clock frequency. Be aware that + * this callback is likely to occur in interrupt context. + */ + +extern int alt_alarm_start (alt_alarm* the_alarm, + alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context); + +/* + * alt_alarm_stop() is used to unregister a callback. Alternatively the callback + * can return zero to unregister. + */ + +extern void alt_alarm_stop (alt_alarm* the_alarm); + +/* + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; +} + +/* + * alt_sysclk_init() is intended to be only used by the system clock driver + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + { + _alt_tick_rate = nticks; + return 0; + } + else + { + return -1; + } +} + +/* + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; +} + +/* + * alt_tick() should only be called by the system clock driver. This is used + * to notify the system that the system timer period has expired. + */ + +extern void alt_tick (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_ALARM_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_cache.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_cache.h index c4d8db9..44d976c 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_cache.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_cache.h @@ -1,117 +1,117 @@ -#ifndef __ALT_CACHE_H__ -#define __ALT_CACHE_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003, 2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include - -#include "alt_types.h" - -/* - * alt_cache.h defines the processor specific functions for manipulating the - * cache. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * alt_icache_flush() is called to flush the instruction cache for a memory - * region of length "len" bytes, starting at address "start". - */ - -extern void alt_icache_flush (void* start, alt_u32 len); - -/* - * alt_dcache_flush() is called to flush the data cache for a memory - * region of length "len" bytes, starting at address "start". - * Any dirty lines in the data cache are written back to memory. - */ - -extern void alt_dcache_flush (void* start, alt_u32 len); - -/* - * alt_dcache_flush() is called to flush the data cache for a memory - * region of length "len" bytes, starting at address "start". - * Any dirty lines in the data cache are NOT written back to memory. - */ - -extern void alt_dcache_flush_no_writeback (void* start, alt_u32 len); - -/* - * Flush the entire instruction cache. - */ - -extern void alt_icache_flush_all (void); - -/* - * Flush the entire data cache. - */ - -extern void alt_dcache_flush_all (void); - -/* - * Allocate a block of uncached memory. - */ - -extern volatile void* alt_uncached_malloc (size_t size); - -/* - * Free a block of uncached memory. - */ - -extern void alt_uncached_free (volatile void* ptr); - -/* - * Convert a pointer to a block of cached memory, into a block of - * uncached memory. - */ - -extern volatile void* alt_remap_uncached (void* ptr, alt_u32 len); - -/* - * Convert a pointer to a block of uncached memory, into a block of - * cached memory. - */ - -extern void* alt_remap_cached (volatile void* ptr, alt_u32 len); - -/* - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_CACHE_H__ */ +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003, 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "alt_types.h" + +/* + * alt_cache.h defines the processor specific functions for manipulating the + * cache. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +extern void alt_icache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are written back to memory. + */ + +extern void alt_dcache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are NOT written back to memory. + */ + +extern void alt_dcache_flush_no_writeback (void* start, alt_u32 len); + +/* + * Flush the entire instruction cache. + */ + +extern void alt_icache_flush_all (void); + +/* + * Flush the entire data cache. + */ + +extern void alt_dcache_flush_all (void); + +/* + * Allocate a block of uncached memory. + */ + +extern volatile void* alt_uncached_malloc (size_t size); + +/* + * Free a block of uncached memory. + */ + +extern void alt_uncached_free (volatile void* ptr); + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +extern volatile void* alt_remap_uncached (void* ptr, alt_u32 len); + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +extern void* alt_remap_cached (volatile void* ptr, alt_u32 len); + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_debug.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_debug.h index d9f9599..af509d8 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_debug.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_debug.h @@ -1,45 +1,45 @@ -#ifndef __ALT_DEBUG_H__ -#define __ALT_DEBUG_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * The ALT_DEVUG_ASSERT macro can be used to generate a debugger break - * from within software. The break is generated if "condition" evaluates to - * false. - */ - -#define ALT_DEBUG_ASSERT(condition) if (!condition) \ -{ \ - __asm__ volatile ("break"); \ -} - -#endif /* __ALT_DEBUG_H__ */ +#ifndef __ALT_DEBUG_H__ +#define __ALT_DEBUG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The ALT_DEVUG_ASSERT macro can be used to generate a debugger break + * from within software. The break is generated if "condition" evaluates to + * false. + */ + +#define ALT_DEBUG_ASSERT(condition) if (!condition) \ +{ \ + __asm__ volatile ("break"); \ +} + +#endif /* __ALT_DEBUG_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dev.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dev.h index 66c5e41..d96327e 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dev.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dev.h @@ -1,115 +1,115 @@ -#ifndef __ALT_DEV_H__ -#define __ALT_DEV_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "system.h" -#include "sys/alt_llist.h" -#include "priv/alt_dev_llist.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The value ALT_IRQ_NOT_CONNECTED is used to represent an unconnected - * interrupt line. It cannot evaluate to a valid interrupt number. - */ - -#define ALT_IRQ_NOT_CONNECTED (-1) - -typedef struct alt_dev_s alt_dev; - -struct stat; - -/* - * The file descriptor structure definition. - */ - -typedef struct alt_fd_s -{ - alt_dev* dev; - alt_u8* priv; - int fd_flags; -} alt_fd; - -/* - * The device structure definition. - */ - -struct alt_dev_s { - alt_llist llist; /* for internal use */ - const char* name; - int (*open) (alt_fd* fd, const char* name, int flags, int mode); - int (*close) (alt_fd* fd); - int (*read) (alt_fd* fd, char* ptr, int len); - int (*write) (alt_fd* fd, const char* ptr, int len); - int (*lseek) (alt_fd* fd, int ptr, int dir); - int (*fstat) (alt_fd* fd, struct stat* buf); - int (*ioctl) (alt_fd* fd, int req, void* arg); -}; - -/* - * Functions used to register device for access through the C standard - * library. - * - * The only difference between alt_dev_reg() and alt_fs_reg() is the - * interpretation that open() places on the device name. In the case of - * alt_dev_reg the device is assumed to be a particular character device, - * and so there must be an exact match in the name for open to succeed. - * In the case of alt_fs_reg() the name of the device is treated as the - * mount point for a directory, and so any call to open() where the name - * is the root of the device filename will succeed. - */ - -extern int alt_fs_reg (alt_dev* dev); - -static ALT_INLINE int alt_dev_reg (alt_dev* dev) -{ - extern alt_llist alt_dev_list; - - return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); -} - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_DEV_H__ */ +#ifndef __ALT_DEV_H__ +#define __ALT_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "system.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The value ALT_IRQ_NOT_CONNECTED is used to represent an unconnected + * interrupt line. It cannot evaluate to a valid interrupt number. + */ + +#define ALT_IRQ_NOT_CONNECTED (-1) + +typedef struct alt_dev_s alt_dev; + +struct stat; + +/* + * The file descriptor structure definition. + */ + +typedef struct alt_fd_s +{ + alt_dev* dev; + alt_u8* priv; + int fd_flags; +} alt_fd; + +/* + * The device structure definition. + */ + +struct alt_dev_s { + alt_llist llist; /* for internal use */ + const char* name; + int (*open) (alt_fd* fd, const char* name, int flags, int mode); + int (*close) (alt_fd* fd); + int (*read) (alt_fd* fd, char* ptr, int len); + int (*write) (alt_fd* fd, const char* ptr, int len); + int (*lseek) (alt_fd* fd, int ptr, int dir); + int (*fstat) (alt_fd* fd, struct stat* buf); + int (*ioctl) (alt_fd* fd, int req, void* arg); +}; + +/* + * Functions used to register device for access through the C standard + * library. + * + * The only difference between alt_dev_reg() and alt_fs_reg() is the + * interpretation that open() places on the device name. In the case of + * alt_dev_reg the device is assumed to be a particular character device, + * and so there must be an exact match in the name for open to succeed. + * In the case of alt_fs_reg() the name of the device is treated as the + * mount point for a directory, and so any call to open() where the name + * is the root of the device filename will succeed. + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dma.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dma.h index 9f9b2ff..88dcda0 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dma.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dma.h @@ -1,226 +1,226 @@ -#ifndef __ALT_DMA_H__ -#define __ALT_DMA_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "sys/alt_dma_dev.h" -#include "alt_types.h" - -#include - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * This header contains the application side interface for accessing DMA - * resources. See alt_dma_dev.h for the dma device driver interface. - * - * The interface model treats a DMA transaction as being composed of two - * halves (read and write). - * - * The application can supply data for transmit using an "alt_dma_txchan" - * descriptor. Alternatively an "alt_dma_rxchan" descriptor can be used to - * receive data. - */ - -/* - * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for - * a DMA transmit device. The name is the name of the associated physical - * device (e.g. "/dev/dma_0"). - * - * The return value will be NULL on failure, and non-NULL otherwise. - */ - -extern alt_dma_txchan alt_dma_txchan_open (const char* name); - -/* - * alt_dma_txchan_close() is provided so that an application can notify the - * system that it has finished with a given DMA transmit channel. This is only - * provided for completness. - */ - -static ALT_INLINE int alt_dma_txchan_close (alt_dma_txchan dma) -{ - return 0; -} - -/* - * alt_dma_txchan_send() posts a transmit request to a DMA transmit channel. - * The input arguments are: - * - * dma: the channel to use. - * from: a pointer to the start of the data to send. - * length: the length of the data to send in bytes. - * done: callback function that will be called once the data has been sent. - * handle: opaque value passed to "done". - * - * The return value will be negative if the request cannot be posted, and - * zero otherwise. - */ - -static ALT_INLINE int alt_dma_txchan_send (alt_dma_txchan dma, - const void* from, - alt_u32 length, - alt_txchan_done* done, - void* handle) -{ - return dma ? dma->dma_send (dma, - from, - length, - done, - handle) : -ENODEV; -} - -/* - * alt_dma_txchan_space() returns the number of tranmit requests that can be - * posted to the specified DMA transmit channel. - * - * A negative value indicates that the value could not be determined. - */ - -static ALT_INLINE int alt_dma_txchan_space (alt_dma_txchan dma) -{ - return dma ? dma->space (dma) : -ENODEV; -} - -/* - * alt_dma_txchan_ioctl() can be used to perform device specific I/O - * operations on the indicated DMA transmit channel. For example some drivers - * support options to control the width of the transfer operations. See - * alt_dma_dev.h for the list of generic requests. - * - * A negative return value indicates failure, otherwise the interpretation - * of the return value is request specific. - */ - -static ALT_INLINE int alt_dma_txchan_ioctl (alt_dma_txchan dma, - int req, - void* arg) -{ - return dma ? dma->ioctl (dma, req, arg) : -ENODEV; -} - -/* - * alt_dma_rxchan_open() is used to obtain an "alt_dma_rxchan" descriptor for - * a DMA receive channel. The name is the name of the associated physical - * device (e.g. "/dev/dma_0"). - * - * The return value will be NULL on failure, and non-NULL otherwise. - */ - -extern alt_dma_rxchan alt_dma_rxchan_open (const char* dev); - -/* - * alt_dma_rxchan_close() is provided so that an application can notify the - * system that it has finished with a given DMA receive channel. This is only - * provided for completness. - */ - -static ALT_INLINE int alt_dma_rxchan_close (alt_dma_rxchan dma) -{ - return 0; -} - -/* - * - */ - -/* - * alt_dma_rxchan_prepare() posts a receive request to a DMA receive channel. - * - * The input arguments are: - * - * dma: the channel to use. - * data: a pointer to the location that data is to be received to. - * len: the maximum length of the data to receive. - * done: callback function that will be called once the data has been - * received. - * handle: opaque value passed to "done". - * - * The return value will be negative if the request cannot be posted, and - * zero otherwise. - */ - -static ALT_INLINE int alt_dma_rxchan_prepare (alt_dma_rxchan dma, - void* data, - alt_u32 len, - alt_rxchan_done* done, - void* handle) -{ - return dma ? dma->prepare (dma, data, len, done, handle) : -ENODEV; -} - -/* - * alt_dma_rxchan_ioctl() can be used to perform device specific I/O - * operations on the indicated DMA receive channel. For example some drivers - * support options to control the width of the transfer operations. See - * alt_dma_dev.h for the list of generic requests. - * - * A negative return value indicates failure, otherwise the interpretation - * of the return value is request specific. - */ - -static ALT_INLINE int alt_dma_rxchan_ioctl (alt_dma_rxchan dma, - int req, - void* arg) -{ - return dma ? dma->ioctl (dma, req, arg) : -ENODEV; -} - -/* - * alt_dma_rxchan_depth() returns the depth of the receive FIFO used to store - * receive requests. - */ - -static ALT_INLINE alt_u32 alt_dma_rxchan_depth(alt_dma_rxchan dma) -{ - return dma->depth; -} - -/* - * - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_DMA_H__ */ +#ifndef __ALT_DMA_H__ +#define __ALT_DMA_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dma_dev.h" +#include "alt_types.h" + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the application side interface for accessing DMA + * resources. See alt_dma_dev.h for the dma device driver interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * The application can supply data for transmit using an "alt_dma_txchan" + * descriptor. Alternatively an "alt_dma_rxchan" descriptor can be used to + * receive data. + */ + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_txchan alt_dma_txchan_open (const char* name); + +/* + * alt_dma_txchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA transmit channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_txchan_close (alt_dma_txchan dma) +{ + return 0; +} + +/* + * alt_dma_txchan_send() posts a transmit request to a DMA transmit channel. + * The input arguments are: + * + * dma: the channel to use. + * from: a pointer to the start of the data to send. + * length: the length of the data to send in bytes. + * done: callback function that will be called once the data has been sent. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_txchan_send (alt_dma_txchan dma, + const void* from, + alt_u32 length, + alt_txchan_done* done, + void* handle) +{ + return dma ? dma->dma_send (dma, + from, + length, + done, + handle) : -ENODEV; +} + +/* + * alt_dma_txchan_space() returns the number of tranmit requests that can be + * posted to the specified DMA transmit channel. + * + * A negative value indicates that the value could not be determined. + */ + +static ALT_INLINE int alt_dma_txchan_space (alt_dma_txchan dma) +{ + return dma ? dma->space (dma) : -ENODEV; +} + +/* + * alt_dma_txchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA transmit channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_txchan_ioctl (alt_dma_txchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_open() is used to obtain an "alt_dma_rxchan" descriptor for + * a DMA receive channel. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_rxchan alt_dma_rxchan_open (const char* dev); + +/* + * alt_dma_rxchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA receive channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_rxchan_close (alt_dma_rxchan dma) +{ + return 0; +} + +/* + * + */ + +/* + * alt_dma_rxchan_prepare() posts a receive request to a DMA receive channel. + * + * The input arguments are: + * + * dma: the channel to use. + * data: a pointer to the location that data is to be received to. + * len: the maximum length of the data to receive. + * done: callback function that will be called once the data has been + * received. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_rxchan_prepare (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle) +{ + return dma ? dma->prepare (dma, data, len, done, handle) : -ENODEV; +} + +/* + * alt_dma_rxchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA receive channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_rxchan_ioctl (alt_dma_rxchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_depth() returns the depth of the receive FIFO used to store + * receive requests. + */ + +static ALT_INLINE alt_u32 alt_dma_rxchan_depth(alt_dma_rxchan dma) +{ + return dma->depth; +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dma_dev.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dma_dev.h index 832463d..65063bd 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dma_dev.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_dma_dev.h @@ -1,200 +1,200 @@ -#ifndef __ALT_DMA_DEV_H__ -#define __ALT_DMA_DEV_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "priv/alt_dev_llist.h" - -#include "alt_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * This header contains the device driver interface for accessing DMA - * resources. See alt_dma.h for the DMA application side interface. - * - * The interface model treats a DMA transaction as being composed of two - * halves (read and write). - * - * An "alt_dma_txchan_dev" is used to describe the device associated with a - * DMA transmit channel. An "alt_dma_rxchan_dev" is used to describe the - * device associated with a DMA receive channel. - */ - -/* - * List of generic ioctl requests that may be supported by a DMA device. - * - * ALT_DMA_RX_ONLY_ON: This causes a DMA channel to operate in a mode - * where only the receiver is under software control. - * The other side reads continously from a single - * location. The address to read is the argument to - * this request. - * ALT_DMA_RX_ONLY_OFF: Return to the default mode where both the receive - * and transmit sides of the DMA can be under software - * control. - * ALT_DMA_TX_ONLY_ON: This causes a DMA channel to operate in a mode - * where only the transmitter is under software control. - * The other side writes continously to a single - * location. The address to write to is the argument to - * this request. - * ALT_DMA_TX_ONLY_OFF: Return to the default mode where both the receive - * and transmit sides of the DMA can be under software - * control. - * ALT_DMA_SET_MODE_8: Transfer data in units of 8 bits. - * ALT_DMA_SET_MODE_16: Transfer data in units of 16 bits. - * ALT_DMA_SET_MODE_32: Transfer data in units of 32 bits. - * ALT_DMA_SET_MODE_64: Transfer data in units of 64 bits. - * ALT_DMA_SET_MODE_128: Transfer data in units of 128 bits. - * ALT_DMA_GET_MODE: Get the current transfer mode. - * - * The use of the macros: ALT_DMA_TX_STREAM_ON, ALT_DMA_TX_STREAM_OFF - * ALT_DMA_RX_STREAM_OFF and ALT_DMA_RX_STREAM_ON are depreciated. You should - * instead use the macros: ALT_DMA_RX_ONLY_ON, ALT_DMA_RX_ONLY_OFF, - * ALT_DMA_TX_ONLY_ON and ALT_DMA_TX_ONLY_OFF. - */ - -#define ALT_DMA_TX_STREAM_ON (0x1) -#define ALT_DMA_TX_STREAM_OFF (0x2) -#define ALT_DMA_RX_STREAM_ON (0x3) -#define ALT_DMA_RX_STREAM_OFF (0x4) -#define ALT_DMA_SET_MODE_8 (0x5) -#define ALT_DMA_SET_MODE_16 (0x6) -#define ALT_DMA_SET_MODE_32 (0x7) -#define ALT_DMA_SET_MODE_64 (0x8) -#define ALT_DMA_SET_MODE_128 (0x9) -#define ALT_DMA_GET_MODE (0xa) - -#define ALT_DMA_RX_ONLY_ON ALT_DMA_TX_STREAM_ON -#define ALT_DMA_RX_ONLY_OFF ALT_DMA_TX_STREAM_OFF -#define ALT_DMA_TX_ONLY_ON ALT_DMA_RX_STREAM_ON -#define ALT_DMA_TX_ONLY_OFF ALT_DMA_RX_STREAM_OFF - -/* - * - */ - -typedef struct alt_dma_txchan_dev_s alt_dma_txchan_dev; -typedef struct alt_dma_rxchan_dev_s alt_dma_rxchan_dev; - -typedef alt_dma_txchan_dev* alt_dma_txchan; -typedef alt_dma_rxchan_dev* alt_dma_rxchan; - -typedef void (alt_txchan_done)(void* handle); -typedef void (alt_rxchan_done)(void* handle, void* data); - -/* - * devices that provide a DMA transmit channel are required to provide an - * instance of the "alt_dma_txchan_dev" structure. - */ - -struct alt_dma_txchan_dev_s { - alt_llist llist; /* for internal use */ - const char* name; /* name of the device instance - * (e.g. "/dev/dma_0"). - */ - int (*space) (alt_dma_txchan dma); /* returns the maximum number of - * transmit requests that can be posted - */ - int (*dma_send) (alt_dma_txchan dma, - const void* from, - alt_u32 len, - alt_txchan_done* done, - void* handle); /* post a transmit request */ - int (*ioctl) (alt_dma_txchan dma, int req, void* arg); /* perform device - * specific I/O control. - */ -}; - -/* - * devices that provide a DMA receive channel are required to provide an - * instance of the "alt_dma_rxchan_dev" structure. - */ - -struct alt_dma_rxchan_dev_s { - alt_llist list; /* for internal use */ - const char* name; /* name of the device instance - * (e.g. "/dev/dma_0"). - */ - alt_u32 depth; /* maximum number of receive requests that - * can be posted. - */ - int (*prepare) (alt_dma_rxchan dma, - void* data, - alt_u32 len, - alt_rxchan_done* done, - void* handle); /* post a receive request */ - int (*ioctl) (alt_dma_rxchan dma, int req, void* arg); /* perform device - * specific I/O control. - */ -}; - -/* - * Register a DMA transmit channel with the system. - */ - -static ALT_INLINE int alt_dma_txchan_reg (alt_dma_txchan_dev* dev) -{ - extern alt_llist alt_dma_txchan_list; - - return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_txchan_list); -} - -/* - * Register a DMA receive channel with the system. - */ - -static ALT_INLINE int alt_dma_rxchan_reg (alt_dma_rxchan_dev* dev) -{ - extern alt_llist alt_dma_rxchan_list; - - return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_rxchan_list); -} - -/* - * - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_DMA_DEV_H__ */ +#ifndef __ALT_DMA_DEV_H__ +#define __ALT_DMA_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the device driver interface for accessing DMA + * resources. See alt_dma.h for the DMA application side interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * An "alt_dma_txchan_dev" is used to describe the device associated with a + * DMA transmit channel. An "alt_dma_rxchan_dev" is used to describe the + * device associated with a DMA receive channel. + */ + +/* + * List of generic ioctl requests that may be supported by a DMA device. + * + * ALT_DMA_RX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the receiver is under software control. + * The other side reads continously from a single + * location. The address to read is the argument to + * this request. + * ALT_DMA_RX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_TX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the transmitter is under software control. + * The other side writes continously to a single + * location. The address to write to is the argument to + * this request. + * ALT_DMA_TX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_SET_MODE_8: Transfer data in units of 8 bits. + * ALT_DMA_SET_MODE_16: Transfer data in units of 16 bits. + * ALT_DMA_SET_MODE_32: Transfer data in units of 32 bits. + * ALT_DMA_SET_MODE_64: Transfer data in units of 64 bits. + * ALT_DMA_SET_MODE_128: Transfer data in units of 128 bits. + * ALT_DMA_GET_MODE: Get the current transfer mode. + * + * The use of the macros: ALT_DMA_TX_STREAM_ON, ALT_DMA_TX_STREAM_OFF + * ALT_DMA_RX_STREAM_OFF and ALT_DMA_RX_STREAM_ON are depreciated. You should + * instead use the macros: ALT_DMA_RX_ONLY_ON, ALT_DMA_RX_ONLY_OFF, + * ALT_DMA_TX_ONLY_ON and ALT_DMA_TX_ONLY_OFF. + */ + +#define ALT_DMA_TX_STREAM_ON (0x1) +#define ALT_DMA_TX_STREAM_OFF (0x2) +#define ALT_DMA_RX_STREAM_ON (0x3) +#define ALT_DMA_RX_STREAM_OFF (0x4) +#define ALT_DMA_SET_MODE_8 (0x5) +#define ALT_DMA_SET_MODE_16 (0x6) +#define ALT_DMA_SET_MODE_32 (0x7) +#define ALT_DMA_SET_MODE_64 (0x8) +#define ALT_DMA_SET_MODE_128 (0x9) +#define ALT_DMA_GET_MODE (0xa) + +#define ALT_DMA_RX_ONLY_ON ALT_DMA_TX_STREAM_ON +#define ALT_DMA_RX_ONLY_OFF ALT_DMA_TX_STREAM_OFF +#define ALT_DMA_TX_ONLY_ON ALT_DMA_RX_STREAM_ON +#define ALT_DMA_TX_ONLY_OFF ALT_DMA_RX_STREAM_OFF + +/* + * + */ + +typedef struct alt_dma_txchan_dev_s alt_dma_txchan_dev; +typedef struct alt_dma_rxchan_dev_s alt_dma_rxchan_dev; + +typedef alt_dma_txchan_dev* alt_dma_txchan; +typedef alt_dma_rxchan_dev* alt_dma_rxchan; + +typedef void (alt_txchan_done)(void* handle); +typedef void (alt_rxchan_done)(void* handle, void* data); + +/* + * devices that provide a DMA transmit channel are required to provide an + * instance of the "alt_dma_txchan_dev" structure. + */ + +struct alt_dma_txchan_dev_s { + alt_llist llist; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + int (*space) (alt_dma_txchan dma); /* returns the maximum number of + * transmit requests that can be posted + */ + int (*dma_send) (alt_dma_txchan dma, + const void* from, + alt_u32 len, + alt_txchan_done* done, + void* handle); /* post a transmit request */ + int (*ioctl) (alt_dma_txchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * devices that provide a DMA receive channel are required to provide an + * instance of the "alt_dma_rxchan_dev" structure. + */ + +struct alt_dma_rxchan_dev_s { + alt_llist list; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + alt_u32 depth; /* maximum number of receive requests that + * can be posted. + */ + int (*prepare) (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle); /* post a receive request */ + int (*ioctl) (alt_dma_rxchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * Register a DMA transmit channel with the system. + */ + +static ALT_INLINE int alt_dma_txchan_reg (alt_dma_txchan_dev* dev) +{ + extern alt_llist alt_dma_txchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_txchan_list); +} + +/* + * Register a DMA receive channel with the system. + */ + +static ALT_INLINE int alt_dma_rxchan_reg (alt_dma_rxchan_dev* dev) +{ + extern alt_llist alt_dma_rxchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_rxchan_list); +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_DEV_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_driver.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_driver.h index eb0f23b..ca7aea1 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_driver.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_driver.h @@ -1,168 +1,168 @@ -#ifndef __ALT_DRIVER_H__ -#define __ALT_DRIVER_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/* - * Macros used to access a driver without HAL file descriptors. - */ - -/* - * ALT_MODULE_CLASS - * - * This macro returns the module class name for the specified module instance. - * It uses information in the system.h file. - * Neither the instance name or class name are quoted (so that they can - * be used with other pre-processor macros). - * - * Example: - * Assume the design has an instance of an altera_avalon_uart called uart1. - * Calling ALT_MODULE_CLASS(uart1) returns altera_avalon_uart. - */ - -#define ALT_MODULE_CLASS(instance) ALT_MODULE_CLASS_ ## instance - - -/* - * ALT_DRIVER_FUNC_NAME - * - * --> instance Instance name. - * --> func Function name. - * - * This macro returns the device driver function name of the specified - * module instance for the specified function name. - * - * Example: - * Assume the design has an instance of an altera_avalon_uart called uart1. - * Calling ALT_DRIVER_FUNC_NAME(uart1, write) returns - * altera_avalon_uart_write. - */ - -#define ALT_DRIVER_FUNC_NAME(instance, func) \ - ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func) -#define ALT_DRIVER_FUNC_NAME1(module_class, func) \ - ALT_DRIVER_FUNC_NAME2(module_class, func) -#define ALT_DRIVER_FUNC_NAME2(module_class, func) \ - module_class ## _ ## func - -/* - * ALT_DRIVER_STATE_STRUCT - * - * --> instance Instance name. - * - * This macro returns the device driver state type name of the specified - * module instance. - * - * Example: - * Assume the design has an instance of an altera_avalon_uart called uart1. - * Calling ALT_DRIVER_STATE_STRUCT(uart1) returns: - * struct altera_avalon_uart_state_s - * - * Note that the ALT_DRIVER_FUNC_NAME macro is used even though "state" isn't - * really a function but it does match the required naming convention. - */ -#define ALT_DRIVER_STATE_STRUCT(instance) \ - struct ALT_DRIVER_FUNC_NAME(instance, state_s) - -/* - * ALT_DRIVER_STATE - * - * --> instance Instance name. - * - * This macro returns the device driver state name of the specified - * module instance. - * - * Example: - * Assume the design has an instance of an altera_avalon_uart called uart1. - * Calling ALT_DRIVER_STATE(uart1) returns uart1. - */ -#define ALT_DRIVER_STATE(instance) instance - -/* - * ALT_DRIVER_WRITE - * - * --> instance Instance name. - * --> buffer Write buffer. - * --> len Length of write buffer data. - * --> flags Control flags (e.g. O_NONBLOCK) - * - * This macro calls the "write" function of the specified driver instance. - */ - -#define ALT_DRIVER_WRITE_EXTERNS(instance) \ - extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ - extern int ALT_DRIVER_FUNC_NAME(instance, write) \ - (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); - -#define ALT_DRIVER_WRITE(instance, buffer, len, flags) \ - ALT_DRIVER_FUNC_NAME(instance, write)(&ALT_DRIVER_STATE(instance), buffer, len, flags) - - -/* - * ALT_DRIVER_READ - * - * --> instance Instance name. - * <-- buffer Read buffer. - * --> len Length of read buffer. - * --> flags Control flags (e.g. O_NONBLOCK) - * - * This macro calls the "read" function of the specified driver instance. - */ - -#define ALT_DRIVER_READ_EXTERNS(instance) \ - extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ - extern int ALT_DRIVER_FUNC_NAME(instance, read) \ - (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); - -#define ALT_DRIVER_READ(instance, buffer, len, flags) \ - ALT_DRIVER_FUNC_NAME(instance, read)(&ALT_DRIVER_STATE(instance), buffer, len, flags) - -/* - * ALT_DRIVER_IOCTL - * - * --> instance Instance name. - * --> req ioctl request (e.g. TIOCSTIMEOUT) - * --> arg Optional argument (void*) - * - * This macro calls the "ioctl" function of the specified driver instance - */ - -#define ALT_DRIVER_IOCTL_EXTERNS(instance) \ - extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ - extern int ALT_DRIVER_FUNC_NAME(instance, ioctl) \ - (ALT_DRIVER_STATE_STRUCT(instance) *, int, void*); - -#define ALT_DRIVER_IOCTL(instance, req, arg) \ - ALT_DRIVER_FUNC_NAME(instance, ioctl)(&ALT_DRIVER_STATE(instance), req, arg) - -#endif /* __ALT_DRIVER_H__ */ +#ifndef __ALT_DRIVER_H__ +#define __ALT_DRIVER_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Macros used to access a driver without HAL file descriptors. + */ + +/* + * ALT_MODULE_CLASS + * + * This macro returns the module class name for the specified module instance. + * It uses information in the system.h file. + * Neither the instance name or class name are quoted (so that they can + * be used with other pre-processor macros). + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_MODULE_CLASS(uart1) returns altera_avalon_uart. + */ + +#define ALT_MODULE_CLASS(instance) ALT_MODULE_CLASS_ ## instance + + +/* + * ALT_DRIVER_FUNC_NAME + * + * --> instance Instance name. + * --> func Function name. + * + * This macro returns the device driver function name of the specified + * module instance for the specified function name. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_FUNC_NAME(uart1, write) returns + * altera_avalon_uart_write. + */ + +#define ALT_DRIVER_FUNC_NAME(instance, func) \ + ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func) +#define ALT_DRIVER_FUNC_NAME1(module_class, func) \ + ALT_DRIVER_FUNC_NAME2(module_class, func) +#define ALT_DRIVER_FUNC_NAME2(module_class, func) \ + module_class ## _ ## func + +/* + * ALT_DRIVER_STATE_STRUCT + * + * --> instance Instance name. + * + * This macro returns the device driver state type name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE_STRUCT(uart1) returns: + * struct altera_avalon_uart_state_s + * + * Note that the ALT_DRIVER_FUNC_NAME macro is used even though "state" isn't + * really a function but it does match the required naming convention. + */ +#define ALT_DRIVER_STATE_STRUCT(instance) \ + struct ALT_DRIVER_FUNC_NAME(instance, state_s) + +/* + * ALT_DRIVER_STATE + * + * --> instance Instance name. + * + * This macro returns the device driver state name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE(uart1) returns uart1. + */ +#define ALT_DRIVER_STATE(instance) instance + +/* + * ALT_DRIVER_WRITE + * + * --> instance Instance name. + * --> buffer Write buffer. + * --> len Length of write buffer data. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "write" function of the specified driver instance. + */ + +#define ALT_DRIVER_WRITE_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, write) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_WRITE(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, write)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + + +/* + * ALT_DRIVER_READ + * + * --> instance Instance name. + * <-- buffer Read buffer. + * --> len Length of read buffer. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "read" function of the specified driver instance. + */ + +#define ALT_DRIVER_READ_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, read) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_READ(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, read)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + +/* + * ALT_DRIVER_IOCTL + * + * --> instance Instance name. + * --> req ioctl request (e.g. TIOCSTIMEOUT) + * --> arg Optional argument (void*) + * + * This macro calls the "ioctl" function of the specified driver instance + */ + +#define ALT_DRIVER_IOCTL_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, ioctl) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, int, void*); + +#define ALT_DRIVER_IOCTL(instance, req, arg) \ + ALT_DRIVER_FUNC_NAME(instance, ioctl)(&ALT_DRIVER_STATE(instance), req, arg) + +#endif /* __ALT_DRIVER_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_errno.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_errno.h index 4d3e50f..23e3096 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_errno.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_errno.h @@ -1,87 +1,87 @@ -#ifndef __ALT_ERRNO_H__ -#define __ALT_ERRNO_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/* - * errno is defined in so that it uses the thread local version - * stored in the location pointed to by "_impure_ptr". This means that the - * accesses to errno within the HAL library can cause the entirety of - * of the structure pointed to by "_impure_ptr" to be added to the - * users application. This can be undesirable in very small footprint systems. - * - * To avoid this happening, the HAL uses the macro ALT_ERRNO, defined below, - * to access errno, rather than accessing it directly. This macro will only - * use the thread local version if some other code has already caused it to be - * included into the system, otherwise it will use the global errno value. - * - * This causes a slight increases in code size where errno is accessed, but - * can lead to significant overall benefits in very small systems. The - * increase is inconsequential when compared to the size of the structure - * pointed to by _impure_ptr. - * - * Note that this macro accesses __errno() using an externally declared - * function pointer (alt_errno). This is done so that the function call uses the - * subroutine call instruction via a register rather than an immediate address. - * This is important in the case that the code has been linked for a high - * address, but __errno() is not being used. In this case the weak linkage - * would have resulted in the instruction: "call 0" which would fail to link. - */ - -extern int* (*alt_errno) (void); - -/* Must define this so that values such as EBADFD are defined in errno.h. */ -#define __LINUX_ERRNO_EXTENSIONS__ - -#include - -#include "alt_types.h" - -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - return ((alt_errno) ? alt_errno() : &errno); -} - -#define ALT_ERRNO *alt_get_errno() - -#endif /* __ALT_ERRNO_H__ */ +#ifndef __ALT_ERRNO_H__ +#define __ALT_ERRNO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * errno is defined in so that it uses the thread local version + * stored in the location pointed to by "_impure_ptr". This means that the + * accesses to errno within the HAL library can cause the entirety of + * of the structure pointed to by "_impure_ptr" to be added to the + * users application. This can be undesirable in very small footprint systems. + * + * To avoid this happening, the HAL uses the macro ALT_ERRNO, defined below, + * to access errno, rather than accessing it directly. This macro will only + * use the thread local version if some other code has already caused it to be + * included into the system, otherwise it will use the global errno value. + * + * This causes a slight increases in code size where errno is accessed, but + * can lead to significant overall benefits in very small systems. The + * increase is inconsequential when compared to the size of the structure + * pointed to by _impure_ptr. + * + * Note that this macro accesses __errno() using an externally declared + * function pointer (alt_errno). This is done so that the function call uses the + * subroutine call instruction via a register rather than an immediate address. + * This is important in the case that the code has been linked for a high + * address, but __errno() is not being used. In this case the weak linkage + * would have resulted in the instruction: "call 0" which would fail to link. + */ + +extern int* (*alt_errno) (void); + +/* Must define this so that values such as EBADFD are defined in errno.h. */ +#define __LINUX_ERRNO_EXTENSIONS__ + +#include + +#include "alt_types.h" + +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + return ((alt_errno) ? alt_errno() : &errno); +} + +#define ALT_ERRNO *alt_get_errno() + +#endif /* __ALT_ERRNO_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_exceptions.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_exceptions.h index 3576a52..b6b82e2 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_exceptions.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_exceptions.h @@ -1,127 +1,127 @@ -#ifndef __ALT_EXCEPTIONS_H__ -#define __ALT_EXCEPTIONS_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ -#include "alt_types.h" -#include "system.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * This file defines instruction-generated exception handling and registry - * API, exception type enumeration, and handler return value enumeration for - * Nios II. - */ - -/* - * The following enumeration describes the value in the CPU EXCEPTION - * register CAUSE bit field. Not all exception types will cause the - * processor to go to the exception vector; these are provided for - * reference. - */ -enum alt_exception_cause_e { - /* Exeption causes that will cause jump to exception vector */ - NIOS2_EXCEPTION_INTERRUPT = 2, - NIOS2_EXCEPTION_TRAP_INST = 3, - NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4, - NIOS2_EXCEPTION_ILLEGAL_INST = 5, - NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6, - NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7, - NIOS2_EXCEPTION_DIVISION_ERROR = 8, - NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9, - NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10, - NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11, - NIOS2_EXCEPTION_TLB_MISS = 12, - NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13, - NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16, - - /* Exception causes that will NOT cause a jump to exception vector */ - NIOS2_EXCEPTION_RESET = 0, - NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1, - NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14, - NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15, - NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17, - /* - * This value is passed to an exception handler's cause argument if - * "extra exceptions" information (EXECPTION) register is not - * present in the processor hardware configuration. - */ - NIOS2_EXCEPTION_CAUSE_NOT_PRESENT = -1 -}; -typedef enum alt_exception_cause_e alt_exception_cause; - -/* - * These define valid return values for a user-defined instruction-generated - * exception handler. The handler should return one of these to indicate - * whether to re-issue the instruction that triggered the exception, or to - * skip it. - */ -enum alt_exception_result_e { - NIOS2_EXCEPTION_RETURN_REISSUE_INST = 0, - NIOS2_EXCEPTION_RETURN_SKIP_INST = 1 -}; -typedef enum alt_exception_result_e alt_exception_result; - -/* - * alt_instruction_exception_register() can be used to register an exception - * handler for instruction-generated exceptions that are not handled by the - * built-in exception handler (i.e. for interrupts). - * - * The registry API is optionally enabled through the "Enable - * Instruction-related Exception API" HAL BSP setting, which will - * define the macro below. - */ -#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API -void alt_instruction_exception_register ( - alt_exception_result (*exception_handler)( - alt_exception_cause cause, - alt_u32 exception_pc, - alt_u32 bad_addr) ); -#endif /*ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ - -/* - * alt_exception_cause_generated_bad_addr() indicates whether a particular - * exception cause value was from an exception-type that generated a valid - * address in the BADADDR register. The contents of BADADDR is passed to - * a user-registered exception handler in all cases, whether valid or not. - * This routine should be called to validate the bad_addr argument to - * your exception handler. - */ -int alt_exception_cause_generated_bad_addr(alt_exception_cause cause); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_EXCEPTIONS_H__ */ +#ifndef __ALT_EXCEPTIONS_H__ +#define __ALT_EXCEPTIONS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This file defines instruction-generated exception handling and registry + * API, exception type enumeration, and handler return value enumeration for + * Nios II. + */ + +/* + * The following enumeration describes the value in the CPU EXCEPTION + * register CAUSE bit field. Not all exception types will cause the + * processor to go to the exception vector; these are provided for + * reference. + */ +enum alt_exception_cause_e { + /* Exeption causes that will cause jump to exception vector */ + NIOS2_EXCEPTION_INTERRUPT = 2, + NIOS2_EXCEPTION_TRAP_INST = 3, + NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4, + NIOS2_EXCEPTION_ILLEGAL_INST = 5, + NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6, + NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7, + NIOS2_EXCEPTION_DIVISION_ERROR = 8, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11, + NIOS2_EXCEPTION_TLB_MISS = 12, + NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13, + NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16, + + /* Exception causes that will NOT cause a jump to exception vector */ + NIOS2_EXCEPTION_RESET = 0, + NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1, + NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14, + NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15, + NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17, + /* + * This value is passed to an exception handler's cause argument if + * "extra exceptions" information (EXECPTION) register is not + * present in the processor hardware configuration. + */ + NIOS2_EXCEPTION_CAUSE_NOT_PRESENT = -1 +}; +typedef enum alt_exception_cause_e alt_exception_cause; + +/* + * These define valid return values for a user-defined instruction-generated + * exception handler. The handler should return one of these to indicate + * whether to re-issue the instruction that triggered the exception, or to + * skip it. + */ +enum alt_exception_result_e { + NIOS2_EXCEPTION_RETURN_REISSUE_INST = 0, + NIOS2_EXCEPTION_RETURN_SKIP_INST = 1 +}; +typedef enum alt_exception_result_e alt_exception_result; + +/* + * alt_instruction_exception_register() can be used to register an exception + * handler for instruction-generated exceptions that are not handled by the + * built-in exception handler (i.e. for interrupts). + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ); +#endif /*ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * alt_exception_cause_generated_bad_addr() indicates whether a particular + * exception cause value was from an exception-type that generated a valid + * address in the BADADDR register. The contents of BADADDR is passed to + * a user-registered exception handler in all cases, whether valid or not. + * This routine should be called to validate the bad_addr argument to + * your exception handler. + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_EXCEPTIONS_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash.h index 527328d..7e903a8 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash.h @@ -1,166 +1,166 @@ -#ifndef __ALT_FLASH_H__ -#define __ALT_FLASH_H__ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/****************************************************************************** -* * -* Alt_flash.h - User interface for flash code * -* * -* Use this interface to avoid being exposed to the internals of the device * -* driver architecture. If you chose to use the flash driver internal * -* structures we don't guarantee not to change them * -* * -* Author PRR * -* * -******************************************************************************/ - - - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -#include "alt_types.h" -#include "alt_flash_types.h" -#include "alt_flash_dev.h" -#include "sys/alt_cache.h" - -alt_flash_fd* alt_flash_open_dev(const char* name); -void alt_flash_close_dev(alt_flash_fd* fd ); - -/* - * alt_write_flash - * - * Program a buffer into flash. - * - * This routine erases all the affected erase blocks (if necessary) - * and then programs the data. However it does not read the data out first - * and preserve and none overwritten data, because this would require very - * large buffers on the target. If you need - * that functionality use the functions below. - */ -static __inline__ int __attribute__ ((always_inline)) alt_write_flash( - alt_flash_fd* fd, - int offset, - const void* src_addr, - int length ) -{ - return fd->write( fd, offset, src_addr, length ); -} - -/* - * alt_read_flash - * - * Read a block of flash for most flashes this is just memcpy - * it's here for completeness in case we need it for some serial flash device - * - */ -static __inline__ int __attribute__ ((always_inline)) alt_read_flash( - alt_flash_fd* fd, int offset, - void* dest_addr, int length ) -{ - return fd->read( fd, offset, dest_addr, length ); -} - -/* - * alt_get_flash_info - * - * Return the information on the flash sectors. - * - */ -static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( - alt_flash_fd* fd, flash_region** info, - int* number_of_regions) -{ - return fd->get_info( fd, info, number_of_regions); -} - -/* - * alt_erase_flash_block - * - * Erase a particular erase block, pass in the offset to the start of - * the block and it's size - */ -static __inline__ int __attribute__ ((always_inline)) alt_erase_flash_block( - alt_flash_fd* fd, int offset, int length) -{ - int ret_code; - ret_code = fd->erase_block( fd, offset ); - - if(!ret_code) - alt_dcache_flush((alt_u8*)fd->base_addr + offset, length); - - return ret_code; -} - -/* - * alt_write_flash_block - * - * Write a particular flash block, block_offset is the offset - * (from the base of flash) to start of the block - * data_offset is the offset (from the base of flash) - * where you wish to start programming - * - * NB this function DOES NOT check that you are only writing a single - * block of data as that would slow down this function. - * - * Use alt_write_flash if you want that level of error checking. - */ - -static __inline__ int __attribute__ ((always_inline)) alt_write_flash_block( - alt_flash_fd* fd, int block_offset, - int data_offset, - const void *data, int length) -{ - - int ret_code; - ret_code = fd->write_block( fd, block_offset, data_offset, data, length ); - - if(!ret_code) - alt_dcache_flush((alt_u8*)fd->base_addr + data_offset, length); - - return ret_code; -} - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_FLASH_H__ */ +#ifndef __ALT_FLASH_H__ +#define __ALT_FLASH_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.h - User interface for flash code * +* * +* Use this interface to avoid being exposed to the internals of the device * +* driver architecture. If you chose to use the flash driver internal * +* structures we don't guarantee not to change them * +* * +* Author PRR * +* * +******************************************************************************/ + + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "alt_types.h" +#include "alt_flash_types.h" +#include "alt_flash_dev.h" +#include "sys/alt_cache.h" + +alt_flash_fd* alt_flash_open_dev(const char* name); +void alt_flash_close_dev(alt_flash_fd* fd ); + +/* + * alt_write_flash + * + * Program a buffer into flash. + * + * This routine erases all the affected erase blocks (if necessary) + * and then programs the data. However it does not read the data out first + * and preserve and none overwritten data, because this would require very + * large buffers on the target. If you need + * that functionality use the functions below. + */ +static __inline__ int __attribute__ ((always_inline)) alt_write_flash( + alt_flash_fd* fd, + int offset, + const void* src_addr, + int length ) +{ + return fd->write( fd, offset, src_addr, length ); +} + +/* + * alt_read_flash + * + * Read a block of flash for most flashes this is just memcpy + * it's here for completeness in case we need it for some serial flash device + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_read_flash( + alt_flash_fd* fd, int offset, + void* dest_addr, int length ) +{ + return fd->read( fd, offset, dest_addr, length ); +} + +/* + * alt_get_flash_info + * + * Return the information on the flash sectors. + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( + alt_flash_fd* fd, flash_region** info, + int* number_of_regions) +{ + return fd->get_info( fd, info, number_of_regions); +} + +/* + * alt_erase_flash_block + * + * Erase a particular erase block, pass in the offset to the start of + * the block and it's size + */ +static __inline__ int __attribute__ ((always_inline)) alt_erase_flash_block( + alt_flash_fd* fd, int offset, int length) +{ + int ret_code; + ret_code = fd->erase_block( fd, offset ); + + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + offset, length); + + return ret_code; +} + +/* + * alt_write_flash_block + * + * Write a particular flash block, block_offset is the offset + * (from the base of flash) to start of the block + * data_offset is the offset (from the base of flash) + * where you wish to start programming + * + * NB this function DOES NOT check that you are only writing a single + * block of data as that would slow down this function. + * + * Use alt_write_flash if you want that level of error checking. + */ + +static __inline__ int __attribute__ ((always_inline)) alt_write_flash_block( + alt_flash_fd* fd, int block_offset, + int data_offset, + const void *data, int length) +{ + + int ret_code; + ret_code = fd->write_block( fd, block_offset, data_offset, data, length ); + + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + data_offset, length); + + return ret_code; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FLASH_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash_dev.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash_dev.h index 8bab601..1c5692e 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash_dev.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash_dev.h @@ -1,98 +1,98 @@ -#ifndef __ALT_FLASH_DEV_H__ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/****************************************************************************** -* * -* Alt_flash_dev.h - Generic Flash device interfaces * -* * -* Author PRR * -* * -******************************************************************************/ -#define __ALT_FLASH_DEV_H__ - -#include "alt_flash_types.h" -#include "sys/alt_llist.h" -#include "priv/alt_dev_llist.h" - -#include "alt_types.h" - -typedef struct alt_flash_dev alt_flash_dev; -typedef alt_flash_dev alt_flash_fd; - -static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd) -{ - extern alt_llist alt_flash_dev_list; - - return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list); -} - -typedef alt_flash_dev* (*alt_flash_open)(alt_flash_dev* flash, - const char* name ); -typedef int (*alt_flash_close)(alt_flash_dev* flash_info); - -typedef int (*alt_flash_write)( alt_flash_dev* flash, int offset, - const void* src_addr, int length ); - -typedef int (*alt_flash_get_flash_info)( alt_flash_dev* flash, flash_region** info, - int* number_of_regions); -typedef int (*alt_flash_write_block)( alt_flash_dev* flash, int block_offset, - int data_offset, const void* data, - int length); -typedef int (*alt_flash_erase_block)( alt_flash_dev* flash, int offset); -typedef int (*alt_flash_read)(alt_flash_dev* flash, int offset, - void* dest_addr, int length ); - -struct alt_flash_dev -{ - alt_llist llist; - const char* name; - alt_flash_open open; - alt_flash_close close; - alt_flash_write write; - alt_flash_read read; - alt_flash_get_flash_info get_info; - alt_flash_erase_block erase_block; - alt_flash_write_block write_block; - void* base_addr; - int length; - int number_of_regions; - flash_region region_info[ALT_MAX_NUMBER_OF_FLASH_REGIONS]; -}; - -#endif /* __ALT_FLASH_DEV_H__ */ +#ifndef __ALT_FLASH_DEV_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_dev.h - Generic Flash device interfaces * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_DEV_H__ + +#include "alt_flash_types.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +typedef struct alt_flash_dev alt_flash_dev; +typedef alt_flash_dev alt_flash_fd; + +static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd) +{ + extern alt_llist alt_flash_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list); +} + +typedef alt_flash_dev* (*alt_flash_open)(alt_flash_dev* flash, + const char* name ); +typedef int (*alt_flash_close)(alt_flash_dev* flash_info); + +typedef int (*alt_flash_write)( alt_flash_dev* flash, int offset, + const void* src_addr, int length ); + +typedef int (*alt_flash_get_flash_info)( alt_flash_dev* flash, flash_region** info, + int* number_of_regions); +typedef int (*alt_flash_write_block)( alt_flash_dev* flash, int block_offset, + int data_offset, const void* data, + int length); +typedef int (*alt_flash_erase_block)( alt_flash_dev* flash, int offset); +typedef int (*alt_flash_read)(alt_flash_dev* flash, int offset, + void* dest_addr, int length ); + +struct alt_flash_dev +{ + alt_llist llist; + const char* name; + alt_flash_open open; + alt_flash_close close; + alt_flash_write write; + alt_flash_read read; + alt_flash_get_flash_info get_info; + alt_flash_erase_block erase_block; + alt_flash_write_block write_block; + void* base_addr; + int length; + int number_of_regions; + flash_region region_info[ALT_MAX_NUMBER_OF_FLASH_REGIONS]; +}; + +#endif /* __ALT_FLASH_DEV_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash_types.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash_types.h index 884cbf8..10f1f01 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash_types.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_flash_types.h @@ -1,64 +1,64 @@ -#ifndef __ALT_FLASH_TYPES_H__ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/****************************************************************************** -* * -* Alt_flash_types.h - Some generic types and defines used by the flash code * -* * -* Author PRR * -* * -******************************************************************************/ -#define __ALT_FLASH_TYPES_H__ - -#ifndef ALT_MAX_NUMBER_OF_FLASH_REGIONS -#define ALT_MAX_NUMBER_OF_FLASH_REGIONS 8 -#endif /* ALT_MAX_NUMBER_OF_FLASH_REGIONS */ - -/* - * Description of a single Erase region - */ -typedef struct flash_region -{ - int offset; - int region_size; - int number_of_blocks; - int block_size; -}flash_region; - -#endif /* __ALT_FLASH_TYPES_H__ */ +#ifndef __ALT_FLASH_TYPES_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_types.h - Some generic types and defines used by the flash code * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_TYPES_H__ + +#ifndef ALT_MAX_NUMBER_OF_FLASH_REGIONS +#define ALT_MAX_NUMBER_OF_FLASH_REGIONS 8 +#endif /* ALT_MAX_NUMBER_OF_FLASH_REGIONS */ + +/* + * Description of a single Erase region + */ +typedef struct flash_region +{ + int offset; + int region_size; + int number_of_blocks; + int block_size; +}flash_region; + +#endif /* __ALT_FLASH_TYPES_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_irq.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_irq.h index 6666e52..96c010d 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_irq.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_irq.h @@ -1,245 +1,245 @@ -#ifndef __ALT_IRQ_H__ -#define __ALT_IRQ_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * alt_irq.h is the Nios II specific implementation of the interrupt controller - * interface. - * - * Nios II includes optional support for an external interrupt controller. - * When an external controller is present, the "Enhanced" interrupt API - * must be used to manage individual interrupts. The enhanced API also - * supports the processor's internal interrupt controller. Certain API - * members are accessible from either the "legacy" or "enhanced" interrpt - * API. - * - * Regardless of which API is in use, this file should be included by - * application code and device drivers that register ISRs or manage interrpts. - */ -#include - -#include "nios2.h" -#include "alt_types.h" -#include "system.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Macros used by alt_irq_enabled - */ -#define ALT_IRQ_ENABLED 1 -#define ALT_IRQ_DISABLED 0 - -/* - * Number of available interrupts in internal interrupt controller. - */ -#define ALT_NIRQ NIOS2_NIRQ - -/* - * Used by alt_irq_disable_all() and alt_irq_enable_all(). - */ -typedef int alt_irq_context; - -/* ISR Prototype */ -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT -typedef void (*alt_isr_func)(void* isr_context); -#else -typedef void (*alt_isr_func)(void* isr_context, alt_u32 id); -#endif - -/* - * The following protypes and routines are supported by both - * the enhanced and legacy interrupt APIs - */ - -/* - * alt_irq_enabled can be called to determine if the processor's global - * interrupt enable is asserted. The return value is zero if interrupts - * are disabled, and non-zero otherwise. - * - * Whether the internal or external interrupt controller is present, - * individual interrupts may still be disabled. Use the other API to query - * a specific interrupt. - */ -static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enabled (void) -{ - int status; - - NIOS2_READ_STATUS (status); - - return status & NIOS2_STATUS_PIE_MSK; -} - -/* - * alt_irq_disable_all() - * - * This routine inhibits all interrupts by negating the status register PIE - * bit. It returns the previous contents of the CPU status register (IRQ - * context) which can be used to restore the status register PIE bit to its - * state before this routine was called. - */ -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - - return context; -} - -/* - * alt_irq_enable_all() - * - * Enable all interrupts that were previously disabled by alt_irq_disable_all() - * - * This routine accepts a context to restore the CPU status register PIE bit - * to the state prior to a call to alt_irq_disable_all(). - - * In the case of nested calls to alt_irq_disable_all()/alt_irq_enable_all(), - * this means that alt_irq_enable_all() does not necessarily re-enable - * interrupts. - * - * This routine will perform a read-modify-write sequence to restore only - * status.PIE if the processor is configured with options that add additional - * writeable status register bits. These include the MMU, MPU, the enhanced - * interrupt controller port, and shadow registers. Otherwise, as a performance - * enhancement, status is overwritten with the prior context. - */ -static ALT_INLINE void ALT_ALWAYS_INLINE - alt_irq_enable_all (alt_irq_context context) -{ -#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || (defined NIOS2_EIC_PRESENT) || \ - (defined NIOS2_MMU_PRESENT) || (defined NIOS2_MPU_PRESENT) - alt_irq_context status; - - NIOS2_READ_STATUS (status); - - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); -#endif -} - -/* - * The function alt_irq_init() is defined within the auto-generated file - * alt_sys_init.c. This function calls the initilization macros for all - * interrupt controllers in the system at config time, before any other - * non-interrupt controller driver is initialized. - * - * The "base" parameter is ignored and only present for backwards-compatibility. - * It is recommended that NULL is passed in for the "base" parameter. - */ -extern void alt_irq_init (const void* base); - -/* - * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. - */ -static ALT_INLINE void ALT_ALWAYS_INLINE - alt_irq_cpu_enable_interrupts () -{ - NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK -#if defined(NIOS2_EIC_PRESENT) && (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) - | NIOS2_STATUS_RSIE_MSK -#endif - ); -} - - -/* - * Prototypes for the enhanced interrupt API. - */ -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT -/* - * alt_ic_isr_register() can be used to register an interrupt handler. If the - * function is succesful, then the requested interrupt will be enabled upon - * return. - */ -extern int alt_ic_isr_register(alt_u32 ic_id, - alt_u32 irq, - alt_isr_func isr, - void *isr_context, - void *flags); - -/* - * alt_ic_irq_enable() and alt_ic_irq_disable() enable/disable a specific - * interrupt by using IRQ port and interrupt controller instance. - */ -int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq); -int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq); - - /* - * alt_ic_irq_enabled() indicates whether a specific interrupt, as - * specified by IRQ port and interrupt controller instance is enabled. - */ -alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq); - -#else -/* - * Prototypes for the legacy interrupt API. - */ -#include "priv/alt_legacy_irq.h" -#endif - - -/* - * alt_irq_pending() returns a bit list of the current pending interrupts. - * This is used by alt_irq_handler() to determine which registered interrupt - * handlers should be called. - * - * This routine is only available for the Nios II internal interrupt - * controller. - */ -#ifndef NIOS2_EIC_PRESENT -static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) -{ - alt_u32 active; - - NIOS2_READ_IPENDING (active); - - return active; -} -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_IRQ_H__ */ +#ifndef __ALT_IRQ_H__ +#define __ALT_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_irq.h is the Nios II specific implementation of the interrupt controller + * interface. + * + * Nios II includes optional support for an external interrupt controller. + * When an external controller is present, the "Enhanced" interrupt API + * must be used to manage individual interrupts. The enhanced API also + * supports the processor's internal interrupt controller. Certain API + * members are accessible from either the "legacy" or "enhanced" interrpt + * API. + * + * Regardless of which API is in use, this file should be included by + * application code and device drivers that register ISRs or manage interrpts. + */ +#include + +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros used by alt_irq_enabled + */ +#define ALT_IRQ_ENABLED 1 +#define ALT_IRQ_DISABLED 0 + +/* + * Number of available interrupts in internal interrupt controller. + */ +#define ALT_NIRQ NIOS2_NIRQ + +/* + * Used by alt_irq_disable_all() and alt_irq_enable_all(). + */ +typedef int alt_irq_context; + +/* ISR Prototype */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +typedef void (*alt_isr_func)(void* isr_context); +#else +typedef void (*alt_isr_func)(void* isr_context, alt_u32 id); +#endif + +/* + * The following protypes and routines are supported by both + * the enhanced and legacy interrupt APIs + */ + +/* + * alt_irq_enabled can be called to determine if the processor's global + * interrupt enable is asserted. The return value is zero if interrupts + * are disabled, and non-zero otherwise. + * + * Whether the internal or external interrupt controller is present, + * individual interrupts may still be disabled. Use the other API to query + * a specific interrupt. + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enabled (void) +{ + int status; + + NIOS2_READ_STATUS (status); + + return status & NIOS2_STATUS_PIE_MSK; +} + +/* + * alt_irq_disable_all() + * + * This routine inhibits all interrupts by negating the status register PIE + * bit. It returns the previous contents of the CPU status register (IRQ + * context) which can be used to restore the status register PIE bit to its + * state before this routine was called. + */ +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + + return context; +} + +/* + * alt_irq_enable_all() + * + * Enable all interrupts that were previously disabled by alt_irq_disable_all() + * + * This routine accepts a context to restore the CPU status register PIE bit + * to the state prior to a call to alt_irq_disable_all(). + + * In the case of nested calls to alt_irq_disable_all()/alt_irq_enable_all(), + * this means that alt_irq_enable_all() does not necessarily re-enable + * interrupts. + * + * This routine will perform a read-modify-write sequence to restore only + * status.PIE if the processor is configured with options that add additional + * writeable status register bits. These include the MMU, MPU, the enhanced + * interrupt controller port, and shadow registers. Otherwise, as a performance + * enhancement, status is overwritten with the prior context. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_enable_all (alt_irq_context context) +{ +#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || (defined NIOS2_EIC_PRESENT) || \ + (defined NIOS2_MMU_PRESENT) || (defined NIOS2_MPU_PRESENT) + alt_irq_context status; + + NIOS2_READ_STATUS (status); + + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); +#endif +} + +/* + * The function alt_irq_init() is defined within the auto-generated file + * alt_sys_init.c. This function calls the initilization macros for all + * interrupt controllers in the system at config time, before any other + * non-interrupt controller driver is initialized. + * + * The "base" parameter is ignored and only present for backwards-compatibility. + * It is recommended that NULL is passed in for the "base" parameter. + */ +extern void alt_irq_init (const void* base); + +/* + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts () +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK +#if defined(NIOS2_EIC_PRESENT) && (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) + | NIOS2_STATUS_RSIE_MSK +#endif + ); +} + + +/* + * Prototypes for the enhanced interrupt API. + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +/* + * alt_ic_isr_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_ic_isr_register(alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void *isr_context, + void *flags); + +/* + * alt_ic_irq_enable() and alt_ic_irq_disable() enable/disable a specific + * interrupt by using IRQ port and interrupt controller instance. + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq); +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq); + + /* + * alt_ic_irq_enabled() indicates whether a specific interrupt, as + * specified by IRQ port and interrupt controller instance is enabled. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq); + +#else +/* + * Prototypes for the legacy interrupt API. + */ +#include "priv/alt_legacy_irq.h" +#endif + + +/* + * alt_irq_pending() returns a bit list of the current pending interrupts. + * This is used by alt_irq_handler() to determine which registered interrupt + * handlers should be called. + * + * This routine is only available for the Nios II internal interrupt + * controller. + */ +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + + return active; +} +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_IRQ_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_irq_entry.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_irq_entry.h index e2008d9..549811c 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_irq_entry.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_irq_entry.h @@ -1,39 +1,39 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * This file pulls in the IRQ entry assembler and C code, which is only - * required if there are any interruptes in the system. - */ - -__asm__( "\n\t.globl alt_irq_entry" ); - -__asm__( "\n\t.globl alt_irq_handler" ); - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file pulls in the IRQ entry assembler and C code, which is only + * required if there are any interruptes in the system. + */ + +__asm__( "\n\t.globl alt_irq_entry" ); + +__asm__( "\n\t.globl alt_irq_handler" ); + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h index 2fe649c..1d1f16f 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h @@ -1,77 +1,77 @@ -#ifndef __ALT_LICENSE_REMINDER_UCOSII_H__ -#define __ALT_LICENSE_REMINDER_UCOSII_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include - -#define ALT_LICENSE_REMINDER_UCOSII_STRING \ - "============== Software License Reminder ===============\n" \ - "\n" \ - "uC/OS-II is provided in source form for FREE evaluation,\n" \ - "for educational use, or for peaceful research. If you\n" \ - "plan on using uC/OS-II in a commercial product you need\n" \ - "to contact Micrium to properly license its use in your\n" \ - "product. Micrium provides ALL the source code on the\n" \ - "Altera distribution for your convenience and to help you\n" \ - "experience uC/OS-II. The fact that the source is provided\n" \ - "does NOT mean that you can use it without paying a\n" \ - "licensing fee. Please help us continue to provide the\n" \ - "Embedded community with the finest software available.\n" \ - "Your honesty is greatly appreciated.\n" \ - "\n" \ - "Please contact:\n" \ - "\n" \ - "M I C R I U M\n" \ - "949 Crestview Circle\n" \ - "Weston, FL 33327-1848\n" \ - "U.S.A.\n" \ - "\n" \ - "Phone : +1 954 217 2036\n" \ - "FAX : +1 954 217 2037\n" \ - "WEB : www.micrium.com\n" \ - "E-mail: Sales@Micrium.com\n" \ - "\n" \ - "========================================================\n" - -#define alt_license_reminder_ucosii() puts(ALT_LICENSE_REMINDER_UCOSII_STRING) - - -#endif /* __ALT_LICENSE_REMINDER_UCOSII_H__ */ - +#ifndef __ALT_LICENSE_REMINDER_UCOSII_H__ +#define __ALT_LICENSE_REMINDER_UCOSII_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include + +#define ALT_LICENSE_REMINDER_UCOSII_STRING \ + "============== Software License Reminder ===============\n" \ + "\n" \ + "uC/OS-II is provided in source form for FREE evaluation,\n" \ + "for educational use, or for peaceful research. If you\n" \ + "plan on using uC/OS-II in a commercial product you need\n" \ + "to contact Micrium to properly license its use in your\n" \ + "product. Micrium provides ALL the source code on the\n" \ + "Altera distribution for your convenience and to help you\n" \ + "experience uC/OS-II. The fact that the source is provided\n" \ + "does NOT mean that you can use it without paying a\n" \ + "licensing fee. Please help us continue to provide the\n" \ + "Embedded community with the finest software available.\n" \ + "Your honesty is greatly appreciated.\n" \ + "\n" \ + "Please contact:\n" \ + "\n" \ + "M I C R I U M\n" \ + "949 Crestview Circle\n" \ + "Weston, FL 33327-1848\n" \ + "U.S.A.\n" \ + "\n" \ + "Phone : +1 954 217 2036\n" \ + "FAX : +1 954 217 2037\n" \ + "WEB : www.micrium.com\n" \ + "E-mail: Sales@Micrium.com\n" \ + "\n" \ + "========================================================\n" + +#define alt_license_reminder_ucosii() puts(ALT_LICENSE_REMINDER_UCOSII_STRING) + + +#endif /* __ALT_LICENSE_REMINDER_UCOSII_H__ */ + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_llist.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_llist.h index 46f81ce..84cb051 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_llist.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_llist.h @@ -1,123 +1,123 @@ -#ifndef __ALT_LIST_H__ -#define __ALT_LIST_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "alt_types.h" - -/* - * alt_llist.h defines structures and functions for use in manipulating linked - * lists. A list is considered to be constructed from a chain of objects of - * type alt_llist, with one object being defined to be the head element. - * - * A list is considered to be empty if it only contains the head element. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * alt_llist is the structure used to represent an element within a linked - * list. - */ - -typedef struct alt_llist_s alt_llist; - -struct alt_llist_s { - alt_llist* next; /* Pointer to the next element in the list. */ - alt_llist* previous; /* Pointer to the previous element in the list. */ -}; - -/* - * ALT_LLIST_HEAD is a macro that can be used to create the head of a new - * linked list. This is named "head". The head element is initialised to - * represent an empty list. - */ - -#define ALT_LLIST_HEAD(head) alt_llist head = {&head, &head} - -/* - * ALT_LLIST_ENTRY is a macro used to define an uninitialised linked list - * entry. This is used to reserve space in structure initialisation for - * structures that inherit form alt_llist. - */ - -#define ALT_LLIST_ENTRY {0, 0} - -/* - * alt_llist_insert() insert adds the linked list entry "entry" as the - * first entry in the linked list "list". "list" is the list head element. - */ - -static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, - alt_llist* entry) -{ - entry->previous = list; - entry->next = list->next; - - list->next->previous = entry; - list->next = entry; -} - -/* - * alt_llist_remove() is called to remove an element from a linked list. The - * input argument is the element to remove. - */ - -static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) -{ - entry->next->previous = entry->previous; - entry->previous->next = entry->next; - - /* - * Set the entry to point to itself, so that any further calls to - * alt_llist_remove() are harmless. - */ - - entry->previous = entry; - entry->next = entry; -} - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_LLIST_H__ */ +#ifndef __ALT_LIST_H__ +#define __ALT_LIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * alt_llist.h defines structures and functions for use in manipulating linked + * lists. A list is considered to be constructed from a chain of objects of + * type alt_llist, with one object being defined to be the head element. + * + * A list is considered to be empty if it only contains the head element. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_llist is the structure used to represent an element within a linked + * list. + */ + +typedef struct alt_llist_s alt_llist; + +struct alt_llist_s { + alt_llist* next; /* Pointer to the next element in the list. */ + alt_llist* previous; /* Pointer to the previous element in the list. */ +}; + +/* + * ALT_LLIST_HEAD is a macro that can be used to create the head of a new + * linked list. This is named "head". The head element is initialised to + * represent an empty list. + */ + +#define ALT_LLIST_HEAD(head) alt_llist head = {&head, &head} + +/* + * ALT_LLIST_ENTRY is a macro used to define an uninitialised linked list + * entry. This is used to reserve space in structure initialisation for + * structures that inherit form alt_llist. + */ + +#define ALT_LLIST_ENTRY {0, 0} + +/* + * alt_llist_insert() insert adds the linked list entry "entry" as the + * first entry in the linked list "list". "list" is the list head element. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + entry->next = list->next; + + list->next->previous = entry; + list->next = entry; +} + +/* + * alt_llist_remove() is called to remove an element from a linked list. The + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + entry->previous->next = entry->next; + + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + entry->next = entry; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_LLIST_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_load.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_load.h index 432e9f2..e4c4c46 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_load.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_load.h @@ -1,78 +1,78 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "alt_types.h" - -/* - * This macro is used to load code/data from its load address to its - * execution address for a given section. The section name is the input - * argument. Note that a leading '.' is assumed in the name. For example - * to load the section .onchip_ram, use: - * - * ALT_LOAD_SECTION_BY_NAME(onchip_ram); - * - * This requires that the apropriate linker symbols have been generated - * for the section in question. This will be the case if you are using the - * default linker script. - */ - -#define ALT_LOAD_SECTION_BY_NAME(name) \ - { \ - extern void _alt_partition_##name##_start; \ - extern void _alt_partition_##name##_end; \ - extern void _alt_partition_##name##_load_addr; \ - \ - alt_load_section(&_alt_partition_##name##_load_addr, \ - &_alt_partition_##name##_start, \ - &_alt_partition_##name##_end); \ - } - -/* - * Function used to load an individual section from flash to RAM. - * - * There is an implicit assumption here that the linker script will ensure - * that all sections are word aligned. - * - */ - -static void ALT_INLINE alt_load_section (alt_u32* from, - alt_u32* to, - alt_u32* end) -{ - if (to != from) - { - while( to != end ) - { - *to++ = *from++; - } - } -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This macro is used to load code/data from its load address to its + * execution address for a given section. The section name is the input + * argument. Note that a leading '.' is assumed in the name. For example + * to load the section .onchip_ram, use: + * + * ALT_LOAD_SECTION_BY_NAME(onchip_ram); + * + * This requires that the apropriate linker symbols have been generated + * for the section in question. This will be the case if you are using the + * default linker script. + */ + +#define ALT_LOAD_SECTION_BY_NAME(name) \ + { \ + extern void _alt_partition_##name##_start; \ + extern void _alt_partition_##name##_end; \ + extern void _alt_partition_##name##_load_addr; \ + \ + alt_load_section(&_alt_partition_##name##_load_addr, \ + &_alt_partition_##name##_start, \ + &_alt_partition_##name##_end); \ + } + +/* + * Function used to load an individual section from flash to RAM. + * + * There is an implicit assumption here that the linker script will ensure + * that all sections are word aligned. + * + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + { + *to++ = *from++; + } + } +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_log_printf.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_log_printf.h index c15ca05..9890091 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_log_printf.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_log_printf.h @@ -1,349 +1,349 @@ -/* alt_log_printf.h - * - * ALT_LOG is designed to provide extra logging/debugging messages from HAL - * through a different port than stdout. It is enabled by the ALT_LOG_ENABLE - * define, which needs to supplied at compile time. When logging is turned off, - * code size is unaffected. Thus, this should be transparent to the user - * when it is not actively turned on, and should not affect projects in any way. - * - * There are macros sprinkled within different components, such as the jtag uart - * and timer, in the HAL code. They are always named ALT_LOG_, and can be - * safely ignored if ALT_LOG is turned off. - * - * To turn on ALT_LOG, ALT_LOG_ENABLE must be defined, and ALT_LOG_PORT_TYPE and - * ALT_LOG_PORT_BASE must be set in system.h. This is done through editing - * .ptf, by editing the alt_log_port_type & alt_log_port_base settings. - * See the documentation html file for examples. - * - * When it is turned on, it will output extra HAL messages to a port specified - * in system.h. This can be a UART or JTAG UART port. By default it will - * output boot messages, detailing every step of the boot process. - * - * Extra logging is designed to be enabled by flags, which are defined in - * alt_log_printf.c. The default value is that all flags are off, so only the - * boot up logging messages show up. ALT_LOG_FLAGS can be set to enable certain - * groupings of flags, and that grouping is done in this file. Each flag can - * also be overridden with a -D at compile time. - * - * This header file includes the necessary prototypes for using the alt_log - * functions. It also contains all the macros that are used to remove the code - * from alt log is turned off. Also, the macros in other HAL files are defined - * here at the bottom. These macros all call some C function that is in - * alt_log_printf.c. - * - * The logging has functions for printing in C (ALT_LOG_PRINTF) and in assembly - * (ALT_LOG_PUTS). This was needed because the assembly printing occurs before - * the device is initialized. The assembly function corrupts register R4-R7, - * which are not used in the normal boot process. For this reason, do not call - * the assembly function in C. - * - * author: gkwan - */ - - -#ifndef __ALT_LOG_PRINTF_H__ -#define __ALT_LOG_PRINTF_H__ - -#include - -/* Global switch to turn on logging functions */ -#ifdef ALT_LOG_ENABLE - - /* ALT_LOG_PORT_TYPE values as defined in system.h. They are defined as - * numbers here first becasue the C preprocessor does not handle string - * comparisons. */ - #define ALTERA_AVALON_JTAG_UART 1 - #define ALTERA_AVALON_UART 0 - - /* If this .h file is included by an assembly file, skip over include files - * that won't compile in assembly. */ - #ifndef ALT_ASM_SRC - #include - #include "sys/alt_alarm.h" - #include "sys/alt_dev.h" - #ifdef __ALTERA_AVALON_JTAG_UART - #include "altera_avalon_jtag_uart.h" - #endif - #endif /* ALT_ASM_SRC */ - - /* These are included for the port register offsets and masks, needed - * to write to the port. Only include if the port type is set correctly, - * otherwise error. If alt_log is turned on and the port to output to is - * incorrect or does not exist, then should exit. */ - #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART - #ifdef __ALTERA_AVALON_JTAG_UART - #include - #else - #error ALT_LOG: JTAG_UART port chosen, but no JTAG_UART in system. - #endif - #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART - #ifdef __ALTERA_AVALON_UART - #include - #else - #error ALT_LOG: UART Port chosen, but no UART in system. - #endif - #else - #error ALT_LOG: alt_log_port_type declaration invalid! - #endif - - /* ALT_LOG_ENABLE turns on the basic printing function */ - #define ALT_LOG_PRINTF(...) do {alt_log_printf_proc(__VA_ARGS__);} while (0) - - /* Assembly macro for printing in assembly, calls tx_log_str - * which is in alt_log_macro.S. - * If alt_log_boot_on_flag is 0, skips the printing */ - #define ALT_LOG_PUTS(str) movhi r4, %hiadj(alt_log_boot_on_flag) ; \ - addi r4, r4, %lo(alt_log_boot_on_flag) ; \ - ldwio r5, 0(r4) ; \ - beq r0, r5, 0f ; \ - movhi r4, %hiadj(str) ; \ - addi r4, r4, %lo(str) ; \ - call tx_log_str ; \ - 0: - - /* These defines are here to faciliate the use of one output function - * (alt_log_txchar) to print to both the JTAG UART or the UART. Depending - * on the port type, the status register, read mask, and output register - * are set to the appropriate value for the port. */ - #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART - #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_JTAG_UART_CONTROL - #define ALT_LOG_PRINT_MSK ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK - #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_JTAG_UART_DATA - #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_JTAG_UART_CONTROL_REG*0x4) - #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_JTAG_UART_DATA_REG*0x4) - #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART - #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_UART_STATUS - #define ALT_LOG_PRINT_MSK ALTERA_AVALON_UART_STATUS_TRDY_MSK - #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_UART_TXDATA - #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_UART_STATUS_REG*0x4) - #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_UART_TXDATA_REG*0x4) - #endif /* ALT_LOG_PORT */ - - /* Grouping of flags via ALT_LOG_FLAGS. Each specific flag can be set via - * -D at compile time, or else they'll be set to a default value according - * to ALT_LOG_FLAGS. ALT_LOG_FLAGS = 0 or not set is the default, where - * only the boot messages will be printed. As ALT_LOG_FLAGS increase, they - * increase in intrusiveness to the program, and will affect performance. - * - * Flag Level 1 - turns on system clock and JTAG UART startup status - * 2 - turns on write echo and JTAG_UART alarm (periodic report) - * 3 - turns on JTAG UART ISR logging - will slow performance - * significantly. - * -1 - All logging output is off, but if ALT_LOG_ENABLE is - * defined all logging function is built and code size - * remains constant - * - * Flag settings - 1 = on, 0 = off. */ - - /* This flag turns on "boot" messages for printing. This includes messages - * during crt0.S, then alt_main, and finally alt_exit. */ - #ifndef ALT_LOG_BOOT_ON_FLAG_SETTING - #if ALT_LOG_FLAGS == 1 - #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == 2 - #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == 3 - #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == -1 /* silent mode */ - #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x0 - #else /* default setting */ - #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 - #endif - #endif /* ALT_LOG_BOOT_ON_FLAG_SETTING */ - - #ifndef ALT_LOG_SYS_CLK_ON_FLAG_SETTING - #if ALT_LOG_FLAGS == 1 - #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == 2 - #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == 3 - #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == -1 /* silent mode */ - #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 - #else /* default setting */ - #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 - #endif - #endif /* ALT_LOG_SYS_CLK_ON_FLAG_SETTING */ - - #ifndef ALT_LOG_WRITE_ON_FLAG_SETTING - #if ALT_LOG_FLAGS == 1 - #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 - #elif ALT_LOG_FLAGS == 2 - #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == 3 - #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == -1 /* silent mode */ - #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 - #else /* default setting */ - #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 - #endif - #endif /* ALT_LOG_WRITE_ON_FLAG_SETTING */ - - #ifndef ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING - #ifndef __ALTERA_AVALON_JTAG_UART - #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 - #elif ALT_LOG_FLAGS == 1 - #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 - #elif ALT_LOG_FLAGS == 2 - #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == 3 - #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == -1 /* silent mode */ - #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 - #else /* default setting */ - #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 - #endif - #endif /* ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING */ - - #ifndef ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING - #ifndef __ALTERA_AVALON_JTAG_UART - #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 - #elif ALT_LOG_FLAGS == 1 - #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == 2 - #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == 3 - #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == -1 /* silent mode */ - #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 - #else /* default setting */ - #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 - #endif - #endif /* ALT_LOG_JTAG_UART_STARTUP_INFO_FLAG_SETTING */ - - #ifndef ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING - #ifndef __ALTERA_AVALON_JTAG_UART - #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 - #elif ALT_LOG_FLAGS == 1 - #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 - #elif ALT_LOG_FLAGS == 2 - #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 - #elif ALT_LOG_FLAGS == 3 - #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x1 - #elif ALT_LOG_FLAGS == -1 /* silent mode */ - #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 - #else /* default setting */ - #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 - #endif - #endif /* ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING */ - -#ifndef ALT_ASM_SRC - /* Function Prototypes */ - void alt_log_txchar(int c,char *uartBase); - void alt_log_private_printf(const char *fmt,int base,va_list args); - void alt_log_repchar(char c,int r,int base); - int alt_log_printf_proc(const char *fmt, ... ); - void alt_log_system_clock(); - #ifdef __ALTERA_AVALON_JTAG_UART - alt_u32 altera_avalon_jtag_uart_report_log(void * context); - void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base); - void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, \ - int base, const char* header); - void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev); - #endif - void alt_log_write(const void *ptr, size_t len); - - /* extern all global variables */ - extern volatile alt_u32 alt_log_boot_on_flag; - extern volatile alt_u8 alt_log_write_on_flag; - extern volatile alt_u8 alt_log_sys_clk_on_flag; - extern volatile alt_u8 alt_log_jtag_uart_alarm_on_flag; - extern volatile alt_u8 alt_log_jtag_uart_isr_on_flag; - extern volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag; - extern volatile int alt_log_sys_clk_count; - extern volatile int alt_system_clock_in_sec; - extern alt_alarm alt_log_jtag_uart_alarm_1; -#endif /* ALT_ASM_SRC */ - - - /* Below are the MACRO defines used in various HAL files. They check - * if their specific flag is turned on; if it is, then it executes its - * code. - * - * To keep this file reasonable, most of these macros calls functions, - * which are defined in alt_log_printf.c. Look there for implementation - * details. */ - - /* Boot Messages Logging */ - #define ALT_LOG_PRINT_BOOT(...) \ - do { if (alt_log_boot_on_flag==1) {ALT_LOG_PRINTF(__VA_ARGS__);} \ - } while (0) - - /* JTAG UART Logging */ - /* number of ticks before alarm runs logging function */ - #ifndef ALT_LOG_JTAG_UART_TICKS_DIVISOR - #define ALT_LOG_JTAG_UART_TICKS_DIVISOR 10 - #endif - #ifndef ALT_LOG_JTAG_UART_TICKS - #define ALT_LOG_JTAG_UART_TICKS \ - (alt_ticks_per_second()/ALT_LOG_JTAG_UART_TICKS_DIVISOR) - #endif - - /* if there's a JTAG UART defined, then enable these macros */ - #ifdef __ALTERA_AVALON_JTAG_UART - - /* Macro in altera_avalon_jtag_uart.c, to register the alarm function. - * Also, the startup register info is also printed here, as this is - * called within the device driver initialization. */ - #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) \ - do { if (alt_log_jtag_uart_alarm_on_flag==1) { \ - alt_alarm_start(&alt_log_jtag_uart_alarm_1, \ - ALT_LOG_JTAG_UART_TICKS, &altera_avalon_jtag_uart_report_log,\ - dev);} \ - if (alt_log_jtag_uart_startup_info_on_flag==1) {\ - alt_log_jtag_uart_startup_info(dev, base);} \ - } while (0) - - /* JTAG UART IRQ Logging (when buffer is empty) - * Inserted in the ISR in altera_avalon_jtag_uart.c */ - #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) \ - do { alt_log_jtag_uart_isr_proc(base, dev); } while (0) - /* else, define macros to nothing. Or else the jtag_uart specific types - * will throw compiler errors */ - #else - #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) - #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) - #endif - - /* System clock logging - * How often (in seconds) the system clock logging prints. - * The default value is every 1 second */ - #ifndef ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER - #define ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER 1 - #endif - #ifndef ALT_LOG_SYS_CLK_INTERVAL - #define ALT_LOG_SYS_CLK_INTERVAL \ - (alt_ticks_per_second()*ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER) - #endif - - /* System clock logging - prints a message every interval (set above) - * to show that the system clock is alive. - * This macro is used in altera_avalon_timer_sc.c */ - #define ALT_LOG_SYS_CLK_HEARTBEAT() \ - do { alt_log_system_clock(); } while (0) - - /* alt_write_logging - echos a message every time write() is called, - * displays the first ALT_LOG_WRITE_ECHO_LEN characters. - * This macro is used in alt_write.c */ - #ifndef ALT_LOG_WRITE_ECHO_LEN - #define ALT_LOG_WRITE_ECHO_LEN 15 - #endif - - #define ALT_LOG_WRITE_FUNCTION(ptr,len) \ - do { alt_log_write(ptr,len); } while (0) - -#else /* ALT_LOG_ENABLE not defined */ - - /* logging is off, set all relevant macros to null */ - #define ALT_LOG_PRINT_BOOT(...) - #define ALT_LOG_PRINTF(...) - #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) - #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) - #define ALT_LOG_SYS_CLK_HEARTBEAT() - #define ALT_LOG_PUTS(str) - #define ALT_LOG_WRITE_FUNCTION(ptr,len) - -#endif /* ALT_LOG_ENABLE */ - -#endif /* __ALT_LOG_PRINTF_H__ */ - +/* alt_log_printf.h + * + * ALT_LOG is designed to provide extra logging/debugging messages from HAL + * through a different port than stdout. It is enabled by the ALT_LOG_ENABLE + * define, which needs to supplied at compile time. When logging is turned off, + * code size is unaffected. Thus, this should be transparent to the user + * when it is not actively turned on, and should not affect projects in any way. + * + * There are macros sprinkled within different components, such as the jtag uart + * and timer, in the HAL code. They are always named ALT_LOG_, and can be + * safely ignored if ALT_LOG is turned off. + * + * To turn on ALT_LOG, ALT_LOG_ENABLE must be defined, and ALT_LOG_PORT_TYPE and + * ALT_LOG_PORT_BASE must be set in system.h. This is done through editing + * .ptf, by editing the alt_log_port_type & alt_log_port_base settings. + * See the documentation html file for examples. + * + * When it is turned on, it will output extra HAL messages to a port specified + * in system.h. This can be a UART or JTAG UART port. By default it will + * output boot messages, detailing every step of the boot process. + * + * Extra logging is designed to be enabled by flags, which are defined in + * alt_log_printf.c. The default value is that all flags are off, so only the + * boot up logging messages show up. ALT_LOG_FLAGS can be set to enable certain + * groupings of flags, and that grouping is done in this file. Each flag can + * also be overridden with a -D at compile time. + * + * This header file includes the necessary prototypes for using the alt_log + * functions. It also contains all the macros that are used to remove the code + * from alt log is turned off. Also, the macros in other HAL files are defined + * here at the bottom. These macros all call some C function that is in + * alt_log_printf.c. + * + * The logging has functions for printing in C (ALT_LOG_PRINTF) and in assembly + * (ALT_LOG_PUTS). This was needed because the assembly printing occurs before + * the device is initialized. The assembly function corrupts register R4-R7, + * which are not used in the normal boot process. For this reason, do not call + * the assembly function in C. + * + * author: gkwan + */ + + +#ifndef __ALT_LOG_PRINTF_H__ +#define __ALT_LOG_PRINTF_H__ + +#include + +/* Global switch to turn on logging functions */ +#ifdef ALT_LOG_ENABLE + + /* ALT_LOG_PORT_TYPE values as defined in system.h. They are defined as + * numbers here first becasue the C preprocessor does not handle string + * comparisons. */ + #define ALTERA_AVALON_JTAG_UART 1 + #define ALTERA_AVALON_UART 0 + + /* If this .h file is included by an assembly file, skip over include files + * that won't compile in assembly. */ + #ifndef ALT_ASM_SRC + #include + #include "sys/alt_alarm.h" + #include "sys/alt_dev.h" + #ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #endif + #endif /* ALT_ASM_SRC */ + + /* These are included for the port register offsets and masks, needed + * to write to the port. Only include if the port type is set correctly, + * otherwise error. If alt_log is turned on and the port to output to is + * incorrect or does not exist, then should exit. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #ifdef __ALTERA_AVALON_JTAG_UART + #include + #else + #error ALT_LOG: JTAG_UART port chosen, but no JTAG_UART in system. + #endif + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #ifdef __ALTERA_AVALON_UART + #include + #else + #error ALT_LOG: UART Port chosen, but no UART in system. + #endif + #else + #error ALT_LOG: alt_log_port_type declaration invalid! + #endif + + /* ALT_LOG_ENABLE turns on the basic printing function */ + #define ALT_LOG_PRINTF(...) do {alt_log_printf_proc(__VA_ARGS__);} while (0) + + /* Assembly macro for printing in assembly, calls tx_log_str + * which is in alt_log_macro.S. + * If alt_log_boot_on_flag is 0, skips the printing */ + #define ALT_LOG_PUTS(str) movhi r4, %hiadj(alt_log_boot_on_flag) ; \ + addi r4, r4, %lo(alt_log_boot_on_flag) ; \ + ldwio r5, 0(r4) ; \ + beq r0, r5, 0f ; \ + movhi r4, %hiadj(str) ; \ + addi r4, r4, %lo(str) ; \ + call tx_log_str ; \ + 0: + + /* These defines are here to faciliate the use of one output function + * (alt_log_txchar) to print to both the JTAG UART or the UART. Depending + * on the port type, the status register, read mask, and output register + * are set to the appropriate value for the port. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_JTAG_UART_CONTROL + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_JTAG_UART_DATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_JTAG_UART_CONTROL_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_JTAG_UART_DATA_REG*0x4) + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_UART_STATUS + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_UART_STATUS_TRDY_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_UART_TXDATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_UART_STATUS_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_UART_TXDATA_REG*0x4) + #endif /* ALT_LOG_PORT */ + + /* Grouping of flags via ALT_LOG_FLAGS. Each specific flag can be set via + * -D at compile time, or else they'll be set to a default value according + * to ALT_LOG_FLAGS. ALT_LOG_FLAGS = 0 or not set is the default, where + * only the boot messages will be printed. As ALT_LOG_FLAGS increase, they + * increase in intrusiveness to the program, and will affect performance. + * + * Flag Level 1 - turns on system clock and JTAG UART startup status + * 2 - turns on write echo and JTAG_UART alarm (periodic report) + * 3 - turns on JTAG UART ISR logging - will slow performance + * significantly. + * -1 - All logging output is off, but if ALT_LOG_ENABLE is + * defined all logging function is built and code size + * remains constant + * + * Flag settings - 1 = on, 0 = off. */ + + /* This flag turns on "boot" messages for printing. This includes messages + * during crt0.S, then alt_main, and finally alt_exit. */ + #ifndef ALT_LOG_BOOT_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #endif + #endif /* ALT_LOG_BOOT_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_SYS_CLK_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_SYS_CLK_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_WRITE_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_WRITE_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_STARTUP_INFO_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING */ + +#ifndef ALT_ASM_SRC + /* Function Prototypes */ + void alt_log_txchar(int c,char *uartBase); + void alt_log_private_printf(const char *fmt,int base,va_list args); + void alt_log_repchar(char c,int r,int base); + int alt_log_printf_proc(const char *fmt, ... ); + void alt_log_system_clock(); + #ifdef __ALTERA_AVALON_JTAG_UART + alt_u32 altera_avalon_jtag_uart_report_log(void * context); + void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base); + void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, \ + int base, const char* header); + void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev); + #endif + void alt_log_write(const void *ptr, size_t len); + + /* extern all global variables */ + extern volatile alt_u32 alt_log_boot_on_flag; + extern volatile alt_u8 alt_log_write_on_flag; + extern volatile alt_u8 alt_log_sys_clk_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_alarm_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_isr_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag; + extern volatile int alt_log_sys_clk_count; + extern volatile int alt_system_clock_in_sec; + extern alt_alarm alt_log_jtag_uart_alarm_1; +#endif /* ALT_ASM_SRC */ + + + /* Below are the MACRO defines used in various HAL files. They check + * if their specific flag is turned on; if it is, then it executes its + * code. + * + * To keep this file reasonable, most of these macros calls functions, + * which are defined in alt_log_printf.c. Look there for implementation + * details. */ + + /* Boot Messages Logging */ + #define ALT_LOG_PRINT_BOOT(...) \ + do { if (alt_log_boot_on_flag==1) {ALT_LOG_PRINTF(__VA_ARGS__);} \ + } while (0) + + /* JTAG UART Logging */ + /* number of ticks before alarm runs logging function */ + #ifndef ALT_LOG_JTAG_UART_TICKS_DIVISOR + #define ALT_LOG_JTAG_UART_TICKS_DIVISOR 10 + #endif + #ifndef ALT_LOG_JTAG_UART_TICKS + #define ALT_LOG_JTAG_UART_TICKS \ + (alt_ticks_per_second()/ALT_LOG_JTAG_UART_TICKS_DIVISOR) + #endif + + /* if there's a JTAG UART defined, then enable these macros */ + #ifdef __ALTERA_AVALON_JTAG_UART + + /* Macro in altera_avalon_jtag_uart.c, to register the alarm function. + * Also, the startup register info is also printed here, as this is + * called within the device driver initialization. */ + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) \ + do { if (alt_log_jtag_uart_alarm_on_flag==1) { \ + alt_alarm_start(&alt_log_jtag_uart_alarm_1, \ + ALT_LOG_JTAG_UART_TICKS, &altera_avalon_jtag_uart_report_log,\ + dev);} \ + if (alt_log_jtag_uart_startup_info_on_flag==1) {\ + alt_log_jtag_uart_startup_info(dev, base);} \ + } while (0) + + /* JTAG UART IRQ Logging (when buffer is empty) + * Inserted in the ISR in altera_avalon_jtag_uart.c */ + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) \ + do { alt_log_jtag_uart_isr_proc(base, dev); } while (0) + /* else, define macros to nothing. Or else the jtag_uart specific types + * will throw compiler errors */ + #else + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #endif + + /* System clock logging + * How often (in seconds) the system clock logging prints. + * The default value is every 1 second */ + #ifndef ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER + #define ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER 1 + #endif + #ifndef ALT_LOG_SYS_CLK_INTERVAL + #define ALT_LOG_SYS_CLK_INTERVAL \ + (alt_ticks_per_second()*ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER) + #endif + + /* System clock logging - prints a message every interval (set above) + * to show that the system clock is alive. + * This macro is used in altera_avalon_timer_sc.c */ + #define ALT_LOG_SYS_CLK_HEARTBEAT() \ + do { alt_log_system_clock(); } while (0) + + /* alt_write_logging - echos a message every time write() is called, + * displays the first ALT_LOG_WRITE_ECHO_LEN characters. + * This macro is used in alt_write.c */ + #ifndef ALT_LOG_WRITE_ECHO_LEN + #define ALT_LOG_WRITE_ECHO_LEN 15 + #endif + + #define ALT_LOG_WRITE_FUNCTION(ptr,len) \ + do { alt_log_write(ptr,len); } while (0) + +#else /* ALT_LOG_ENABLE not defined */ + + /* logging is off, set all relevant macros to null */ + #define ALT_LOG_PRINT_BOOT(...) + #define ALT_LOG_PRINTF(...) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_SYS_CLK_HEARTBEAT() + #define ALT_LOG_PUTS(str) + #define ALT_LOG_WRITE_FUNCTION(ptr,len) + +#endif /* ALT_LOG_ENABLE */ + +#endif /* __ALT_LOG_PRINTF_H__ */ + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_set_args.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_set_args.h index 3750e67..a9372c5 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_set_args.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_set_args.h @@ -1,71 +1,71 @@ -#ifndef __ALT_SET_ARGS_H__ -#define __ALT_SET_ARGS_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The function alt_set_args() is provided in order to define the input - * arguments to main(). If this function is not called before main() then the - * argument list passed to main() will be empty. - * - * It is expected that this function will only be used by the ihost/iclient - * utility. - */ - -static inline void alt_set_args (int argc, char** argv, char** envp) -{ - extern int alt_argc; - extern char** alt_argv; - extern char** alt_envp; - - alt_argc = argc; - alt_argv = argv; - alt_envp = envp; -} - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_SET_ARGS_H__ */ +#ifndef __ALT_SET_ARGS_H__ +#define __ALT_SET_ARGS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_set_args() is provided in order to define the input + * arguments to main(). If this function is not called before main() then the + * argument list passed to main() will be empty. + * + * It is expected that this function will only be used by the ihost/iclient + * utility. + */ + +static inline void alt_set_args (int argc, char** argv, char** envp) +{ + extern int alt_argc; + extern char** alt_argv; + extern char** alt_envp; + + alt_argc = argc; + alt_argv = argv; + alt_envp = envp; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SET_ARGS_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sim.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sim.h index 06bd27a..63afad9 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sim.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sim.h @@ -1,91 +1,91 @@ -#ifndef __ALT_SIM_H__ -#define __ALT_SIM_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ -#include "system.h" -#include "alt_types.h" - -/* - * Instructions that might mean something special to a simulator. - * These have no special effect on real hardware (they are just nops). - */ -#define ALT_SIM_FAIL() \ - do { __asm volatile ("cmpltui r0, r0, 0xabc1"); } while (0) - -#define ALT_SIM_PASS() \ - do { __asm volatile ("cmpltui r0, r0, 0xabc2"); } while (0) - -#define ALT_SIM_IN_TOP_OF_HOT_LOOP() \ - do { __asm volatile ("cmpltui r0, r0, 0xabc3"); } while (0) - -/* - * Routine called on exit. - */ -static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) -{ - int r2 = exit_code; - -#if defined(NIOS2_HAS_DEBUG_STUB) && (defined(ALT_BREAK_ON_EXIT) || defined(ALT_PROVIDE_GMON)) - - int r3 = (1 << 2); - -#ifdef ALT_PROVIDE_GMON - extern unsigned int alt_gmon_data[]; - int r4 = (int)alt_gmon_data; - r3 |= (1 << 4); -#define ALT_GMON_DATA ,"D04"(r4) -#else -#define ALT_GMON_DATA -#endif /* ALT_PROVIDE_GMON */ - - if (r2) { - ALT_SIM_FAIL(); - } else { - ALT_SIM_PASS(); - } - - __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ - - __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); - -#else /* !DEBUG_STUB */ - if (r2) { - ALT_SIM_FAIL(); - } else { - ALT_SIM_PASS(); - } -#endif /* DEBUG_STUB */ -} - -#define ALT_SIM_HALT(exit_code) \ - alt_sim_halt(exit_code) - -#endif /* __ALT_SIM_H__ */ +#ifndef __ALT_SIM_H__ +#define __ALT_SIM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" +#include "alt_types.h" + +/* + * Instructions that might mean something special to a simulator. + * These have no special effect on real hardware (they are just nops). + */ +#define ALT_SIM_FAIL() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc1"); } while (0) + +#define ALT_SIM_PASS() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc2"); } while (0) + +#define ALT_SIM_IN_TOP_OF_HOT_LOOP() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc3"); } while (0) + +/* + * Routine called on exit. + */ +static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + int r2 = exit_code; + +#if defined(NIOS2_HAS_DEBUG_STUB) && (defined(ALT_BREAK_ON_EXIT) || defined(ALT_PROVIDE_GMON)) + + int r3 = (1 << 2); + +#ifdef ALT_PROVIDE_GMON + extern unsigned int alt_gmon_data[]; + int r4 = (int)alt_gmon_data; + r3 |= (1 << 4); +#define ALT_GMON_DATA ,"D04"(r4) +#else +#define ALT_GMON_DATA +#endif /* ALT_PROVIDE_GMON */ + + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } + + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } +#endif /* DEBUG_STUB */ +} + +#define ALT_SIM_HALT(exit_code) \ + alt_sim_halt(exit_code) + +#endif /* __ALT_SIM_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_stack.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_stack.h index e30652a..ebcad7a 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_stack.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_stack.h @@ -1,126 +1,126 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#ifndef __ALT_STACK_H__ -#define __ALT_STACK_H__ - -/* - * alt_stack.h is the nios2 specific implementation of functions used by the - * stack overflow code. - */ - -#include "nios2.h" - -#include "alt_types.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - - -extern char * alt_stack_limit_value; - -#ifdef ALT_EXCEPTION_STACK -extern char __alt_exception_stack_pointer[]; /* set by the linker */ -#endif /* ALT_EXCEPTION_STACK */ - - -/* - * alt_stack_limit can be called to determine the current value of the stack - * limit register. - */ - -static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_limit (void) -{ - char * limit; - NIOS2_READ_ET(limit); - - return limit; -} - -/* - * alt_stack_pointer can be called to determine the current value of the stack - * pointer register. - */ - -static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_pointer (void) -{ - char * pointer; - NIOS2_READ_SP(pointer); - - return pointer; -} - - -#ifdef ALT_EXCEPTION_STACK - -/* - * alt_exception_stack_pointer returns the normal stack pointer from - * where it is stored on the exception stack (uppermost 4 bytes). This - * is really only useful during exception processing, and is only - * available if a separate exception stack has been configured. - */ - -static ALT_INLINE char * ALT_ALWAYS_INLINE alt_exception_stack_pointer (void) -{ - return (char *) *(alt_u32 *)(__alt_exception_stack_pointer - sizeof(alt_u32)); -} - -#endif /* ALT_EXCEPTION_STACK */ - - -/* - * alt_set_stack_limit can be called to update the current value of the stack - * limit register. - */ - -static ALT_INLINE void ALT_ALWAYS_INLINE alt_set_stack_limit (char * limit) -{ - alt_stack_limit_value = limit; - NIOS2_WRITE_ET(limit); -} - -/* - * alt_report_stack_overflow reports that a stack overflow happened. - */ - -static ALT_INLINE void ALT_ALWAYS_INLINE alt_report_stack_overflow (void) -{ - NIOS2_REPORT_STACK_OVERFLOW(); -} - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_STACK_H__ */ - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_STACK_H__ +#define __ALT_STACK_H__ + +/* + * alt_stack.h is the nios2 specific implementation of functions used by the + * stack overflow code. + */ + +#include "nios2.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +extern char * alt_stack_limit_value; + +#ifdef ALT_EXCEPTION_STACK +extern char __alt_exception_stack_pointer[]; /* set by the linker */ +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_stack_limit can be called to determine the current value of the stack + * limit register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_limit (void) +{ + char * limit; + NIOS2_READ_ET(limit); + + return limit; +} + +/* + * alt_stack_pointer can be called to determine the current value of the stack + * pointer register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_pointer (void) +{ + char * pointer; + NIOS2_READ_SP(pointer); + + return pointer; +} + + +#ifdef ALT_EXCEPTION_STACK + +/* + * alt_exception_stack_pointer returns the normal stack pointer from + * where it is stored on the exception stack (uppermost 4 bytes). This + * is really only useful during exception processing, and is only + * available if a separate exception stack has been configured. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_exception_stack_pointer (void) +{ + return (char *) *(alt_u32 *)(__alt_exception_stack_pointer - sizeof(alt_u32)); +} + +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_set_stack_limit can be called to update the current value of the stack + * limit register. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_set_stack_limit (char * limit) +{ + alt_stack_limit_value = limit; + NIOS2_WRITE_ET(limit); +} + +/* + * alt_report_stack_overflow reports that a stack overflow happened. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_report_stack_overflow (void) +{ + NIOS2_REPORT_STACK_OVERFLOW(); +} + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_STACK_H__ */ + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_stdio.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_stdio.h index 1730360..7ae05d4 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_stdio.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_stdio.h @@ -1,62 +1,62 @@ -#ifndef __ALT_STDIO_H__ -#define __ALT_STDIO_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/* - * Definitions for ALT stdio routines. - */ - -#include - - -#ifdef __cplusplus -extern "C" { -#endif - -int alt_getchar(); -int alt_putchar(int c); -int alt_putstr(const char* str); -void alt_printf(const char *fmt, ...); - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_STDIO_H__ */ +#ifndef __ALT_STDIO_H__ +#define __ALT_STDIO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definitions for ALT stdio routines. + */ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +int alt_getchar(); +int alt_putchar(int c); +int alt_putstr(const char* str); +void alt_printf(const char *fmt, ...); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_STDIO_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sys_init.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sys_init.h index e4abc28..3b18059 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sys_init.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sys_init.h @@ -1,62 +1,62 @@ -#ifndef __ALT_SYS_INIT_H__ -#define __ALT_SYS_INIT_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The function alt_sys_init() is defined within the auto-generated file: - * alt_sys_init.c. This function calls the initilisation macros for all - * devices, file systems, and software components within the system. - * - * The list of initilisation macros to use is constructed using the PTF and - * STF files associated with the system. - */ - -extern void alt_sys_init (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_SYS_INIT_H__ */ +#ifndef __ALT_SYS_INIT_H__ +#define __ALT_SYS_INIT_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_sys_init() is defined within the auto-generated file: + * alt_sys_init.c. This function calls the initilisation macros for all + * devices, file systems, and software components within the system. + * + * The list of initilisation macros to use is constructed using the PTF and + * STF files associated with the system. + */ + +extern void alt_sys_init (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SYS_INIT_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sys_wrappers.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sys_wrappers.h index 044833b..eea552d 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sys_wrappers.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_sys_wrappers.h @@ -1,100 +1,100 @@ -#ifndef __ALT_SYS_WRAPPERS_H__ -#define __ALT_SYS_WRAPPERS_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * This file provides the prototypes for the HAL 'UNIX style functions. The - * names of these functions are defined in alt_syscall.h. THese are defined to - * be the standard names when running the standalone HAL, e.g. open(), close() - * etc., but the names may be redefined as a part of an operating system port - * in order to avoid name clashes. - */ - -#include "os/alt_syscall.h" - -#include -#include -#include -#include -#include -#include - -extern int ALT_CLOSE (int __fd); -extern int ALT_EXECVE (const char *__path, - char * const __argv[], - char * const __envp[]); -extern void ALT_EXIT (int __status); -extern int ALT_FSTAT (int file, struct stat *st); -extern int ALT_FCNTL (int file, int cmd, ...); -extern pid_t ALT_FORK (void); -extern pid_t ALT_GETPID (void); - -#if defined (__GNUC__) && __GNUC__ >= 4 -extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, - void *ptimezone); -#else -extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, - struct timezone *ptimezone); -#endif - -extern int ALT_IOCTL (int file, int req, void* arg); -extern int ALT_ISATTY (int file); -extern int ALT_KILL (int pid, int sig); -extern int ALT_LINK (const char *existing, const char *new); -extern off_t ALT_LSEEK (int file, off_t ptr, int dir); -extern int ALT_OPEN (const char* file, int flags, ...); -extern int ALT_READ (int file, void *ptr, size_t len); -extern int ALT_RENAME (char *existing, char *new); -extern void* ALT_SBRK (ptrdiff_t incr); -extern int ALT_SETTIMEOFDAY (const struct timeval *t, - const struct timezone *tz); -extern int ALT_STAT (const char *file, struct stat *st); -extern clock_t ALT_TIMES (struct tms *buf); -extern int ALT_UNLINK (const char *name); - -#if defined (__GNUC__) && __GNUC__ >= 4 -int ALT_USLEEP (useconds_t us); -#else -unsigned int ALT_USLEEP (unsigned int us); -#endif - -extern int ALT_WAIT (int *status); -extern int ALT_WRITE (int file, const void *ptr, size_t len); - - -extern char** ALT_ENVIRON; - -/* - * - */ - -#endif /* __ALT_SYS_WRAPPERS_H__ */ +#ifndef __ALT_SYS_WRAPPERS_H__ +#define __ALT_SYS_WRAPPERS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides the prototypes for the HAL 'UNIX style functions. The + * names of these functions are defined in alt_syscall.h. THese are defined to + * be the standard names when running the standalone HAL, e.g. open(), close() + * etc., but the names may be redefined as a part of an operating system port + * in order to avoid name clashes. + */ + +#include "os/alt_syscall.h" + +#include +#include +#include +#include +#include +#include + +extern int ALT_CLOSE (int __fd); +extern int ALT_EXECVE (const char *__path, + char * const __argv[], + char * const __envp[]); +extern void ALT_EXIT (int __status); +extern int ALT_FSTAT (int file, struct stat *st); +extern int ALT_FCNTL (int file, int cmd, ...); +extern pid_t ALT_FORK (void); +extern pid_t ALT_GETPID (void); + +#if defined (__GNUC__) && __GNUC__ >= 4 +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + void *ptimezone); +#else +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + struct timezone *ptimezone); +#endif + +extern int ALT_IOCTL (int file, int req, void* arg); +extern int ALT_ISATTY (int file); +extern int ALT_KILL (int pid, int sig); +extern int ALT_LINK (const char *existing, const char *new); +extern off_t ALT_LSEEK (int file, off_t ptr, int dir); +extern int ALT_OPEN (const char* file, int flags, ...); +extern int ALT_READ (int file, void *ptr, size_t len); +extern int ALT_RENAME (char *existing, char *new); +extern void* ALT_SBRK (ptrdiff_t incr); +extern int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz); +extern int ALT_STAT (const char *file, struct stat *st); +extern clock_t ALT_TIMES (struct tms *buf); +extern int ALT_UNLINK (const char *name); + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us); +#else +unsigned int ALT_USLEEP (unsigned int us); +#endif + +extern int ALT_WAIT (int *status); +extern int ALT_WRITE (int file, const void *ptr, size_t len); + + +extern char** ALT_ENVIRON; + +/* + * + */ + +#endif /* __ALT_SYS_WRAPPERS_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_timestamp.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_timestamp.h index 8a18da2..ec704ba 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_timestamp.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_timestamp.h @@ -1,60 +1,60 @@ -#ifndef __ALT_TIMESTAMP_H__ -#define __ALT_TIMESTAMP_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#include "alt_types.h" -#include "altera_avalon_timer.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -extern int alt_timestamp_start (void); - -extern alt_timestamp_type alt_timestamp (void); - -extern alt_u32 alt_timestamp_freq (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __ALT_TIMESTAMP_H__ */ +#ifndef __ALT_TIMESTAMP_H__ +#define __ALT_TIMESTAMP_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "altera_avalon_timer.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +extern int alt_timestamp_start (void); + +extern alt_timestamp_type alt_timestamp (void); + +extern alt_u32 alt_timestamp_freq (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_TIMESTAMP_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_warning.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_warning.h index b66e71a..01318bd 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_warning.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/alt_warning.h @@ -1,75 +1,75 @@ -#ifndef __WARNING_H__ -#define __WARNING_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* - * alt_warning.h provides macro definitions that can be used to generate link - * time warnings. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The symbol "__alt_invalid" is used to force a link error. There should be - * no corresponding implementation of this function. - */ - -extern void __alt_invalid (void); - -#define ALT_LINK_WARNING(symbol, msg) \ - __asm__(".ifndef __evoke_link_warning_" #symbol \ - "\n\t .section .gnu.warning." #symbol \ - "\n__evoke_link_warning_" #symbol ":\n\t .string \x22" msg "\x22 \n\t .previous" \ - "\n .endif"); - -/* A canned warning for sysdeps/stub functions. */ - -#define ALT_STUB_WARNING(name) \ - ALT_LINK_WARNING (name, \ - "warning: " #name " is not implemented and will always fail") - -#define ALT_OBSOLETE_FUNCTION_WARNING(name) \ - ALT_LINK_WARNING (name, \ - "warning: " #name " is a deprecated function") - -#define ALT_LINK_ERROR(msg) \ - ALT_LINK_WARNING (__alt_invalid, msg); \ - __alt_invalid() - -#ifdef __cplusplus -} -#endif - -#endif /* __WARNING_H__ */ +#ifndef __WARNING_H__ +#define __WARNING_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_warning.h provides macro definitions that can be used to generate link + * time warnings. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The symbol "__alt_invalid" is used to force a link error. There should be + * no corresponding implementation of this function. + */ + +extern void __alt_invalid (void); + +#define ALT_LINK_WARNING(symbol, msg) \ + __asm__(".ifndef __evoke_link_warning_" #symbol \ + "\n\t .section .gnu.warning." #symbol \ + "\n__evoke_link_warning_" #symbol ":\n\t .string \x22" msg "\x22 \n\t .previous" \ + "\n .endif"); + +/* A canned warning for sysdeps/stub functions. */ + +#define ALT_STUB_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is not implemented and will always fail") + +#define ALT_OBSOLETE_FUNCTION_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is a deprecated function") + +#define ALT_LINK_ERROR(msg) \ + ALT_LINK_WARNING (__alt_invalid, msg); \ + __alt_invalid() + +#ifdef __cplusplus +} +#endif + +#endif /* __WARNING_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/ioctl.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/ioctl.h index 4d565df..453283b 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/ioctl.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/ioctl.h @@ -1,90 +1,90 @@ -#ifndef __IOCTL_H__ -#define __IOCTL_H__ - -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The ioctl() system call be used to initiate a variety of control operations - * on a file descriptor. For the most part this simply translates to a call to - * the ioctl() function of the associated device driver (TIOCEXCL and - * TIOCNXCL are notable exceptions - see ioctl.c for details). - * - * The interpretation of the ioctl requests are therefore device specific. - * - * This function is equivalent to the standard Posix ioctl() call. - */ - -extern int ioctl (int fd, int req, void* arg); - -/* - * list of ioctl calls handled by the system ioctl implementation. - */ - -#define TIOCEXCL 0x740d /* exclusive use of the device */ -#define TIOCNXCL 0x740e /* allow multiple use of the device */ - -/* - * ioctl calls which can be handled by device drivers. - */ - -#define TIOCOUTQ 0x7472 /* get output queue size */ -#define TIOCMGET 0x741d /* get termios flags */ -#define TIOCMSET 0x741a /* set termios flags */ - -/* - * ioctl calls specific to JTAG UART. - */ - -#define TIOCSTIMEOUT 0x6a01 /* Set Timeout before assuming no host present */ -#define TIOCGCONNECTED 0x6a02 /* Get indication of whether host is connected */ - -/* - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __IOCTL_H__ */ +#ifndef __IOCTL_H__ +#define __IOCTL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The ioctl() system call be used to initiate a variety of control operations + * on a file descriptor. For the most part this simply translates to a call to + * the ioctl() function of the associated device driver (TIOCEXCL and + * TIOCNXCL are notable exceptions - see ioctl.c for details). + * + * The interpretation of the ioctl requests are therefore device specific. + * + * This function is equivalent to the standard Posix ioctl() call. + */ + +extern int ioctl (int fd, int req, void* arg); + +/* + * list of ioctl calls handled by the system ioctl implementation. + */ + +#define TIOCEXCL 0x740d /* exclusive use of the device */ +#define TIOCNXCL 0x740e /* allow multiple use of the device */ + +/* + * ioctl calls which can be handled by device drivers. + */ + +#define TIOCOUTQ 0x7472 /* get output queue size */ +#define TIOCMGET 0x741d /* get termios flags */ +#define TIOCMSET 0x741a /* set termios flags */ + +/* + * ioctl calls specific to JTAG UART. + */ + +#define TIOCSTIMEOUT 0x6a01 /* Set Timeout before assuming no host present */ +#define TIOCGCONNECTED 0x6a02 /* Get indication of whether host is connected */ + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IOCTL_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/termios.h b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/termios.h index cd09539..d271387 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/termios.h +++ b/software/qsys_tutorial_lcd4_bsp/HAL/inc/sys/termios.h @@ -1,181 +1,181 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * -* * -******************************************************************************/ - -/* - * This is the termios.h file provided with newlib. The only modification has - * been to the baud rate macro definitions, and an increase in the size of the - * termios structure to accomodate this. - */ - - -#ifndef _SYS_TERMIOS_H -# define _SYS_TERMIOS_H - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -# define _XCGETA (('x'<<8)|1) -# define _XCSETA (('x'<<8)|2) -# define _XCSETAW (('x'<<8)|3) -# define _XCSETAF (('x'<<8)|4) -# define _TCSBRK (('T'<<8)|5) -# define _TCFLSH (('T'<<8)|7) -# define _TCXONC (('T'<<8)|6) - -# define TCOOFF 0 -# define TCOON 1 -# define TCIOFF 2 -# define TCION 3 - -# define TCIFLUSH 0 -# define TCOFLUSH 1 -# define TCIOFLUSH 2 - -# define NCCS 13 - -# define TCSAFLUSH _XCSETAF -# define TCSANOW _XCSETA -# define TCSADRAIN _XCSETAW -# define TCSADFLUSH _XCSETAF - -# define IGNBRK 000001 -# define BRKINT 000002 -# define IGNPAR 000004 -# define INPCK 000020 -# define ISTRIP 000040 -# define INLCR 000100 -# define IGNCR 000200 -# define ICRNL 000400 -# define IXON 002000 -# define IXOFF 010000 - -# define OPOST 000001 -# define OCRNL 000004 -# define ONLCR 000010 -# define ONOCR 000020 -# define TAB3 014000 - -# define CLOCAL 004000 -# define CREAD 000200 -# define CSIZE 000060 -# define CS5 0 -# define CS6 020 -# define CS7 040 -# define CS8 060 -# define CSTOPB 000100 -# define HUPCL 002000 -# define PARENB 000400 -# define PAODD 001000 - -#define CCTS_OFLOW 010000 -#define CRTS_IFLOW 020000 -#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) - -# define ECHO 0000010 -# define ECHOE 0000020 -# define ECHOK 0000040 -# define ECHONL 0000100 -# define ICANON 0000002 -# define IEXTEN 0000400 /* anybody know *what* this does?! */ -# define ISIG 0000001 -# define NOFLSH 0000200 -# define TOSTOP 0001000 - -# define VEOF 4 /* also VMIN -- thanks, AT&T */ -# define VEOL 5 /* also VTIME -- thanks again */ -# define VERASE 2 -# define VINTR 0 -# define VKILL 3 -# define VMIN 4 /* also VEOF */ -# define VQUIT 1 -# define VSUSP 10 -# define VTIME 5 /* also VEOL */ -# define VSTART 11 -# define VSTOP 12 - -# define B0 0 -# define B50 50 -# define B75 75 -# define B110 110 -# define B134 134 -# define B150 150 -# define B200 200 -# define B300 300 -# define B600 600 -# define B1200 1200 -# define B1800 1800 -# define B2400 2400 -# define B4800 4800 -# define B9600 9600 -# define B19200 19200 -# define B38400 38400 -# define B57600 57600 -# define B115200 115200 - -typedef unsigned char cc_t; -typedef unsigned short tcflag_t; -typedef unsigned long speed_t; - -struct termios { - tcflag_t c_iflag; - tcflag_t c_oflag; - tcflag_t c_cflag; - tcflag_t c_lflag; - char c_line; - cc_t c_cc[NCCS]; - speed_t c_ispeed; - speed_t c_ospeed; -}; - -# ifndef _NO_MACROS - -# define cfgetospeed(tp) ((tp)->c_ospeed) -# define cfgetispeed(tp) ((tp)->c_ispeed) -# define cfsetospeed(tp,s) (((tp)->c_ospeed = (s)), 0) -# define cfsetispeed(tp,s) (((tp)->c_ispeed = (s)), 0) -# define tcdrain(fd) _ioctl (fd, _TCSBRK, 1) -# endif /* _NO_MACROS */ - -#ifdef __cplusplus -} -#endif - -#endif /* _SYS_TERMIOS_H */ - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This is the termios.h file provided with newlib. The only modification has + * been to the baud rate macro definitions, and an increase in the size of the + * termios structure to accomodate this. + */ + + +#ifndef _SYS_TERMIOS_H +# define _SYS_TERMIOS_H + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +# define _XCGETA (('x'<<8)|1) +# define _XCSETA (('x'<<8)|2) +# define _XCSETAW (('x'<<8)|3) +# define _XCSETAF (('x'<<8)|4) +# define _TCSBRK (('T'<<8)|5) +# define _TCFLSH (('T'<<8)|7) +# define _TCXONC (('T'<<8)|6) + +# define TCOOFF 0 +# define TCOON 1 +# define TCIOFF 2 +# define TCION 3 + +# define TCIFLUSH 0 +# define TCOFLUSH 1 +# define TCIOFLUSH 2 + +# define NCCS 13 + +# define TCSAFLUSH _XCSETAF +# define TCSANOW _XCSETA +# define TCSADRAIN _XCSETAW +# define TCSADFLUSH _XCSETAF + +# define IGNBRK 000001 +# define BRKINT 000002 +# define IGNPAR 000004 +# define INPCK 000020 +# define ISTRIP 000040 +# define INLCR 000100 +# define IGNCR 000200 +# define ICRNL 000400 +# define IXON 002000 +# define IXOFF 010000 + +# define OPOST 000001 +# define OCRNL 000004 +# define ONLCR 000010 +# define ONOCR 000020 +# define TAB3 014000 + +# define CLOCAL 004000 +# define CREAD 000200 +# define CSIZE 000060 +# define CS5 0 +# define CS6 020 +# define CS7 040 +# define CS8 060 +# define CSTOPB 000100 +# define HUPCL 002000 +# define PARENB 000400 +# define PAODD 001000 + +#define CCTS_OFLOW 010000 +#define CRTS_IFLOW 020000 +#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) + +# define ECHO 0000010 +# define ECHOE 0000020 +# define ECHOK 0000040 +# define ECHONL 0000100 +# define ICANON 0000002 +# define IEXTEN 0000400 /* anybody know *what* this does?! */ +# define ISIG 0000001 +# define NOFLSH 0000200 +# define TOSTOP 0001000 + +# define VEOF 4 /* also VMIN -- thanks, AT&T */ +# define VEOL 5 /* also VTIME -- thanks again */ +# define VERASE 2 +# define VINTR 0 +# define VKILL 3 +# define VMIN 4 /* also VEOF */ +# define VQUIT 1 +# define VSUSP 10 +# define VTIME 5 /* also VEOL */ +# define VSTART 11 +# define VSTOP 12 + +# define B0 0 +# define B50 50 +# define B75 75 +# define B110 110 +# define B134 134 +# define B150 150 +# define B200 200 +# define B300 300 +# define B600 600 +# define B1200 1200 +# define B1800 1800 +# define B2400 2400 +# define B4800 4800 +# define B9600 9600 +# define B19200 19200 +# define B38400 38400 +# define B57600 57600 +# define B115200 115200 + +typedef unsigned char cc_t; +typedef unsigned short tcflag_t; +typedef unsigned long speed_t; + +struct termios { + tcflag_t c_iflag; + tcflag_t c_oflag; + tcflag_t c_cflag; + tcflag_t c_lflag; + char c_line; + cc_t c_cc[NCCS]; + speed_t c_ispeed; + speed_t c_ospeed; +}; + +# ifndef _NO_MACROS + +# define cfgetospeed(tp) ((tp)->c_ospeed) +# define cfgetispeed(tp) ((tp)->c_ispeed) +# define cfsetospeed(tp,s) (((tp)->c_ospeed = (s)), 0) +# define cfsetispeed(tp,s) (((tp)->c_ispeed = (s)), 0) +# define tcdrain(fd) _ioctl (fd, _TCSBRK, 1) +# endif /* _NO_MACROS */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_TERMIOS_H */ + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_alarm_start.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_alarm_start.c index 7739959..2bd672f 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_alarm_start.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_alarm_start.c @@ -1,112 +1,112 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#include "sys/alt_alarm.h" -#include "sys/alt_irq.h" - -/* - * alt_alarm_start is called to register an alarm with the system. The - * "alarm" structure passed as an input argument does not need to be - * initialised by the user. This is done within this function. - * - * The remaining input arguments are: - * - * nticks - The time to elapse until the alarm executes. This is specified in - * system clock ticks. - * callback - The function to run when the indicated time has elapsed. - * context - An opaque value, passed to the callback function. -* - * Care should be taken when defining the callback function since it is - * likely to execute in interrupt context. In particular, this mean that - * library calls like printf() should not be made, since they can result in - * deadlock. - * - * The interval to be used for the next callback is the return - * value from the callback function. A return value of zero indicates that the - * alarm should be unregistered. - * - * alt_alarm_start() will fail if the timer facility has not been enabled - * (i.e. there is no system clock). Failure is indicated by a negative return - * value. - */ - -int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, - alt_u32 (*callback) (void* context), - void* context) -{ - alt_irq_context irq_context; - alt_u32 current_nticks = 0; - - if (alt_ticks_per_second ()) - { - if (alarm) - { - alarm->callback = callback; - alarm->context = context; - - irq_context = alt_irq_disable_all (); - - current_nticks = alt_nticks(); - - alarm->time = nticks + current_nticks + 1; - - /* - * If the desired alarm time causes a roll-over, set the rollover - * flag. This will prevent the subsequent tick event from causing - * an alarm too early. - */ - if(alarm->time < current_nticks) - { - alarm->rollover = 1; - } - else - { - alarm->rollover = 0; - } - - alt_llist_insert (&alt_alarm_list, &alarm->llist); - alt_irq_enable_all (irq_context); - - return 0; - } - else - { - return -EINVAL; - } - } - else - { - return -ENOTSUP; - } -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_irq.h" + +/* + * alt_alarm_start is called to register an alarm with the system. The + * "alarm" structure passed as an input argument does not need to be + * initialised by the user. This is done within this function. + * + * The remaining input arguments are: + * + * nticks - The time to elapse until the alarm executes. This is specified in + * system clock ticks. + * callback - The function to run when the indicated time has elapsed. + * context - An opaque value, passed to the callback function. +* + * Care should be taken when defining the callback function since it is + * likely to execute in interrupt context. In particular, this mean that + * library calls like printf() should not be made, since they can result in + * deadlock. + * + * The interval to be used for the next callback is the return + * value from the callback function. A return value of zero indicates that the + * alarm should be unregistered. + * + * alt_alarm_start() will fail if the timer facility has not been enabled + * (i.e. there is no system clock). Failure is indicated by a negative return + * value. + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + + if (alt_ticks_per_second ()) + { + if (alarm) + { + alarm->callback = callback; + alarm->context = context; + + irq_context = alt_irq_disable_all (); + + current_nticks = alt_nticks(); + + alarm->time = nticks + current_nticks + 1; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + { + alarm->rollover = 1; + } + else + { + alarm->rollover = 0; + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + alt_irq_enable_all (irq_context); + + return 0; + } + else + { + return -EINVAL; + } + } + else + { + return -ENOTSUP; + } +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_busy_sleep.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_busy_sleep.c index 561c0be..1b910a5 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_busy_sleep.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_busy_sleep.c @@ -1,133 +1,133 @@ -/* - * Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * ------------ - * - * Altera does not recommend, suggest or require that this reference design - * file be used in conjunction or combination with any other product. - * - * alt_busy_sleep.c - Microsecond delay routine which uses a calibrated busy - * loop to perform the delay. This is used to implement - * usleep for both uC/OS-II and the standalone HAL. - * - * Author PRR - * - * Calibrated delay with no timer required - * - * The ASM instructions in the routine are equivalent to - * - * for (i=0;i -#include - -#include "system.h" -#include "alt_types.h" - -#include "priv/alt_busy_sleep.h" - -unsigned int alt_busy_sleep (unsigned int us) -{ -/* - * Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software - * is built targetting ModelSim RTL simulation, the delay will be - * skipped to speed up simulation. - */ -#ifndef ALT_SIM_OPTIMIZE - int i; - int big_loops; - alt_u32 cycles_per_loop; - - if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny")) - { - cycles_per_loop = 9; - } - else - { - cycles_per_loop = 3; - } - - - big_loops = us / (INT_MAX/ - (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); - - if (big_loops) - { - for(i=0;i +#include + +#include "system.h" +#include "alt_types.h" + +#include "priv/alt_busy_sleep.h" + +unsigned int alt_busy_sleep (unsigned int us) +{ +/* + * Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software + * is built targetting ModelSim RTL simulation, the delay will be + * skipped to speed up simulation. + */ +#ifndef ALT_SIM_OPTIMIZE + int i; + int big_loops; + alt_u32 cycles_per_loop; + + if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny")) + { + cycles_per_loop = 9; + } + else + { + cycles_per_loop = 3; + } + + + big_loops = us / (INT_MAX/ + (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); + + if (big_loops) + { + for(i=0;i - -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "priv/alt_file.h" -#include "os/alt_syscall.h" - -#ifdef ALT_USE_DIRECT_DRIVERS - -int ALT_CLOSE (int fildes) -{ - /* Generate a link time warning, should this function ever be called. */ - - ALT_STUB_WARNING(close); - - /* Indicate an error */ - - ALT_ERRNO = ENOSYS; - return -1; -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -/* - * close() is called by an application to release a file descriptor. If the - * associated file system/device has a close() callback function registered - * then this called. The file descriptor is then marked as free. - * - * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h - */ - -int ALT_CLOSE (int fildes) -{ - alt_fd* fd; - int rval; - - /* - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; - - if (fd) - { - /* - * If the associated file system/device has a close function, call it so - * that any necessary cleanup code can run. - */ - - rval = (fd->dev->close) ? fd->dev->close(fd) : 0; - - /* Free the file descriptor structure and return. */ - - alt_release_fd (fildes); - if (rval < 0) - { - ALT_ERRNO = -rval; - return -1; - } - return 0; - } - else - { - ALT_ERRNO = EBADFD; - return -1; - } -} - -#endif /* ALT_USE_DIRECT_DRIVERS */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_CLOSE (int fildes) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(close); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * close() is called by an application to release a file descriptor. If the + * associated file system/device has a close() callback function registered + * then this called. The file descriptor is then marked as free. + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + + if (fd) + { + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + if (rval < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return 0; + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush.c index 7ecc91a..8afe062 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush.c @@ -1,97 +1,97 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "nios2.h" -#include "system.h" - -#include "alt_types.h" -#include "sys/alt_cache.h" - -/* - * Nios II version 1.2 and newer supports the "flush by address" instruction, in - * addition to the "flush by line" instruction provided by older versions of - * the core. This newer instruction is used by preference when it is - * available. - */ - -#ifdef NIOS2_FLUSHDA_SUPPORTED -#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushda (%0)" :: "r" (i)); -#else -#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushd (%0)" :: "r" (i)); -#endif /* NIOS2_FLUSHDA_SUPPORTED */ - -/* - * alt_dcache_flush() is called to flush the data cache for a memory - * region of length "len" bytes, starting at address "start". - * - * Any dirty lines in the data cache are written back to memory. - */ - -void alt_dcache_flush (void* start, alt_u32 len) -{ -#if NIOS2_DCACHE_SIZE > 0 - - char* i; - char* end; - - /* - * This is the most we would ever need to flush. - * - * SPR 196942, 2006.01.13: The cache flush loop below will use the - * 'flushda' instruction if its available; in that case each line - * must be flushed individually, and thus 'len' cannot be trimmed. - */ - #ifndef NIOS2_FLUSHDA_SUPPORTED - if (len > NIOS2_DCACHE_SIZE) - { - len = NIOS2_DCACHE_SIZE; - } - #endif - - end = ((char*) start) + len; - - for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) - { - ALT_FLUSH_DATA(i); - } - - /* - * For an unaligned flush request, we've got one more line left. - * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a - * multiple of 2 (which it always is). - */ - - if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) - { - ALT_FLUSH_DATA(i); - } - -#endif /* NIOS2_DCACHE_SIZE > 0 */ -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * Nios II version 1.2 and newer supports the "flush by address" instruction, in + * addition to the "flush by line" instruction provided by older versions of + * the core. This newer instruction is used by preference when it is + * available. + */ + +#ifdef NIOS2_FLUSHDA_SUPPORTED +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushda (%0)" :: "r" (i)); +#else +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushd (%0)" :: "r" (i)); +#endif /* NIOS2_FLUSHDA_SUPPORTED */ + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are written back to memory. + */ + +void alt_dcache_flush (void* start, alt_u32 len) +{ +#if NIOS2_DCACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + * + * SPR 196942, 2006.01.13: The cache flush loop below will use the + * 'flushda' instruction if its available; in that case each line + * must be flushed individually, and thus 'len' cannot be trimmed. + */ + #ifndef NIOS2_FLUSHDA_SUPPORTED + if (len > NIOS2_DCACHE_SIZE) + { + len = NIOS2_DCACHE_SIZE; + } + #endif + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA(i); + } + +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush_all.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush_all.c index 6529231..80735b7 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush_all.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush_all.c @@ -1,51 +1,51 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "nios2.h" -#include "system.h" - -#include "alt_types.h" -#include "sys/alt_cache.h" - -/* - * alt_dcache_flush_all() is called to flush the entire data cache. - */ - -void alt_dcache_flush_all (void) -{ -#if NIOS2_DCACHE_SIZE > 0 - char* i; - - for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) - { - __asm__ volatile ("flushd (%0)" :: "r" (i)); - } -#endif /* NIOS2_DCACHE_SIZE > 0 */ -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush_no_writeback.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush_no_writeback.c index c65ca7d..3b277d2 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush_no_writeback.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dcache_flush_no_writeback.c @@ -1,88 +1,88 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "nios2.h" -#include "system.h" - -#include "alt_types.h" -#include "sys/alt_cache.h" - -/* - * The INITDA instruction was added to Nios II in the 8.0 release. - * - * The INITDA instruction has one of the following possible behaviors - * depending on the processor configuration: - * 1) Flushes a line by address but does NOT write back dirty data. - * Occurs when a data cache is present that supports INITDA. - * The macro NIOS2_INITDA_SUPPORTED is defined in system.h. - * 2) Takes an unimplemented instruction exception. - * Occurs when a data cache is present that doesn't support INITDA. - * 3) Performs no operation - * Occurs when there is no data cache present. - * The macro NIOS2_DCACHE_SIZE is 0 in system.h. - */ - -#define ALT_FLUSH_DATA_NO_WRITEBACK(i) \ - __asm__ volatile ("initda (%0)" :: "r" (i)); - -/* - * alt_dcache_flush_no_writeback() is called to flush the data cache for a - * memory region of length "len" bytes, starting at address "start". - * - * Any dirty lines in the data cache are NOT written back to memory. - * Make sure you really want this behavior. If you aren't 100% sure, - * use the alt_dcache_flush() routine instead. - */ - -void alt_dcache_flush_no_writeback (void* start, alt_u32 len) -{ -#if defined(NIOS2_INITDA_SUPPORTED) - - char* i; - char* end = ((char*) start) + len; - - for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) - { - ALT_FLUSH_DATA_NO_WRITEBACK(i); - } - - /* - * For an unaligned flush request, we've got one more line left. - * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a - * multiple of 2 (which it always is). - */ - - if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) - { - ALT_FLUSH_DATA_NO_WRITEBACK(i); - } - -#endif /* NIOS2_INITDA_SUPPORTED */ -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * The INITDA instruction was added to Nios II in the 8.0 release. + * + * The INITDA instruction has one of the following possible behaviors + * depending on the processor configuration: + * 1) Flushes a line by address but does NOT write back dirty data. + * Occurs when a data cache is present that supports INITDA. + * The macro NIOS2_INITDA_SUPPORTED is defined in system.h. + * 2) Takes an unimplemented instruction exception. + * Occurs when a data cache is present that doesn't support INITDA. + * 3) Performs no operation + * Occurs when there is no data cache present. + * The macro NIOS2_DCACHE_SIZE is 0 in system.h. + */ + +#define ALT_FLUSH_DATA_NO_WRITEBACK(i) \ + __asm__ volatile ("initda (%0)" :: "r" (i)); + +/* + * alt_dcache_flush_no_writeback() is called to flush the data cache for a + * memory region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are NOT written back to memory. + * Make sure you really want this behavior. If you aren't 100% sure, + * use the alt_dcache_flush() routine instead. + */ + +void alt_dcache_flush_no_writeback (void* start, alt_u32 len) +{ +#if defined(NIOS2_INITDA_SUPPORTED) + + char* i; + char* end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + +#endif /* NIOS2_INITDA_SUPPORTED */ +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dev.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dev.c index ebc15e5..92f3f2a 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dev.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dev.c @@ -1,149 +1,149 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include -#include -#include -#include - -#include "sys/alt_dev.h" -#include "priv/alt_file.h" - -#include "alt_types.h" - -#include "system.h" - -/* - * This file contains the data constructs used to control access to device and - * filesytems. - */ - -/* - * "alt_fs_list" is the head of a linked list of registered filesystems. It is - * initialised as an empty list. New entries can be added using the - * alt_fs_reg() function. - */ - -ALT_LLIST_HEAD(alt_fs_list); - - -/* - * "alt_dev_list" is the head of a linked list of registered devices. It is - * configured at startup to include a single device, "alt_dev_null". This - * device is discussed below. - */ - -extern alt_dev alt_dev_null; /* forward declaration */ - -alt_llist alt_dev_list = {&alt_dev_null.llist, &alt_dev_null.llist}; - -/* - * alt_dev_null_write() is the implementation of the write() function used - * by the alt_dev_null device. It simple discards all data passed to it, and - * indicates that the data has been successfully transmitted. - */ - -static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) -{ - return len; -} - -/* - * "alt_dev_null" is used to allow output to be redirected to nowhere. It is - * the only device registered before the call to alt_sys_init(). At startup - * stin, stdout & stderr are all directed towards this device so that library - * calls like printf() will be safe but inefectual. - */ - -alt_dev alt_dev_null = { - { - &alt_dev_list, - &alt_dev_list - }, - "/dev/null", - NULL, /* open */ - NULL, /* close */ - NULL, /* write */ - alt_dev_null_write, /* write */ - NULL, /* lseek */ - NULL, /* fstat */ - NULL /* ioctl */ - }; - -/* - * "alt_fd_list_lock" is a semaphore used to control access to the file - * descriptor list. This is used to ensure that access to the list is thread - * safe. - */ - -ALT_SEM(alt_fd_list_lock) - -/* - * "alt_max_fd" is used to make access to the file descriptor list more - * efficent. It is set to be the value of the highest allocated file - * descriptor. This saves having to search the entire pool of unallocated - * file descriptors when looking for a match. - */ - -alt_32 alt_max_fd = -1; - -/* - * "alt_fd_list" is the file descriptor pool. The first three entries in the - * array are configured as standard in, standard out, and standard error. These - * are all initialised so that accesses are directed to the alt_dev_null - * device. The remaining file descriptors are initialised as unallocated. - * - * The maximum number of file descriptors within the system is specified by the - * user defined macro "ALT_MAX_FD". This is defined in "system.h", which is - * auto-genereated using the projects PTF and STF files. - */ - -alt_fd alt_fd_list[ALT_MAX_FD] = - { - { - &alt_dev_null, /* standard in */ - 0, - 0 - }, - { - &alt_dev_null, /* standard out */ - 0, - 0 - }, - { - &alt_dev_null, /* standard error */ - 0, - 0 - } - /* all other elements are set to zero */ - }; +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * This file contains the data constructs used to control access to device and + * filesytems. + */ + +/* + * "alt_fs_list" is the head of a linked list of registered filesystems. It is + * initialised as an empty list. New entries can be added using the + * alt_fs_reg() function. + */ + +ALT_LLIST_HEAD(alt_fs_list); + + +/* + * "alt_dev_list" is the head of a linked list of registered devices. It is + * configured at startup to include a single device, "alt_dev_null". This + * device is discussed below. + */ + +extern alt_dev alt_dev_null; /* forward declaration */ + +alt_llist alt_dev_list = {&alt_dev_null.llist, &alt_dev_null.llist}; + +/* + * alt_dev_null_write() is the implementation of the write() function used + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + return len; +} + +/* + * "alt_dev_null" is used to allow output to be redirected to nowhere. It is + * the only device registered before the call to alt_sys_init(). At startup + * stin, stdout & stderr are all directed towards this device so that library + * calls like printf() will be safe but inefectual. + */ + +alt_dev alt_dev_null = { + { + &alt_dev_list, + &alt_dev_list + }, + "/dev/null", + NULL, /* open */ + NULL, /* close */ + NULL, /* write */ + alt_dev_null_write, /* write */ + NULL, /* lseek */ + NULL, /* fstat */ + NULL /* ioctl */ + }; + +/* + * "alt_fd_list_lock" is a semaphore used to control access to the file + * descriptor list. This is used to ensure that access to the list is thread + * safe. + */ + +ALT_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is used to make access to the file descriptor list more + * efficent. It is set to be the value of the highest allocated file + * descriptor. This saves having to search the entire pool of unallocated + * file descriptors when looking for a match. + */ + +alt_32 alt_max_fd = -1; + +/* + * "alt_fd_list" is the file descriptor pool. The first three entries in the + * array are configured as standard in, standard out, and standard error. These + * are all initialised so that accesses are directed to the alt_dev_null + * device. The remaining file descriptors are initialised as unallocated. + * + * The maximum number of file descriptors within the system is specified by the + * user defined macro "ALT_MAX_FD". This is defined in "system.h", which is + * auto-genereated using the projects PTF and STF files. + */ + +alt_fd alt_fd_list[ALT_MAX_FD] = + { + { + &alt_dev_null, /* standard in */ + 0, + 0 + }, + { + &alt_dev_null, /* standard out */ + 0, + 0 + }, + { + &alt_dev_null, /* standard error */ + 0, + 0 + } + /* all other elements are set to zero */ + }; diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dev_llist_insert.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dev_llist_insert.c index fa7239d..5e8a952 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dev_llist_insert.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dev_llist_insert.c @@ -1,59 +1,59 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "priv/alt_dev_llist.h" -#include "sys/alt_errno.h" - -/* - * - */ - -int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) -{ - /* - * check that the device exists, and that it has a valid name. - */ - - if (!dev || !dev->name) - { - ALT_ERRNO = EINVAL; - return -EINVAL; - } - - /* - * register the device. - */ - - alt_llist_insert(list, &dev->llist); - - return 0; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" +#include "sys/alt_errno.h" + +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + { + ALT_ERRNO = EINVAL; + return -EINVAL; + } + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + + return 0; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dma_rxchan_open.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dma_rxchan_open.c index 6ea3b78..5d461d9 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dma_rxchan_open.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dma_rxchan_open.c @@ -1,63 +1,63 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_dma.h" -#include "sys/alt_errno.h" -#include "priv/alt_file.h" - -/* - * The list of registered DMA receive channels. - */ - -ALT_LLIST_HEAD(alt_dma_rxchan_list); - -/* - * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for - * a DMA transmit device. The name is the name of the associated physical - * device (e.g. "/dev/dma_0"). - * - * The return value will be NULL on failure, and non-NULL otherwise. - */ - -alt_dma_rxchan alt_dma_rxchan_open (const char* name) -{ - alt_dma_rxchan dev; - - dev = (alt_dma_rxchan) alt_find_dev (name, &alt_dma_rxchan_list); - - if (!dev) - { - ALT_ERRNO = ENODEV; - } - - return dev; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered DMA receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_rxchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_rxchan alt_dma_rxchan_open (const char* name) +{ + alt_dma_rxchan dev; + + dev = (alt_dma_rxchan) alt_find_dev (name, &alt_dma_rxchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dma_txchan_open.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dma_txchan_open.c index f41fa81..99f9181 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dma_txchan_open.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_dma_txchan_open.c @@ -1,63 +1,63 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_dma.h" -#include "sys/alt_errno.h" -#include "priv/alt_file.h" - -/* - * The list of registered receive channels. - */ - -ALT_LLIST_HEAD(alt_dma_txchan_list); - -/* - * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for - * a DMA transmit device. The name is the name of the associated physical - * device (e.g. "/dev/dma_0"). - * - * The return value will be NULL on failure, and non-NULL otherwise. - */ - -alt_dma_txchan alt_dma_txchan_open (const char* name) -{ - alt_dma_txchan dev; - - dev = (alt_dma_txchan) alt_find_dev (name, &alt_dma_txchan_list); - - if (!dev) - { - ALT_ERRNO = ENODEV; - } - - return dev; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_txchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_txchan alt_dma_txchan_open (const char* name) +{ + alt_dma_txchan dev; + + dev = (alt_dma_txchan) alt_find_dev (name, &alt_dma_txchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_do_ctors.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_do_ctors.c index ff5a1f7..be1c134 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_do_ctors.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_do_ctors.c @@ -1,64 +1,64 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * -* * -* Overriding HAL Functions * -* * -* To provide your own implementation of a HAL function, include the file in * -* your Nios II IDE application project. When building the executable, the * -* Nios II IDE finds your function first, and uses it in place of the HAL * -* version. * -* * -******************************************************************************/ - -/* - * - */ - -typedef void (*constructor) (void); -extern constructor __CTOR_LIST__[]; -extern constructor __CTOR_END__[]; - -/* - * Run the C++ static constructors. - */ - -void _do_ctors(void) -{ - constructor* ctor; - - for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) - (*ctor) (); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*constructor) (void); +extern constructor __CTOR_LIST__[]; +extern constructor __CTOR_END__[]; + +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + (*ctor) (); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_do_dtors.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_do_dtors.c index 565c99f..b61166a 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_do_dtors.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_do_dtors.c @@ -1,64 +1,64 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * -* * -* Overriding HAL Functions * -* * -* To provide your own implementation of a HAL function, include the file in * -* your Nios II IDE application project. When building the executable, the * -* Nios II IDE finds your function first, and uses it in place of the HAL * -* version. * -* * -******************************************************************************/ - -/* - * - */ - -typedef void (*destructor) (void); -extern destructor __DTOR_LIST__[]; -extern destructor __DTOR_END__[]; - -/* - * Run the C++ static destructors. - */ - -void _do_dtors(void) -{ - destructor* dtor; - - for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) - (*dtor) (); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*destructor) (void); +extern destructor __DTOR_LIST__[]; +extern destructor __DTOR_END__[]; + +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + (*dtor) (); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_env_lock.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_env_lock.c index fc25a0c..0c5d522 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_env_lock.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_env_lock.c @@ -1,53 +1,53 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -/* - * These are the empty env lock/unlock stubs required by newlib. These are - * used to make accesses to environment variables thread safe. The default HAL - * configuration is single threaded, so there is nothing to do here. Note that - * this requires that environment variables are never manipulated by an interrupt - * service routine. - */ - -void __env_lock ( struct _reent *_r ) -{ -} - -/* - * - */ - -void __env_unlock ( struct _reent *_r ) -{ -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +/* + * These are the empty env lock/unlock stubs required by newlib. These are + * used to make accesses to environment variables thread safe. The default HAL + * configuration is single threaded, so there is nothing to do here. Note that + * this requires that environment variables are never manipulated by an interrupt + * service routine. + */ + +void __env_lock ( struct _reent *_r ) +{ +} + +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_environ.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_environ.c index 404efc4..780635a 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_environ.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_environ.c @@ -1,42 +1,42 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "os/alt_syscall.h" - -/* - * These are the environment variables passed to the C code. By default there - * are no variables registered. An application can manipulate this list using - * getenv() and setenv(). - */ - -char *__env[1] = { 0 }; -char **ALT_ENVIRON = __env; +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * These are the environment variables passed to the C code. By default there + * are no variables registered. An application can manipulate this list using + * getenv() and setenv(). + */ + +char *__env[1] = { 0 }; +char **ALT_ENVIRON = __env; diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_errno.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_errno.c index 1d8368d..4c5ca3e 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_errno.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_errno.c @@ -1,44 +1,44 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/* - * This file defines the alt_errno global variable. See comments in - * alt_errno.h for the use of this variable. - */ - - -#include "sys/alt_errno.h" -#include "alt_types.h" - -extern int ALT_WEAK *__errno (void); - -int* (*alt_errno) (void) = __errno; +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file defines the alt_errno global variable. See comments in + * alt_errno.h for the use of this variable. + */ + + +#include "sys/alt_errno.h" +#include "alt_types.h" + +extern int ALT_WEAK *__errno (void); + +int* (*alt_errno) (void) = __errno; diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_entry.S b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_entry.S index 3afab93..486465b 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_entry.S +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_entry.S @@ -1,360 +1,360 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "system.h" - -/* - * This is the exception entry point code, which saves all the caller saved - * registers and then handles the appropriate exception. It should be pulled - * in using a .globl from all the exception handler routines. This scheme is - * used so that if an interrupt is never registered, then this code will not - * appear in the generated executable, thereby improving code footprint. - * - * If an external interrpt controller (EIC) is present, it will supply an - * interrupt vector address to the processor when an interrupt occurs. For - * The Altera Vectored Interrupt Controller (VIC) driver will establish a - * vector table and the processor will jump directly to the appropriate - * table entry, funnel routine, and then user ISR. This will bypass this code - * in entirety. This code might still be linked into a system with an EIC, - * but would then be used only for non-interrupt exceptions. - */ - - /* - * Explicitly allow the use of r1 (the assembler temporary register) - * within this code. This register is normally reserved for the use of - * the assembler. - */ - .set noat - - /* - * The top and bottom of the exception stack - */ -#ifdef ALT_EXCEPTION_STACK - - .globl __alt_exception_stack_pointer - -#ifdef ALT_STACK_CHECK - - .globl __alt_exception_stack_limit - - /* - * We need to store the value of the stack limit after interrupt somewhere. - */ - .globl alt_exception_old_stack_limit - -#endif -#endif - - .section .exceptions.entry.label, "xa" - - .globl alt_exception - .type alt_exception, @function -alt_exception: - - .section .exceptions.entry, "xa" - -#ifdef ALT_EXCEPTION_STACK - -#ifdef ALT_STACK_CHECK - stw et, %gprel(alt_exception_old_stack_limit)(gp) -#endif - - movhi et, %hiadj(__alt_exception_stack_pointer - 80) - addi et, et, %lo(__alt_exception_stack_pointer - 80) - stw sp, 76(et) - mov sp, et - -#ifdef ALT_STACK_CHECK - movhi et, %hiadj(__alt_exception_stack_limit) - addi et, et, %lo(__alt_exception_stack_limit) - stw et, %gprel(alt_stack_limit_value)(gp) -#endif - -#else - /* - * Process an exception. For all exceptions we must preserve all - * caller saved registers on the stack (See the Nios2 ABI - * documentation for details). - */ - - addi sp, sp, -76 - -#ifdef ALT_STACK_CHECK - - bltu sp, et, .Lstack_overflow - -#endif - -#endif - - stw ra, 0(sp) - - /* - * Leave a gap in the stack frame at 4(sp) for the muldiv handler to - * store zero into. - */ - - stw r1, 8(sp) - stw r2, 12(sp) - stw r3, 16(sp) - stw r4, 20(sp) - stw r5, 24(sp) - stw r6, 28(sp) - stw r7, 32(sp) - - rdctl r5, estatus - - stw r8, 36(sp) - stw r9, 40(sp) - stw r10, 44(sp) - stw r11, 48(sp) - stw r12, 52(sp) - stw r13, 56(sp) - stw r14, 60(sp) - stw r15, 64(sp) - - /* - * ea-4 contains the address of the instruction being executed - * when the exception occured. For interrupt exceptions, we will - * will be re-issue the isntruction. Store it in 72(sp) - */ - stw r5, 68(sp) /* estatus */ - addi r15, ea, -4 /* instruction that caused exception */ - stw r15, 72(sp) - - /* - * The interrupt testing code (.exceptions.irqtest) will be - * linked here. If the Internal Interrupt Controller (IIC) is - * present (an EIC is not present), the presense of an interrupt - * is determined by examining CPU control registers or an interrupt - * custom instruction, if present. - * - * If the IIC is used and an interrupt is active, the code linked - * here will call the HAL IRQ handler (alt_irq_handler()) which - * successively calls registered interrupt handler(s) until no - * interrupts remain pending. It then jumps to .exceptions.exit. If - * there is no interrupt then it continues to .exception.notirq, below. - */ - - .section .exceptions.notirq, "xa" - - /* - * Prepare to service unimplemtned instructions or traps, - * each of which is optionally inked into section .exceptions.soft, - * which will preceed .exceptions.unknown below. - * - * Unlike interrupts, we want to skip the exception-causing instructon - * upon completion, so we write ea (address of instruction *after* - * the one where the exception occured) into 72(sp). The actual - * instruction that caused the exception is written in r2, which these - * handlers will utilize. - */ - stw ea, 72(sp) /* Don't re-issue */ - ldw r2, -4(ea) /* Instruction that caused exception */ - - /* - * Other exception handling code, if enabled, will be linked here. - * This includes unimplemted (multiply/divide) instruction support - * (a BSP generaton option), and a trap handler (that would typically - * be augmented with user-specific code). These are not linked in by - * default. - */ - - /* - * In the context of linker sections, "unknown" are all exceptions - * not handled by the built-in handlers above (interupt, and trap or - * unimplemented instruction decoding, if enabled). - * - * Advanced exception types can be serviced by registering a handler. - * To do so, enable the "Enable Instruction-related Exception API" HAL - * BSP setting. If this setting is disabled, this handler code will - * either break (if the debug core is present) or enter an infinite - * loop because we don't how how to handle the exception. - */ - .section .exceptions.unknown -#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API - /* - * The C-based HAL routine alt_instruction_exception_entry() will - * attempt to service the exception by calling a user-registered - * exception handler using alt_instruction_exception_register(). - * If no handler was registered it will either break (if the - * debugger is present) or go into an infinite loop since the - * handling behavior is undefined; in that case we will not return here. - */ - - /* Load exception-causing address as first argument (r4) */ - addi r4, ea, -4 - - /* Call the instruction-exception entry */ - call alt_instruction_exception_entry - - /* - * If alt_instruction_exception_entry() returned, the exception was - * serviced by a user-registered routine. Its return code (now in r2) - * indicates whether to re-issue or skip the exception-causing - * instruction - * - * Return code was 0: Skip. The instruction after the exception is - * already stored in 72(sp). - */ - bne r2, r0, .Lexception_exit - - /* - * Otherwise, modify 72(sp) to re-issue the instruction that caused the - * exception. - */ - addi r15, ea, -4 /* instruction that caused exception */ - stw r15, 72(sp) - -#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */ - - /* - * We got here because an instruction-related exception occured, but the - * handler API was not compiled in. We do not presume to know how to - * handle it. If the debugger is present, break, otherwise hang. - * - * If you get here then one of the following could have happened: - * - * - An instruction-generated exception occured, and the processor - * does not have the extra exceptions feature enabled, or you - * have not registered a handler using - * alt_instruction_exception_register() - * - * Some examples of instruction-generated exceptions and why they - * might occur: - * - * - Your program could have been compiled for a full-featured - * Nios II core, but it is running on a smaller core, and - * instruction emulation has been disabled by defining - * ALT_NO_INSTRUCTION_EMULATION. - * - * You can work around the problem by re-enabling instruction - * emulation, or you can figure out why your program is being - * compiled for a system other than the one that it is running on. - * - * - Your program has executed a trap instruction, but has not - * implemented a handler for this instruction. - * - * - Your program has executed an illegal instruction (one which is - * not defined in the instruction set). - * - * - Your processor includes an MMU or MPU, and you have enabled it - * before registering an exception handler to service exceptions it - * generates. - * - * The problem could also be hardware related: - * - If your hardware is broken and is generating spurious interrupts - * (a peripheral which negates its interrupt output before its - * interrupt handler has been executed will cause spurious - * interrupts) - */ -#ifdef NIOS2_HAS_DEBUG_STUB - /* - * Either tell the user now (if there is a debugger attached) or go into - * the debug monitor which will loop until a debugger is attached. - */ - break -#else - /* - * If there is no debug stub then a BREAK will probably cause a reboot. - * An infinate loop will probably be more useful. - */ -0: - br 0b -#endif /* NIOS2_HAS_DEBUG_STUB */ - -#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ - - .section .exceptions.exit.label -.Lexception_exit: - - .section .exceptions.exit, "xa" - - /* - * Restore the saved registers, so that all general purpose registers - * have been restored to their state at the time the interrupt occured. - */ - - ldw r5, 68(sp) - ldw ea, 72(sp) /* This becomes the PC once eret is executed */ - ldw ra, 0(sp) - - wrctl estatus, r5 - - ldw r1, 8(sp) - ldw r2, 12(sp) - ldw r3, 16(sp) - ldw r4, 20(sp) - ldw r5, 24(sp) - ldw r6, 28(sp) - ldw r7, 32(sp) - -#ifdef ALT_EXCEPTION_STACK -#ifdef ALT_STACK_CHECK - ldw et, %gprel(alt_exception_old_stack_limit)(gp) -#endif -#endif - - ldw r8, 36(sp) - ldw r9, 40(sp) - ldw r10, 44(sp) - ldw r11, 48(sp) - ldw r12, 52(sp) - ldw r13, 56(sp) - ldw r14, 60(sp) - ldw r15, 64(sp) - -#ifdef ALT_EXCEPTION_STACK - -#ifdef ALT_STACK_CHECK - stw et, %gprel(alt_stack_limit_value)(gp) - stw zero, %gprel(alt_exception_old_stack_limit)(gp) -#endif - - ldw sp, 76(sp) - -#else - addi sp, sp, 76 - -#endif - - /* - * Return to the interrupted instruction. - */ - - eret - -#ifdef ALT_STACK_CHECK - -.Lstack_overflow: - break 3 - -#endif - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the exception entry point code, which saves all the caller saved + * registers and then handles the appropriate exception. It should be pulled + * in using a .globl from all the exception handler routines. This scheme is + * used so that if an interrupt is never registered, then this code will not + * appear in the generated executable, thereby improving code footprint. + * + * If an external interrpt controller (EIC) is present, it will supply an + * interrupt vector address to the processor when an interrupt occurs. For + * The Altera Vectored Interrupt Controller (VIC) driver will establish a + * vector table and the processor will jump directly to the appropriate + * table entry, funnel routine, and then user ISR. This will bypass this code + * in entirety. This code might still be linked into a system with an EIC, + * but would then be used only for non-interrupt exceptions. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + + /* + * The top and bottom of the exception stack + */ +#ifdef ALT_EXCEPTION_STACK + + .globl __alt_exception_stack_pointer + +#ifdef ALT_STACK_CHECK + + .globl __alt_exception_stack_limit + + /* + * We need to store the value of the stack limit after interrupt somewhere. + */ + .globl alt_exception_old_stack_limit + +#endif +#endif + + .section .exceptions.entry.label, "xa" + + .globl alt_exception + .type alt_exception, @function +alt_exception: + + .section .exceptions.entry, "xa" + +#ifdef ALT_EXCEPTION_STACK + +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + movhi et, %hiadj(__alt_exception_stack_pointer - 80) + addi et, et, %lo(__alt_exception_stack_pointer - 80) + stw sp, 76(et) + mov sp, et + +#ifdef ALT_STACK_CHECK + movhi et, %hiadj(__alt_exception_stack_limit) + addi et, et, %lo(__alt_exception_stack_limit) + stw et, %gprel(alt_stack_limit_value)(gp) +#endif + +#else + /* + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios2 ABI + * documentation for details). + */ + + addi sp, sp, -76 + +#ifdef ALT_STACK_CHECK + + bltu sp, et, .Lstack_overflow + +#endif + +#endif + + stw ra, 0(sp) + + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + stw r1, 8(sp) + stw r2, 12(sp) + stw r3, 16(sp) + stw r4, 20(sp) + stw r5, 24(sp) + stw r6, 28(sp) + stw r7, 32(sp) + + rdctl r5, estatus + + stw r8, 36(sp) + stw r9, 40(sp) + stw r10, 44(sp) + stw r11, 48(sp) + stw r12, 52(sp) + stw r13, 56(sp) + stw r14, 60(sp) + stw r15, 64(sp) + + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + + /* + * The interrupt testing code (.exceptions.irqtest) will be + * linked here. If the Internal Interrupt Controller (IIC) is + * present (an EIC is not present), the presense of an interrupt + * is determined by examining CPU control registers or an interrupt + * custom instruction, if present. + * + * If the IIC is used and an interrupt is active, the code linked + * here will call the HAL IRQ handler (alt_irq_handler()) which + * successively calls registered interrupt handler(s) until no + * interrupts remain pending. It then jumps to .exceptions.exit. If + * there is no interrupt then it continues to .exception.notirq, below. + */ + + .section .exceptions.notirq, "xa" + + /* + * Prepare to service unimplemtned instructions or traps, + * each of which is optionally inked into section .exceptions.soft, + * which will preceed .exceptions.unknown below. + * + * Unlike interrupts, we want to skip the exception-causing instructon + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* Don't re-issue */ + ldw r2, -4(ea) /* Instruction that caused exception */ + + /* + * Other exception handling code, if enabled, will be linked here. + * This includes unimplemted (multiply/divide) instruction support + * (a BSP generaton option), and a trap handler (that would typically + * be augmented with user-specific code). These are not linked in by + * default. + */ + + /* + * In the context of linker sections, "unknown" are all exceptions + * not handled by the built-in handlers above (interupt, and trap or + * unimplemented instruction decoding, if enabled). + * + * Advanced exception types can be serviced by registering a handler. + * To do so, enable the "Enable Instruction-related Exception API" HAL + * BSP setting. If this setting is disabled, this handler code will + * either break (if the debug core is present) or enter an infinite + * loop because we don't how how to handle the exception. + */ + .section .exceptions.unknown +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + /* + * The C-based HAL routine alt_instruction_exception_entry() will + * attempt to service the exception by calling a user-registered + * exception handler using alt_instruction_exception_register(). + * If no handler was registered it will either break (if the + * debugger is present) or go into an infinite loop since the + * handling behavior is undefined; in that case we will not return here. + */ + + /* Load exception-causing address as first argument (r4) */ + addi r4, ea, -4 + + /* Call the instruction-exception entry */ + call alt_instruction_exception_entry + + /* + * If alt_instruction_exception_entry() returned, the exception was + * serviced by a user-registered routine. Its return code (now in r2) + * indicates whether to re-issue or skip the exception-causing + * instruction + * + * Return code was 0: Skip. The instruction after the exception is + * already stored in 72(sp). + */ + bne r2, r0, .Lexception_exit + + /* + * Otherwise, modify 72(sp) to re-issue the instruction that caused the + * exception. + */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + +#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */ + + /* + * We got here because an instruction-related exception occured, but the + * handler API was not compiled in. We do not presume to know how to + * handle it. If the debugger is present, break, otherwise hang. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious + * interrupts) + */ +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break +#else + /* + * If there is no debug stub then a BREAK will probably cause a reboot. + * An infinate loop will probably be more useful. + */ +0: + br 0b +#endif /* NIOS2_HAS_DEBUG_STUB */ + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + + .section .exceptions.exit.label +.Lexception_exit: + + .section .exceptions.exit, "xa" + + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + ldw ra, 0(sp) + + wrctl estatus, r5 + + ldw r1, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + +#ifdef ALT_EXCEPTION_STACK +#ifdef ALT_STACK_CHECK + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif +#endif + + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + +#ifdef ALT_EXCEPTION_STACK + +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_stack_limit_value)(gp) + stw zero, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + ldw sp, 76(sp) + +#else + addi sp, sp, 76 + +#endif + + /* + * Return to the interrupted instruction. + */ + + eret + +#ifdef ALT_STACK_CHECK + +.Lstack_overflow: + break 3 + +#endif + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_muldiv.S b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_muldiv.S index 55617a6..6a794a3 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_muldiv.S +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_muldiv.S @@ -1,583 +1,583 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - - /* - * This is the software multiply/divide handler for Nios2. - */ - - /* - * Provide a label which can be used to pull this file in. - */ - - .section .exceptions.start - .globl alt_exception_muldiv -alt_exception_muldiv: - - /* - * Pull in the entry/exit code. - */ - .globl alt_exception - - - .section .exceptions.soft, "xa" - - - /* INSTRUCTION EMULATION - * --------------------- - * - * Nios II processors generate exceptions for unimplemented instructions. - * The routines below emulate these instructions. Depending on the - * processor core, the only instructions that might need to be emulated - * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu. - * - * The emulations match the instructions, except for the following - * limitations: - * - * 1) The emulation routines do not emulate the use of the exception - * temporary register (et) as a source operand because the exception - * handler already has modified it. - * - * 2) The routines do not emulate the use of the stack pointer (sp) or the - * exception return address register (ea) as a destination because - * modifying these registers crashes the exception handler or the - * interrupted routine. - * - * 3) To save code size, the routines do not emulate the use of the - * breakpoint registers (ba and bt) as operands. - * - * Detailed Design - * --------------- - * - * The emulation routines expect the contents of integer registers r0-r31 - * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The - * routines retrieve source operands from the stack and modify the - * destination register's value on the stack prior to the end of the - * exception handler. Then all registers except the destination register - * are restored to their previous values. - * - * The instruction that causes the exception is found at address -4(ea). - * The instruction's OP and OPX fields identify the operation to be - * performed. - * - * One instruction, muli, is an I-type instruction that is identified by - * an OP field of 0x24. - * - * muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24- - * 27 22 6 0 <-- LSB of field - * - * The remaining emulated instructions are R-type and have an OP field - * of 0x3a. Their OPX fields identify them. - * - * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a- - * 27 22 17 11 6 0 <-- LSB of field - * - * - */ - - - /* - * Split the instruction into its fields. We need 4*A, 4*B, and 4*C as - * offsets to the stack pointer for access to the stored register values. - */ - /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */ - roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */ - roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */ - roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */ - srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */ - xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */ - roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */ - andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */ - xori r3, r3, 0x40 - andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */ - andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */ - andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */ - - /* Now either - * r5 = OP - * r3 = 4*(A^16) - * r4 = IMM16 (sign extended) - * r6 = 4*(B^16) - * r7 = 4*(C^16) - * or - * r5 = OP - */ - - - /* - * Save everything on the stack to make it easy for the emulation routines - * to retrieve the source register operands. The exception entry code has - * already saved some of this so we don't need to do it all again. - */ - - addi sp, sp, -60 - stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */ - /* Register at and r2-r15 have already been saved. */ - - stw r16, 0(sp) - stw r17, 4(sp) - stw r18, 8(sp) - stw r19, 12(sp) - stw r20, 16(sp) - stw r21, 20(sp) - stw r22, 24(sp) - stw r23, 28(sp) - /* et @ 32 - Has already been changed.*/ - /* bt @ 36 - Usually isn't an operand. */ - stw gp, 40(sp) - stw sp, 44(sp) - stw fp, 48(sp) - /* ea @ 52 - Don't bother to save - it's already been changed */ - /* ba @ 56 - Breakpoint register usually isn't an operand */ - /* ra @ 60 - Has already been saved */ - - - /* - * Prepare for either multiplication or division loop. - * They both loop 32 times. - */ - movi r14, 32 - - - /* - * Get the operands. - * - * It is necessary to check for muli because it uses an I-type instruction - * format, while the other instructions are have an R-type format. - */ - add r3, r3, sp /* r3 = address of A-operand. */ - ldw r3, 0(r3) /* r3 = A-operand. */ - movi r15, 0x24 /* muli opcode (I-type instruction format) */ - beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */ - - add r6, r6, sp /* r6 = address of B-operand. */ - ldw r6, 0(r6) /* r6 = B-operand. */ - /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */ - /* IMM16 not needed, align OPX portion */ - /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */ - srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */ - andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */ - - /* Now - * r5 = OP - * r3 = src1 - * r6 = src2 - * r4 = OPX (no longer can be muli) - * r7 = 4*(C^16) - * r14 = loop counter - */ - - /* ILLEGAL-INSTRUCTION EXCEPTION - * ----------------------------- - * - * This code is for Nios II cores that generate exceptions when attempting - * to execute illegal instructions. Nios II cores that support an - * illegal-instruction exception are identified by the presence of the - * macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h . - * - * Remember that illegal instructions are different than unimplemented - * instructions. Illegal instructions are instruction encodings that - * have not been defined by the Nios II ISA. Unimplemented instructions - * are legal instructions that must be emulated by some Nios II cores. - * - * If we get here, all instructions except multiplies and divides - * are illegal. - * - * This code assumes that OP is not muli (because muli was tested above). - * All other multiplies and divides are legal. Anything else is illegal. - */ - - movi r8, 0x3a /* OP for R-type mul* and div* */ - bne r5, r8, .Lnot_muldiv - - /* r15 already is 0x24 */ /* OPX of divu */ - beq r4, r15, .Ldivide - - movi r15,0x27 /* OPX of mul */ - beq r4, r15, .Lmultiply - - movi r15,0x07 /* OPX of mulxuu */ - beq r4, r15, .Lmultiply - - movi r15,0x17 /* OPX of mulxsu */ - beq r4, r15, .Lmultiply - - movi r15,0x1f /* OPX of mulxss */ - beq r4, r15, .Lmultiply - - movi r15,0x25 /* OPX of div */ - bne r4, r15, .Lnot_muldiv - - - /* DIVISION - * - * Divide an unsigned dividend by an unsigned divisor using - * a shift-and-subtract algorithm. The example below shows - * 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a - * single register to store both the dividend and the quotient, - * allowing both values to be shifted with a single instruction. - * - * remainder dividend:quotient - * --------- ----------------- - * initialize 00000000 00101011: - * shift 00000000 0101011:_ - * remainder >= divisor? no 00000000 0101011:0 - * shift 00000000 101011:0_ - * remainder >= divisor? no 00000000 101011:00 - * shift 00000001 01011:00_ - * remainder >= divisor? no 00000001 01011:000 - * shift 00000010 1011:000_ - * remainder >= divisor? no 00000010 1011:0000 - * shift 00000101 011:0000_ - * remainder >= divisor? no 00000101 011:00000 - * shift 00001010 11:00000_ - * remainder >= divisor? yes 00001010 11:000001 - * remainder -= divisor - 00000111 - * ---------- - * 00000011 11:000001 - * shift 00000111 1:000001_ - * remainder >= divisor? yes 00000111 1:0000011 - * remainder -= divisor - 00000111 - * ---------- - * 00000000 1:0000011 - * shift 00000001 :0000011_ - * remainder >= divisor? no 00000001 :00000110 - * - * The quotient is 00000110. - */ - -.Ldivide: - /* - * Prepare for division by assuming the result - * is unsigned, and storing its "sign" as 0. - */ - movi r17, 0 - - - /* Which division opcode? */ - xori r15, r4, 0x25 /* OPX of div */ - bne r15, zero, .Lunsigned_division - - - /* - * OPX is div. Determine and store the sign of the quotient. - * Then take the absolute value of both operands. - */ - xor r17, r3, r6 /* MSB contains sign of quotient */ - bge r3, zero, 0f - sub r3, zero, r3 /* -r3 */ -0: - bge r6, zero, 0f - sub r6, zero, r6 /* -r6 */ -0: - - -.Lunsigned_division: - /* Initialize the unsigned-division loop. */ - movi r13, 0 /* remainder = 0 */ - - /* Now - * r3 = dividend : quotient - * r4 = 0x25 for div, 0x24 for divu - * r6 = divisor - * r13 = remainder - * r14 = loop counter (already initialized to 32) - * r17 = MSB contains sign of quotient - */ - - - /* - * for (count = 32; count > 0; --count) - * { - */ -.Ldivide_loop: - - /* - * Division: - * - * (remainder:dividend:quotient) <<= 1; - */ - slli r13, r13, 1 - cmplt r15, r3, zero /* r15 = MSB of r3 */ - or r13, r13, r15 - slli r3, r3, 1 - - - /* - * if (remainder >= divisor) - * { - * set LSB of quotient - * remainder -= divisor; - * } - */ - bltu r13, r6, .Ldiv_skip - ori r3, r3, 1 - sub r13, r13, r6 -.Ldiv_skip: - - /* - * } - */ - subi r14, r14, 1 - bne r14, zero, .Ldivide_loop - - mov r9, r3 - - - /* Now - * r9 = quotient - * r4 = 0x25 for div, 0x24 for divu - * r7 = 4*(C^16) - * r17 = MSB contains sign of quotient - */ - - - /* - * Conditionally negate signed quotient. If quotient is unsigned, - * the sign already is initialized to 0. - */ - bge r17, zero, .Lstore_result - sub r9, zero, r9 /* -r9 */ - - br .Lstore_result - - - - - /* MULTIPLICATION - * - * A "product" is the number that one gets by summing a "multiplicand" - * several times. The "multiplier" specifies the number of copies of the - * multiplicand that are summed. - * - * Actual multiplication algorithms don't use repeated addition, however. - * Shift-and-add algorithms get the same answer as repeated addition, and - * they are faster. To compute the lower half of a product (pppp below) - * one shifts the product left before adding in each of the partial products - * (a * mmmm) through (d * mmmm). - * - * To compute the upper half of a product (PPPP below), one adds in the - * partial products (d * mmmm) through (a * mmmm), each time following the - * add by a right shift of the product. - * - * mmmm - * * abcd - * ------ - * #### = d * mmmm - * #### = c * mmmm - * #### = b * mmmm - * #### = a * mmmm - * -------- - * PPPPpppp - * - * The example above shows 4 partial products. Computing actual Nios II - * products requires 32 partials. - * - * It is possible to compute the result of mulxsu from the result of mulxuu - * because the only difference between the results of these two opcodes is - * the value of the partial product associated with the sign bit of rA. - * - * mulxsu = mulxuu - ((rA < 0) ? rB : 0); - * - * It is possible to compute the result of mulxss from the result of mulxsu - * because the only difference between the results of these two opcodes is - * the value of the partial product associated with the sign bit of rB. - * - * mulxss = mulxsu - ((rB < 0) ? rA : 0); - * - */ - -.Lmul_immed: - /* Opcode is muli. Change it into mul for remainder of algorithm. */ - mov r7, r6 /* Field B is dest register, not field C. */ - mov r6, r4 /* Field IMM16 is src2, not field B. */ - movi r4, 0x27 /* OPX of mul is 0x27 */ - -.Lmultiply: - /* Initialize the multiplication loop. */ - movi r9, 0 /* mul_product = 0 */ - movi r10, 0 /* mulxuu_product = 0 */ - mov r11, r6 /* save original multiplier for mulxsu and mulxss */ - mov r12, r6 /* mulxuu_multiplier (will be shifted) */ - movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */ - - /* Now - * r3 = multiplicand - * r6 = mul_multiplier - * r7 = 4 * dest_register (used later as offset to sp) - * r9 = mul_product - * r10 = mulxuu_product - * r11 = original multiplier - * r12 = mulxuu_multiplier - * r14 = loop counter (already initialized) - * r15 = temp - * r16 = 1 - */ - - - /* - * for (count = 32; count > 0; --count) - * { - */ -.Lmultiply_loop: - - /* - * mul_product <<= 1; - * lsb = multiplier & 1; - */ - slli r9, r9, 1 - andi r15, r12, 1 - - /* - * if (lsb == 1) - * { - * mulxuu_product += multiplicand; - * } - */ - beq r15, zero, .Lmulx_skip - add r10, r10, r3 - cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */ - ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */ -.Lmulx_skip: - - /* - * if (MSB of mul_multiplier == 1) - * { - * mul_product += multiplicand; - * } - */ - bge r6, zero, .Lmul_skip - add r9, r9, r3 -.Lmul_skip: - - /* - * mulxuu_product >>= 1; logical shift - * mul_multiplier <<= 1; done with MSB - * mulx_multiplier >>= 1; done with LSB - */ - srli r10, r10, 1 - or r10, r10, r15 /* OR in the saved carry bit. */ - slli r6, r6, 1 - srli r12, r12, 1 - - - /* - * } - */ - subi r14, r14, 1 - bne r14, zero, .Lmultiply_loop - - - /* - * Multiply emulation loop done. - */ - - /* Now - * r3 = multiplicand - * r4 = OPX - * r7 = 4 * dest_register (used later as offset to sp) - * r9 = mul_product - * r10 = mulxuu_product - * r11 = original multiplier - * r15 = temp - */ - - - /* - * Select/compute the result based on OPX. - */ - - - /* OPX == mul? Then store. */ - xori r15, r4, 0x27 - beq r15, zero, .Lstore_result - - /* It's one of the mulx.. opcodes. Move over the result. */ - mov r9, r10 - - /* OPX == mulxuu? Then store. */ - xori r15, r4, 0x07 - beq r15, zero, .Lstore_result - - /* Compute mulxsu - * - * mulxsu = mulxuu - ((rA < 0) ? rB : 0); - */ - bge r3, zero, .Lmulxsu_skip - sub r9, r9, r11 -.Lmulxsu_skip: - - /* OPX == mulxsu? Then store. */ - xori r15, r4, 0x17 - beq r15, zero, .Lstore_result - - /* Compute mulxss - * - * mulxss = mulxsu - ((rB < 0) ? rA : 0); - */ - bge r11, zero, .Lmulxss_skip - sub r9, r9, r3 -.Lmulxss_skip: - /* At this point, assume that OPX is mulxss, so store */ - - -.Lstore_result: - add r7, r7, sp - stw r9, 0(r7) - - ldw r16, 0(sp) - ldw r17, 4(sp) - ldw r18, 8(sp) - ldw r19, 12(sp) - ldw r20, 16(sp) - ldw r21, 20(sp) - ldw r22, 24(sp) - ldw r23, 28(sp) - - /* bt @ 32 - Breakpoint register usually isn't an operand. */ - /* et @ 36 - Don't corrupt et. */ - /* gp @ 40 - Don't corrupt gp. */ - /* sp @ 44 - Don't corrupt sp. */ - ldw fp, 48(sp) - /* ea @ 52 - Don't corrupt ea. */ - /* ba @ 56 - Breakpoint register usually isn't an operand. */ - - addi sp, sp, 60 - - br .Lexception_exit - - -.Lnot_muldiv: - - addi sp, sp, 60 - - - .section .exceptions.exit.label -.Lexception_exit: - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the software multiply/divide handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_muldiv +alt_exception_muldiv: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + + .section .exceptions.soft, "xa" + + + /* INSTRUCTION EMULATION + * --------------------- + * + * Nios II processors generate exceptions for unimplemented instructions. + * The routines below emulate these instructions. Depending on the + * processor core, the only instructions that might need to be emulated + * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu. + * + * The emulations match the instructions, except for the following + * limitations: + * + * 1) The emulation routines do not emulate the use of the exception + * temporary register (et) as a source operand because the exception + * handler already has modified it. + * + * 2) The routines do not emulate the use of the stack pointer (sp) or the + * exception return address register (ea) as a destination because + * modifying these registers crashes the exception handler or the + * interrupted routine. + * + * 3) To save code size, the routines do not emulate the use of the + * breakpoint registers (ba and bt) as operands. + * + * Detailed Design + * --------------- + * + * The emulation routines expect the contents of integer registers r0-r31 + * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The + * routines retrieve source operands from the stack and modify the + * destination register's value on the stack prior to the end of the + * exception handler. Then all registers except the destination register + * are restored to their previous values. + * + * The instruction that causes the exception is found at address -4(ea). + * The instruction's OP and OPX fields identify the operation to be + * performed. + * + * One instruction, muli, is an I-type instruction that is identified by + * an OP field of 0x24. + * + * muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24- + * 27 22 6 0 <-- LSB of field + * + * The remaining emulated instructions are R-type and have an OP field + * of 0x3a. Their OPX fields identify them. + * + * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a- + * 27 22 17 11 6 0 <-- LSB of field + * + * + */ + + + /* + * Split the instruction into its fields. We need 4*A, 4*B, and 4*C as + * offsets to the stack pointer for access to the stored register values. + */ + /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */ + roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */ + roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */ + roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */ + srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */ + xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */ + roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */ + andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */ + xori r3, r3, 0x40 + andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */ + andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */ + andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */ + + /* Now either + * r5 = OP + * r3 = 4*(A^16) + * r4 = IMM16 (sign extended) + * r6 = 4*(B^16) + * r7 = 4*(C^16) + * or + * r5 = OP + */ + + + /* + * Save everything on the stack to make it easy for the emulation routines + * to retrieve the source register operands. The exception entry code has + * already saved some of this so we don't need to do it all again. + */ + + addi sp, sp, -60 + stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */ + /* Register at and r2-r15 have already been saved. */ + + stw r16, 0(sp) + stw r17, 4(sp) + stw r18, 8(sp) + stw r19, 12(sp) + stw r20, 16(sp) + stw r21, 20(sp) + stw r22, 24(sp) + stw r23, 28(sp) + /* et @ 32 - Has already been changed.*/ + /* bt @ 36 - Usually isn't an operand. */ + stw gp, 40(sp) + stw sp, 44(sp) + stw fp, 48(sp) + /* ea @ 52 - Don't bother to save - it's already been changed */ + /* ba @ 56 - Breakpoint register usually isn't an operand */ + /* ra @ 60 - Has already been saved */ + + + /* + * Prepare for either multiplication or division loop. + * They both loop 32 times. + */ + movi r14, 32 + + + /* + * Get the operands. + * + * It is necessary to check for muli because it uses an I-type instruction + * format, while the other instructions are have an R-type format. + */ + add r3, r3, sp /* r3 = address of A-operand. */ + ldw r3, 0(r3) /* r3 = A-operand. */ + movi r15, 0x24 /* muli opcode (I-type instruction format) */ + beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */ + + add r6, r6, sp /* r6 = address of B-operand. */ + ldw r6, 0(r6) /* r6 = B-operand. */ + /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */ + /* IMM16 not needed, align OPX portion */ + /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */ + srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */ + andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */ + + /* Now + * r5 = OP + * r3 = src1 + * r6 = src2 + * r4 = OPX (no longer can be muli) + * r7 = 4*(C^16) + * r14 = loop counter + */ + + /* ILLEGAL-INSTRUCTION EXCEPTION + * ----------------------------- + * + * This code is for Nios II cores that generate exceptions when attempting + * to execute illegal instructions. Nios II cores that support an + * illegal-instruction exception are identified by the presence of the + * macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h . + * + * Remember that illegal instructions are different than unimplemented + * instructions. Illegal instructions are instruction encodings that + * have not been defined by the Nios II ISA. Unimplemented instructions + * are legal instructions that must be emulated by some Nios II cores. + * + * If we get here, all instructions except multiplies and divides + * are illegal. + * + * This code assumes that OP is not muli (because muli was tested above). + * All other multiplies and divides are legal. Anything else is illegal. + */ + + movi r8, 0x3a /* OP for R-type mul* and div* */ + bne r5, r8, .Lnot_muldiv + + /* r15 already is 0x24 */ /* OPX of divu */ + beq r4, r15, .Ldivide + + movi r15,0x27 /* OPX of mul */ + beq r4, r15, .Lmultiply + + movi r15,0x07 /* OPX of mulxuu */ + beq r4, r15, .Lmultiply + + movi r15,0x17 /* OPX of mulxsu */ + beq r4, r15, .Lmultiply + + movi r15,0x1f /* OPX of mulxss */ + beq r4, r15, .Lmultiply + + movi r15,0x25 /* OPX of div */ + bne r4, r15, .Lnot_muldiv + + + /* DIVISION + * + * Divide an unsigned dividend by an unsigned divisor using + * a shift-and-subtract algorithm. The example below shows + * 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a + * single register to store both the dividend and the quotient, + * allowing both values to be shifted with a single instruction. + * + * remainder dividend:quotient + * --------- ----------------- + * initialize 00000000 00101011: + * shift 00000000 0101011:_ + * remainder >= divisor? no 00000000 0101011:0 + * shift 00000000 101011:0_ + * remainder >= divisor? no 00000000 101011:00 + * shift 00000001 01011:00_ + * remainder >= divisor? no 00000001 01011:000 + * shift 00000010 1011:000_ + * remainder >= divisor? no 00000010 1011:0000 + * shift 00000101 011:0000_ + * remainder >= divisor? no 00000101 011:00000 + * shift 00001010 11:00000_ + * remainder >= divisor? yes 00001010 11:000001 + * remainder -= divisor - 00000111 + * ---------- + * 00000011 11:000001 + * shift 00000111 1:000001_ + * remainder >= divisor? yes 00000111 1:0000011 + * remainder -= divisor - 00000111 + * ---------- + * 00000000 1:0000011 + * shift 00000001 :0000011_ + * remainder >= divisor? no 00000001 :00000110 + * + * The quotient is 00000110. + */ + +.Ldivide: + /* + * Prepare for division by assuming the result + * is unsigned, and storing its "sign" as 0. + */ + movi r17, 0 + + + /* Which division opcode? */ + xori r15, r4, 0x25 /* OPX of div */ + bne r15, zero, .Lunsigned_division + + + /* + * OPX is div. Determine and store the sign of the quotient. + * Then take the absolute value of both operands. + */ + xor r17, r3, r6 /* MSB contains sign of quotient */ + bge r3, zero, 0f + sub r3, zero, r3 /* -r3 */ +0: + bge r6, zero, 0f + sub r6, zero, r6 /* -r6 */ +0: + + +.Lunsigned_division: + /* Initialize the unsigned-division loop. */ + movi r13, 0 /* remainder = 0 */ + + /* Now + * r3 = dividend : quotient + * r4 = 0x25 for div, 0x24 for divu + * r6 = divisor + * r13 = remainder + * r14 = loop counter (already initialized to 32) + * r17 = MSB contains sign of quotient + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Ldivide_loop: + + /* + * Division: + * + * (remainder:dividend:quotient) <<= 1; + */ + slli r13, r13, 1 + cmplt r15, r3, zero /* r15 = MSB of r3 */ + or r13, r13, r15 + slli r3, r3, 1 + + + /* + * if (remainder >= divisor) + * { + * set LSB of quotient + * remainder -= divisor; + * } + */ + bltu r13, r6, .Ldiv_skip + ori r3, r3, 1 + sub r13, r13, r6 +.Ldiv_skip: + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Ldivide_loop + + mov r9, r3 + + + /* Now + * r9 = quotient + * r4 = 0x25 for div, 0x24 for divu + * r7 = 4*(C^16) + * r17 = MSB contains sign of quotient + */ + + + /* + * Conditionally negate signed quotient. If quotient is unsigned, + * the sign already is initialized to 0. + */ + bge r17, zero, .Lstore_result + sub r9, zero, r9 /* -r9 */ + + br .Lstore_result + + + + + /* MULTIPLICATION + * + * A "product" is the number that one gets by summing a "multiplicand" + * several times. The "multiplier" specifies the number of copies of the + * multiplicand that are summed. + * + * Actual multiplication algorithms don't use repeated addition, however. + * Shift-and-add algorithms get the same answer as repeated addition, and + * they are faster. To compute the lower half of a product (pppp below) + * one shifts the product left before adding in each of the partial products + * (a * mmmm) through (d * mmmm). + * + * To compute the upper half of a product (PPPP below), one adds in the + * partial products (d * mmmm) through (a * mmmm), each time following the + * add by a right shift of the product. + * + * mmmm + * * abcd + * ------ + * #### = d * mmmm + * #### = c * mmmm + * #### = b * mmmm + * #### = a * mmmm + * -------- + * PPPPpppp + * + * The example above shows 4 partial products. Computing actual Nios II + * products requires 32 partials. + * + * It is possible to compute the result of mulxsu from the result of mulxuu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rA. + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + * + * It is possible to compute the result of mulxss from the result of mulxsu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rB. + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + * + */ + +.Lmul_immed: + /* Opcode is muli. Change it into mul for remainder of algorithm. */ + mov r7, r6 /* Field B is dest register, not field C. */ + mov r6, r4 /* Field IMM16 is src2, not field B. */ + movi r4, 0x27 /* OPX of mul is 0x27 */ + +.Lmultiply: + /* Initialize the multiplication loop. */ + movi r9, 0 /* mul_product = 0 */ + movi r10, 0 /* mulxuu_product = 0 */ + mov r11, r6 /* save original multiplier for mulxsu and mulxss */ + mov r12, r6 /* mulxuu_multiplier (will be shifted) */ + movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */ + + /* Now + * r3 = multiplicand + * r6 = mul_multiplier + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r12 = mulxuu_multiplier + * r14 = loop counter (already initialized) + * r15 = temp + * r16 = 1 + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Lmultiply_loop: + + /* + * mul_product <<= 1; + * lsb = multiplier & 1; + */ + slli r9, r9, 1 + andi r15, r12, 1 + + /* + * if (lsb == 1) + * { + * mulxuu_product += multiplicand; + * } + */ + beq r15, zero, .Lmulx_skip + add r10, r10, r3 + cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */ + ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */ +.Lmulx_skip: + + /* + * if (MSB of mul_multiplier == 1) + * { + * mul_product += multiplicand; + * } + */ + bge r6, zero, .Lmul_skip + add r9, r9, r3 +.Lmul_skip: + + /* + * mulxuu_product >>= 1; logical shift + * mul_multiplier <<= 1; done with MSB + * mulx_multiplier >>= 1; done with LSB + */ + srli r10, r10, 1 + or r10, r10, r15 /* OR in the saved carry bit. */ + slli r6, r6, 1 + srli r12, r12, 1 + + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Lmultiply_loop + + + /* + * Multiply emulation loop done. + */ + + /* Now + * r3 = multiplicand + * r4 = OPX + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r15 = temp + */ + + + /* + * Select/compute the result based on OPX. + */ + + + /* OPX == mul? Then store. */ + xori r15, r4, 0x27 + beq r15, zero, .Lstore_result + + /* It's one of the mulx.. opcodes. Move over the result. */ + mov r9, r10 + + /* OPX == mulxuu? Then store. */ + xori r15, r4, 0x07 + beq r15, zero, .Lstore_result + + /* Compute mulxsu + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + */ + bge r3, zero, .Lmulxsu_skip + sub r9, r9, r11 +.Lmulxsu_skip: + + /* OPX == mulxsu? Then store. */ + xori r15, r4, 0x17 + beq r15, zero, .Lstore_result + + /* Compute mulxss + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + */ + bge r11, zero, .Lmulxss_skip + sub r9, r9, r3 +.Lmulxss_skip: + /* At this point, assume that OPX is mulxss, so store */ + + +.Lstore_result: + add r7, r7, sp + stw r9, 0(r7) + + ldw r16, 0(sp) + ldw r17, 4(sp) + ldw r18, 8(sp) + ldw r19, 12(sp) + ldw r20, 16(sp) + ldw r21, 20(sp) + ldw r22, 24(sp) + ldw r23, 28(sp) + + /* bt @ 32 - Breakpoint register usually isn't an operand. */ + /* et @ 36 - Don't corrupt et. */ + /* gp @ 40 - Don't corrupt gp. */ + /* sp @ 44 - Don't corrupt sp. */ + ldw fp, 48(sp) + /* ea @ 52 - Don't corrupt ea. */ + /* ba @ 56 - Breakpoint register usually isn't an operand. */ + + addi sp, sp, 60 + + br .Lexception_exit + + +.Lnot_muldiv: + + addi sp, sp, 60 + + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_trap.S b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_trap.S index 60a3d40..bd9a9f5 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_trap.S +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exception_trap.S @@ -1,81 +1,81 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - - /* - * This is the trap exception handler for Nios2. - */ - - /* - * Provide a label which can be used to pull this file in. - */ - - .section .exceptions.start - .globl alt_exception_trap -alt_exception_trap: - - /* - * Pull in the entry/exit code. - */ - .globl alt_exception - - .section .exceptions.soft, "xa" - -.Ltrap_handler: - - /* - * Did a trap instruction cause the exception? - * - * The instruction which the exception occurred on has been loaded - * into r2 by code in alt_exception_entry.S - * - */ - - movhi r3,0x003b /* upper half of trap opcode */ - ori r3,r3,0x683a /* lower half of trap opcode */ - bne r2,r3,.Lnot_trap - - /* - * There is no trap handler defined here, and so executing a trap - * instruction causes a software break. If you provide a trap handler, - * then you must replace the break instruction below with your handler. - * Your handler must preserve ea and the usual callee saved registers. - */ - - break - - br .Lexception_exit - -.Lnot_trap: - - - .section .exceptions.exit.label -.Lexception_exit: - - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the trap exception handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_trap +alt_exception_trap: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + .section .exceptions.soft, "xa" + +.Ltrap_handler: + + /* + * Did a trap instruction cause the exception? + * + * The instruction which the exception occurred on has been loaded + * into r2 by code in alt_exception_entry.S + * + */ + + movhi r3,0x003b /* upper half of trap opcode */ + ori r3,r3,0x683a /* lower half of trap opcode */ + bne r2,r3,.Lnot_trap + + /* + * There is no trap handler defined here, and so executing a trap + * instruction causes a software break. If you provide a trap handler, + * then you must replace the break instruction below with your handler. + * Your handler must preserve ea and the usual callee saved registers. + */ + + break + + br .Lexception_exit + +.Lnot_trap: + + + .section .exceptions.exit.label +.Lexception_exit: + + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_execve.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_execve.c index 27b99cf..51bfcc4 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_execve.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_execve.c @@ -1,55 +1,55 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "os/alt_syscall.h" - -/* - * execve() is used by newlib to launch new processes. This is unsupported in - * the HAL environment. However a "do-nothing" implementation is still - * provied for newlib compatability. - * - * ALT_EXECVE is mapped onto the execve() system call in alt_syscall.h - */ - -int ALT_EXECVE (char *name, char ** argv, char** env) -{ - /* Generate a link time warning, should this function ever be called. */ - - ALT_STUB_WARNING(execve); - - /* Indicate an error */ - - ALT_ERRNO = ENOSYS; - return -1; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * execve() is used by newlib to launch new processes. This is unsupported in + * the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_EXECVE is mapped onto the execve() system call in alt_syscall.h + */ + +int ALT_EXECVE (char *name, char ** argv, char** env) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(execve); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exit.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exit.c index 971b35e..46cbe18 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exit.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_exit.c @@ -1,71 +1,71 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_irq.h" -#include "sys/alt_sim.h" -#include "os/alt_hooks.h" -#include "os/alt_syscall.h" - -#include "alt_types.h" -#include "sys/alt_log_printf.h" -/* - * _exit() is called by exit() in order to terminate the current process. - * Typically this is called when main() completes. It should never return. - * Since there is nowhere to go once this process completes, this - * implementation simply blocks forever. - * - * Note that interrupts are not disabled so that execution outside of this - * thread is allowed to continue. - * - * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h - */ - -void ALT_EXIT (int exit_code) -{ - /* ALT_LOG - please see HAL/inc/alt_log_printf.h for details */ - ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); - ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); - /* Stop all other threads */ - - ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); - ALT_OS_STOP(); - - /* Provide notification to the simulator that we've stopped */ - - ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); - ALT_SIM_HALT(exit_code); - - /* spin forever, since there's no where to go back to */ - - ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); - while (1); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_sim.h" +#include "os/alt_hooks.h" +#include "os/alt_syscall.h" + +#include "alt_types.h" +#include "sys/alt_log_printf.h" +/* + * _exit() is called by exit() in order to terminate the current process. + * Typically this is called when main() completes. It should never return. + * Since there is nowhere to go once this process completes, this + * implementation simply blocks forever. + * + * Note that interrupts are not disabled so that execution outside of this + * thread is allowed to continue. + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + /* ALT_LOG - please see HAL/inc/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fcntl.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fcntl.c index 69c1544..382fa43 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fcntl.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fcntl.c @@ -1,101 +1,101 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include - -#include -#include - -#include "sys/alt_errno.h" -#include "priv/alt_file.h" -#include "alt_types.h" -#include "os/alt_syscall.h" - -#define ALT_FCNTL_FLAGS_MASK ((alt_u32) (O_APPEND | O_NONBLOCK)) - -/* - * fcntl() is a limited implementation of the standard fcntl() system call. - * It can be used to change the state of the flags associated with an open - * file descriptor. Normally these flags are set during the call to - * open(). It is anticipated that the main use of this function will be to - * change the state of a device from blocking to non-blocking (where this is - * supported). - * - * The input argument "fd" is the file descriptor to be manipulated. "cmd" - * is the command to execute. This can be either F_GETFL (return the - * current value of the flags) or F_SETFL (set the value of the flags). - * - * If "cmd" is F_SETFL then the argument "arg" is the new value of flags, - * otherwise "arg" is ignored. Only the flags: O_APPEND and O_NONBLOCK - * can be updated by a call to fcntl(). All other flags remain - * unchanged. - * - * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h - */ - -int ALT_FCNTL (int file, int cmd, ...) -{ - alt_fd* fd; - long flags; - va_list argp; - - /* - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - - if (fd) - { - switch (cmd) - { - case F_GETFL: - return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK); - case F_SETFL: - va_start(argp, cmd); - flags = va_arg(argp, long); - fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK; - fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK); - va_end(argp); - return 0; - default: - ALT_ERRNO = EINVAL; - return -1; - } - } - - ALT_ERRNO = EBADFD; - return -1; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include +#include + +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#define ALT_FCNTL_FLAGS_MASK ((alt_u32) (O_APPEND | O_NONBLOCK)) + +/* + * fcntl() is a limited implementation of the standard fcntl() system call. + * It can be used to change the state of the flags associated with an open + * file descriptor. Normally these flags are set during the call to + * open(). It is anticipated that the main use of this function will be to + * change the state of a device from blocking to non-blocking (where this is + * supported). + * + * The input argument "fd" is the file descriptor to be manipulated. "cmd" + * is the command to execute. This can be either F_GETFL (return the + * current value of the flags) or F_SETFL (set the value of the flags). + * + * If "cmd" is F_SETFL then the argument "arg" is the new value of flags, + * otherwise "arg" is ignored. Only the flags: O_APPEND and O_NONBLOCK + * can be updated by a call to fcntl(). All other flags remain + * unchanged. + * + * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h + */ + +int ALT_FCNTL (int file, int cmd, ...) +{ + alt_fd* fd; + long flags; + va_list argp; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + switch (cmd) + { + case F_GETFL: + return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK); + case F_SETFL: + va_start(argp, cmd); + flags = va_arg(argp, long); + fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK; + fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK); + va_end(argp); + return 0; + default: + ALT_ERRNO = EINVAL; + return -1; + } + } + + ALT_ERRNO = EBADFD; + return -1; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fd_lock.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fd_lock.c index 0e2a85d..162295a 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fd_lock.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fd_lock.c @@ -1,75 +1,75 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#include "priv/alt_file.h" - -/* - * alt_fd_lock() is called as a consequence of an ioctl call to gain exclusive - * access to a device, i.e.: - * - * ioctl (fd, TIOCEXCL, NULL); - * - * If there are no other open file descriptors which reference the same - * device, then alt_fd_lock() will grant the lock. Further calls to open() - * for this device will fail until the lock is released. - * - * This is done by calling close() for this file descriptor, or by calling: - * - * ioctl (fd, TIOCNXCL, NULL); - * - * The return value is zero for success, or negative in the case of failure. - */ - -int alt_fd_lock (alt_fd* fd) -{ - int i; - int rc = 0; - - ALT_SEM_PEND(alt_fd_list_lock, 0); - - for (i = 0; i < alt_max_fd; i++) - { - if ((&alt_fd_list[i] != fd) && (alt_fd_list[i].dev == fd->dev)) - { - rc = -EACCES; - goto alt_fd_lock_exit; - } - } - fd->fd_flags |= ALT_FD_EXCL; - - alt_fd_lock_exit: - - ALT_SEM_POST(alt_fd_list_lock); - return rc; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_lock() is called as a consequence of an ioctl call to gain exclusive + * access to a device, i.e.: + * + * ioctl (fd, TIOCEXCL, NULL); + * + * If there are no other open file descriptors which reference the same + * device, then alt_fd_lock() will grant the lock. Further calls to open() + * for this device will fail until the lock is released. + * + * This is done by calling close() for this file descriptor, or by calling: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * The return value is zero for success, or negative in the case of failure. + */ + +int alt_fd_lock (alt_fd* fd) +{ + int i; + int rc = 0; + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + for (i = 0; i < alt_max_fd; i++) + { + if ((&alt_fd_list[i] != fd) && (alt_fd_list[i].dev == fd->dev)) + { + rc = -EACCES; + goto alt_fd_lock_exit; + } + } + fd->fd_flags |= ALT_FD_EXCL; + + alt_fd_lock_exit: + + ALT_SEM_POST(alt_fd_list_lock); + return rc; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fd_unlock.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fd_unlock.c index fb700dc..5f50386 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fd_unlock.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fd_unlock.c @@ -1,56 +1,56 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#include "priv/alt_file.h" - -/* - * alt_fd_unlock() is the inverse of alt_fd_lock(). It is called as a - * consequence of a TIOCNXCL ioctl request, e.g: - * - * ioctl (fd, TIOCNXCL, NULL); - * - * It enables multiple file descriptors to exist for the same device. This - * is normally the case, but it may have been disabled by a previous call to - * alt_fd_lock(). - * - * Return zero on sucess, and a negative value on failure. - * - * The current implementation always succeeds. - */ - -int alt_fd_unlock (alt_fd* fd) -{ - fd->fd_flags &= ~ALT_FD_EXCL; - return 0; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_unlock() is the inverse of alt_fd_lock(). It is called as a + * consequence of a TIOCNXCL ioctl request, e.g: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * It enables multiple file descriptors to exist for the same device. This + * is normally the case, but it may have been disabled by a previous call to + * alt_fd_lock(). + * + * Return zero on sucess, and a negative value on failure. + * + * The current implementation always succeeds. + */ + +int alt_fd_unlock (alt_fd* fd) +{ + fd->fd_flags &= ~ALT_FD_EXCL; + return 0; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_find_dev.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_find_dev.c index 37aefa4..964f63f 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_find_dev.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_find_dev.c @@ -1,88 +1,88 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include -#include - -#include "sys/alt_dev.h" -#include "priv/alt_file.h" - -#include "alt_types.h" - -/* - * alt_find_dev() is used by open() in order to locate a previously registered - * device with the name "name". The input argument "llist" is a pointer to the - * head of the device list to search. - * - * The return value is a pointer to the matching device, or NULL if there is - * no match. - * - * "name" must be an exact match for the devices registered name for a match to - * be found. - */ - -alt_dev* alt_find_dev(const char* name, alt_llist* llist) -{ - alt_dev* next = (alt_dev*) llist->next; - alt_32 len; - - len = strlen(name) + 1; - - /* - * Check each list entry in turn, until a match is found, or we reach the - * end of the list (i.e. next winds up pointing back to the list head). - */ - - while (next != (alt_dev*) llist) - { - - /* - * memcmp() is used here rather than strcmp() in order to reduce the size - * of the executable. - */ - - if (!memcmp (next->name, name, len)) - { - /* match found */ - - return next; - } - next = (alt_dev*) next->llist.next; - } - - /* No match found */ - - return NULL; -} - - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_dev() is used by open() in order to locate a previously registered + * device with the name "name". The input argument "llist" is a pointer to the + * head of the device list to search. + * + * The return value is a pointer to the matching device, or NULL if there is + * no match. + * + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + alt_dev* next = (alt_dev*) llist->next; + alt_32 len; + + len = strlen(name) + 1; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + { + + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_find_file.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_find_file.c index 2d97ec2..ae30e93 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_find_file.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_find_file.c @@ -1,89 +1,89 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include -#include - -#include "sys/alt_dev.h" -#include "priv/alt_file.h" - -#include "alt_types.h" - -/* - * alt_find_file() is used by open() in order to locate a previously registered - * filesystem that owns that mount point that contains the file named "name". - * - * The return value is a pointer to the matching filesystem, or NULL if there is - * no match. - * - * A match is considered to have been found if the filesystem name followed by - * either '/' or '\0' is the prefix of the filename. For example the filename: - * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". - */ - -alt_dev* alt_find_file (const char* name) -{ - alt_dev* next = (alt_dev*) alt_fs_list.next; - - alt_32 len; - - /* - * Check each list entry in turn, until a match is found, or we reach the - * end of the list (i.e. next winds up pointing back to the list head). - */ - - while (next != (alt_dev*) &alt_fs_list) - { - len = strlen(next->name); - - if (next->name[len-1] == '/') - { - len -= 1; - } - - if (((name[len] == '/') || (name[len] == '\0')) && - !memcmp (next->name, name, len)) - { - /* match found */ - - return next; - } - next = (alt_dev*) next->llist.next; - } - - /* No match found */ - - return NULL; -} - - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_file() is used by open() in order to locate a previously registered + * filesystem that owns that mount point that contains the file named "name". + * + * The return value is a pointer to the matching filesystem, or NULL if there is + * no match. + * + * A match is considered to have been found if the filesystem name followed by + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + alt_dev* next = (alt_dev*) alt_fs_list.next; + + alt_32 len; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + { + len = strlen(next->name); + + if (next->name[len-1] == '/') + { + len -= 1; + } + + if (((name[len] == '/') || (name[len] == '\0')) && + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_flash_dev.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_flash_dev.c index 213f721..0acffc7 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_flash_dev.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_flash_dev.c @@ -1,69 +1,69 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/****************************************************************************** -* * -* Alt_flash.c - Functions to register a flash device to the "generic" flash * -* interface * -* * -* Author PRR * -* * -******************************************************************************/ - -#include -#include "sys/alt_llist.h" -#include "sys/alt_flash_dev.h" -#include "priv/alt_file.h" - -ALT_LLIST_HEAD(alt_flash_dev_list); - -alt_flash_fd* alt_flash_open_dev(const char* name) -{ - alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list); - - if ((dev) && dev->open) - { - return dev->open(dev, name); - } - - return dev; -} - -void alt_flash_close_dev(alt_flash_fd* fd) -{ - if (fd && fd->close) - { - fd->close(fd); - } - return; -} - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.c - Functions to register a flash device to the "generic" flash * +* interface * +* * +* Author PRR * +* * +******************************************************************************/ + +#include +#include "sys/alt_llist.h" +#include "sys/alt_flash_dev.h" +#include "priv/alt_file.h" + +ALT_LLIST_HEAD(alt_flash_dev_list); + +alt_flash_fd* alt_flash_open_dev(const char* name) +{ + alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list); + + if ((dev) && dev->open) + { + return dev->open(dev, name); + } + + return dev; +} + +void alt_flash_close_dev(alt_flash_fd* fd) +{ + if (fd && fd->close) + { + fd->close(fd); + } + return; +} + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fork.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fork.c index ce74df0..b6edbb5 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fork.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fork.c @@ -1,57 +1,57 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_warning.h" -#include "sys/alt_errno.h" -#include "os/alt_syscall.h" - -/* - * The fork() system call is used by newlib to create a duplicate copy of the - * curent process. This is unsupported in the HAL environment. However a - * "do-nothing" implementation is still provied for newlib compatability. - * - * ALT_FORK is mapped onto the fork() system call in alt_syscall.h - */ - -int ALT_FORK (void) -{ - /* Generate a link time warning, should this function ever be called. */ - - ALT_STUB_WARNING(fork); - - /* Indicate an error */ - - ALT_ERRNO = ENOSYS; - return -1; -} - - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * The fork() system call is used by newlib to create a duplicate copy of the + * curent process. This is unsupported in the HAL environment. However a + * "do-nothing" implementation is still provied for newlib compatability. + * + * ALT_FORK is mapped onto the fork() system call in alt_syscall.h + */ + +int ALT_FORK (void) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(fork); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fs_reg.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fs_reg.c index 13437a1..e88a340 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fs_reg.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fs_reg.c @@ -1,75 +1,75 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#include "sys/alt_dev.h" -#include "priv/alt_file.h" - -/* - * The alt_fs_reg() function is used to register a file system. Once registered - * a device can be accessed using the standard posix calls: open(), read(), - * write() etc. - * - * System behaviour is undefined in the event that a file system is registered - * with a name that conflicts with an existing device or file system. - * - * alt_fs_reg() is not thread safe in the sense that there should be no other - * thread using the file system list at the time that alt_dev_reg() is called. In - * practice this means that alt_fs_reg() should only be called while operating - * in a single threaded mode. The expectation is that it will only be called - * by the file system initilisation functions invoked by alt_sys_init(), which in - * turn should only be called by the single threaded C startup code. - * - * A return value of zero indicates success. A negative return value indicates - * failure. - */ - -int alt_fs_reg (alt_dev* dev) -{ - /* - * check that the device has a name. - */ - - if (!dev->name) - { - return -ENODEV; - } - - /* - * register the file system. - */ - - alt_llist_insert(&alt_fs_list, &dev->llist); - - return 0; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * The alt_fs_reg() function is used to register a file system. Once registered + * a device can be accessed using the standard posix calls: open(), read(), + * write() etc. + * + * System behaviour is undefined in the event that a file system is registered + * with a name that conflicts with an existing device or file system. + * + * alt_fs_reg() is not thread safe in the sense that there should be no other + * thread using the file system list at the time that alt_dev_reg() is called. In + * practice this means that alt_fs_reg() should only be called while operating + * in a single threaded mode. The expectation is that it will only be called + * by the file system initilisation functions invoked by alt_sys_init(), which in + * turn should only be called by the single threaded C startup code. + * + * A return value of zero indicates success. A negative return value indicates + * failure. + */ + +int alt_fs_reg (alt_dev* dev) +{ + /* + * check that the device has a name. + */ + + if (!dev->name) + { + return -ENODEV; + } + + /* + * register the file system. + */ + + alt_llist_insert(&alt_fs_list, &dev->llist); + + return 0; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fstat.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fstat.c index af5d527..3248764 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fstat.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_fstat.c @@ -1,128 +1,128 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include - -#include "sys/alt_dev.h" -#include "sys/alt_warning.h" -#include "sys/alt_errno.h" -#include "priv/alt_file.h" -#include "os/alt_syscall.h" - -/* - * The fstat() system call is used to obtain information about the capabilities - * of an open file descriptor. By default file descriptors are marked as - * being character devices. If a device or file system wishes to advertise - * alternative capabilities then they can register an fstat() function within - * their associated alt_dev structure. This will be called to fill in the - * entries in the imput "st" structure. - * - * This function is provided for compatability with newlib. - * - * ALT_FSTAT is mapped onto the fstat() system call in alt_syscall.h - */ - -#ifdef ALT_USE_DIRECT_DRIVERS - -#include "system.h" - -/* - * Provide minimal version that just describes all file descriptors - * as character devices for provided stdio devices. - */ -int ALT_FSTAT (int file, struct stat *st) -{ - switch (file) { -#ifdef ALT_STDIN_PRESENT - case 0: /* stdin file descriptor */ -#endif /* ALT_STDIN_PRESENT */ -#ifdef ALT_STDOUT_PRESENT - case 1: /* stdout file descriptor */ -#endif /* ALT_STDOUT_PRESENT */ -#ifdef ALT_STDERR_PRESENT - case 2: /* stderr file descriptor */ -#endif /* ALT_STDERR_PRESENT */ - st->st_mode = _IFCHR; - return 0; - default: - return -1; - } - -#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) - /* Generate a link time warning, should this function ever be called. */ - ALT_STUB_WARNING(fstat); -#endif -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -int ALT_FSTAT (int file, struct stat *st) -{ - alt_fd* fd; - - /* - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - - if (fd) - { - /* Call the drivers fstat() function to fill out the "st" structure. */ - - if (fd->dev->fstat) - { - return fd->dev->fstat(fd, st); - } - - /* - * If no function is provided, mark the fd as belonging to a character - * device. - */ - - else - { - st->st_mode = _IFCHR; - return 0; - } - } - else - { - ALT_ERRNO = EBADFD; - return -1; - } -} - -#endif /* ALT_USE_DIRECT_DRIVERS */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The fstat() system call is used to obtain information about the capabilities + * of an open file descriptor. By default file descriptors are marked as + * being character devices. If a device or file system wishes to advertise + * alternative capabilities then they can register an fstat() function within + * their associated alt_dev structure. This will be called to fill in the + * entries in the imput "st" structure. + * + * This function is provided for compatability with newlib. + * + * ALT_FSTAT is mapped onto the fstat() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as character devices for provided stdio devices. + */ +int ALT_FSTAT (int file, struct stat *st) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + st->st_mode = _IFCHR; + return 0; + default: + return -1; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(fstat); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + alt_fd* fd; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + { + return fd->dev->fstat(fd, st); + } + + /* + * If no function is provided, mark the fd as belonging to a character + * device. + */ + + else + { + st->st_mode = _IFCHR; + return 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_get_fd.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_get_fd.c index db17b2c..f42944b 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_get_fd.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_get_fd.c @@ -1,105 +1,105 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include -#include - -#include "sys/alt_dev.h" -#include "priv/alt_file.h" - -#include "alt_types.h" - -#include "system.h" - -/* - * alt_get_fd() is called to allocate a new file descriptor from the file - * descriptor pool. If a file descriptor is succesfully allocated, it is - * configured to refer to device "dev". - * - * The return value is the index of the file descriptor structure (i.e. - * the offset of the file descriptor within the file descriptor array). A - * negative value indicates failure. - */ - -int alt_get_fd (alt_dev* dev) -{ - alt_32 i; - int rc = -EMFILE; - - /* - * Take the alt_fd_list_lock semaphore in order to avoid races when - * accessing the file descriptor pool. - */ - - ALT_SEM_PEND(alt_fd_list_lock, 0); - - /* - * Search through the list of file descriptors, and allocate the first - * free descriptor that's found. - * - * If a free descriptor is found, then the value of "alt_max_fd" is - * updated accordingly. "alt_max_fd" is a 'highwater mark' which - * indicates the highest file descriptor ever allocated. This is used to - * improve efficency when searching the file descriptor list, and - * therefore reduce contention on the alt_fd_list_lock semaphore. - */ - - for (i = 0; i < ALT_MAX_FD; i++) - { - if (!alt_fd_list[i].dev) - { - alt_fd_list[i].dev = dev; - if (i > alt_max_fd) - { - alt_max_fd = i; - } - rc = i; - goto alt_get_fd_exit; - } - } - - alt_get_fd_exit: - - /* - * Release the alt_fd_list_lock semaphore now that we are done with the - * file descriptor pool. - */ - - ALT_SEM_POST(alt_fd_list_lock); - - return rc; -} - - - - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * alt_get_fd() is called to allocate a new file descriptor from the file + * descriptor pool. If a file descriptor is succesfully allocated, it is + * configured to refer to device "dev". + * + * The return value is the index of the file descriptor structure (i.e. + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + alt_32 i; + int rc = -EMFILE; + + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + /* + * Search through the list of file descriptors, and allocate the first + * free descriptor that's found. + * + * If a free descriptor is found, then the value of "alt_max_fd" is + * updated accordingly. "alt_max_fd" is a 'highwater mark' which + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + { + if (!alt_fd_list[i].dev) + { + alt_fd_list[i].dev = dev; + if (i > alt_max_fd) + { + alt_max_fd = i; + } + rc = i; + goto alt_get_fd_exit; + } + } + + alt_get_fd_exit: + + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + + return rc; +} + + + + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_getchar.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_getchar.c index a8f50d5..3e7df79 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_getchar.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_getchar.c @@ -1,61 +1,61 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#ifdef ALT_USE_DIRECT_DRIVERS -#include "system.h" -#include "sys/alt_driver.h" -#include "sys/alt_stdio.h" -#include "priv/alt_file.h" -#include "unistd.h" -#endif - -/* - * Uses the ALT_DRIVER_READ() macro to call directly to driver if available. - * Otherwise, uses newlib provided getchar() routine. - */ -int -alt_getchar(void) -{ -#ifdef ALT_USE_DIRECT_DRIVERS - ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); - char c; - - if (ALT_DRIVER_READ(ALT_STDIN_DEV, &c, 1, alt_fd_list[STDIN_FILENO].fd_flags) <= 0) { - return -1; - } - return c; -#else - return getchar(); -#endif -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#include "priv/alt_file.h" +#include "unistd.h" +#endif + +/* + * Uses the ALT_DRIVER_READ() macro to call directly to driver if available. + * Otherwise, uses newlib provided getchar() routine. + */ +int +alt_getchar(void) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); + char c; + + if (ALT_DRIVER_READ(ALT_STDIN_DEV, &c, 1, alt_fd_list[STDIN_FILENO].fd_flags) <= 0) { + return -1; + } + return c; +#else + return getchar(); +#endif +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_getpid.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_getpid.c index 2228c7e..b63ec33 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_getpid.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_getpid.c @@ -1,47 +1,47 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "os/alt_syscall.h" - -/* - * The getpid() system call is used by newlib to obtain the current process - * id. Since there is only ever a single process in the HAL environment, - * this just returns a constant. - * - * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h - */ - -int ALT_GETPID (void) -{ - return 0; -} - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * The getpid() system call is used by newlib to obtain the current process + * id. Since there is only ever a single process in the HAL environment, + * this just returns a constant. + * + * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h + */ + +int ALT_GETPID (void) +{ + return 0; +} + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_gettod.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_gettod.c index ed86cba..46b12c2 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_gettod.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_gettod.c @@ -1,125 +1,125 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include -#include - -#include "sys/alt_alarm.h" -#include "alt_types.h" -#include "os/alt_syscall.h" - -/* - * Macro defining the number of micoseconds in a second. - */ - -#define ALT_US (1000000) - -/* - * "alt_timezone" and "alt_resettime" are the values of the the reset time and - * time zone set through the last call to settimeofday(). By default they are - * zero initialised. - */ - -struct timezone alt_timezone = {0, 0}; -struct timeval alt_resettime = {0, 0}; - -/* - * gettimeofday() can be called to obtain a time structure which indicates the - * current "wall clock" time. This is calculated using the elapsed number of - * system clock ticks, and the value of "alt_resettime" and "alt_timezone" set - * through the last call to settimeofday(). - * - * Warning: if this function is called concurrently with a call to - * settimeofday(), the value returned by gettimeofday() will be unreliable. - * - * ALT_GETTIMEOFDAY is mapped onto the gettimeofday() system call in - * alt_syscall.h - */ - - -#if defined (__GNUC__) && (__GNUC__ >= 4) -int ALT_GETTIMEOFDAY (struct timeval *ptimeval, void *ptimezone_vptr) -{ - struct timezone *ptimezone = (struct timezone*)ptimezone_vptr; -#else -int ALT_GETTIMEOFDAY (struct timeval *ptimeval, struct timezone *ptimezone) -{ -#endif - - alt_u32 nticks = alt_nticks (); - alt_u32 tick_rate = alt_ticks_per_second (); - - /* - * Check to see if the system clock is running. This is indicated by a - * non-zero system clock rate. If the system clock is not running, an error - * is generated and the contents of "ptimeval" and "ptimezone" are not - * updated. - */ - - if (tick_rate) - { - ptimeval->tv_sec = alt_resettime.tv_sec + nticks/tick_rate; - ptimeval->tv_usec = alt_resettime.tv_usec + - (alt_u32)(((alt_u64)nticks*(ALT_US/tick_rate))%ALT_US); - - while(ptimeval->tv_usec < 0) { - if (ptimeval->tv_sec <= 0) - { - ptimeval->tv_sec = 0; - ptimeval->tv_usec = 0; - break; - } - else - { - ptimeval->tv_sec--; - ptimeval->tv_usec += ALT_US; - } - } - - while(ptimeval->tv_usec >= ALT_US) { - ptimeval->tv_sec++; - ptimeval->tv_usec -= ALT_US; - } - - if (ptimezone) - { - ptimezone->tz_minuteswest = alt_timezone.tz_minuteswest; - ptimezone->tz_dsttime = alt_timezone.tz_dsttime; - } - - return 0; - } - - return -ENOTSUP; -} - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_alarm.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +struct timezone alt_timezone = {0, 0}; +struct timeval alt_resettime = {0, 0}; + +/* + * gettimeofday() can be called to obtain a time structure which indicates the + * current "wall clock" time. This is calculated using the elapsed number of + * system clock ticks, and the value of "alt_resettime" and "alt_timezone" set + * through the last call to settimeofday(). + * + * Warning: if this function is called concurrently with a call to + * settimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_GETTIMEOFDAY is mapped onto the gettimeofday() system call in + * alt_syscall.h + */ + + +#if defined (__GNUC__) && (__GNUC__ >= 4) +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, void *ptimezone_vptr) +{ + struct timezone *ptimezone = (struct timezone*)ptimezone_vptr; +#else +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, struct timezone *ptimezone) +{ +#endif + + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* + * Check to see if the system clock is running. This is indicated by a + * non-zero system clock rate. If the system clock is not running, an error + * is generated and the contents of "ptimeval" and "ptimezone" are not + * updated. + */ + + if (tick_rate) + { + ptimeval->tv_sec = alt_resettime.tv_sec + nticks/tick_rate; + ptimeval->tv_usec = alt_resettime.tv_usec + + (alt_u32)(((alt_u64)nticks*(ALT_US/tick_rate))%ALT_US); + + while(ptimeval->tv_usec < 0) { + if (ptimeval->tv_sec <= 0) + { + ptimeval->tv_sec = 0; + ptimeval->tv_usec = 0; + break; + } + else + { + ptimeval->tv_sec--; + ptimeval->tv_usec += ALT_US; + } + } + + while(ptimeval->tv_usec >= ALT_US) { + ptimeval->tv_sec++; + ptimeval->tv_usec -= ALT_US; + } + + if (ptimezone) + { + ptimezone->tz_minuteswest = alt_timezone.tz_minuteswest; + ptimezone->tz_dsttime = alt_timezone.tz_dsttime; + } + + return 0; + } + + return -ENOTSUP; +} + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_gmon.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_gmon.c index 6add9f1..fce7587 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_gmon.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_gmon.c @@ -1,272 +1,272 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include -#include -#include - -#include "priv/nios2_gmon_data.h" - -#include "sys/alt_irq.h" -#include "sys/alt_alarm.h" - - -/* Macros */ - -/* How large should the bins be which we use to generate the histogram */ -#define PCSAMPLE_BYTES_PER_BUCKET 32 - -#define NIOS2_READ_EA(dest) __asm__ ("mov %0, ea" : "=r" (dest)) - -/* The compiler inserts calls to mcount() at the start of - * every function call. The structure mcount_fn_arc records t - * he return address of the function called (in from_pc) - * and the return address of the mcount function - * (in self_pc). The number of times this arc is executed is - * recorded in the field count. - */ -struct mcount_fn_arc -{ - struct mcount_fn_arc * next; - void * from_pc; - unsigned int count; -}; - -/* We need to maintain a list of pointers to the heads of each adjacency - * list so that we can find them when writing out the gmon.out file. Since - * we don't know at the start of program execution how many functions will - * be called we use a list structure to do this. - */ -struct mcount_fn_entry -{ - struct mcount_fn_entry * next; - void * self_pc; - struct mcount_fn_arc * arc_head; -}; - -/* function prototypes */ - -void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) __attribute__ ((no_instrument_function)); - -static __inline__ void * mcount_allocate(unsigned int size) __attribute__ ((no_instrument_function)); -static int nios2_pcsample_init(void) __attribute__ ((no_instrument_function)); -static alt_u32 nios2_pcsample(void* alarm) __attribute__ ((no_instrument_function)); - -/* global variables */ - -/* stext and etext are defined in the linker script */ -extern char stext[]; -extern char etext[]; - -/* Is the PC sampling stuff enabled yet? */ -static int pcsample_need_init = 1; - -#define HASH_BUCKETS 64 /* Must be a power of 2 */ - -/* This points to the list of adjacency list pointers. */ -struct mcount_fn_entry * __mcount_fn_head[HASH_BUCKETS]; - -/* pointer to the in-memory buffer containing the histogram */ -static unsigned short* s_pcsamples = 0; - -/* the address of the start and end of text section */ -static const unsigned int s_low_pc = (unsigned int)stext; -static const unsigned int s_high_pc = (unsigned int)etext; - -/* the alarm structure to register for pc sampling */ -static alt_alarm s_nios2_pcsample_alarm; - -unsigned int alt_gmon_data[GMON_DATA_SIZE] = -{ - 0x6e6f6d67, /* "gmon" */ - GMON_DATA_SIZE, - 0, - (unsigned int)stext, - (unsigned int)etext, - PCSAMPLE_BYTES_PER_BUCKET, - 0, - (unsigned int)__mcount_fn_head, - (unsigned int)(__mcount_fn_head + HASH_BUCKETS) -}; - -/* This holds the current slab of memory we're allocating out of */ -static char * mcount_slab_ptr = 0; -static int mcount_slab_size = 0; - -#define MCOUNT_SLAB_INCREMENT 1020 - - -/* - * We can't use malloc to allocate memory because that's too complicated, and - * can't be called at interrupt time. Use the lower level allocator instead - * because that's interrupt safe (and because we never free anything). - * - * For speed, we allocate a block of data at once. - */ -static __inline__ void * mcount_allocate(unsigned int size) -{ - void * data; - - if (size > mcount_slab_size) - { - mcount_slab_ptr = sbrk(MCOUNT_SLAB_INCREMENT); - mcount_slab_size = MCOUNT_SLAB_INCREMENT; - } - - data = mcount_slab_ptr; - mcount_slab_ptr += size; - mcount_slab_size -= size; - - return data; -} - - -/* - * Add the arc with the values of frompc and topc given to the graph. - * This function might be called at interrupt time so must be able to - * cope with reentrancy. - * - * The fast case, where we have already allocated a function arc, has been - * handled by the assmebler code. - */ -void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) -{ - alt_irq_context context; - struct mcount_fn_arc * arc_entry; - - /* Keep trying to start up the PC sampler until it is running. - * (It can't start until the timer is going). - */ - if (pcsample_need_init) - { - pcsample_need_init = 0; - pcsample_need_init = nios2_pcsample_init(); - } - - /* - * We must disable interrupts around the allocation and the list update to - * prevent corruption if the instrumented function is re-entrant. - * - * It's safe for the code above to be stepping through the chain and be - * interrupted by this code modifying it - there is an edge case which will - * leave two copies of the same arc on the list (both with count=1), but - * this is dealt with on the host. - */ - context = alt_irq_disable_all(); - - if (fn_entry == NULL) - { - /* Add it to the list of functions we must output later. */ - fn_entry = (struct mcount_fn_entry *)mcount_allocate(sizeof(struct mcount_fn_entry)); - - fn_entry->self_pc = self_pc; - fn_entry->arc_head = NULL; - - fn_entry->next = *fn_head; - *fn_head = fn_entry; - } - - /* We will need a new list entry - if there was a list entry before - * then the assembler code would have handled it. */ - arc_entry = (struct mcount_fn_arc *)mcount_allocate(sizeof(struct mcount_fn_arc)); - - arc_entry->from_pc = from_pc; - arc_entry->count = 1; - - arc_entry->next = fn_entry->arc_head; - fn_entry->arc_head = arc_entry; - - alt_irq_enable_all(context); -} - - -/* - * nios2_pcsample_init starts profiling. - * It is called the first time mcount is called, and on subsequent calls to - * mcount until it returns zero. It initializes the pc histogram and turns on - * timer driven pc sampling. - */ -static int nios2_pcsample_init(void) -{ - unsigned int pcsamples_size; - - /* We sample the PC every tick */ - unsigned int prof_rate = alt_ticks_per_second(); - if (prof_rate == 0) - return 1; - - /* allocate the histogram buffer s_pcsamples */ - pcsamples_size = (s_high_pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; - s_pcsamples = (unsigned short*)sbrk(pcsamples_size * sizeof(unsigned short)); - - if (s_pcsamples != 0) - { - /* initialize the buffer to zero */ - memset(s_pcsamples, 0, pcsamples_size * sizeof(unsigned short)); - - alt_gmon_data[GMON_DATA_PROFILE_DATA] = (int)s_pcsamples; - alt_gmon_data[GMON_DATA_PROFILE_RATE] = prof_rate; - - /* Sample every tick (it's cheap) */ - alt_alarm_start(&s_nios2_pcsample_alarm, 1, nios2_pcsample, 0); - } - - return 0; -} - - -/* - * Sample the PC value and store it in the histogram - */ -static alt_u32 nios2_pcsample(void* context) -{ - unsigned int pc; - unsigned int bucket; - - /* read the exception return address - this will be - * inaccurate if there are nested interrupts but we - * assume that this is rare and the inaccuracy will - * not be great */ - NIOS2_READ_EA(pc); - - /* - * If we're within the profilable range then increment the relevant - * bucket in the histogram - */ - if (pc >= s_low_pc && pc < s_high_pc && s_pcsamples != 0) - { - bucket = (pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; - s_pcsamples[bucket]++; - } - - /* Sample every tick */ - return 1; -} - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include + +#include "priv/nios2_gmon_data.h" + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" + + +/* Macros */ + +/* How large should the bins be which we use to generate the histogram */ +#define PCSAMPLE_BYTES_PER_BUCKET 32 + +#define NIOS2_READ_EA(dest) __asm__ ("mov %0, ea" : "=r" (dest)) + +/* The compiler inserts calls to mcount() at the start of + * every function call. The structure mcount_fn_arc records t + * he return address of the function called (in from_pc) + * and the return address of the mcount function + * (in self_pc). The number of times this arc is executed is + * recorded in the field count. + */ +struct mcount_fn_arc +{ + struct mcount_fn_arc * next; + void * from_pc; + unsigned int count; +}; + +/* We need to maintain a list of pointers to the heads of each adjacency + * list so that we can find them when writing out the gmon.out file. Since + * we don't know at the start of program execution how many functions will + * be called we use a list structure to do this. + */ +struct mcount_fn_entry +{ + struct mcount_fn_entry * next; + void * self_pc; + struct mcount_fn_arc * arc_head; +}; + +/* function prototypes */ + +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) __attribute__ ((no_instrument_function)); + +static __inline__ void * mcount_allocate(unsigned int size) __attribute__ ((no_instrument_function)); +static int nios2_pcsample_init(void) __attribute__ ((no_instrument_function)); +static alt_u32 nios2_pcsample(void* alarm) __attribute__ ((no_instrument_function)); + +/* global variables */ + +/* stext and etext are defined in the linker script */ +extern char stext[]; +extern char etext[]; + +/* Is the PC sampling stuff enabled yet? */ +static int pcsample_need_init = 1; + +#define HASH_BUCKETS 64 /* Must be a power of 2 */ + +/* This points to the list of adjacency list pointers. */ +struct mcount_fn_entry * __mcount_fn_head[HASH_BUCKETS]; + +/* pointer to the in-memory buffer containing the histogram */ +static unsigned short* s_pcsamples = 0; + +/* the address of the start and end of text section */ +static const unsigned int s_low_pc = (unsigned int)stext; +static const unsigned int s_high_pc = (unsigned int)etext; + +/* the alarm structure to register for pc sampling */ +static alt_alarm s_nios2_pcsample_alarm; + +unsigned int alt_gmon_data[GMON_DATA_SIZE] = +{ + 0x6e6f6d67, /* "gmon" */ + GMON_DATA_SIZE, + 0, + (unsigned int)stext, + (unsigned int)etext, + PCSAMPLE_BYTES_PER_BUCKET, + 0, + (unsigned int)__mcount_fn_head, + (unsigned int)(__mcount_fn_head + HASH_BUCKETS) +}; + +/* This holds the current slab of memory we're allocating out of */ +static char * mcount_slab_ptr = 0; +static int mcount_slab_size = 0; + +#define MCOUNT_SLAB_INCREMENT 1020 + + +/* + * We can't use malloc to allocate memory because that's too complicated, and + * can't be called at interrupt time. Use the lower level allocator instead + * because that's interrupt safe (and because we never free anything). + * + * For speed, we allocate a block of data at once. + */ +static __inline__ void * mcount_allocate(unsigned int size) +{ + void * data; + + if (size > mcount_slab_size) + { + mcount_slab_ptr = sbrk(MCOUNT_SLAB_INCREMENT); + mcount_slab_size = MCOUNT_SLAB_INCREMENT; + } + + data = mcount_slab_ptr; + mcount_slab_ptr += size; + mcount_slab_size -= size; + + return data; +} + + +/* + * Add the arc with the values of frompc and topc given to the graph. + * This function might be called at interrupt time so must be able to + * cope with reentrancy. + * + * The fast case, where we have already allocated a function arc, has been + * handled by the assmebler code. + */ +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) +{ + alt_irq_context context; + struct mcount_fn_arc * arc_entry; + + /* Keep trying to start up the PC sampler until it is running. + * (It can't start until the timer is going). + */ + if (pcsample_need_init) + { + pcsample_need_init = 0; + pcsample_need_init = nios2_pcsample_init(); + } + + /* + * We must disable interrupts around the allocation and the list update to + * prevent corruption if the instrumented function is re-entrant. + * + * It's safe for the code above to be stepping through the chain and be + * interrupted by this code modifying it - there is an edge case which will + * leave two copies of the same arc on the list (both with count=1), but + * this is dealt with on the host. + */ + context = alt_irq_disable_all(); + + if (fn_entry == NULL) + { + /* Add it to the list of functions we must output later. */ + fn_entry = (struct mcount_fn_entry *)mcount_allocate(sizeof(struct mcount_fn_entry)); + + fn_entry->self_pc = self_pc; + fn_entry->arc_head = NULL; + + fn_entry->next = *fn_head; + *fn_head = fn_entry; + } + + /* We will need a new list entry - if there was a list entry before + * then the assembler code would have handled it. */ + arc_entry = (struct mcount_fn_arc *)mcount_allocate(sizeof(struct mcount_fn_arc)); + + arc_entry->from_pc = from_pc; + arc_entry->count = 1; + + arc_entry->next = fn_entry->arc_head; + fn_entry->arc_head = arc_entry; + + alt_irq_enable_all(context); +} + + +/* + * nios2_pcsample_init starts profiling. + * It is called the first time mcount is called, and on subsequent calls to + * mcount until it returns zero. It initializes the pc histogram and turns on + * timer driven pc sampling. + */ +static int nios2_pcsample_init(void) +{ + unsigned int pcsamples_size; + + /* We sample the PC every tick */ + unsigned int prof_rate = alt_ticks_per_second(); + if (prof_rate == 0) + return 1; + + /* allocate the histogram buffer s_pcsamples */ + pcsamples_size = (s_high_pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples = (unsigned short*)sbrk(pcsamples_size * sizeof(unsigned short)); + + if (s_pcsamples != 0) + { + /* initialize the buffer to zero */ + memset(s_pcsamples, 0, pcsamples_size * sizeof(unsigned short)); + + alt_gmon_data[GMON_DATA_PROFILE_DATA] = (int)s_pcsamples; + alt_gmon_data[GMON_DATA_PROFILE_RATE] = prof_rate; + + /* Sample every tick (it's cheap) */ + alt_alarm_start(&s_nios2_pcsample_alarm, 1, nios2_pcsample, 0); + } + + return 0; +} + + +/* + * Sample the PC value and store it in the histogram + */ +static alt_u32 nios2_pcsample(void* context) +{ + unsigned int pc; + unsigned int bucket; + + /* read the exception return address - this will be + * inaccurate if there are nested interrupts but we + * assume that this is rare and the inaccuracy will + * not be great */ + NIOS2_READ_EA(pc); + + /* + * If we're within the profilable range then increment the relevant + * bucket in the histogram + */ + if (pc >= s_low_pc && pc < s_high_pc && s_pcsamples != 0) + { + bucket = (pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples[bucket]++; + } + + /* Sample every tick */ + return 1; +} + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_icache_flush.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_icache_flush.c index 4b706ed..1662991 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_icache_flush.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_icache_flush.c @@ -1,84 +1,84 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "nios2.h" -#include "system.h" - -#include "alt_types.h" -#include "sys/alt_cache.h" - -/* - * alt_icache_flush() is called to flush the instruction cache for a memory - * region of length "len" bytes, starting at address "start". - */ - -void alt_icache_flush (void* start, alt_u32 len) -{ -#if NIOS2_ICACHE_SIZE > 0 - - char* i; - char* end; - - /* - * This is the most we would ever need to flush. - */ - - if (len > NIOS2_ICACHE_SIZE) - { - len = NIOS2_ICACHE_SIZE; - } - - end = ((char*) start) + len; - - for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) - { - __asm__ volatile ("flushi %0" :: "r" (i)); - } - - /* - * For an unaligned flush request, we've got one more line left. - * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a - * multiple of 2 (which it always is). - */ - - if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) - { - __asm__ volatile ("flushi %0" :: "r" (i)); - } - - /* - * Having flushed the cache, flush any stale instructions in the - * pipeline - */ - - __asm__ volatile ("flushp"); - -#endif /* NIOS2_ICACHE_SIZE > 0 */ -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +void alt_icache_flush (void* start, alt_u32 len) +{ +#if NIOS2_ICACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + */ + + if (len > NIOS2_ICACHE_SIZE) + { + len = NIOS2_ICACHE_SIZE; + } + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * Having flushed the cache, flush any stale instructions in the + * pipeline + */ + + __asm__ volatile ("flushp"); + +#endif /* NIOS2_ICACHE_SIZE > 0 */ +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_icache_flush_all.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_icache_flush_all.c index 5088552..dc40ea8 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_icache_flush_all.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_icache_flush_all.c @@ -1,46 +1,46 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "nios2.h" -#include "system.h" - -#include "alt_types.h" -#include "sys/alt_cache.h" - -/* - * alt_icache_flush_all() is called to flush the entire instruction cache. - */ - -void alt_icache_flush_all (void) -{ -#if NIOS2_ICACHE_SIZE > 0 - alt_icache_flush (0, NIOS2_ICACHE_SIZE); -#endif -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); +#endif +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_iic.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_iic.c index 1db5afa..4821f25 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_iic.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_iic.c @@ -1,106 +1,106 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ -#include "system.h" - -/* - * This file implements the HAL Enhanced interrupt API for Nios II processors - * with an internal interrupt controller (IIC). For most routines, this serves - * as a wrapper layer over the legacy interrupt API (which must be used with - * the IIC only). - * - * Use of the enhanced API is recommended so that application and device - * drivers are compatible with a Nios II system configured with an external - * interrupt controller (EIC), or IIC. This will afford maximum portability. - * - * If an EIC is present, the EIC device driver must provide these routines, - * because their operation will be specific to that EIC type. - */ -#ifndef NIOS2_EIC_PRESENT -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - -#include "sys/alt_irq.h" -#include "priv/alt_iic_isr_register.h" -#include "priv/alt_legacy_irq.h" - -/** @Function Description: This function registers an interrupt handler. - * If the function is succesful, then the requested interrupt will be enabled upon - * return. Registering a NULL handler will disable the interrupt. - * @API Type: External - * @param ic_id Ignored. - * @param irq IRQ number - * @return 0 if successful, else error (-1) - */ -int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, - void *isr_context, void *flags) -{ - return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); -} - -/** @Function Description: This function enables a single interrupt. - * @API Type: External - * @param ic_id Ignored. - * @param irq IRQ number - * @return 0 if successful, else error (-1) - */ -int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) -{ - return alt_irq_enable(irq); -} - -/** @Function Description: This function disables a single interrupt. - * @API Type: External - * @param ic_id Ignored. - * @param irq IRQ number - * @return 0 if successful, else error (-1) - */ -int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) -{ - return alt_irq_disable(irq); -} - -/** @Function Description: This function to determine if corresponding - * interrupt is enabled. - * @API Type: External - * @param ic_id Ignored. - * @param irq IRQ number - * @return Zero if corresponding interrupt is disabled and - * non-zero otherwise. - */ -alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) -{ - alt_u32 irq_enabled; - - NIOS2_READ_IENABLE(irq_enabled); - - return (irq_enabled & (1 << irq)) ? 1: 0; -} - -#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ -#endif /* NIOS2_EIC_PRESENT */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" + +/* + * This file implements the HAL Enhanced interrupt API for Nios II processors + * with an internal interrupt controller (IIC). For most routines, this serves + * as a wrapper layer over the legacy interrupt API (which must be used with + * the IIC only). + * + * Use of the enhanced API is recommended so that application and device + * drivers are compatible with a Nios II system configured with an external + * interrupt controller (EIC), or IIC. This will afford maximum portability. + * + * If an EIC is present, the EIC device driver must provide these routines, + * because their operation will be specific to that EIC type. + */ +#ifndef NIOS2_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" +#include "priv/alt_legacy_irq.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); +} + +/** @Function Description: This function enables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_enable(irq); +} + +/** @Function Description: This function disables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_disable(irq); +} + +/** @Function Description: This function to determine if corresponding + * interrupt is enabled. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return Zero if corresponding interrupt is disabled and + * non-zero otherwise. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) +{ + alt_u32 irq_enabled; + + NIOS2_READ_IENABLE(irq_enabled); + + return (irq_enabled & (1 << irq)) ? 1: 0; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* NIOS2_EIC_PRESENT */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_iic_isr_register.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_iic_isr_register.c index b104395..2e6bf5b 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_iic_isr_register.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_iic_isr_register.c @@ -1,104 +1,104 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ -#include -#include "system.h" - -/* - * Provides an interrupt registry mechanism for the any CPUs internal interrupt - * controller (IIC) when the enhanced interrupt API is active. - */ -#ifndef ALT_CPU_EIC_PRESENT -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - -#include "alt_types.h" -#include "sys/alt_irq.h" -#include "priv/alt_iic_isr_register.h" - -/* - * The header, alt_irq_entry.h, contains the exception entry point, and is - * provided by the processor component. It is included here, so that the code - * will be added to the executable only if alt_irq_register() is present, i.e. - * if no interrupts are registered - there's no need to provide any - * interrupt handling. - */ - -#include "sys/alt_irq_entry.h" - -/* - * The header, alt_irq_table.h contains a table describing which function - * handles each interrupt. - */ - -#include "priv/alt_irq_table.h" - -/** @Function Description: This function registers an interrupt handler. - * If the function is succesful, then the requested interrupt will be enabled - * upon return. Registering a NULL handler will disable the interrupt. - * - * @API Type: External - * @param ic_id Interrupt controller ID - * @param irq IRQ ID number - * @param isr Pointer to interrupt service routine - * @param isr_context Opaque pointer passed to ISR - * @param flags - * @return 0 if successful, else error (-1) - */ -int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, - void *isr_context, void *flags) -{ - int rc = -EINVAL; - int id = irq; /* IRQ interpreted as the interrupt ID. */ - alt_irq_context status; - - if (id < ALT_NIRQ) - { - /* - * interrupts are disabled while the handler tables are updated to ensure - * that an interrupt doesn't occur while the tables are in an inconsistant - * state. - */ - - status = alt_irq_disable_all(); - - alt_irq[id].handler = isr; - alt_irq[id].context = isr_context; - - rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); - - alt_irq_enable_all(status); - } - - return rc; -} - -#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ -#endif /* ALT_CPU_EIC_PRESENT */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * Provides an interrupt registry mechanism for the any CPUs internal interrupt + * controller (IIC) when the enhanced interrupt API is active. + */ +#ifndef ALT_CPU_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "alt_types.h" +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled + * upon return. Registering a NULL handler will disable the interrupt. + * + * @API Type: External + * @param ic_id Interrupt controller ID + * @param irq IRQ ID number + * @param isr Pointer to interrupt service routine + * @param isr_context Opaque pointer passed to ISR + * @param flags + * @return 0 if successful, else error (-1) + */ +int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + int rc = -EINVAL; + int id = irq; /* IRQ interpreted as the interrupt ID. */ + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all(); + + alt_irq[id].handler = isr; + alt_irq[id].context = isr_context; + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + + alt_irq_enable_all(status); + } + + return rc; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_instruction_exception_entry.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_instruction_exception_entry.c index f4f52fc..5cc8767 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_instruction_exception_entry.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_instruction_exception_entry.c @@ -1,203 +1,203 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ -#include "sys/alt_exceptions.h" -#include "nios2.h" -#include "alt_types.h" -#include "system.h" - -/* - * This file implements support for calling user-registered handlers for - * instruction-generated exceptions. This handler could also be reached - * in the event of a spurious interrupt. - * - * The handler code is optionally enabled through the "Enable - * Instruction-related Exception API" HAL BSP setting, which will - * define the macro below. - */ -#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API - -/* Function pointer to exception callback routine */ -alt_exception_result (*alt_instruction_exception_handler) - (alt_exception_cause, alt_u32, alt_u32) = 0x0; - -/* Link entry routine to .exceptions section */ -int alt_instruction_exception_entry (alt_u32 exception_pc) - __attribute__ ((section (".exceptions"))); - -/* - * This is the entry point for instruction-generated exceptions handling. - * This routine will be called by alt_exceptions_entry.S, after it determines - * that an exception could not be handled by handlers that preceed that - * of instruction-generated exceptions (such as interrupts). - * - * For this to function properly, you must register an exception handler - * using alt_instruction_exception_register(). This routine will call - * that handler if it has been registered. Absent a handler, it will - * break break or hang as discussed below. - */ -int alt_instruction_exception_entry (alt_u32 exception_pc) -{ - alt_u32 cause, badaddr; - -/* - * If the processor hardware has the optional EXCEPTIONS & BADADDR registers, - * read them and pass their content to the user handler. These are always - * present if the MMU or MPU is enabled, and optionally for other advanced - * exception types via the "Extra exceptions information" setting in the - * processor (hardware) configuration. - * - * If these registers are not present, the cause field will be set to - * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should - * check the validity of the cause argument before proceeding. - */ -#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO - /* Get exception cause & "badaddr" */ - NIOS2_READ_EXCEPTION(cause); - cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >> - NIOS2_EXCEPTION_REG_CAUSE_OFST ); - - NIOS2_READ_BADADDR(badaddr); -#else - cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT; - badaddr = 0; -#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */ - - if(alt_instruction_exception_handler) { - /* - * Call handler. Its return value indicates whether the exception-causing - * instruction should be re-issued. The code that called us, - * alt_eceptions_entry.S, will look at this value and adjust the ea - * register as necessary - */ - return alt_instruction_exception_handler(cause, exception_pc, badaddr); - } - /* - * We got here because an instruction-generated exception occured, but no - * handler is present. We do not presume to know how to handle it. If the - * debugger is present, break, otherwise hang. - * - * If you've reached here in the debugger, consider examining the - * EXCEPTIONS register cause bit-field, which was read into the 'cause' - * variable above, and compare it against the exceptions-type enumeration - * in alt_exceptions.h. This register is availabe if the MMU or MPU is - * present, or if the "Extra exceptions information" hardware option is - * selected. - * - * If you get here then one of the following could have happened: - * - * - An instruction-generated exception occured, and the processor - * does not have the extra exceptions feature enabled, or you - * have not registered a handler using - * alt_instruction_exception_register() - * - * Some examples of instruction-generated exceptions and why they - * might occur: - * - * - Your program could have been compiled for a full-featured - * Nios II core, but it is running on a smaller core, and - * instruction emulation has been disabled by defining - * ALT_NO_INSTRUCTION_EMULATION. - * - * You can work around the problem by re-enabling instruction - * emulation, or you can figure out why your program is being - * compiled for a system other than the one that it is running on. - * - * - Your program has executed a trap instruction, but has not - * implemented a handler for this instruction. - * - * - Your program has executed an illegal instruction (one which is - * not defined in the instruction set). - * - * - Your processor includes an MMU or MPU, and you have enabled it - * before registering an exception handler to service exceptions it - * generates. - * - * The problem could also be hardware related: - * - If your hardware is broken and is generating spurious interrupts - * (a peripheral which negates its interrupt output before its - * interrupt handler has been executed will cause spurious interrupts) - */ - else { -#ifdef NIOS2_HAS_DEBUG_STUB - NIOS2_BREAK(); -#else - while(1) - ; -#endif /* NIOS2_HAS_DEBUG_STUB */ - } - - /* // We should not get here. Remove compiler warning. */ - return NIOS2_EXCEPTION_RETURN_REISSUE_INST; -} - -#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ - -/* - * This routine indicates whether a particular exception cause will have - * set a valid address into the BADADDR register, which is included - * in the arguments to a user-registered instruction-generated exception - * handler. Many exception types do not set valid contents in BADADDR; - * this is a convenience routine to easily test the validity of that - * argument in your handler. - * - * Note that this routine will return false (0) for cause '12', - * TLB miss. This is because there are four exception types that - * share that cause, two of which do not have a valid BADADDR. You - * must determine BADADDR's validity for these. - * - * Arguments: - * cause: The 5-bit exception cause field of the EXCEPTIONS register, - * shifted to the LSB position. You may pass the 'cause' argument - * in a handler you registered directy to this routine. - * - * Return: 1: BADADDR (bad_addr argument to handler) is valid - * 0: BADADDR is not valid - */ -int alt_exception_cause_generated_bad_addr(alt_exception_cause cause) -{ - switch (cause) { - case NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR: - return 1; - case NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR: - return 1; - case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC: - return 1; - case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION: - return 1; - case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION: - return 1; - case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION: - return 1; - default: - return 0; - } -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. This handler could also be reached + * in the event of a spurious interrupt. + * + * The handler code is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* Function pointer to exception callback routine */ +alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32) = 0x0; + +/* Link entry routine to .exceptions section */ +int alt_instruction_exception_entry (alt_u32 exception_pc) + __attribute__ ((section (".exceptions"))); + +/* + * This is the entry point for instruction-generated exceptions handling. + * This routine will be called by alt_exceptions_entry.S, after it determines + * that an exception could not be handled by handlers that preceed that + * of instruction-generated exceptions (such as interrupts). + * + * For this to function properly, you must register an exception handler + * using alt_instruction_exception_register(). This routine will call + * that handler if it has been registered. Absent a handler, it will + * break break or hang as discussed below. + */ +int alt_instruction_exception_entry (alt_u32 exception_pc) +{ + alt_u32 cause, badaddr; + +/* + * If the processor hardware has the optional EXCEPTIONS & BADADDR registers, + * read them and pass their content to the user handler. These are always + * present if the MMU or MPU is enabled, and optionally for other advanced + * exception types via the "Extra exceptions information" setting in the + * processor (hardware) configuration. + * + * If these registers are not present, the cause field will be set to + * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should + * check the validity of the cause argument before proceeding. + */ +#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO + /* Get exception cause & "badaddr" */ + NIOS2_READ_EXCEPTION(cause); + cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >> + NIOS2_EXCEPTION_REG_CAUSE_OFST ); + + NIOS2_READ_BADADDR(badaddr); +#else + cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT; + badaddr = 0; +#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */ + + if(alt_instruction_exception_handler) { + /* + * Call handler. Its return value indicates whether the exception-causing + * instruction should be re-issued. The code that called us, + * alt_eceptions_entry.S, will look at this value and adjust the ea + * register as necessary + */ + return alt_instruction_exception_handler(cause, exception_pc, badaddr); + } + /* + * We got here because an instruction-generated exception occured, but no + * handler is present. We do not presume to know how to handle it. If the + * debugger is present, break, otherwise hang. + * + * If you've reached here in the debugger, consider examining the + * EXCEPTIONS register cause bit-field, which was read into the 'cause' + * variable above, and compare it against the exceptions-type enumeration + * in alt_exceptions.h. This register is availabe if the MMU or MPU is + * present, or if the "Extra exceptions information" hardware option is + * selected. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious interrupts) + */ + else { +#ifdef NIOS2_HAS_DEBUG_STUB + NIOS2_BREAK(); +#else + while(1) + ; +#endif /* NIOS2_HAS_DEBUG_STUB */ + } + + /* // We should not get here. Remove compiler warning. */ + return NIOS2_EXCEPTION_RETURN_REISSUE_INST; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * This routine indicates whether a particular exception cause will have + * set a valid address into the BADADDR register, which is included + * in the arguments to a user-registered instruction-generated exception + * handler. Many exception types do not set valid contents in BADADDR; + * this is a convenience routine to easily test the validity of that + * argument in your handler. + * + * Note that this routine will return false (0) for cause '12', + * TLB miss. This is because there are four exception types that + * share that cause, two of which do not have a valid BADADDR. You + * must determine BADADDR's validity for these. + * + * Arguments: + * cause: The 5-bit exception cause field of the EXCEPTIONS register, + * shifted to the LSB position. You may pass the 'cause' argument + * in a handler you registered directy to this routine. + * + * Return: 1: BADADDR (bad_addr argument to handler) is valid + * 0: BADADDR is not valid + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause) +{ + switch (cause) { + case NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR: + return 1; + case NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR: + return 1; + case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC: + return 1; + case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION: + return 1; + case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION: + return 1; + case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION: + return 1; + default: + return 0; + } +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_instruction_exception_register.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_instruction_exception_register.c index b059e1d..395c644 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_instruction_exception_register.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_instruction_exception_register.c @@ -1,82 +1,82 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ -#include "sys/alt_exceptions.h" -#include "alt_types.h" -#include "system.h" - -/* - * This file implements support for calling user-registered handlers for - * instruction-generated exceptions. - * - * The registry API is optionally enabled through the "Enable - * Instruction-related Exception API" HAL BSP setting, which will - * define the macro below. - */ -#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API - -/* - * The header, alt_exception_handler_registry.h contains a struct describing - * the registered exception handler - */ -#include "priv/alt_exception_handler_registry.h" - -/* - * Pull in the exception entry assembly code. This will not be linked in - * unless this object is linked into the executable (i.e. only if - * alt_instruction_exception_register() is called). - */ -__asm__( "\n\t.globl alt_exception" ); - -/* - * alt_instruction_exception_register() is called to register a handler to - * service instruction-generated exceptions that are not handled by the - * default exception handler code (interrupts, and optionally unimplemented - * instructions and traps). - * - * Passing null (0x0) in the handler argument will disable a previously- - * registered handler. - * - * Note that if no handler is registered, exceptions that are not processed - * using the built-in handler (interrupts, and optionally unimplemented - * instructions and traps) are treated as unknown exceptions, resulting - * in either a break or an infinite loop. - */ -void alt_instruction_exception_register ( - alt_exception_result (*exception_handler)( - alt_exception_cause cause, - alt_u32 exception_pc, - alt_u32 bad_addr) ) -{ - alt_instruction_exception_handler = exception_handler; -} - -#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* + * The header, alt_exception_handler_registry.h contains a struct describing + * the registered exception handler + */ +#include "priv/alt_exception_handler_registry.h" + +/* + * Pull in the exception entry assembly code. This will not be linked in + * unless this object is linked into the executable (i.e. only if + * alt_instruction_exception_register() is called). + */ +__asm__( "\n\t.globl alt_exception" ); + +/* + * alt_instruction_exception_register() is called to register a handler to + * service instruction-generated exceptions that are not handled by the + * default exception handler code (interrupts, and optionally unimplemented + * instructions and traps). + * + * Passing null (0x0) in the handler argument will disable a previously- + * registered handler. + * + * Note that if no handler is registered, exceptions that are not processed + * using the built-in handler (interrupts, and optionally unimplemented + * instructions and traps) are treated as unknown exceptions, resulting + * in either a break or an infinite loop. + */ +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ) +{ + alt_instruction_exception_handler = exception_handler; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_io_redirect.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_io_redirect.c index 8c862f7..049ed62 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_io_redirect.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_io_redirect.c @@ -1,98 +1,98 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include -#include -#include - -#include "sys/alt_dev.h" -#include "priv/alt_file.h" - - -/* - * alt_open_fd() is similar to open() in that it is used to obtain a file - * descriptor for the file named "name". The "flags" and "mode" arguments are - * identical to the "flags" and "mode" arguments of open(). - * - * The distinction between the two functions is that the file descriptor - * structure to use is passed in as an argument, rather than allocated from the - * list of free file descriptors. - * - * This is used by alt_io_redirect() to redirect the stdin, stdout and stderr - * file descriptors to point to new devices. - * - * If the device can not be succesfully opened, then the input file descriptor - * remains unchanged. - */ - -static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) -{ - int old; - - old = open (name, flags, mode); - - if (old >= 0) - { - fd->dev = alt_fd_list[old].dev; - fd->priv = alt_fd_list[old].priv; - fd->fd_flags = alt_fd_list[old].fd_flags; - - alt_release_fd (old); - } -} - -/* - * alt_io_redirect() is called once the device/filesystem lists have been - * initialised, but before main(). Its function is to redirect standard in, - * standard out and standard error so that they point to the devices selected by - * the user (as defined in system.h). - * - * Prior to the call to this function, io is directed towards /dev/null. If - * i/o can not be redirected to the requested device, for example if the device - * does not exist, then it remains directed at /dev/null. - */ - -void alt_io_redirect(const char* stdout_dev, - const char* stdin_dev, - const char* stderr_dev) -{ - /* Redirect the channels */ - - alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); - alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); - alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); -} - - - - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + + +/* + * alt_open_fd() is similar to open() in that it is used to obtain a file + * descriptor for the file named "name". The "flags" and "mode" arguments are + * identical to the "flags" and "mode" arguments of open(). + * + * The distinction between the two functions is that the file descriptor + * structure to use is passed in as an argument, rather than allocated from the + * list of free file descriptors. + * + * This is used by alt_io_redirect() to redirect the stdin, stdout and stderr + * file descriptors to point to new devices. + * + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + int old; + + old = open (name, flags, mode); + + if (old >= 0) + { + fd->dev = alt_fd_list[old].dev; + fd->priv = alt_fd_list[old].priv; + fd->fd_flags = alt_fd_list[old].fd_flags; + + alt_release_fd (old); + } +} + +/* + * alt_io_redirect() is called once the device/filesystem lists have been + * initialised, but before main(). Its function is to redirect standard in, + * standard out and standard error so that they point to the devices selected by + * the user (as defined in system.h). + * + * Prior to the call to this function, io is directed towards /dev/null. If + * i/o can not be redirected to the requested device, for example if the device + * does not exist, then it remains directed at /dev/null. + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); +} + + + + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_ioctl.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_ioctl.c index f5d7ef1..510b40d 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_ioctl.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_ioctl.c @@ -1,170 +1,170 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#include "sys/ioctl.h" -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "priv/alt_file.h" -#include "os/alt_syscall.h" - -/* - * The ioctl() system call is provided so that application code can manipulate - * the i/o capabilities of a device in device specific ways. This is identical - * to the standard posix ioctl() function. - * - * In general this implementation simply vectors ioctl requests to the - * apropriate drivers ioctl function (as registered in the drivers alt_dev - * structure). - * - * However in the case of devices (as oposed to filesystem), the TIOCEXCL and - * TIOCNXCL requests are handled without reference to the driver. These - * requests are used to lock/release a device for exclusive access. - * - * Handling these requests centrally eases the task of device driver - * development. - * - * ALT_IOCTL is mapped onto the ioctl() system call in alt_syscall.h - */ - -#ifdef ALT_USE_DIRECT_DRIVERS - -#include "system.h" -#include "sys/alt_driver.h" - -/* - * Provide minimal version that calls ioctl routine of provided stdio devices. - */ -int ALT_IOCTL (int file, int req, void* arg) -{ -#ifdef ALT_STDIN_PRESENT - ALT_DRIVER_IOCTL_EXTERNS(ALT_STDIN_DEV); -#endif -#ifdef ALT_STDOUT_PRESENT - ALT_DRIVER_IOCTL_EXTERNS(ALT_STDOUT_DEV); -#endif -#ifdef ALT_STDERR_PRESENT - ALT_DRIVER_IOCTL_EXTERNS(ALT_STDERR_DEV); -#endif - -#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) - /* Generate a link time warning, should this function ever be called. */ - ALT_STUB_WARNING(ioctl); -#endif - - switch (file) { -#ifdef ALT_STDIN_PRESENT - case 0: /* stdin file descriptor */ - return ALT_DRIVER_IOCTL(ALT_STDIN_DEV, req, arg); -#endif /* ALT_STDIN_PRESENT */ -#ifdef ALT_STDOUT_PRESENT - case 1: /* stdout file descriptor */ - return ALT_DRIVER_IOCTL(ALT_STDOUT_DEV, req, arg); -#endif /* ALT_STDOUT_PRESENT */ -#ifdef ALT_STDERR_PRESENT - case 2: /* stderr file descriptor */ - return ALT_DRIVER_IOCTL(ALT_STDERR_DEV, req, arg); -#endif /* ALT_STDERR_PRESENT */ - default: - ALT_ERRNO = EBADFD; - return -1; - } -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -int ALT_IOCTL (int file, int req, void* arg) -{ - alt_fd* fd; - int rc; - - /* - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - - if (fd) - { - - /* - * In the case of device drivers (not file systems) handle the TIOCEXCL - * and TIOCNXCL requests as special cases. - */ - - if (fd->fd_flags & ALT_FD_DEV) - { - if (req == TIOCEXCL) - { - rc = alt_fd_lock (fd); - goto ioctl_done; - } - else if (req == TIOCNXCL) - { - rc = alt_fd_unlock (fd); - goto ioctl_done; - } - } - - /* - * If the driver provides an ioctl() function, call that to handle the - * request, otherwise set the return code to indicate that the request - * could not be processed. - */ - - if (fd->dev->ioctl) - { - rc = fd->dev->ioctl(fd, req, arg); - } - else - { - rc = -ENOTTY; - } - } - else - { - rc = -EBADFD; - } - -ioctl_done: - - if (rc < 0) - { - ALT_ERRNO = -rc; - } - return rc; -} - -#endif /* ALT_USE_DIRECT_DRIVERS */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/ioctl.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The ioctl() system call is provided so that application code can manipulate + * the i/o capabilities of a device in device specific ways. This is identical + * to the standard posix ioctl() function. + * + * In general this implementation simply vectors ioctl requests to the + * apropriate drivers ioctl function (as registered in the drivers alt_dev + * structure). + * + * However in the case of devices (as oposed to filesystem), the TIOCEXCL and + * TIOCNXCL requests are handled without reference to the driver. These + * requests are used to lock/release a device for exclusive access. + * + * Handling these requests centrally eases the task of device driver + * development. + * + * ALT_IOCTL is mapped onto the ioctl() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that calls ioctl routine of provided stdio devices. + */ +int ALT_IOCTL (int file, int req, void* arg) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDIN_DEV); +#endif +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(ioctl); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDIN_DEV, req, arg); +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDOUT_DEV, req, arg); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDERR_DEV, req, arg); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_IOCTL (int file, int req, void* arg) +{ + alt_fd* fd; + int rc; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + + /* + * In the case of device drivers (not file systems) handle the TIOCEXCL + * and TIOCNXCL requests as special cases. + */ + + if (fd->fd_flags & ALT_FD_DEV) + { + if (req == TIOCEXCL) + { + rc = alt_fd_lock (fd); + goto ioctl_done; + } + else if (req == TIOCNXCL) + { + rc = alt_fd_unlock (fd); + goto ioctl_done; + } + } + + /* + * If the driver provides an ioctl() function, call that to handle the + * request, otherwise set the return code to indicate that the request + * could not be processed. + */ + + if (fd->dev->ioctl) + { + rc = fd->dev->ioctl(fd, req, arg); + } + else + { + rc = -ENOTTY; + } + } + else + { + rc = -EBADFD; + } + +ioctl_done: + + if (rc < 0) + { + ALT_ERRNO = -rc; + } + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_entry.S b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_entry.S index d3efe7d..8ee89e1 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_entry.S +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_entry.S @@ -1,108 +1,108 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "system.h" - -/* - * This is the interrupt exception entry point code, which saves all the - * registers and calls the interrupt handler. It should be pulled in using - * a .globl from alt_irq_register.c. This scheme is used so that if an - * interrupt is never registered, then this code will not appear in the - * generated executable, thereby improving code footprint. - */ - - /* - * Explicitly allow the use of r1 (the assembler temporary register) - * within this code. This register is normally reserved for the use of - * the compiler. - */ - .set noat - - /* - * Pull in the exception handler register save code. - */ - .globl alt_exception - - .globl alt_irq_entry - .section .exceptions.entry.label, "xa" -alt_irq_entry: - - /* - * Section .exceptions.entry is in alt_exception_entry.S - * This saves all the caller saved registers and reads estatus into r5 - */ - - .section .exceptions.irqtest, "xa" - -#ifdef ALT_CI_INTERRUPT_VECTOR_N - /* - * Use the interrupt vector custom instruction if present to accelerate - * this code. - * If the interrupt vector custom instruction returns a negative - * value, there are no interrupts active (estatus.pie is 0 - * or ipending is 0) so assume it is a software exception. - */ - custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0 - blt r4, r0, .Lnot_irq -#else - /* - * Test to see if the exception was a software exception or caused - * by an external interrupt, and vector accordingly. - */ - rdctl r4, ipending - andi r2, r5, 1 - beq r2, zero, .Lnot_irq - beq r4, zero, .Lnot_irq -#endif /* ALT_CI_INTERRUPT_VECTOR_N */ - - .section .exceptions.irqhandler, "xa" - /* - * Now that all necessary registers have been preserved, call - * alt_irq_handler() to process the interrupts. - */ - - call alt_irq_handler - - .section .exceptions.irqreturn, "xa" - - br .Lexception_exit - - .section .exceptions.notirq.label, "xa" - -.Lnot_irq: - - /* - * Section .exceptions.exit is in alt_exception_entry.S - * This restores all the caller saved registers - */ - - .section .exceptions.exit.label -.Lexception_exit: - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the interrupt exception entry point code, which saves all the + * registers and calls the interrupt handler. It should be pulled in using + * a .globl from alt_irq_register.c. This scheme is used so that if an + * interrupt is never registered, then this code will not appear in the + * generated executable, thereby improving code footprint. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the compiler. + */ + .set noat + + /* + * Pull in the exception handler register save code. + */ + .globl alt_exception + + .globl alt_irq_entry + .section .exceptions.entry.label, "xa" +alt_irq_entry: + + /* + * Section .exceptions.entry is in alt_exception_entry.S + * This saves all the caller saved registers and reads estatus into r5 + */ + + .section .exceptions.irqtest, "xa" + +#ifdef ALT_CI_INTERRUPT_VECTOR_N + /* + * Use the interrupt vector custom instruction if present to accelerate + * this code. + * If the interrupt vector custom instruction returns a negative + * value, there are no interrupts active (estatus.pie is 0 + * or ipending is 0) so assume it is a software exception. + */ + custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0 + blt r4, r0, .Lnot_irq +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + andi r2, r5, 1 + beq r2, zero, .Lnot_irq + beq r4, zero, .Lnot_irq +#endif /* ALT_CI_INTERRUPT_VECTOR_N */ + + .section .exceptions.irqhandler, "xa" + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + + .section .exceptions.notirq.label, "xa" + +.Lnot_irq: + + /* + * Section .exceptions.exit is in alt_exception_entry.S + * This restores all the caller saved registers + */ + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_handler.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_handler.c index 3253d02..bb52fc8 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_handler.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_handler.c @@ -1,169 +1,169 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include "system.h" - -/* - * This interrupt handler only works with an internal interrupt controller - * (IIC). Processors with an external interrupt controller (EIC) use an - * implementation provided by an EIC driver. - */ -#ifndef ALT_CPU_EIC_PRESENT - -#include "sys/alt_irq.h" -#include "os/alt_hooks.h" - -#include "alt_types.h" - -/* - * A table describing each interrupt handler. The index into the array is the - * interrupt id associated with the handler. - * - * When an interrupt occurs, the associated handler is called with - * the argument stored in the context member. - */ -struct ALT_IRQ_HANDLER -{ -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - void (*handler)(void*); -#else - void (*handler)(void*, alt_u32); -#endif - void *context; -} alt_irq[ALT_NIRQ]; - -/* - * alt_irq_handler() is called by the interrupt exception handler in order to - * process any outstanding interrupts. - * - * It is defined here since it is linked in using weak linkage. - * This means that if there is never a call to alt_irq_register() (above) then - * this function will not get linked in to the executable. This is acceptable - * since if no handler is ever registered, then an interrupt can never occur. - * - * If Nios II interrupt vector custom instruction exists, use it to accelerate - * the dispatch of interrupt handlers. The Nios II interrupt vector custom - * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. - */ - -void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); -void alt_irq_handler (void) -{ -#ifdef ALT_CI_INTERRUPT_VECTOR - alt_32 offset; - char* alt_irq_base = (char*)alt_irq; -#else - alt_u32 active; - alt_u32 mask; - alt_u32 i; -#endif /* ALT_CI_INTERRUPT_VECTOR */ - - /* - * Notify the operating system that we are at interrupt level. - */ - - ALT_OS_INT_ENTER(); - -#ifdef ALT_CI_INTERRUPT_VECTOR - /* - * Call the interrupt vector custom instruction using the - * ALT_CI_INTERRUPT_VECTOR macro. - * It returns the offset into the vector table of the lowest-valued pending - * interrupt (corresponds to highest priority) or a negative value if none. - * The custom instruction assumes that each table entry is eight bytes. - */ - while ((offset = ALT_CI_INTERRUPT_VECTOR) >= 0) { - struct ALT_IRQ_HANDLER* handler_entry = - (struct ALT_IRQ_HANDLER*)(alt_irq_base + offset); -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - handler_entry->handler(handler_entry->context); -#else - handler_entry->handler(handler_entry->context, offset >> 3); -#endif - } -#else /* ALT_CI_INTERRUPT_VECTOR */ - /* - * Obtain from the interrupt controller a bit list of pending interrupts, - * and then process the highest priority interrupt. This process loops, - * loading the active interrupt list on each pass until alt_irq_pending() - * return zero. - * - * The maximum interrupt latency for the highest priority interrupt is - * reduced by finding out which interrupts are pending as late as possible. - * Consider the case where the high priority interupt is asserted during - * the interrupt entry sequence for a lower priority interrupt to see why - * this is the case. - */ - - active = alt_irq_pending (); - - do - { - i = 0; - mask = 1; - - /* - * Test each bit in turn looking for an active interrupt. Once one is - * found, the interrupt handler asigned by a call to alt_irq_register() is - * called to clear the interrupt condition. - */ - - do - { - if (active & mask) - { -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - alt_irq[i].handler(alt_irq[i].context); -#else - alt_irq[i].handler(alt_irq[i].context, i); -#endif - break; - } - mask <<= 1; - i++; - - } while (1); - - active = alt_irq_pending (); - - } while (active); -#endif /* ALT_CI_INTERRUPT_VECTOR */ - - /* - * Notify the operating system that interrupt processing is complete. - */ - - ALT_OS_INT_EXIT(); -} - -#endif /* ALT_CPU_EIC_PRESENT */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include "system.h" + +/* + * This interrupt handler only works with an internal interrupt controller + * (IIC). Processors with an external interrupt controller (EIC) use an + * implementation provided by an EIC driver. + */ +#ifndef ALT_CPU_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * A table describing each interrupt handler. The index into the array is the + * interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + */ +struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +/* + * alt_irq_handler() is called by the interrupt exception handler in order to + * process any outstanding interrupts. + * + * It is defined here since it is linked in using weak linkage. + * This means that if there is never a call to alt_irq_register() (above) then + * this function will not get linked in to the executable. This is acceptable + * since if no handler is ever registered, then an interrupt can never occur. + * + * If Nios II interrupt vector custom instruction exists, use it to accelerate + * the dispatch of interrupt handlers. The Nios II interrupt vector custom + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ +#ifdef ALT_CI_INTERRUPT_VECTOR + alt_32 offset; + char* alt_irq_base = (char*)alt_irq; +#else + alt_u32 active; + alt_u32 mask; + alt_u32 i; +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + +#ifdef ALT_CI_INTERRUPT_VECTOR + /* + * Call the interrupt vector custom instruction using the + * ALT_CI_INTERRUPT_VECTOR macro. + * It returns the offset into the vector table of the lowest-valued pending + * interrupt (corresponds to highest priority) or a negative value if none. + * The custom instruction assumes that each table entry is eight bytes. + */ + while ((offset = ALT_CI_INTERRUPT_VECTOR) >= 0) { + struct ALT_IRQ_HANDLER* handler_entry = + (struct ALT_IRQ_HANDLER*)(alt_irq_base + offset); +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + handler_entry->handler(handler_entry->context); +#else + handler_entry->handler(handler_entry->context, offset >> 3); +#endif + } +#else /* ALT_CI_INTERRUPT_VECTOR */ + /* + * Obtain from the interrupt controller a bit list of pending interrupts, + * and then process the highest priority interrupt. This process loops, + * loading the active interrupt list on each pass until alt_irq_pending() + * return zero. + * + * The maximum interrupt latency for the highest priority interrupt is + * reduced by finding out which interrupts are pending as late as possible. + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + + do + { + i = 0; + mask = 1; + + /* + * Test each bit in turn looking for an active interrupt. Once one is + * found, the interrupt handler asigned by a call to alt_irq_register() is + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + + } while (active); +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); +} + +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_register.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_register.c index b5ea474..cf7261e 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_register.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_register.c @@ -1,102 +1,102 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ -#include -#include "system.h" - -/* - * This interrupt registry mechanism works with the Nios II internal interrupt - * controller (IIC) only. Systems with an external interrupt controller (EIC), - * or those with the IIC who are using the enhanced interrupt API will - * utilize the alt_ic_isr_register() routine to register an interrupt. - */ -#ifndef NIOS2_EIC_PRESENT - -#include "sys/alt_irq.h" -#include "priv/alt_legacy_irq.h" -#include "os/alt_hooks.h" - -#include "alt_types.h" - -/* - * The header, alt_irq_entry.h, contains the exception entry point, and is - * provided by the processor component. It is included here, so that the code - * will be added to the executable only if alt_irq_register() is present, i.e. - * if no interrupts are registered - there's no need to provide any - * interrupt handling. - */ - -#include "sys/alt_irq_entry.h" - -/* - * The header, alt_irq_table.h contains a table describing which function - * handles each interrupt. - */ - -#include "priv/alt_irq_table.h" - -/* - * alt_irq_handler() is called to register an interrupt handler. If the - * function is succesful, then the requested interrupt will be enabled upon - * return. Registering a NULL handler will disable the interrupt. - * - * The return value is 0 if the interrupt handler was registered and the - * interrupt was enabled, otherwise it is negative. - */ - -int alt_irq_register (alt_u32 id, - void* context, - alt_isr_func handler) -{ - int rc = -EINVAL; - alt_irq_context status; - - if (id < ALT_NIRQ) - { - /* - * interrupts are disabled while the handler tables are updated to ensure - * that an interrupt doesn't occur while the tables are in an inconsistant - * state. - */ - - status = alt_irq_disable_all (); - - alt_irq[id].handler = handler; - alt_irq[id].context = context; - - rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); - - alt_irq_enable_all(status); - } - return rc; -} -#endif /* NIOS2_EIC_PRESENT */ - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * This interrupt registry mechanism works with the Nios II internal interrupt + * controller (IIC) only. Systems with an external interrupt controller (EIC), + * or those with the IIC who are using the enhanced interrupt API will + * utilize the alt_ic_isr_register() routine to register an interrupt. + */ +#ifndef NIOS2_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_legacy_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/* + * alt_irq_handler() is called to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * + * The return value is 0 if the interrupt handler was registered and the + * interrupt was enabled, otherwise it is negative. + */ + +int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler) +{ + int rc = -EINVAL; + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + + alt_irq[id].handler = handler; + alt_irq[id].context = context; + + rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); + + alt_irq_enable_all(status); + } + return rc; +} +#endif /* NIOS2_EIC_PRESENT */ + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_vars.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_vars.c index 8c0a18d..4f4d140 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_vars.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_irq_vars.c @@ -1,47 +1,47 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "alt_types.h" - -#include "system.h" - -/* - * These global variables are used to save the current list of enabled - * interrupts. See alt_irq.h for further details. - */ - -volatile alt_u32 alt_irq_active = 0; - -#ifndef ALT_EXCEPTION_STACK - -volatile alt_u32 alt_priority_mask = (alt_u32) -1; - -#endif - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#include "system.h" + +/* + * These global variables are used to save the current list of enabled + * interrupts. See alt_irq.h for further details. + */ + +volatile alt_u32 alt_irq_active = 0; + +#ifndef ALT_EXCEPTION_STACK + +volatile alt_u32 alt_priority_mask = (alt_u32) -1; + +#endif + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_isatty.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_isatty.c index 9276472..73677dd 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_isatty.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_isatty.c @@ -1,125 +1,125 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include - -#include "sys/alt_dev.h" -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "priv/alt_file.h" -#include "os/alt_syscall.h" - -#ifdef ALT_USE_DIRECT_DRIVERS - -#include "system.h" - -/* - * Provide minimal version that just describes all file descriptors - * as tty devices for provided stdio devices. - */ -int ALT_ISATTY (int file) -{ - switch (file) { -#ifdef ALT_STDIN_PRESENT - case 0: /* stdin file descriptor */ -#endif /* ALT_STDIN_PRESENT */ -#ifdef ALT_STDOUT_PRESENT - case 1: /* stdout file descriptor */ -#endif /* ALT_STDOUT_PRESENT */ -#ifdef ALT_STDERR_PRESENT - case 2: /* stderr file descriptor */ -#endif /* ALT_STDERR_PRESENT */ - return 1; - default: - return 0; - } - -#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) - /* Generate a link time warning, should this function ever be called. */ - ALT_STUB_WARNING(isatty); -#endif -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ -/* - * isatty() can be used to determine whether the input file descriptor "file" - * refers to a terminal device or not. If it is a terminal device then the - * return value is one, otherwise it is zero. - * - * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h - */ - -int ALT_ISATTY (int file) -{ - alt_fd* fd; - struct stat stat; - - /* - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - - if (fd) - { - /* - * If a device driver does not provide an fstat() function, then it is - * treated as a terminal device by default. - */ - - if (!fd->dev->fstat) - { - return 1; - } - - /* - * If a driver does provide an implementation of the fstat() function, then - * this is called so that the device can identify itself. - */ - - else - { - fstat (file, &stat); - return (stat.st_mode == _IFCHR) ? 1 : 0; - } - } - else - { - ALT_ERRNO = EBADFD; - return 0; - } -} - -#endif /* ALT_USE_DIRECT_DRIVERS */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as tty devices for provided stdio devices. + */ +int ALT_ISATTY (int file) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + return 1; + default: + return 0; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(isatty); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ +/* + * isatty() can be used to determine whether the input file descriptor "file" + * refers to a terminal device or not. If it is a terminal device then the + * return value is one, otherwise it is zero. + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + alt_fd* fd; + struct stat stat; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + { + return 1; + } + + /* + * If a driver does provide an implementation of the fstat() function, then + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + return (stat.st_mode == _IFCHR) ? 1 : 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return 0; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_kill.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_kill.c index 42c2e1d..58097d1 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_kill.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_kill.c @@ -1,121 +1,121 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include - -#include "sys/alt_errno.h" -#include "os/alt_syscall.h" - - -/* - * kill() is used by newlib in order to send signals to processes. Since there - * is only a single process in the HAL, the only valid values for pid are - * either the current process id, or the broadcast values, i.e. pid must be - * less than or equal to zero. - * - * ALT_KILL is mapped onto the kill() system call in alt_syscall.h - */ - -int ALT_KILL (int pid, int sig) -{ - int status = 0; - - if (pid <= 0) - { - switch (sig) - { - case 0: - - /* The null signal is used to check that a pid is valid. */ - - break; - - case SIGABRT: - case SIGALRM: - case SIGFPE: - case SIGILL: - case SIGKILL: - case SIGPIPE: - case SIGQUIT: - case SIGSEGV: - case SIGTERM: - case SIGUSR1: - case SIGUSR2: - case SIGBUS: - case SIGPOLL: - case SIGPROF: - case SIGSYS: - case SIGTRAP: - case SIGVTALRM: - case SIGXCPU: - case SIGXFSZ: - - /* - * The Posix standard defines the default behaviour for all these signals - * as being eqivalent to a call to _exit(). No mechanism is provided to - * change this behaviour. - */ - - _exit(0); - case SIGCHLD: - case SIGURG: - - /* - * The Posix standard defines these signals to be ignored by default. No - * mechanism is provided to change this behaviour. - */ - - break; - default: - - /* Tried to send an unsupported signal */ - - status = EINVAL; - } - } - - else if (pid > 0) - { - /* Attempted to signal a non-existant process */ - - status = ESRCH; - } - - if (status) - { - ALT_ERRNO = status; - return -1; - } - - return 0; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + + +/* + * kill() is used by newlib in order to send signals to processes. Since there + * is only a single process in the HAL, the only valid values for pid are + * either the current process id, or the broadcast values, i.e. pid must be + * less than or equal to zero. + * + * ALT_KILL is mapped onto the kill() system call in alt_syscall.h + */ + +int ALT_KILL (int pid, int sig) +{ + int status = 0; + + if (pid <= 0) + { + switch (sig) + { + case 0: + + /* The null signal is used to check that a pid is valid. */ + + break; + + case SIGABRT: + case SIGALRM: + case SIGFPE: + case SIGILL: + case SIGKILL: + case SIGPIPE: + case SIGQUIT: + case SIGSEGV: + case SIGTERM: + case SIGUSR1: + case SIGUSR2: + case SIGBUS: + case SIGPOLL: + case SIGPROF: + case SIGSYS: + case SIGTRAP: + case SIGVTALRM: + case SIGXCPU: + case SIGXFSZ: + + /* + * The Posix standard defines the default behaviour for all these signals + * as being eqivalent to a call to _exit(). No mechanism is provided to + * change this behaviour. + */ + + _exit(0); + case SIGCHLD: + case SIGURG: + + /* + * The Posix standard defines these signals to be ignored by default. No + * mechanism is provided to change this behaviour. + */ + + break; + default: + + /* Tried to send an unsupported signal */ + + status = EINVAL; + } + } + + else if (pid > 0) + { + /* Attempted to signal a non-existant process */ + + status = ESRCH; + } + + if (status) + { + ALT_ERRNO = status; + return -1; + } + + return 0; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_link.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_link.c index d796c59..a57a5c4 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_link.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_link.c @@ -1,56 +1,56 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_warning.h" -#include "sys/alt_errno.h" -#include "os/alt_syscall.h" - -/* - * link() is used by newlib to create a new link to an existing file. This is - * unsupported in the HAL environment. However a "do-nothing" implementation - * is still provied for newlib compatability. - * - * ALT_LINK is mapped onto the link() system call in alt_syscall.h - */ - -int ALT_LINK ( char *existing, char *new) -{ - /* Generate a link time warning, should this function ever be called. */ - - ALT_STUB_WARNING(link); - - /* Indicate an error */ - - ALT_ERRNO = ENOSYS; - return -1; -} - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * link() is used by newlib to create a new link to an existing file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_LINK is mapped onto the link() system call in alt_syscall.h + */ + +int ALT_LINK ( char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(link); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_load.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_load.c index ffab4b9..27d492b 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_load.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_load.c @@ -1,88 +1,88 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_load.h" -#include "sys/alt_cache.h" - -/* - * Linker defined symbols. - */ - -extern void __flash_rwdata_start; -extern void __ram_rwdata_start; -extern void __ram_rwdata_end; -extern void __flash_rodata_start; -extern void __ram_rodata_start; -extern void __ram_rodata_end; -extern void __flash_exceptions_start; -extern void __ram_exceptions_start; -extern void __ram_exceptions_end; - -/* - * alt_load() is called when the code is executing from flash. In this case - * there is no bootloader, so this application is responsible for loading to - * RAM any sections that are required. - */ - -void alt_load (void) -{ - /* - * Copy the .rwdata section. - */ - - alt_load_section (&__flash_rwdata_start, - &__ram_rwdata_start, - &__ram_rwdata_end); - - /* - * Copy the exception handler. - */ - - alt_load_section (&__flash_exceptions_start, - &__ram_exceptions_start, - &__ram_exceptions_end); - - /* - * Copy the .rodata section. - */ - - alt_load_section (&__flash_rodata_start, - &__ram_rodata_start, - &__ram_rodata_end); - - /* - * Now ensure that the caches are in synch. - */ - - alt_dcache_flush_all(); - alt_icache_flush_all(); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_load.h" +#include "sys/alt_cache.h" + +/* + * Linker defined symbols. + */ + +extern void __flash_rwdata_start; +extern void __ram_rwdata_start; +extern void __ram_rwdata_end; +extern void __flash_rodata_start; +extern void __ram_rodata_start; +extern void __ram_rodata_end; +extern void __flash_exceptions_start; +extern void __ram_exceptions_start; +extern void __ram_exceptions_end; + +/* + * alt_load() is called when the code is executing from flash. In this case + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + &__ram_rwdata_start, + &__ram_rwdata_end); + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + &__ram_exceptions_start, + &__ram_exceptions_end); + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + &__ram_rodata_start, + &__ram_rodata_end); + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + alt_icache_flush_all(); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_log_macro.S b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_log_macro.S index 499c4ad..2e3cc26 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_log_macro.S +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_log_macro.S @@ -1,56 +1,56 @@ -/* alt_log_macro.S - * - * Implements the function tx_log_str, called by the assembly macro - * ALT_LOG_PUTS(). The macro will be empty when logging is turned off, - * and this function will not be compiled. When logging is on, - * this function is used to print out the strings defined in the beginning - * of alt_log_printf.c, using port information taken from system.h and - * alt_log_printf.h. - * - * This routine only handles strings, and sends a character into the defined - * output device's output buffer when the device is ready. It's intended for - * debugging purposes, where messages can be set to print out at certain - * points in the boot code to indicate the progress of the program. - * - */ - -#ifndef __ALT_LOG_MACROS__ -#define __ALT_LOG_MACROS__ - -/* define this flag to skip assembly-incompatible parts - * of various include files. */ -#define ALT_ASM_SRC - -#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. - - #include "system.h" - #include "sys/alt_log_printf.h" - - .global tx_log_str -tx_log_str: - /* load base uart / jtag uart address into r6 */ - movhi r6, %hiadj(ALT_LOG_PORT_BASE) - addi r6, r6, %lo(ALT_LOG_PORT_BASE) -tx_next_char: - /* if pointer points to null, return - * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */ - ldb r7, (r4) - beq r0, r7, end_tx - - /* check device transmit ready */ -wait_tx_ready_loop: - ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6) - andi r5, r5, ALT_LOG_PRINT_MSK - beq r5, r0, wait_tx_ready_loop - /* write char */ - stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6) - /* advance string pointer */ - addi r4, r4, 1 - br tx_next_char -end_tx: - ret - -#endif - -#endif /* __ALT_LOG_MACROS__ */ - +/* alt_log_macro.S + * + * Implements the function tx_log_str, called by the assembly macro + * ALT_LOG_PUTS(). The macro will be empty when logging is turned off, + * and this function will not be compiled. When logging is on, + * this function is used to print out the strings defined in the beginning + * of alt_log_printf.c, using port information taken from system.h and + * alt_log_printf.h. + * + * This routine only handles strings, and sends a character into the defined + * output device's output buffer when the device is ready. It's intended for + * debugging purposes, where messages can be set to print out at certain + * points in the boot code to indicate the progress of the program. + * + */ + +#ifndef __ALT_LOG_MACROS__ +#define __ALT_LOG_MACROS__ + +/* define this flag to skip assembly-incompatible parts + * of various include files. */ +#define ALT_ASM_SRC + +#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. + + #include "system.h" + #include "sys/alt_log_printf.h" + + .global tx_log_str +tx_log_str: + /* load base uart / jtag uart address into r6 */ + movhi r6, %hiadj(ALT_LOG_PORT_BASE) + addi r6, r6, %lo(ALT_LOG_PORT_BASE) +tx_next_char: + /* if pointer points to null, return + * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */ + ldb r7, (r4) + beq r0, r7, end_tx + + /* check device transmit ready */ +wait_tx_ready_loop: + ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6) + andi r5, r5, ALT_LOG_PRINT_MSK + beq r5, r0, wait_tx_ready_loop + /* write char */ + stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6) + /* advance string pointer */ + addi r4, r4, 1 + br tx_next_char +end_tx: + ret + +#endif + +#endif /* __ALT_LOG_MACROS__ */ + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_log_printf.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_log_printf.c index 1f7056d..af0116f 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_log_printf.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_log_printf.c @@ -1,479 +1,479 @@ - -/* alt_log_printf.c - * - * This file implements the various C functions used for the - * alt_log logging/debugging print functions. The functions - * sit as is here - the job of hiding them from the compiler - * if logging is disabled is accomplished in the .h file. - * - * All the global variables for alt_log are defined here. - * These include the various flags that turn on additional - * logging options; the strings for assembly printing; and - * other globals needed by different logging options. - * - * There are 4 functions that handle the actual printing: - * alt_log_txchar: Actual function that puts 1 char to UART/JTAG UART. - * alt_log_repchar: Calls alt_log_txchar 'n' times - used by - * alt_log_private_printf for formatting. - * alt_log_private_printf: - * Stripped down implementation of printf - no floats. - * alt_log_printf_proc: - * Wrapper function for private_printf. - * - * The rest of the functions are called by the macros which - * were called by code in the other components. Each function - * is preceded by a comment, about which file it gets called - * in, and what its purpose is. - * - * author: gkwan - */ - -/* skip all code if enable is off */ -#ifdef ALT_LOG_ENABLE - -#include -#include -#include -#ifdef __ALTERA_AVALON_JTAG_UART - #include "altera_avalon_jtag_uart.h" - #include -#endif -#include "sys/alt_log_printf.h" - -/* strings for assembly puts */ -char alt_log_msg_bss[] = "[crt0.S] Clearing BSS \r\n";; -char alt_log_msg_alt_main[] = "[crt0.S] Calling alt_main.\r\n"; -char alt_log_msg_stackpointer[] \ - = "[crt0.S] Setting up stack and global pointers.\r\n"; -char alt_log_msg_cache[] = "[crt0.S] Inst & Data Cache Initialized.\r\n"; -/* char array allocation for alt_write */ -char alt_log_write_buf[ALT_LOG_WRITE_ECHO_LEN+2]; - -/* global variables for all 'on' flags */ - -/* - * The boot message flag is linked into the data (rwdata) section - * because if it is zero, it would otherwise be placed in the bss section. - * alt_log examines this variable before the BSS is cleared in the boot-up - * process. - */ -volatile alt_u32 alt_log_boot_on_flag \ - __attribute__ ((section (".data"))) = ALT_LOG_BOOT_ON_FLAG_SETTING; - -volatile alt_u8 alt_log_write_on_flag = ALT_LOG_WRITE_ON_FLAG_SETTING; - -volatile alt_u8 alt_log_sys_clk_on_flag = ALT_LOG_SYS_CLK_ON_FLAG_SETTING; - -volatile alt_u8 alt_log_jtag_uart_alarm_on_flag = \ - ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING; - -volatile alt_u8 alt_log_jtag_uart_isr_on_flag = \ - ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING; - -volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag = \ - ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING; - -/* Global alarm object for recurrent JTAG UART status printing */ -alt_alarm alt_log_jtag_uart_alarm_1; - -/* Global ints for system clock printing and count */ -volatile int alt_log_sys_clk_count; -volatile int alt_system_clock_in_sec; - -/* enum used by alt_log_private_printf */ -enum -{ - pfState_chars, - pfState_firstFmtChar, - pfState_otherFmtChar -}; - - - - -/* Function to put one char onto the UART/JTAG UART txdata register. */ -void alt_log_txchar(int c,char *base) -{ - /* Wait until the device is ready for a character */ - while((ALT_LOG_PRINT_REG_RD(base) & ALT_LOG_PRINT_MSK) == 0) - ; - /* And pop the character into the register */ - ALT_LOG_PRINT_TXDATA_WR(base,c); -} - - -/* Called by alt_log_private_printf to print out characters repeatedly */ -void alt_log_repchar(char c,int r,int base) -{ - while(r-- > 0) - alt_log_txchar(c,(char*) base); -} - - -/* Stripped down printf function */ -void alt_log_private_printf(const char *fmt,int base,va_list args) - { - const char *w; - char c; - int state; - int fmtLeadingZero = 0; /* init these all to 0 for -W warnings. */ - int fmtLong = 0; - int fmtBeforeDecimal = 0; - int fmtAfterDecimal = 0; - int fmtBase = 0; - int fmtSigned = 0; - int fmtCase = 0; /* For hex format, if 1, A-F, else a-f. */ - - w = fmt; - state = pfState_chars; - - while(0 != (c = *w++)) - { - switch(state) - { - case pfState_chars: - if(c == '%') - { - fmtLeadingZero = 0; - fmtLong = 0; - fmtBase = 10; - fmtSigned = 1; - fmtCase = 0; /* Only %X sets this. */ - fmtBeforeDecimal = -1; - fmtAfterDecimal = -1; - state = pfState_firstFmtChar; - } - else - { - alt_log_txchar(c,(char*)base); - } - break; - - case pfState_firstFmtChar: - if(c == '0') - { - fmtLeadingZero = 1; - state = pfState_otherFmtChar; - } - else if(c == '%') - { - alt_log_txchar(c,(char*)base); - state = pfState_chars; - } - else - { - state = pfState_otherFmtChar; - goto otherFmtChar; - } - break; - - case pfState_otherFmtChar: -otherFmtChar: - if(c == '.') - { - fmtAfterDecimal = 0; - } - else if('0' <= c && c <= '9') - { - c -= '0'; - if(fmtAfterDecimal < 0) /* still before decimal */ - { - if(fmtBeforeDecimal < 0) - { - fmtBeforeDecimal = 0; - } - else - { - fmtBeforeDecimal *= 10; - } - fmtBeforeDecimal += c; - } - else - { - fmtAfterDecimal = (fmtAfterDecimal * 10) + c; - } - } - else if(c == 'l') - { - fmtLong = 1; - } - else /* we're up to the letter which determines type */ - { - switch(c) - { - case 'd': - case 'i': -doIntegerPrint: - { - unsigned long v; - unsigned long p; /* biggest power of fmtBase */ - unsigned long vShrink; /* used to count digits */ - int sign; - int digitCount; - - /* Get the value */ - if(fmtLong) - { - if (fmtSigned) - { - v = va_arg(args,long); - } - else - { - v = va_arg(args,unsigned long); - } - } - else - { - if (fmtSigned) - { - v = va_arg(args,int); - } - else - { - v = va_arg(args,unsigned int); - } - } - - /* Strip sign */ - sign = 0; - /* (assumes sign bit is #31) */ - if( fmtSigned && (v & (0x80000000)) ) - { - v = ~v + 1; - sign = 1; - } - - /* Count digits, and get largest place value */ - vShrink = v; - p = 1; - digitCount = 1; - while( (vShrink = vShrink / fmtBase) > 0 ) - { - digitCount++; - p *= fmtBase; - } - - /* Print leading characters & sign */ - fmtBeforeDecimal -= digitCount; - if(fmtLeadingZero) - { - if(sign) - { - alt_log_txchar('-',(char*)base); - fmtBeforeDecimal--; - } - alt_log_repchar('0',fmtBeforeDecimal,base); - } - else - { - if(sign) - { - fmtBeforeDecimal--; - } - alt_log_repchar(' ',fmtBeforeDecimal,base); - if(sign) - { - alt_log_txchar('-',(char*)base); - } - } - - /* Print numbery parts */ - while(p) - { - unsigned char d; - - d = v / p; - d += '0'; - if(d > '9') - { - d += (fmtCase ? 'A' : 'a') - '0' - 10; - } - alt_log_txchar(d,(char*)base); - - v = v % p; - p = p / fmtBase; - } - } - - state = pfState_chars; - break; - - case 'u': - fmtSigned = 0; - goto doIntegerPrint; - case 'o': - fmtSigned = 0; - fmtBase = 8; - goto doIntegerPrint; - case 'x': - fmtSigned = 0; - fmtBase = 16; - goto doIntegerPrint; - case 'X': - fmtSigned = 0; - fmtBase = 16; - fmtCase = 1; - goto doIntegerPrint; - - case 'c': - alt_log_repchar(' ',fmtBeforeDecimal-1,base); - alt_log_txchar(va_arg(args,int),(char*)base); - break; - - case 's': - { - char *s; - - s = va_arg(args,char *); - alt_log_repchar(' ',fmtBeforeDecimal-strlen(s),base); - - while(*s) - alt_log_txchar(*s++,(char*)base); - } - break; - } /* switch last letter of fmt */ - state=pfState_chars; - } - break; - } /* switch */ - } /* while chars left */ - } /* printf */ - -/* Main logging printf function */ -int alt_log_printf_proc(const char *fmt, ... ) -{ - va_list args; - - va_start (args, fmt); - alt_log_private_printf(fmt,ALT_LOG_PORT_BASE,args); - return (0); -} - -/* Below are the functions called by different macros in various components. */ - -/* If the system has a JTAG_UART, include JTAG_UART debugging functions */ -#ifdef __ALTERA_AVALON_JTAG_UART - -/* The alarm function in altera_avalon_jtag_uart.c. - * This function, when turned on, prints out the status - * of the JTAG UART Control register, every ALT_LOG_JTAG_UART_TICKS. - * If the flag is off, the alarm should never be registered, and this - * function should never run */ -alt_u32 altera_avalon_jtag_uart_report_log(void * context) -{ - if (alt_log_jtag_uart_alarm_on_flag) { - altera_avalon_jtag_uart_state* dev = (altera_avalon_jtag_uart_state*) context; - const char* header="JTAG Alarm:"; - alt_log_jtag_uart_print_control_reg(dev, dev->base, header); - return ALT_LOG_JTAG_UART_TICKS; - } - else - { - /* If flag is not on, return 0 to disable future alarms. - * Should never be here, alarm should not be enabled at all. */ - return 0; - } -} - -void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, int base, const char* header) -{ - unsigned int control, space, ac, wi, ri, we, re; - control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); - space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> - ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; - we= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK) >> - ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST; - re= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK) >> - ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST; - ri= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) >> - ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST; - wi= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) >> - ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST; - ac= (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) >> - ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST; - -#ifdef ALTERA_AVALON_JTAG_UART_SMALL - ALT_LOG_PRINTF( - "%s HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", - header,space,ac,wi,ri,we,re); -#else - ALT_LOG_PRINTF( - "%s SW CirBuf = %d, HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", - header,(dev->tx_out-dev->tx_in),space,ac,wi,ri,we,re); -#endif - - return; - -} - -/* In altera_avalon_jtag_uart.c - * Same output as the alarm function above, but this is called in the driver - * init function. Hence, it gives the status of the JTAG UART control register - * right at the initialization of the driver */ -void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base) -{ - const char* header="JTAG Startup Info:"; - alt_log_jtag_uart_print_control_reg(dev, base, header); - return; -} - -/* In altera_avalon_jtag_uart.c - * When turned on, this function will print out the status of the jtag uart - * control register every time there is a jtag uart "almost-empty" interrupt. */ -void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev) -{ - if (alt_log_jtag_uart_isr_on_flag) { - const char* header="JTAG IRQ:"; - alt_log_jtag_uart_print_control_reg(dev, base, header); - } - return; -} - -#endif /* __ALTERA_AVALON_JTAG_UART */ - -/* In alt_write.c - * When the alt_log_write_on_flag is turned on, this function gets called - * every time alt_write gets called. The first - * ALT_LOG_WRITE_ECHO_LEN characters of every printf command (or any command - * that eventually calls write()) gets echoed to the alt_log output. */ -void alt_log_write(const void *ptr, size_t len) -{ - if (alt_log_write_on_flag) { - int temp_cnt; - int length=(ALT_LOG_WRITE_ECHO_LEN>len) ? len : ALT_LOG_WRITE_ECHO_LEN; - - if (length < 2) return; - - strncpy (alt_log_write_buf,ptr,length); - alt_log_write_buf[length-1]='\n'; - alt_log_write_buf[length]='\r'; - alt_log_write_buf[length+1]='\0'; - - /* Escape Ctrl-D's. If the Ctrl-D gets sent it might kill the terminal - * connection of alt_log. It will get replaced by 'D'. */ - for (temp_cnt=0;temp_cnt < length; temp_cnt++) { - if (alt_log_write_buf[temp_cnt]== 0x4) { - alt_log_write_buf[temp_cnt]='D'; - } - } - ALT_LOG_PRINTF("Write Echo: %s",alt_log_write_buf); - } -} - -/* In altera_avalon_timer_sc - * This function prints out a system clock is alive message - * every ALT_LOG_SYS_CLK_INTERVAL (in ticks). */ -void alt_log_system_clock() -{ - if (alt_log_sys_clk_on_flag) { - alt_log_sys_clk_count++; - if (alt_log_sys_clk_count > ALT_LOG_SYS_CLK_INTERVAL) { - alt_log_sys_clk_count = 0; - ALT_LOG_PRINTF("System Clock On %u\r\n",alt_system_clock_in_sec++); - } - } -} - - -#endif + +/* alt_log_printf.c + * + * This file implements the various C functions used for the + * alt_log logging/debugging print functions. The functions + * sit as is here - the job of hiding them from the compiler + * if logging is disabled is accomplished in the .h file. + * + * All the global variables for alt_log are defined here. + * These include the various flags that turn on additional + * logging options; the strings for assembly printing; and + * other globals needed by different logging options. + * + * There are 4 functions that handle the actual printing: + * alt_log_txchar: Actual function that puts 1 char to UART/JTAG UART. + * alt_log_repchar: Calls alt_log_txchar 'n' times - used by + * alt_log_private_printf for formatting. + * alt_log_private_printf: + * Stripped down implementation of printf - no floats. + * alt_log_printf_proc: + * Wrapper function for private_printf. + * + * The rest of the functions are called by the macros which + * were called by code in the other components. Each function + * is preceded by a comment, about which file it gets called + * in, and what its purpose is. + * + * author: gkwan + */ + +/* skip all code if enable is off */ +#ifdef ALT_LOG_ENABLE + +#include +#include +#include +#ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #include +#endif +#include "sys/alt_log_printf.h" + +/* strings for assembly puts */ +char alt_log_msg_bss[] = "[crt0.S] Clearing BSS \r\n";; +char alt_log_msg_alt_main[] = "[crt0.S] Calling alt_main.\r\n"; +char alt_log_msg_stackpointer[] \ + = "[crt0.S] Setting up stack and global pointers.\r\n"; +char alt_log_msg_cache[] = "[crt0.S] Inst & Data Cache Initialized.\r\n"; +/* char array allocation for alt_write */ +char alt_log_write_buf[ALT_LOG_WRITE_ECHO_LEN+2]; + +/* global variables for all 'on' flags */ + +/* + * The boot message flag is linked into the data (rwdata) section + * because if it is zero, it would otherwise be placed in the bss section. + * alt_log examines this variable before the BSS is cleared in the boot-up + * process. + */ +volatile alt_u32 alt_log_boot_on_flag \ + __attribute__ ((section (".data"))) = ALT_LOG_BOOT_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_write_on_flag = ALT_LOG_WRITE_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_sys_clk_on_flag = ALT_LOG_SYS_CLK_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_alarm_on_flag = \ + ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_isr_on_flag = \ + ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag = \ + ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING; + +/* Global alarm object for recurrent JTAG UART status printing */ +alt_alarm alt_log_jtag_uart_alarm_1; + +/* Global ints for system clock printing and count */ +volatile int alt_log_sys_clk_count; +volatile int alt_system_clock_in_sec; + +/* enum used by alt_log_private_printf */ +enum +{ + pfState_chars, + pfState_firstFmtChar, + pfState_otherFmtChar +}; + + + + +/* Function to put one char onto the UART/JTAG UART txdata register. */ +void alt_log_txchar(int c,char *base) +{ + /* Wait until the device is ready for a character */ + while((ALT_LOG_PRINT_REG_RD(base) & ALT_LOG_PRINT_MSK) == 0) + ; + /* And pop the character into the register */ + ALT_LOG_PRINT_TXDATA_WR(base,c); +} + + +/* Called by alt_log_private_printf to print out characters repeatedly */ +void alt_log_repchar(char c,int r,int base) +{ + while(r-- > 0) + alt_log_txchar(c,(char*) base); +} + + +/* Stripped down printf function */ +void alt_log_private_printf(const char *fmt,int base,va_list args) + { + const char *w; + char c; + int state; + int fmtLeadingZero = 0; /* init these all to 0 for -W warnings. */ + int fmtLong = 0; + int fmtBeforeDecimal = 0; + int fmtAfterDecimal = 0; + int fmtBase = 0; + int fmtSigned = 0; + int fmtCase = 0; /* For hex format, if 1, A-F, else a-f. */ + + w = fmt; + state = pfState_chars; + + while(0 != (c = *w++)) + { + switch(state) + { + case pfState_chars: + if(c == '%') + { + fmtLeadingZero = 0; + fmtLong = 0; + fmtBase = 10; + fmtSigned = 1; + fmtCase = 0; /* Only %X sets this. */ + fmtBeforeDecimal = -1; + fmtAfterDecimal = -1; + state = pfState_firstFmtChar; + } + else + { + alt_log_txchar(c,(char*)base); + } + break; + + case pfState_firstFmtChar: + if(c == '0') + { + fmtLeadingZero = 1; + state = pfState_otherFmtChar; + } + else if(c == '%') + { + alt_log_txchar(c,(char*)base); + state = pfState_chars; + } + else + { + state = pfState_otherFmtChar; + goto otherFmtChar; + } + break; + + case pfState_otherFmtChar: +otherFmtChar: + if(c == '.') + { + fmtAfterDecimal = 0; + } + else if('0' <= c && c <= '9') + { + c -= '0'; + if(fmtAfterDecimal < 0) /* still before decimal */ + { + if(fmtBeforeDecimal < 0) + { + fmtBeforeDecimal = 0; + } + else + { + fmtBeforeDecimal *= 10; + } + fmtBeforeDecimal += c; + } + else + { + fmtAfterDecimal = (fmtAfterDecimal * 10) + c; + } + } + else if(c == 'l') + { + fmtLong = 1; + } + else /* we're up to the letter which determines type */ + { + switch(c) + { + case 'd': + case 'i': +doIntegerPrint: + { + unsigned long v; + unsigned long p; /* biggest power of fmtBase */ + unsigned long vShrink; /* used to count digits */ + int sign; + int digitCount; + + /* Get the value */ + if(fmtLong) + { + if (fmtSigned) + { + v = va_arg(args,long); + } + else + { + v = va_arg(args,unsigned long); + } + } + else + { + if (fmtSigned) + { + v = va_arg(args,int); + } + else + { + v = va_arg(args,unsigned int); + } + } + + /* Strip sign */ + sign = 0; + /* (assumes sign bit is #31) */ + if( fmtSigned && (v & (0x80000000)) ) + { + v = ~v + 1; + sign = 1; + } + + /* Count digits, and get largest place value */ + vShrink = v; + p = 1; + digitCount = 1; + while( (vShrink = vShrink / fmtBase) > 0 ) + { + digitCount++; + p *= fmtBase; + } + + /* Print leading characters & sign */ + fmtBeforeDecimal -= digitCount; + if(fmtLeadingZero) + { + if(sign) + { + alt_log_txchar('-',(char*)base); + fmtBeforeDecimal--; + } + alt_log_repchar('0',fmtBeforeDecimal,base); + } + else + { + if(sign) + { + fmtBeforeDecimal--; + } + alt_log_repchar(' ',fmtBeforeDecimal,base); + if(sign) + { + alt_log_txchar('-',(char*)base); + } + } + + /* Print numbery parts */ + while(p) + { + unsigned char d; + + d = v / p; + d += '0'; + if(d > '9') + { + d += (fmtCase ? 'A' : 'a') - '0' - 10; + } + alt_log_txchar(d,(char*)base); + + v = v % p; + p = p / fmtBase; + } + } + + state = pfState_chars; + break; + + case 'u': + fmtSigned = 0; + goto doIntegerPrint; + case 'o': + fmtSigned = 0; + fmtBase = 8; + goto doIntegerPrint; + case 'x': + fmtSigned = 0; + fmtBase = 16; + goto doIntegerPrint; + case 'X': + fmtSigned = 0; + fmtBase = 16; + fmtCase = 1; + goto doIntegerPrint; + + case 'c': + alt_log_repchar(' ',fmtBeforeDecimal-1,base); + alt_log_txchar(va_arg(args,int),(char*)base); + break; + + case 's': + { + char *s; + + s = va_arg(args,char *); + alt_log_repchar(' ',fmtBeforeDecimal-strlen(s),base); + + while(*s) + alt_log_txchar(*s++,(char*)base); + } + break; + } /* switch last letter of fmt */ + state=pfState_chars; + } + break; + } /* switch */ + } /* while chars left */ + } /* printf */ + +/* Main logging printf function */ +int alt_log_printf_proc(const char *fmt, ... ) +{ + va_list args; + + va_start (args, fmt); + alt_log_private_printf(fmt,ALT_LOG_PORT_BASE,args); + return (0); +} + +/* Below are the functions called by different macros in various components. */ + +/* If the system has a JTAG_UART, include JTAG_UART debugging functions */ +#ifdef __ALTERA_AVALON_JTAG_UART + +/* The alarm function in altera_avalon_jtag_uart.c. + * This function, when turned on, prints out the status + * of the JTAG UART Control register, every ALT_LOG_JTAG_UART_TICKS. + * If the flag is off, the alarm should never be registered, and this + * function should never run */ +alt_u32 altera_avalon_jtag_uart_report_log(void * context) +{ + if (alt_log_jtag_uart_alarm_on_flag) { + altera_avalon_jtag_uart_state* dev = (altera_avalon_jtag_uart_state*) context; + const char* header="JTAG Alarm:"; + alt_log_jtag_uart_print_control_reg(dev, dev->base, header); + return ALT_LOG_JTAG_UART_TICKS; + } + else + { + /* If flag is not on, return 0 to disable future alarms. + * Should never be here, alarm should not be enabled at all. */ + return 0; + } +} + +void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, int base, const char* header) +{ + unsigned int control, space, ac, wi, ri, we, re; + control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + we= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST; + re= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST; + ri= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST; + wi= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST; + ac= (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST; + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + ALT_LOG_PRINTF( + "%s HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,space,ac,wi,ri,we,re); +#else + ALT_LOG_PRINTF( + "%s SW CirBuf = %d, HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,(dev->tx_out-dev->tx_in),space,ac,wi,ri,we,re); +#endif + + return; + +} + +/* In altera_avalon_jtag_uart.c + * Same output as the alarm function above, but this is called in the driver + * init function. Hence, it gives the status of the JTAG UART control register + * right at the initialization of the driver */ +void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base) +{ + const char* header="JTAG Startup Info:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + return; +} + +/* In altera_avalon_jtag_uart.c + * When turned on, this function will print out the status of the jtag uart + * control register every time there is a jtag uart "almost-empty" interrupt. */ +void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev) +{ + if (alt_log_jtag_uart_isr_on_flag) { + const char* header="JTAG IRQ:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + } + return; +} + +#endif /* __ALTERA_AVALON_JTAG_UART */ + +/* In alt_write.c + * When the alt_log_write_on_flag is turned on, this function gets called + * every time alt_write gets called. The first + * ALT_LOG_WRITE_ECHO_LEN characters of every printf command (or any command + * that eventually calls write()) gets echoed to the alt_log output. */ +void alt_log_write(const void *ptr, size_t len) +{ + if (alt_log_write_on_flag) { + int temp_cnt; + int length=(ALT_LOG_WRITE_ECHO_LEN>len) ? len : ALT_LOG_WRITE_ECHO_LEN; + + if (length < 2) return; + + strncpy (alt_log_write_buf,ptr,length); + alt_log_write_buf[length-1]='\n'; + alt_log_write_buf[length]='\r'; + alt_log_write_buf[length+1]='\0'; + + /* Escape Ctrl-D's. If the Ctrl-D gets sent it might kill the terminal + * connection of alt_log. It will get replaced by 'D'. */ + for (temp_cnt=0;temp_cnt < length; temp_cnt++) { + if (alt_log_write_buf[temp_cnt]== 0x4) { + alt_log_write_buf[temp_cnt]='D'; + } + } + ALT_LOG_PRINTF("Write Echo: %s",alt_log_write_buf); + } +} + +/* In altera_avalon_timer_sc + * This function prints out a system clock is alive message + * every ALT_LOG_SYS_CLK_INTERVAL (in ticks). */ +void alt_log_system_clock() +{ + if (alt_log_sys_clk_on_flag) { + alt_log_sys_clk_count++; + if (alt_log_sys_clk_count > ALT_LOG_SYS_CLK_INTERVAL) { + alt_log_sys_clk_count = 0; + ALT_LOG_PRINTF("System Clock On %u\r\n",alt_system_clock_in_sec++); + } + } +} + + +#endif diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_lseek.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_lseek.c index 7857b0d..a56dbfb 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_lseek.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_lseek.c @@ -1,117 +1,117 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "priv/alt_file.h" -#include "os/alt_syscall.h" - -#ifdef ALT_USE_DIRECT_DRIVERS - -off_t ALT_LSEEK (int file, off_t ptr, int dir) -{ - /* Generate a link time warning, should this function ever be called. */ - - ALT_STUB_WARNING(lseek); - - /* Indicate an error */ - - ALT_ERRNO = ENOSYS; - return -1; -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -/* - * lseek() can be called to move the read/write pointer associated with the - * file descriptor "file". This function simply vectors the call to the lseek() - * function provided by the driver associated with the file descriptor. - * - * If the driver does not provide an implementation of lseek() an error is - * indicated. - * - * lseek() corresponds to the standard lseek() function. - * - * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h - * - */ - -off_t ALT_LSEEK (int file, off_t ptr, int dir) -{ - alt_fd* fd; - off_t rc = 0; - - /* - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - - if (fd) - { - /* - * If the device driver provides an implementation of the lseek() function, - * then call that to process the request. - */ - - if (fd->dev->lseek) - { - rc = fd->dev->lseek(fd, ptr, dir); - } - /* - * Otherwise return an error. - */ - - else - { - rc = -ENOTSUP; - } - } - else - { - rc = -EBADFD; - } - - if (rc < 0) - { - ALT_ERRNO = -rc; - rc = -1; - } - - return rc; -} - -#endif /* ALT_USE_DIRECT_DRIVERS */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(lseek); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * lseek() can be called to move the read/write pointer associated with the + * file descriptor "file". This function simply vectors the call to the lseek() + * function provided by the driver associated with the file descriptor. + * + * If the driver does not provide an implementation of lseek() an error is + * indicated. + * + * lseek() corresponds to the standard lseek() function. + * + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + alt_fd* fd; + off_t rc = 0; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + { + rc = fd->dev->lseek(fd, ptr, dir); + } + /* + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + } + } + else + { + rc = -EBADFD; + } + + if (rc < 0) + { + ALT_ERRNO = -rc; + rc = -1; + } + + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_main.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_main.c index a96229b..33e3463 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_main.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_main.c @@ -1,161 +1,161 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include "sys/alt_dev.h" -#include "sys/alt_sys_init.h" -#include "sys/alt_irq.h" -#include "sys/alt_dev.h" - -#include "os/alt_hooks.h" - -#include "priv/alt_file.h" -#include "alt_types.h" - -#include "system.h" - -#include "sys/alt_log_printf.h" - -extern void _do_ctors(void); -extern void _do_dtors(void); - -/* - * Standard arguments for main. By default, no arguments are passed to main. - * However a device driver may choose to configure these arguments by calling - * alt_set_args(). The expectation is that this facility will only be used by - * the iclient/ihost utility. - */ - -int alt_argc = 0; -char** alt_argv = {NULL}; -char** alt_envp = {NULL}; - -/* - * Prototype for the entry point to the users application. - */ - -extern int main (int, char **, char **); - -/* - * alt_main is the C entry point for the HAL. It is called by the assembler - * startup code in the processor specific crt0.S. It is responsible for: - * completing the C runtime configuration; configuring all the - * devices/filesystems/components in the system; and call the entry point for - * the users application, i.e. main(). - */ - -void alt_main (void) -{ -#ifndef ALT_NO_EXIT - int result; -#endif - - /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ - ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); - /* Initialize the interrupt controller. */ - alt_irq_init (NULL); - - /* Initialize the operating system */ - ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); - ALT_OS_INIT(); - - /* - * Initialize the semaphore used to control access to the file descriptor - * list. - */ - - ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); - ALT_SEM_CREATE (&alt_fd_list_lock, 1); - - /* Initialize the device drivers/software components. */ - ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); - alt_sys_init(); - ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_sys_init.\r\n"); - -#if !defined(ALT_USE_DIRECT_DRIVERS) && (defined(ALT_STDIN_PRESENT) || defined(ALT_STDOUT_PRESENT) || defined(ALT_STDERR_PRESENT)) - - /* - * Redirect stdio to the apropriate devices now that the devices have - * been initialized. This is only done if the user has requested these - * devices be present (not equal to /dev/null) and if direct drivers - * aren't being used. - */ - - ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); - alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); -#endif - -#ifndef ALT_NO_C_PLUS_PLUS - /* - * Call the C++ constructors - */ - - ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); - _do_ctors (); -#endif /* ALT_NO_C_PLUS_PLUS */ - -#if !defined(ALT_NO_C_PLUS_PLUS) && !defined(ALT_NO_CLEAN_EXIT) && !defined(ALT_NO_EXIT) - /* - * Set the C++ destructors to be called at system shutdown. This is only done - * if a clean exit has been requested (i.e. the exit() function has not been - * redefined as _exit()). This is in the interest of reducing code footprint, - * in that the atexit() overhead is removed when it's not needed. - */ - - ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); - atexit (_do_dtors); -#endif - - /* - * Finally, call main(). The return code is then passed to a subsequent - * call to exit() unless the application is never supposed to exit. - */ - - ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); - -#ifdef ALT_NO_EXIT - main (alt_argc, alt_argv, alt_envp); -#else - result = main (alt_argc, alt_argv, alt_envp); - close(STDOUT_FILENO); - exit (result); -#endif - - ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n"); -} - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_sys_init.h" +#include "sys/alt_irq.h" +#include "sys/alt_dev.h" + +#include "os/alt_hooks.h" + +#include "priv/alt_file.h" +#include "alt_types.h" + +#include "system.h" + +#include "sys/alt_log_printf.h" + +extern void _do_ctors(void); +extern void _do_dtors(void); + +/* + * Standard arguments for main. By default, no arguments are passed to main. + * However a device driver may choose to configure these arguments by calling + * alt_set_args(). The expectation is that this facility will only be used by + * the iclient/ihost utility. + */ + +int alt_argc = 0; +char** alt_argv = {NULL}; +char** alt_envp = {NULL}; + +/* + * Prototype for the entry point to the users application. + */ + +extern int main (int, char **, char **); + +/* + * alt_main is the C entry point for the HAL. It is called by the assembler + * startup code in the processor specific crt0.S. It is responsible for: + * completing the C runtime configuration; configuring all the + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ +#ifndef ALT_NO_EXIT + int result; +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + + /* + * Initialize the semaphore used to control access to the file descriptor + * list. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_sys_init.\r\n"); + +#if !defined(ALT_USE_DIRECT_DRIVERS) && (defined(ALT_STDIN_PRESENT) || defined(ALT_STDOUT_PRESENT) || defined(ALT_STDERR_PRESENT)) + + /* + * Redirect stdio to the apropriate devices now that the devices have + * been initialized. This is only done if the user has requested these + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); +#endif + +#ifndef ALT_NO_C_PLUS_PLUS + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); +#endif /* ALT_NO_C_PLUS_PLUS */ + +#if !defined(ALT_NO_C_PLUS_PLUS) && !defined(ALT_NO_CLEAN_EXIT) && !defined(ALT_NO_EXIT) + /* + * Set the C++ destructors to be called at system shutdown. This is only done + * if a clean exit has been requested (i.e. the exit() function has not been + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); +#endif + + /* + * Finally, call main(). The return code is then passed to a subsequent + * call to exit() unless the application is never supposed to exit. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + close(STDOUT_FILENO); + exit (result); +#endif + + ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n"); +} + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_malloc_lock.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_malloc_lock.c index 8c78f46..89c2dd4 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_malloc_lock.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_malloc_lock.c @@ -1,52 +1,52 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -/* - * These are the empty malloc lock/unlock stubs required by newlib. These are - * used to make newlib's malloc() function thread safe. The default HAL - * configuration is single threaded, so there is nothing to do here. Note that - * this requires that malloc is never called by an interrupt service routine. - */ - -void __malloc_lock ( struct _reent *_r ) -{ -} - -/* - * - */ - -void __malloc_unlock ( struct _reent *_r ) -{ -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +/* + * These are the empty malloc lock/unlock stubs required by newlib. These are + * used to make newlib's malloc() function thread safe. The default HAL + * configuration is single threaded, so there is nothing to do here. Note that + * this requires that malloc is never called by an interrupt service routine. + */ + +void __malloc_lock ( struct _reent *_r ) +{ +} + +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_mcount.S b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_mcount.S index 3837523..cf510da 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_mcount.S +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_mcount.S @@ -1,198 +1,198 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* mcount or _mcount is inserted by GCC before the function prologue of every - * function when a program is compiled for profiling. At the start of mcount, - * we guarantee that: - * ra = self_pc (an address in the function which called mcount) - * r8 = from_pc (an address in the function which called mcount's caller) - * - * Because this is always called at the start of a function we can corrupt - * r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain - * function arguments for the instrumented function) or r8 (which holds ra - * for the instrumented function). - */ - - .global __mcount_fn_head - - .global mcount - - /* _mcount is used by gcc4 */ - .global _mcount - -_mcount: -mcount: - /* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose - * the bucket because bits 1:0 will always be 0, and because the distribution - * of values for bits 4:2 won't be even (aligning on cache line boundaries - * will skew it). Higher bits should be fairly random. - */ - /* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */ - - srli r2, ra, 3 - movhi r3, %hiadj(__mcount_fn_head) - addi r3, r3, %lo(__mcount_fn_head) - andi r2, r2, 0xFC - add r11, r2, r3 - - /* The fast case is where we have already allocated a function arc, and so - * also a function pointer. - */ - - /* First find the function being called (using self_pc) */ - mov r10, r11 -0: - ldw r10, 0(r10) - beq r10, zero, .Lnew_arc - ldw r2, 4(r10) - bne r2, ra, 0b - - /* Found a function entry for this PC. Now look for an arc with a matching - * from_pc value. There will always be at least one arc. */ - ldw r3, 8(r10) -0: - ldw r2, 4(r3) - beq r2, r8, .Lfound_arc - ldw r3, 0(r3) - bne r3, zero, 0b - -.Lnew_arc: - addi sp, sp, -24 - -.LCFI0: - stw ra, 0(sp) - stw r4, 4(sp) - stw r5, 8(sp) - stw r6, 12(sp) - stw r7, 16(sp) - stw r8, 20(sp) - -.LCFI1: - /* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */ - mov r4, ra - mov r5, r8 - mov r6, r10 - mov r7, r11 - call __mcount_record - - /* restore registers from the stack */ - ldw ra, 0(sp) - ldw r4, 4(sp) - ldw r5, 8(sp) - ldw r6, 12(sp) - ldw r7, 16(sp) - ldw r8, 20(sp) - - addi sp, sp, 24 - -.LCFI2: - ret - -.Lfound_arc: - /* We've found the correct arc record. Increment the count and return */ - ldw r2, 8(r3) - addi r2, r2, 1 - stw r2, 8(r3) - ret - -.Lmcount_end: - - - -/* - * Dwarf2 debug information for the function. This provides GDB with the - * information it needs to backtrace out of this function. - */ - - .section .debug_frame,"",@progbits -.LCIE: - .4byte 2f - 1f /* Length */ -1: - .4byte 0xffffffff /* CIE id */ - .byte 0x1 /* Version */ - .string "" /* Augmentation */ - .uleb128 0x1 /* Code alignment factor */ - .sleb128 -4 /* Data alignment factor */ - .byte 0x1f /* Return address register */ - - .byte 0xc /* Define CFA */ - .uleb128 0x1b /* Register 27 (sp) */ - .uleb128 0x0 /* Offset 0 */ - - .align 2 /* Padding */ -2: - -.LFDE_mcount: - .4byte 2f - 1f /* Length */ -1: - .4byte .LCIE /* Pointer to CIE */ - .4byte mcount /* Start of table entry */ - .4byte .Lmcount_end - mcount /* Size of table entry */ - - .byte 0x4 /* Advance location */ - .4byte .LCFI0 - mcount /* to .LCFI0 */ - .byte 0xe /* Define CFA offset */ - .uleb128 24 /* to 24 */ - - .byte 0x4 /* Advance location */ - .4byte .LCFI1 - .LCFI0 /* to .LCFI1 */ - .byte 0x9f /* Store ra */ - .uleb128 0x6 /* at CFA-24 */ - .byte 0x84 /* Store r4 */ - .uleb128 0x5 /* at CFA-20 */ - .byte 0x85 /* Store r5 */ - .uleb128 0x4 /* at CFA-16 */ - .byte 0x86 /* Store r6 */ - .uleb128 0x3 /* at CFA-12 */ - .byte 0x87 /* Store r7 */ - .uleb128 0x2 /* at CFA-8 */ - .byte 0x88 /* Store r8 */ - .uleb128 0x1 /* at CFA-4 */ - - .byte 0x4 /* Advance location */ - .4byte .LCFI2 - .LCFI1 /* to .LCFI2 */ - .byte 0xe /* Define CFA offset */ - .uleb128 0 /* to 0 */ - .byte 0x8 /* Same value */ - .uleb128 31 /* for ra */ - .byte 0x8 /* Same value */ - .uleb128 4 /* for r4 */ - .byte 0x8 /* Same value */ - .uleb128 5 /* for r5 */ - .byte 0x8 /* Same value */ - .uleb128 6 /* for r6 */ - .byte 0x8 /* Same value */ - .uleb128 7 /* for r7 */ - .byte 0x8 /* Same value */ - .uleb128 8 /* for r8 */ - - .align 2 -2: - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* mcount or _mcount is inserted by GCC before the function prologue of every + * function when a program is compiled for profiling. At the start of mcount, + * we guarantee that: + * ra = self_pc (an address in the function which called mcount) + * r8 = from_pc (an address in the function which called mcount's caller) + * + * Because this is always called at the start of a function we can corrupt + * r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain + * function arguments for the instrumented function) or r8 (which holds ra + * for the instrumented function). + */ + + .global __mcount_fn_head + + .global mcount + + /* _mcount is used by gcc4 */ + .global _mcount + +_mcount: +mcount: + /* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose + * the bucket because bits 1:0 will always be 0, and because the distribution + * of values for bits 4:2 won't be even (aligning on cache line boundaries + * will skew it). Higher bits should be fairly random. + */ + /* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */ + + srli r2, ra, 3 + movhi r3, %hiadj(__mcount_fn_head) + addi r3, r3, %lo(__mcount_fn_head) + andi r2, r2, 0xFC + add r11, r2, r3 + + /* The fast case is where we have already allocated a function arc, and so + * also a function pointer. + */ + + /* First find the function being called (using self_pc) */ + mov r10, r11 +0: + ldw r10, 0(r10) + beq r10, zero, .Lnew_arc + ldw r2, 4(r10) + bne r2, ra, 0b + + /* Found a function entry for this PC. Now look for an arc with a matching + * from_pc value. There will always be at least one arc. */ + ldw r3, 8(r10) +0: + ldw r2, 4(r3) + beq r2, r8, .Lfound_arc + ldw r3, 0(r3) + bne r3, zero, 0b + +.Lnew_arc: + addi sp, sp, -24 + +.LCFI0: + stw ra, 0(sp) + stw r4, 4(sp) + stw r5, 8(sp) + stw r6, 12(sp) + stw r7, 16(sp) + stw r8, 20(sp) + +.LCFI1: + /* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */ + mov r4, ra + mov r5, r8 + mov r6, r10 + mov r7, r11 + call __mcount_record + + /* restore registers from the stack */ + ldw ra, 0(sp) + ldw r4, 4(sp) + ldw r5, 8(sp) + ldw r6, 12(sp) + ldw r7, 16(sp) + ldw r8, 20(sp) + + addi sp, sp, 24 + +.LCFI2: + ret + +.Lfound_arc: + /* We've found the correct arc record. Increment the count and return */ + ldw r2, 8(r3) + addi r2, r2, 1 + stw r2, 8(r3) + ret + +.Lmcount_end: + + + +/* + * Dwarf2 debug information for the function. This provides GDB with the + * information it needs to backtrace out of this function. + */ + + .section .debug_frame,"",@progbits +.LCIE: + .4byte 2f - 1f /* Length */ +1: + .4byte 0xffffffff /* CIE id */ + .byte 0x1 /* Version */ + .string "" /* Augmentation */ + .uleb128 0x1 /* Code alignment factor */ + .sleb128 -4 /* Data alignment factor */ + .byte 0x1f /* Return address register */ + + .byte 0xc /* Define CFA */ + .uleb128 0x1b /* Register 27 (sp) */ + .uleb128 0x0 /* Offset 0 */ + + .align 2 /* Padding */ +2: + +.LFDE_mcount: + .4byte 2f - 1f /* Length */ +1: + .4byte .LCIE /* Pointer to CIE */ + .4byte mcount /* Start of table entry */ + .4byte .Lmcount_end - mcount /* Size of table entry */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI0 - mcount /* to .LCFI0 */ + .byte 0xe /* Define CFA offset */ + .uleb128 24 /* to 24 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI1 - .LCFI0 /* to .LCFI1 */ + .byte 0x9f /* Store ra */ + .uleb128 0x6 /* at CFA-24 */ + .byte 0x84 /* Store r4 */ + .uleb128 0x5 /* at CFA-20 */ + .byte 0x85 /* Store r5 */ + .uleb128 0x4 /* at CFA-16 */ + .byte 0x86 /* Store r6 */ + .uleb128 0x3 /* at CFA-12 */ + .byte 0x87 /* Store r7 */ + .uleb128 0x2 /* at CFA-8 */ + .byte 0x88 /* Store r8 */ + .uleb128 0x1 /* at CFA-4 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI2 - .LCFI1 /* to .LCFI2 */ + .byte 0xe /* Define CFA offset */ + .uleb128 0 /* to 0 */ + .byte 0x8 /* Same value */ + .uleb128 31 /* for ra */ + .byte 0x8 /* Same value */ + .uleb128 4 /* for r4 */ + .byte 0x8 /* Same value */ + .uleb128 5 /* for r5 */ + .byte 0x8 /* Same value */ + .uleb128 6 /* for r6 */ + .byte 0x8 /* Same value */ + .uleb128 7 /* for r7 */ + .byte 0x8 /* Same value */ + .uleb128 8 /* for r8 */ + + .align 2 +2: + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_open.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_open.c index 4790f53..d7040bc 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_open.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_open.c @@ -1,173 +1,173 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "priv/alt_file.h" -#include "alt_types.h" -#include "os/alt_syscall.h" - -#ifdef ALT_USE_DIRECT_DRIVERS - -int ALT_OPEN (const char* file, int flags, int mode) -{ - /* Generate a link time warning, should this function ever be called. */ - - ALT_STUB_WARNING(open); - - /* Indicate an error */ - - ALT_ERRNO = ENOSYS; - return -1; -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -extern alt_llist alt_dev_list; - -/* - * alt_file_locked() is used by open() to ensure that a device has not been - * previously locked for exclusive access using ioctl(). This test is only - * performed for devices. Filesystems are required to handle the ioctl() call - * themselves, and report the error from the filesystems open() function. - */ - -static int alt_file_locked (alt_fd* fd) -{ - alt_u32 i; - - /* - * Mark the file descriptor as belonging to a device. - */ - - fd->fd_flags |= ALT_FD_DEV; - - /* - * Loop through all current file descriptors searching for one that's locked - * for exclusive access. If a match is found, generate an error. - */ - - for (i = 0; i <= alt_max_fd; i++) - { - if ((alt_fd_list[i].dev == fd->dev) && - (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && - (&alt_fd_list[i] != fd)) - { - return -EACCES; - } - } - - /* The device is not locked */ - - return 0; -} - -/* - * open() is called in order to get a file descriptor that reference the file - * or device named "name". This descriptor can then be used to manipulate the - * file/device using the standard system calls, e.g. write(), read(), ioctl() - * etc. - * - * This is equivalent to the standard open() system call. - * - * ALT_OPEN is mapped onto the open() system call in alt_syscall.h - */ - -int ALT_OPEN (const char* file, int flags, int mode) -{ - alt_dev* dev; - alt_fd* fd; - int index = -1; - int status = -ENODEV; - int isafs = 0; - - /* - * Check the device list, to see if a device with a matching name is - * registered. - */ - - if (!(dev = alt_find_dev (file, &alt_dev_list))) - { - /* No matching device, so try the filesystem list */ - - dev = alt_find_file (file); - isafs = 1; - } - - /* - * If a matching device or filesystem is found, allocate a file descriptor. - */ - - if (dev) - { - if ((index = alt_get_fd (dev)) < 0) - { - status = index; - } - else - { - fd = &alt_fd_list[index]; - fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); - - /* If this is a device, ensure it isn't already locked */ - - if (isafs || ((status = alt_file_locked (fd)) >= 0)) - { - /* - * If the device or filesystem provides an open() callback function, - * call it now to perform any device/filesystem specific operations. - */ - - status = (dev->open) ? dev->open(fd, file, flags, mode): 0; - } - } - } - else - { - status = -ENODEV; - } - - /* Allocation failed, so clean up and return an error */ - - if (status < 0) - { - alt_release_fd (index); - ALT_ERRNO = -status; - return -1; - } - - /* return the reference upon success */ - - return index; -} - -#endif /* ALT_USE_DIRECT_DRIVERS */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_OPEN (const char* file, int flags, int mode) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(open); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +extern alt_llist alt_dev_list; + +/* + * alt_file_locked() is used by open() to ensure that a device has not been + * previously locked for exclusive access using ioctl(). This test is only + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + alt_u32 i; + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + { + if ((alt_fd_list[i].dev == fd->dev) && + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + } + } + + /* The device is not locked */ + + return 0; +} + +/* + * open() is called in order to get a file descriptor that reference the file + * or device named "name". This descriptor can then be used to manipulate the + * file/device using the standard system calls, e.g. write(), read(), ioctl() + * etc. + * + * This is equivalent to the standard open() system call. + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + alt_dev* dev; + alt_fd* fd; + int index = -1; + int status = -ENODEV; + int isafs = 0; + + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + isafs = 1; + } + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + { + if ((index = alt_get_fd (dev)) < 0) + { + status = index; + } + else + { + fd = &alt_fd_list[index]; + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + { + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + } + } + } + else + { + status = -ENODEV; + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + { + alt_release_fd (index); + ALT_ERRNO = -status; + return -1; + } + + /* return the reference upon success */ + + return index; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_printf.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_printf.c index e742b57..fe5bcd3 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_printf.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_printf.c @@ -1,127 +1,127 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -/* - * This file provides a very minimal printf implementation for use with very - * small applications. Only the following format strings are supported: - * %x - * %s - * %c - * %% - */ - -#include -#include "sys/alt_stdio.h" - -/* - * ALT printf function - */ -void -alt_printf(const char* fmt, ... ) -{ - va_list args; - va_start(args, fmt); - const char *w; - char c; - - /* Process format string. */ - w = fmt; - while ((c = *w++) != 0) - { - /* If not a format escape character, just print */ - /* character. Otherwise, process format string. */ - if (c != '%') - { - alt_putchar(c); - } - else - { - /* Get format character. If none */ - /* available, processing is complete. */ - if ((c = *w++) != 0) - { - if (c == '%') - { - /* Process "%" escape sequence. */ - alt_putchar(c); - } - else if (c == 'c') - { - int v = va_arg(args, int); - alt_putchar(v); - } - else if (c == 'x') - { - /* Process hexadecimal number format. */ - unsigned long v = va_arg(args, unsigned long); - unsigned long digit; - int digit_shift; - - /* If the number value is zero, just print and continue. */ - if (v == 0) - { - alt_putchar('0'); - continue; - } - - /* Find first non-zero digit. */ - digit_shift = 28; - while (!(v & (0xF << digit_shift))) - digit_shift -= 4; - - /* Print digits. */ - for (; digit_shift >= 0; digit_shift -= 4) - { - digit = (v & (0xF << digit_shift)) >> digit_shift; - if (digit <= 9) - c = '0' + digit; - else - c = 'a' + digit - 10; - alt_putchar(c); - } - } - else if (c == 's') - { - /* Process string format. */ - char *s = va_arg(args, char *); - - while(*s) - alt_putchar(*s++); - } - } - else - { - break; - } - } - } -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file provides a very minimal printf implementation for use with very + * small applications. Only the following format strings are supported: + * %x + * %s + * %c + * %% + */ + +#include +#include "sys/alt_stdio.h" + +/* + * ALT printf function + */ +void +alt_printf(const char* fmt, ... ) +{ + va_list args; + va_start(args, fmt); + const char *w; + char c; + + /* Process format string. */ + w = fmt; + while ((c = *w++) != 0) + { + /* If not a format escape character, just print */ + /* character. Otherwise, process format string. */ + if (c != '%') + { + alt_putchar(c); + } + else + { + /* Get format character. If none */ + /* available, processing is complete. */ + if ((c = *w++) != 0) + { + if (c == '%') + { + /* Process "%" escape sequence. */ + alt_putchar(c); + } + else if (c == 'c') + { + int v = va_arg(args, int); + alt_putchar(v); + } + else if (c == 'x') + { + /* Process hexadecimal number format. */ + unsigned long v = va_arg(args, unsigned long); + unsigned long digit; + int digit_shift; + + /* If the number value is zero, just print and continue. */ + if (v == 0) + { + alt_putchar('0'); + continue; + } + + /* Find first non-zero digit. */ + digit_shift = 28; + while (!(v & (0xF << digit_shift))) + digit_shift -= 4; + + /* Print digits. */ + for (; digit_shift >= 0; digit_shift -= 4) + { + digit = (v & (0xF << digit_shift)) >> digit_shift; + if (digit <= 9) + c = '0' + digit; + else + c = 'a' + digit - 10; + alt_putchar(c); + } + } + else if (c == 's') + { + /* Process string format. */ + char *s = va_arg(args, char *); + + while(*s) + alt_putchar(*s++); + } + } + else + { + break; + } + } + } +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_putchar.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_putchar.c index badaa02..900bb9f 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_putchar.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_putchar.c @@ -1,59 +1,59 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#ifdef ALT_USE_DIRECT_DRIVERS -#include "system.h" -#include "sys/alt_driver.h" -#include "sys/alt_stdio.h" -#endif - -/* - * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. - * Otherwise, uses newlib provided putchar() routine. - */ -int -alt_putchar(int c) -{ -#ifdef ALT_USE_DIRECT_DRIVERS - ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); - char c1 = (char)(c & 0xff); - - if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) { - return -1; - } - return c; -#else - return putchar(c); -#endif -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided putchar() routine. + */ +int +alt_putchar(int c) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + char c1 = (char)(c & 0xff); + + if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) { + return -1; + } + return c; +#else + return putchar(c); +#endif +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_putstr.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_putstr.c index 5345945..131ba19 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_putstr.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_putstr.c @@ -1,55 +1,55 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#ifdef ALT_USE_DIRECT_DRIVERS -#include -#include "system.h" -#include "sys/alt_driver.h" -#include "sys/alt_stdio.h" -#endif - -/* - * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. - * Otherwise, uses newlib provided fputs() routine. - */ -int -alt_putstr(const char* str) -{ -#ifdef ALT_USE_DIRECT_DRIVERS - ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); - return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, str, strlen(str), 0); -#else - return fputs(str, stdout); -#endif -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided fputs() routine. + */ +int +alt_putstr(const char* str) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, str, strlen(str), 0); +#else + return fputs(str, stdout); +#endif +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_read.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_read.c index 1c89777..920ab13 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_read.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_read.c @@ -1,125 +1,125 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include - -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "priv/alt_file.h" -#include "os/alt_syscall.h" - -/* - * The read() system call is used to read a block of data from a file or device. - * This function simply vectors the request to the device driver associated - * with the input file descriptor "file". - * - * ALT_READ is mapped onto the read() system call in alt_syscall.h - */ - -#ifdef ALT_USE_DIRECT_DRIVERS - -#include "system.h" -#include "sys/alt_driver.h" - -/* - * Provide minimal version that just reads from the stdin device when provided. - */ - -int ALT_READ (int file, void *ptr, size_t len) -{ -#ifdef ALT_STDIN_PRESENT - ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); -#endif - -#if !defined(ALT_STDIN_PRESENT) - /* Generate a link time warning, should this function ever be called. */ - ALT_STUB_WARNING(read); -#endif - - switch (file) { -#ifdef ALT_STDIN_PRESENT - case 0: /* stdin file descriptor */ - return ALT_DRIVER_READ(ALT_STDIN_DEV, ptr, len, 0); -#endif /* ALT_STDIN_PRESENT */ - default: - ALT_ERRNO = EBADFD; - return -1; - } -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -int ALT_READ (int file, void *ptr, size_t len) -{ - alt_fd* fd; - int rval; - - /* - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - - if (fd) - { - /* - * If the file has not been opened with read access, or if the driver does - * not provide an implementation of read(), generate an error. Otherwise - * call the drivers read() function to process the request. - */ - - if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && - (fd->dev->read)) - { - if ((rval = fd->dev->read(fd, ptr, len)) < 0) - { - ALT_ERRNO = -rval; - return -1; - } - return rval; - } - else - { - ALT_ERRNO = EACCES; - } - } - else - { - ALT_ERRNO = EBADFD; - } - return -1; -} - -#endif /* ALT_USE_DIRECT_DRIVERS */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The read() system call is used to read a block of data from a file or device. + * This function simply vectors the request to the device driver associated + * with the input file descriptor "file". + * + * ALT_READ is mapped onto the read() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just reads from the stdin device when provided. + */ + +int ALT_READ (int file, void *ptr, size_t len) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(read); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_READ(ALT_STDIN_DEV, ptr, len, 0); +#endif /* ALT_STDIN_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_release_fd.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_release_fd.c index 84733a7..c22a97f 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_release_fd.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_release_fd.c @@ -1,54 +1,54 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_dev.h" -#include "priv/alt_file.h" - -/* - * alt_release_fd() is called to free an allocated file descriptor. This is - * done by setting the device pointer in the file descriptor structure to zero. - * - * File descriptors correcponding to standard in, standard out and standard - * error cannont be released backed to the pool. They are always reserved. - */ - -void alt_release_fd (int fd) -{ - if (fd > 2) - { - alt_fd_list[fd].fd_flags = 0; - alt_fd_list[fd].dev = 0; - } -} - - - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * alt_release_fd() is called to free an allocated file descriptor. This is + * done by setting the device pointer in the file descriptor structure to zero. + * + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + if (fd > 2) + { + alt_fd_list[fd].fd_flags = 0; + alt_fd_list[fd].dev = 0; + } +} + + + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_remap_cached.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_remap_cached.c index f61cb9c..6afc465 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_remap_cached.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_remap_cached.c @@ -1,50 +1,50 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "sys/alt_cache.h" -#include "system.h" - -#ifdef NIOS2_MMU_PRESENT -/* Convert KERNEL region address to IO region address */ -#define BYPASS_DCACHE_MASK (0x1 << 29) -#else -/* Set bit 31 of address to bypass D-cache */ -#define BYPASS_DCACHE_MASK (0x1 << 31) -#endif - -/* - * Convert a pointer to a block of uncached memory, into a block of - * cached memory. - */ - -void* alt_remap_cached (volatile void* ptr, alt_u32 len) -{ - return (void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +void* alt_remap_cached (volatile void* ptr, alt_u32 len) +{ + return (void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_remap_uncached.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_remap_uncached.c index 7ff6302..e533f94 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_remap_uncached.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_remap_uncached.c @@ -1,51 +1,51 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "sys/alt_cache.h" -#include "system.h" - -#ifdef NIOS2_MMU_PRESENT -/* Convert KERNEL region address to IO region address */ -#define BYPASS_DCACHE_MASK (0x1 << 29) -#else -/* Set bit 31 of address to bypass D-cache */ -#define BYPASS_DCACHE_MASK (0x1 << 31) -#endif - -/* - * Convert a pointer to a block of cached memory, into a block of - * uncached memory. - */ - -volatile void* alt_remap_uncached (void* ptr, alt_u32 len) -{ - alt_dcache_flush (ptr, len); - return (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +volatile void* alt_remap_uncached (void* ptr, alt_u32 len) +{ + alt_dcache_flush (ptr, len); + return (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_rename.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_rename.c index 48afac0..26db44d 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_rename.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_rename.c @@ -1,55 +1,55 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "os/alt_syscall.h" - -/* - * _rename() is used by newlib to rename an existing file. This is unsupported - * in the HAL environment. However a "do-nothing" implementation is still - * provied for newlib compatability. - * - * ALT_RENAME is mapped onto the _rename() system call in alt_syscall.h - */ - -int ALT_RENAME (char *existing, char *new) -{ - /* Generate a link time warning, should this function ever be called. */ - - ALT_STUB_WARNING(_rename); - - /* Indicate an error */ - - ALT_ERRNO = ENOSYS; - return -1; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * _rename() is used by newlib to rename an existing file. This is unsupported + * in the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_RENAME is mapped onto the _rename() system call in alt_syscall.h + */ + +int ALT_RENAME (char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(_rename); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_sbrk.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_sbrk.c index b8c3799..7ab3367 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_sbrk.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_sbrk.c @@ -1,136 +1,136 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#include "os/alt_syscall.h" - -#include "sys/alt_irq.h" -#include "sys/alt_stack.h" - -#include "system.h" - -/* - * sbrk() is called to dynamically extend the data segment for the application. - * Thie input argument "incr" is the size of the block to allocate. - * - * This simple implementation does not perform any bounds checking. Memory will - * be allocated, even if the request region colides with the stack or overflows - * the available physical memory. - * - * ALT_SBRK is mapped onto the sbrk() system call in alt_syscall.h - * - * This function is called by the profiling code to allocate memory so must be - * safe if called from an interrupt context. It must also not be instrumented - * because that would lead to an infinate loop. - */ - -extern char __alt_heap_start[]; /* set by linker */ -extern char __alt_heap_limit[]; /* set by linker */ - -static char *heap_end = __alt_heap_start; - -#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) -char * alt_exception_old_stack_limit = NULL; -#endif - -caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); - -caddr_t ALT_SBRK (int incr) -{ - alt_irq_context context; - char *prev_heap_end; - - context = alt_irq_disable_all(); - - /* Always return data aligned on a word boundary */ - heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); - -#ifdef ALT_MAX_HEAP_BYTES - /* - * User specified a maximum heap size. Return -1 if it would - * be exceeded by this sbrk call. - */ - if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { - alt_irq_enable_all(context); - return (caddr_t)-1; - } -#else - if ((heap_end + incr) > __alt_heap_limit) { - alt_irq_enable_all(context); - return (caddr_t)-1; - } -#endif - - prev_heap_end = heap_end; - heap_end += incr; - -#ifdef ALT_STACK_CHECK - /* - * If the stack and heap are contiguous then extending the heap reduces the - * space available for the stack. If we are still using the default stack - * then adjust the stack limit to note this, while checking for stack - * pointer overflow. - * If the stack limit isn't pointing at the top of the heap then the code - * is using a different stack so none of this needs to be done. - */ - - if (alt_stack_limit() == prev_heap_end) - { - if (alt_stack_pointer() <= heap_end) - alt_report_stack_overflow(); - - alt_set_stack_limit(heap_end); - } - -#ifdef ALT_EXCEPTION_STACK - /* - * If we are executing from the exception stack then compare against the - * stack we switched away from as well. The exception stack is a fixed - * size so doesn't need to be checked. - */ - - if (alt_exception_old_stack_limit == prev_heap_end) - { - if (alt_exception_old_stack_limit <= heap_end) - alt_report_stack_overflow(); - - alt_exception_old_stack_limit = heap_end; - } -#endif - -#endif - - alt_irq_enable_all(context); - - return (caddr_t) prev_heap_end; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "os/alt_syscall.h" + +#include "sys/alt_irq.h" +#include "sys/alt_stack.h" + +#include "system.h" + +/* + * sbrk() is called to dynamically extend the data segment for the application. + * Thie input argument "incr" is the size of the block to allocate. + * + * This simple implementation does not perform any bounds checking. Memory will + * be allocated, even if the request region colides with the stack or overflows + * the available physical memory. + * + * ALT_SBRK is mapped onto the sbrk() system call in alt_syscall.h + * + * This function is called by the profiling code to allocate memory so must be + * safe if called from an interrupt context. It must also not be instrumented + * because that would lead to an infinate loop. + */ + +extern char __alt_heap_start[]; /* set by linker */ +extern char __alt_heap_limit[]; /* set by linker */ + +static char *heap_end = __alt_heap_start; + +#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) +char * alt_exception_old_stack_limit = NULL; +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + +#ifdef ALT_MAX_HEAP_BYTES + /* + * User specified a maximum heap size. Return -1 if it would + * be exceeded by this sbrk call. + */ + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#endif + + prev_heap_end = heap_end; + heap_end += incr; + +#ifdef ALT_STACK_CHECK + /* + * If the stack and heap are contiguous then extending the heap reduces the + * space available for the stack. If we are still using the default stack + * then adjust the stack limit to note this, while checking for stack + * pointer overflow. + * If the stack limit isn't pointing at the top of the heap then the code + * is using a different stack so none of this needs to be done. + */ + + if (alt_stack_limit() == prev_heap_end) + { + if (alt_stack_pointer() <= heap_end) + alt_report_stack_overflow(); + + alt_set_stack_limit(heap_end); + } + +#ifdef ALT_EXCEPTION_STACK + /* + * If we are executing from the exception stack then compare against the + * stack we switched away from as well. The exception stack is a fixed + * size so doesn't need to be checked. + */ + + if (alt_exception_old_stack_limit == prev_heap_end) + { + if (alt_exception_old_stack_limit <= heap_end) + alt_report_stack_overflow(); + + alt_exception_old_stack_limit = heap_end; + } +#endif + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_settod.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_settod.c index 59db0f8..13349b8 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_settod.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_settod.c @@ -1,96 +1,96 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include - -#include "sys/alt_errno.h" -#include "sys/alt_alarm.h" -#include "os/alt_syscall.h" - -/* - * "alt_timezone" and "alt_resettime" are the values of the the reset time and - * time zone set through the last call to settimeofday(). By default they are - * zero initialised. - */ - -extern struct timezone alt_timezone; -extern struct timeval alt_resettime; - -/* - * Macro defining the number of micoseconds in a second. - */ - -#define ALT_US (1000000) - - -/* - * settimeofday() can be called to calibrate the system clock, so that - * subsequent calls to gettimeofday() will return the elapsed "wall clock" - * time. - * - * This is done by updating the global structures "alt_resettime" and - * "alt_timezone" so that an immediate call to gettimeofday() would return - * the value specified by "t" and "tz". - * - * Warning: if this function is called concurrently with a call to - * gettimeofday(), the value returned by gettimeofday() will be unreliable. - * - * ALT_SETTIMEOFDAY is mapped onto the settimeofday() system call in - * alt_syscall.h - */ - -int ALT_SETTIMEOFDAY (const struct timeval *t, - const struct timezone *tz) -{ - alt_u32 nticks = alt_nticks (); - alt_u32 tick_rate = alt_ticks_per_second (); - - /* If there is a system clock available, update the current time */ - - if (tick_rate) - { - alt_resettime.tv_sec = t->tv_sec - nticks/tick_rate; - alt_resettime.tv_usec = t->tv_usec - - ((nticks*(ALT_US/tick_rate))%ALT_US); - - alt_timezone.tz_minuteswest = tz->tz_minuteswest; - alt_timezone.tz_dsttime = tz->tz_dsttime; - - return 0; - } - - /* There's no system clock available */ - - ALT_ERRNO = ENOSYS; - return -1; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +extern struct timezone alt_timezone; +extern struct timeval alt_resettime; + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + + +/* + * settimeofday() can be called to calibrate the system clock, so that + * subsequent calls to gettimeofday() will return the elapsed "wall clock" + * time. + * + * This is done by updating the global structures "alt_resettime" and + * "alt_timezone" so that an immediate call to gettimeofday() would return + * the value specified by "t" and "tz". + * + * Warning: if this function is called concurrently with a call to + * gettimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_SETTIMEOFDAY is mapped onto the settimeofday() system call in + * alt_syscall.h + */ + +int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz) +{ + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* If there is a system clock available, update the current time */ + + if (tick_rate) + { + alt_resettime.tv_sec = t->tv_sec - nticks/tick_rate; + alt_resettime.tv_usec = t->tv_usec - + ((nticks*(ALT_US/tick_rate))%ALT_US); + + alt_timezone.tz_minuteswest = tz->tz_minuteswest; + alt_timezone.tz_dsttime = tz->tz_dsttime; + + return 0; + } + + /* There's no system clock available */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_software_exception.S b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_software_exception.S index 2142594..0a9381e 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_software_exception.S +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_software_exception.S @@ -1,53 +1,53 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - - /* - * This file provides the global symbol: software_exception. It is provided to - * support legacy code, and should not be used by new software. - * - * It is used by legacy code to invoke the software exception handler as - * defined by version 1.0 of the Nios II kit. It should only be used when you - * are providing your own interrupt entry point, i.e. you are not using - * alt_irq_entry. - */ - -#include "system.h" - - /* - * Pull in the exception handler. - */ - - .globl alt_exception - - .section .exceptions.entry.label, "xa" - - .globl software_exception - .type software_exception, @function -software_exception: +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This file provides the global symbol: software_exception. It is provided to + * support legacy code, and should not be used by new software. + * + * It is used by legacy code to invoke the software exception handler as + * defined by version 1.0 of the Nios II kit. It should only be used when you + * are providing your own interrupt entry point, i.e. you are not using + * alt_irq_entry. + */ + +#include "system.h" + + /* + * Pull in the exception handler. + */ + + .globl alt_exception + + .section .exceptions.entry.label, "xa" + + .globl software_exception + .type software_exception, @function +software_exception: diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_stat.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_stat.c index 44e207b..c196d0c 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_stat.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_stat.c @@ -1,59 +1,59 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include -#include -#include - -#include "os/alt_syscall.h" - -/* - * The stat() function is similar to the fstat() function in that it is used to - * obtain status information about a file. Instead of using an open file - * descriptor (like fstat()), stat() takes the name of a file as an input - * argument. - * - * ALT_STAT is mapped onto the stat() system call in alt_syscall.h - */ - -int ALT_STAT (const char *file, struct stat *st) -{ - int fd; - int rc; - - fd = open (file, 0); - rc = fstat (fd, st); - close (fd); - - return rc; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "os/alt_syscall.h" + +/* + * The stat() function is similar to the fstat() function in that it is used to + * obtain status information about a file. Instead of using an open file + * descriptor (like fstat()), stat() takes the name of a file as an input + * argument. + * + * ALT_STAT is mapped onto the stat() system call in alt_syscall.h + */ + +int ALT_STAT (const char *file, struct stat *st) +{ + int fd; + int rc; + + fd = open (file, 0); + rc = fstat (fd, st); + close (fd); + + return rc; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_tick.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_tick.c index c73488d..23719b1 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_tick.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_tick.c @@ -1,149 +1,149 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_irq.h" -#include "sys/alt_alarm.h" -#include "os/alt_hooks.h" -#include "alt_types.h" - -/* - * "_alt_tick_rate" is used to store the value of the system clock frequency - * in ticks per second. It is initialised to zero, which corresponds to there - * being no system clock facility available. - */ - -alt_u32 _alt_tick_rate = 0; - -/* - * "_alt_nticks" is the number of system clock ticks that have elapsed since - * reset. - */ - -volatile alt_u32 _alt_nticks = 0; - -/* - * "alt_alarm_list" is the head of a linked list of registered alarms. This is - * initialised to be an empty list. - */ - -ALT_LLIST_HEAD(alt_alarm_list); - -/* - * alt_alarm_stop() is called to remove an alarm from the list of registered - * alarms. Alternatively an alarm can unregister itself by returning zero when - * the alarm executes. - */ - -void alt_alarm_stop (alt_alarm* alarm) -{ - alt_irq_context irq_context; - - irq_context = alt_irq_disable_all(); - alt_llist_remove (&alarm->llist); - alt_irq_enable_all (irq_context); -} - -/* - * alt_tick() is periodically called by the system clock driver in order to - * process the registered list of alarms. Each alarm is registed with a - * callback interval, and a callback function, "callback". - * - * The return value of the callback function indicates how many ticks are to - * elapse until the next callback. A return value of zero indicates that the - * alarm should be deactivated. - * - * alt_tick() is expected to run at interrupt level. - */ - -void alt_tick (void) -{ - alt_alarm* next; - alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; - - alt_u32 next_callback; - - /* update the tick counter */ - - _alt_nticks++; - - /* process the registered callbacks */ - - while (alarm != (alt_alarm*) &alt_alarm_list) - { - next = (alt_alarm*) alarm->llist.next; - - /* - * Upon the tick-counter rolling over it is safe to clear the - * roll-over flag; once the flag is cleared this (or subsequnt) - * tick events are enabled to generate an alarm event. - */ - if ((alarm->rollover) && (_alt_nticks == 0)) - { - alarm->rollover = 0; - } - - /* if the alarm period has expired, make the callback */ - if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) - { - next_callback = alarm->callback (alarm->context); - - /* deactivate the alarm if the return value is zero */ - - if (next_callback == 0) - { - alt_alarm_stop (alarm); - } - else - { - alarm->time += next_callback; - - /* - * If the desired alarm time causes a roll-over, set the rollover - * flag. This will prevent the subsequent tick event from causing - * an alarm too early. - */ - if(alarm->time < _alt_nticks) - { - alarm->rollover = 1; - } - } - } - alarm = next; - } - - /* - * Update the operating system specific timer facilities. - */ - - ALT_OS_TIME_TICK(); -} - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "os/alt_hooks.h" +#include "alt_types.h" + +/* + * "_alt_tick_rate" is used to store the value of the system clock frequency + * in ticks per second. It is initialised to zero, which corresponds to there + * being no system clock facility available. + */ + +alt_u32 _alt_tick_rate = 0; + +/* + * "_alt_nticks" is the number of system clock ticks that have elapsed since + * reset. + */ + +volatile alt_u32 _alt_nticks = 0; + +/* + * "alt_alarm_list" is the head of a linked list of registered alarms. This is + * initialised to be an empty list. + */ + +ALT_LLIST_HEAD(alt_alarm_list); + +/* + * alt_alarm_stop() is called to remove an alarm from the list of registered + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + alt_llist_remove (&alarm->llist); + alt_irq_enable_all (irq_context); +} + +/* + * alt_tick() is periodically called by the system clock driver in order to + * process the registered list of alarms. Each alarm is registed with a + * callback interval, and a callback function, "callback". + * + * The return value of the callback function indicates how many ticks are to + * elapse until the next callback. A return value of zero indicates that the + * alarm should be deactivated. + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + { + next = (alt_alarm*) alarm->llist.next; + + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + { + alarm->rollover = 0; + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + { + next_callback = alarm->callback (alarm->context); + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + { + alt_alarm_stop (alarm); + } + else + { + alarm->time += next_callback; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + { + alarm->rollover = 1; + } + } + } + alarm = next; + } + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); +} + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_times.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_times.c index 4dd965d..6543164 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_times.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_times.c @@ -1,71 +1,71 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include - -#include "sys/alt_errno.h" -#include "sys/alt_alarm.h" -#include "os/alt_syscall.h" - -/* - * The times() function is used by newlib to obtain elapsed time information. - * The return value is the elapsed time since reset in system clock ticks. Note - * that this is distinct from the strict Posix version of times(), which should - * return the time since: 0 hours, 0 minutes, 0 seconds, January 1, 1970, GMT. - * - * The input structure is filled in with time accounting information. This - * implementation attributes all cpu time to the system. - * - * ALT_TIMES is mapped onto the times() system call in alt_syscall.h - */ - -clock_t ALT_TIMES (struct tms *buf) -{ - clock_t ticks = alt_nticks(); - - /* If there is no system clock present, generate an error */ - - if (!alt_ticks_per_second()) - { - ALT_ERRNO = ENOSYS; - return 0; - } - - /* Otherwise return the elapsed time */ - - buf->tms_utime = 0; - buf->tms_stime = ticks; - buf->tms_cutime = 0; - buf->tms_cstime = 0; - - return ticks; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * The times() function is used by newlib to obtain elapsed time information. + * The return value is the elapsed time since reset in system clock ticks. Note + * that this is distinct from the strict Posix version of times(), which should + * return the time since: 0 hours, 0 minutes, 0 seconds, January 1, 1970, GMT. + * + * The input structure is filled in with time accounting information. This + * implementation attributes all cpu time to the system. + * + * ALT_TIMES is mapped onto the times() system call in alt_syscall.h + */ + +clock_t ALT_TIMES (struct tms *buf) +{ + clock_t ticks = alt_nticks(); + + /* If there is no system clock present, generate an error */ + + if (!alt_ticks_per_second()) + { + ALT_ERRNO = ENOSYS; + return 0; + } + + /* Otherwise return the elapsed time */ + + buf->tms_utime = 0; + buf->tms_stime = ticks; + buf->tms_cutime = 0; + buf->tms_cstime = 0; + + return ticks; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_uncached_free.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_uncached_free.c index 6e362ba..37f4ac1 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_uncached_free.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_uncached_free.c @@ -1,49 +1,49 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "sys/alt_cache.h" -#include "system.h" - -#ifdef NIOS2_MMU_PRESENT -/* Convert KERNEL region address to IO region address */ -#define BYPASS_DCACHE_MASK (0x1 << 29) -#else -/* Set bit 31 of address to bypass D-cache */ -#define BYPASS_DCACHE_MASK (0x1 << 31) -#endif - -/* - * Free a block of uncached memory. - */ - -void alt_uncached_free (volatile void* ptr) -{ - free ((void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK)); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Free a block of uncached memory. + */ + +void alt_uncached_free (volatile void* ptr) +{ + free ((void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK)); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_uncached_malloc.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_uncached_malloc.c index ab3416d..325132e 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_uncached_malloc.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_uncached_malloc.c @@ -1,55 +1,55 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "sys/alt_cache.h" -#include "system.h" - -#ifdef NIOS2_MMU_PRESENT -/* Convert KERNEL region address to IO region address */ -#define BYPASS_DCACHE_MASK (0x1 << 29) -#else -/* Set bit 31 of address to bypass D-cache */ -#define BYPASS_DCACHE_MASK (0x1 << 31) -#endif - -/* - * Allocate a block of uncached memory. - */ - -volatile void* alt_uncached_malloc (size_t size) -{ - void* ptr; - - ptr = malloc (size); - - alt_dcache_flush (ptr, size); - - return ptr ? (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK) : NULL; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Allocate a block of uncached memory. + */ + +volatile void* alt_uncached_malloc (size_t size) +{ + void* ptr; + + ptr = malloc (size); + + alt_dcache_flush (ptr, size); + + return ptr ? (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK) : NULL; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_unlink.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_unlink.c index 29e35d6..606f019 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_unlink.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_unlink.c @@ -1,55 +1,55 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "os/alt_syscall.h" - -/* - * unlink() is used by newlib to delete an existing link to a file. This is - * unsupported in the HAL environment. However a "do-nothing" implementation - * is still provied for newlib compatability. - * - * ALT_UNLINK is mapped onto the unlink() system call in alt_syscall.h - */ - -int ALT_UNLINK (char *name) -{ - /* Generate a link time warning, should this function ever be called. */ - - ALT_STUB_WARNING(unlink); - - /* Indicate an error */ - - ALT_ERRNO = ENOSYS; - return -1; -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * unlink() is used by newlib to delete an existing link to a file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_UNLINK is mapped onto the unlink() system call in alt_syscall.h + */ + +int ALT_UNLINK (char *name) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(unlink); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_usleep.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_usleep.c index 2330eb8..eea89cd 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_usleep.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_usleep.c @@ -1,52 +1,52 @@ -/* - * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * ------------ - * - * Altera does not recommend, suggest or require that this reference design - * file be used in conjunction or combination with any other product. - * - * usleep.c - Microsecond delay routine - */ - -#include - -#include "priv/alt_busy_sleep.h" -#include "os/alt_syscall.h" - -/* - * This function simply calls alt_busy_sleep() to perform the delay. This - * function implements the delay as a calibrated "busy loop". - * - * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h - */ - - - -#if defined (__GNUC__) && __GNUC__ >= 4 -int ALT_USLEEP (useconds_t us) -#else -unsigned int ALT_USLEEP (unsigned int us) -#endif -{ - return alt_busy_sleep(us); -} +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + * + * usleep.c - Microsecond delay routine + */ + +#include + +#include "priv/alt_busy_sleep.h" +#include "os/alt_syscall.h" + +/* + * This function simply calls alt_busy_sleep() to perform the delay. This + * function implements the delay as a calibrated "busy loop". + * + * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h + */ + + + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us) +#else +unsigned int ALT_USLEEP (unsigned int us) +#endif +{ + return alt_busy_sleep(us); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_wait.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_wait.c index a42f80f..dd768ad 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_wait.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_wait.c @@ -1,52 +1,52 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include "sys/alt_errno.h" -#include "os/alt_syscall.h" - -/* - * wait() is used by newlib to wait for all child processes to exit. Since the - * HAL does not support spawning child processes, this returns immediately as - * there can't be anythign to wait for. - * - * ALT_WAIT is mapped onto the wait() system call in alt_syscall.h - */ - -int ALT_WAIT (int *status) -{ - *status = 0; - - ALT_ERRNO = ECHILD; - - return -1; -} - +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * wait() is used by newlib to wait for all child processes to exit. Since the + * HAL does not support spawning child processes, this returns immediately as + * there can't be anythign to wait for. + * + * ALT_WAIT is mapped onto the wait() system call in alt_syscall.h + */ + +int ALT_WAIT (int *status) +{ + *status = 0; + + ALT_ERRNO = ECHILD; + + return -1; +} + diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_write.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_write.c index 51debb5..d161cdf 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_write.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/alt_write.c @@ -1,138 +1,138 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - -#include -#include - -#include "sys/alt_errno.h" -#include "sys/alt_warning.h" -#include "priv/alt_file.h" -#include "os/alt_syscall.h" - -#include "sys/alt_log_printf.h" - -/* - * The write() system call is used to write a block of data to a file or - * device. This function simply vectors the request to the device driver - * associated with the input file descriptor "file". - * - * ALT_WRITE is mapped onto the write() system call in alt_syscall.h - */ - -#ifdef ALT_USE_DIRECT_DRIVERS - -#include "system.h" -#include "sys/alt_driver.h" - -/* - * Provide minimal version that just writes to the stdout/stderr devices - * when provided. - */ - -int ALT_WRITE (int file, const void *ptr, size_t len) -{ -#ifdef ALT_STDOUT_PRESENT - ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); -#endif -#ifdef ALT_STDERR_PRESENT - ALT_DRIVER_WRITE_EXTERNS(ALT_STDERR_DEV); -#endif - -#if !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) - /* Generate a link time warning, should this function ever be called. */ - ALT_STUB_WARNING(write); -#endif - - switch (file) { -#ifdef ALT_STDOUT_PRESENT - case 1: /* stdout file descriptor */ - return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, ptr, len, 0); -#endif /* ALT_STDOUT_PRESENT */ -#ifdef ALT_STDERR_PRESENT - case 2: /* stderr file descriptor */ - return ALT_DRIVER_WRITE(ALT_STDERR_DEV, ptr, len, 0); -#endif /* ALT_STDERR_PRESENT */ - default: - ALT_ERRNO = EBADFD; - return -1; - } -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -int ALT_WRITE (int file, const void *ptr, size_t len) -{ - alt_fd* fd; - int rval; - - /* - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - - if (fd) - { - /* - * If the file has not been opened with write access, or if the driver does - * not provide an implementation of write(), generate an error. Otherwise - * call the drivers write() function to process the request. - */ - - if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) - { - - /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ - ALT_LOG_WRITE_FUNCTION(ptr,len); - - if ((rval = fd->dev->write(fd, ptr, len)) < 0) - { - ALT_ERRNO = -rval; - return -1; - } - return rval; - } - else - { - ALT_ERRNO = EACCES; - } - } - else - { - ALT_ERRNO = EBADFD; - } - return -1; -} - -#endif /* ALT_USE_DIRECT_DRIVERS */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#include "sys/alt_log_printf.h" + +/* + * The write() system call is used to write a block of data to a file or + * device. This function simply vectors the request to the device driver + * associated with the input file descriptor "file". + * + * ALT_WRITE is mapped onto the write() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just writes to the stdout/stderr devices + * when provided. + */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(write); +#endif + + switch (file) { +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, ptr, len, 0); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDERR_DEV, ptr, len, 0); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/altera_nios2_qsys_irq.c b/software/qsys_tutorial_lcd4_bsp/HAL/src/altera_nios2_qsys_irq.c index c7a4f93..c719dbc 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/altera_nios2_qsys_irq.c +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/altera_nios2_qsys_irq.c @@ -1,37 +1,37 @@ -/* - * Copyright (c) 2009 Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to - * deal in the Software without restriction, including without limitation the - * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * altera_nios2_irq.c - Support for Nios II internal interrupt controller. - * - */ - -#include "sys/alt_irq.h" -#include "altera_nios2_qsys_irq.h" - -/* - * To initialize the internal interrupt controller, just clear the IENABLE - * register so that all possible IRQs are disabled. - */ -void altera_nios2_qsys_irq_init(void) -{ - NIOS2_WRITE_IENABLE(0); -} +/* + * Copyright (c) 2009 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * altera_nios2_irq.c - Support for Nios II internal interrupt controller. + * + */ + +#include "sys/alt_irq.h" +#include "altera_nios2_qsys_irq.h" + +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_qsys_irq_init(void) +{ + NIOS2_WRITE_IENABLE(0); +} diff --git a/software/qsys_tutorial_lcd4_bsp/HAL/src/crt0.S b/software/qsys_tutorial_lcd4_bsp/HAL/src/crt0.S index 582445d..739e45e 100644 --- a/software/qsys_tutorial_lcd4_bsp/HAL/src/crt0.S +++ b/software/qsys_tutorial_lcd4_bsp/HAL/src/crt0.S @@ -1,456 +1,456 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "system.h" -#include "nios2.h" - -/* Setup header files to work with assembler code. */ -#define ALT_ASM_SRC - -/* Debug logging facility */ -#include "sys/alt_log_printf.h" - -/*************************************************************************\ -| MACROS | -\*************************************************************************/ - -/* - * The new build tools explicitly define macros when alt_load() - * must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that - * those macros are controlling if alt_load() needs to be called. - */ -#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED - -/* Need to call alt_load() if any of these sections are being copied. */ -#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS) -#define CALL_ALT_LOAD -#endif - -#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ - -/* - * The legacy build tools use the following macros to detect when alt_load() - * needs to be called. - */ - -#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \ - ((res##_BASE != rodata##_BASE) || \ - (res##_BASE != rwdata##_BASE) || \ - (res##_BASE != exc##_BASE)) - -#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \ - __ALT_LOAD_SECTIONS(res, text, rodata, exc) - -#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \ - ALT_RODATA_DEVICE, \ - ALT_RWDATA_DEVICE, \ - ALT_EXCEPTIONS_DEVICE) - -/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */ -#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS -#define CALL_ALT_LOAD -#endif - -#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ - -/* - * When the legacy build tools define a macro called ALT_NO_BOOTLOADER, - * it indicates that initialization code is allowed at the reset address. - * The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for - * the same purpose. - */ -#ifdef ALT_NO_BOOTLOADER -#define ALT_ALLOW_CODE_AT_RESET -#endif - -/*************************************************************************\ -| EXTERNAL REFERENCES | -\*************************************************************************/ - -/* - * The entry point for user code is either "main" in hosted mode, or - * "alt_main" in standalone mode. These are explicitly referenced here, - * to ensure they are built into the executable. This allows the user - * to build them into libraries, rather than supplying them in object - * files at link time. - */ - .globl main - .globl alt_main - -/* - * Create a reference to the software multiply/divide and trap handers, - * so that if they are provided, they will appear in the executable. - */ -#ifndef ALT_NO_INSTRUCTION_EMULATION - .globl alt_exception_muldiv -#endif -#ifdef ALT_TRAP_HANDLER - .globl alt_exception_trap -#endif - -/* - * Linker defined symbols used to initialize bss. - */ -.globl __bss_start -.globl __bss_end - -/*************************************************************************\ -| RESET SECTION (.entry) | -\*************************************************************************/ - -/* - * This is the reset entry point for Nios II. - * - * At reset, only the cache line which contain the reset vector is - * initialized by the hardware. The code within the first cache line - * initializes the remainder of the instruction cache. - */ - - .section .entry, "xa" - .align 5 - -/* - * Explicitly allow the use of r1 (the assembler temporary register) - * within this code. This register is normally reserved for the use of - * the assembler. - */ - .set noat - -/* - * Some tools want to know where the reset vector is. - * Code isn't always provided at the reset vector but at least the - * __reset label always contains the reset vector address because - * it is defined at the start of the .entry section. - */ - - .globl __reset - .type __reset, @function -__reset: - -/* - * Initialize the instruction cache if present (i.e. size > 0) and - * reset code is allowed unless optimizing for RTL simulation. - * RTL simulations can ensure the instruction cache is already initialized - * so skipping this loop speeds up RTL simulation. - */ - -#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE) - /* Assume the instruction cache size is always a power of two. */ -#if NIOS2_ICACHE_SIZE > 0x8000 - movhi r2, %hi(NIOS2_ICACHE_SIZE) -#else - movui r2, NIOS2_ICACHE_SIZE -#endif - -0: - initi r2 - addi r2, r2, -NIOS2_ICACHE_LINE_SIZE - bgt r2, zero, 0b -1: - - /* - * The following debug information tells the ISS not to run the loop above - * but to perform its actions using faster internal code. - */ - .pushsection .debug_alt_sim_info - .int 1, 1, 0b, 1b - .popsection -#endif /* Initialize Instruction Cache */ - -/* - * Jump to the _start entry point in the .text section if reset code - * is allowed or if optimizing for RTL simulation. - */ -#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) - /* Jump to the _start entry point in the .text section. */ - movhi r1, %hi(_start) - ori r1, r1, %lo(_start) - jmp r1 - - .size __reset, . - __reset -#endif /* Jump to _start */ - -/* - * When not using exit, provide an _exit symbol to prevent unresolved - * references to _exit from the linker script. - */ -#ifdef ALT_NO_EXIT - .globl _exit -_exit: -#endif - -/*************************************************************************\ -| TEXT SECTION (.text) | -\*************************************************************************/ - -/* - * Start of the .text section, and also the code entry point when - * the code is executed by a bootloader rather than directly from reset. - */ - .section .text - .align 2 - - .globl _start - .type _start, @function -_start: - -/* - * Initialize the data cache if present (i.e. size > 0) and not - * optimizing for RTL simulation. - * RTL simulations can ensure the data cache is already initialized - * so skipping this loop speeds up RTL simulation. - */ - -#if NIOS2_DCACHE_SIZE > 0 && !defined(ALT_SIM_OPTIMIZE) - - /* Assume the data cache size is always a power of two. */ -#if NIOS2_DCACHE_SIZE > 0x8000 - movhi r2, %hi(NIOS2_DCACHE_SIZE) -#else - movui r2, NIOS2_DCACHE_SIZE -#endif - -0: - initd 0(r2) - addi r2, r2, -NIOS2_DCACHE_LINE_SIZE - bgt r2, zero, 0b -1: - - /* - * The following debug information tells the ISS not to run the loop above - * but to perform its actions using faster internal code. - */ - .pushsection .debug_alt_sim_info - .int 2, 1, 0b, 1b - .popsection - -#endif /* Initialize Data Cache */ - - /* Log that caches have been initialized. */ - ALT_LOG_PUTS(alt_log_msg_cache) - - /* Log that the stack pointer is about to be setup. */ - ALT_LOG_PUTS(alt_log_msg_stackpointer) - -#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) - /* - * Now that the caches are initialized, set up the stack pointer. - * The value provided by the linker is assumed to be correctly aligned. - */ - movhi sp, %hi(__alt_stack_pointer) - ori sp, sp, %lo(__alt_stack_pointer) - - /* Set up the global pointer. */ - movhi gp, %hi(_gp) - ori gp, gp, %lo(_gp) - -#else /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */ - - /* - * Set up the GP and SP in all shadow register sets. - */ - - /* - * Check current register set number, if CPU resets into a shadow register - * set, switch register set to 0 by writing zero to SSTATUS register and - * execute an ERET instruction that just jumps to the next PC address - * (use the NEXTPC instruction to get this). - */ - - rdctl r2, status - - /* Get the current register set number (STATUS.CRS). */ - andi r3, r2, NIOS2_STATUS_CRS_MSK - - /* Skip switch register set if STATUS.CRS is 0. */ - beq r3, zero, .Lskip_switch_reg_set - - .set nobreak - - /* Current register set is non-zero, set SSTATUS to 0. */ - mov sstatus, zero - - /* Get next pc and store in ea. */ - nextpc ea - - /* Point to instruction after eret. */ - addi ea, ea, 8 - - /* - * Execute ERET instruction that just jumps to the next PC address - */ - eret - -.Lskip_switch_reg_set: - mov r2, zero - - /* Reset STATUS register */ - wrctl status, r2 - - movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS - - /* Set up the stack pointer in register set 0. */ - movhi sp, %hi(__alt_stack_pointer) - ori sp, sp, %lo(__alt_stack_pointer) - - /* Set up the global pointer in register set 0. */ - movhi gp, %hi(_gp) - ori gp, gp, %lo(_gp) - -.Lsetup_sp_and_gp_loop: - /* - * Setup GP and SP for shadow register set - * from NIOS2_NUM_OF_SHADOW_REG_SETS to 0 - */ - - /* Skip if number of register sets is 0. */ - beq r3, zero, .Lno_shadow_register_set - - - /* Add previous register set STATUS.PRS by 1 */ - movhi r4, 1 - add r2, r2, r4 - - /* Write STATUS */ - wrctl status, r2 - - /* Clear r0 in the shadow register set (not done by hardware) */ - wrprs r0, r0 - - /* Write the GP in previous register set */ - wrprs gp, gp - - /* Only write the SP in previous register set - * if using the seperate exception stack. For normal case (single stack), - * funnel code would read the SP from previous register set. - */ -#ifdef ALT_INTERRUPT_STACK - - movhi et, %hiadj(__alt_interrupt_stack_pointer) - addi et, et, %lo(__alt_interrupt_stack_pointer) - wrprs sp, et - -#endif /* ALT_INTERRUPT_STACK */ - - /* Decrease number of register set counter by 1 */ - addi r3, r3, -1 - - br .Lsetup_sp_and_gp_loop -.Lno_shadow_register_set: - -#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS */ -/* - * Clear the BSS if not optimizing for RTL simulation. - * - * This uses the symbols: __bss_start and __bss_end, which are defined - * by the linker script. They mark the begining and the end of the bss - * region. The linker script guarantees that these values are word aligned. - */ -#ifndef ALT_SIM_OPTIMIZE - /* Log that the BSS is about to be cleared. */ - ALT_LOG_PUTS(alt_log_msg_bss) - - movhi r2, %hi(__bss_start) - ori r2, r2, %lo(__bss_start) - - movhi r3, %hi(__bss_end) - ori r3, r3, %lo(__bss_end) - - beq r2, r3, 1f - -0: - stw zero, (r2) - addi r2, r2, 4 - bltu r2, r3, 0b - -1: - - /* - * The following debug information tells the ISS not to run the loop above - * but to perform its actions using faster internal code. - */ - .pushsection .debug_alt_sim_info - .int 3, 1, 0b, 1b - .popsection -#endif /* ALT_SIM_OPTIMIZE */ - -/* - * The alt_load() facility is normally used when there is no bootloader. - * It copies some sections into RAM so it acts like a mini-bootloader. - */ -#ifdef CALL_ALT_LOAD - -#ifdef ALT_STACK_CHECK - /* - * If the user has selected stack checking then we need to set up a safe - * value in the stack limit register so that the relocation functions - * don't think the stack has overflowed (the contents of the rwdata - * section aren't defined until alt_load() has been called). - */ - mov et, zero -#endif - - call alt_load - -#endif /* CALL_ALT_LOAD */ - -#ifdef ALT_STACK_CHECK - /* - * Set up the stack limit (if required). The linker has set up the - * copy of the variable which is in memory. - */ - - ldw et, %gprel(alt_stack_limit_value)(gp) -#endif - - /* Log that alt_main is about to be called. */ - ALT_LOG_PUTS(alt_log_msg_alt_main) - - /* Call the C entry point. It should never return. */ - call alt_main - - /* Wait in infinite loop in case alt_main does return. */ -alt_after_alt_main: - br alt_after_alt_main - - .size _start, . - _start - -/* - * Add information about the stack base if stack overflow checking is enabled. - */ -#ifdef ALT_STACK_CHECK - .globl alt_stack_limit_value - .section .sdata,"aws",@progbits - .align 2 - .type alt_stack_limit_value, @object - .size alt_stack_limit_value, 4 -alt_stack_limit_value: - .long __alt_stack_limit -#endif +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" +#include "nios2.h" + +/* Setup header files to work with assembler code. */ +#define ALT_ASM_SRC + +/* Debug logging facility */ +#include "sys/alt_log_printf.h" + +/*************************************************************************\ +| MACROS | +\*************************************************************************/ + +/* + * The new build tools explicitly define macros when alt_load() + * must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that + * those macros are controlling if alt_load() needs to be called. + */ +#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED + +/* Need to call alt_load() if any of these sections are being copied. */ +#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS) +#define CALL_ALT_LOAD +#endif + +#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * The legacy build tools use the following macros to detect when alt_load() + * needs to be called. + */ + +#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + ((res##_BASE != rodata##_BASE) || \ + (res##_BASE != rwdata##_BASE) || \ + (res##_BASE != exc##_BASE)) + +#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + __ALT_LOAD_SECTIONS(res, text, rodata, exc) + +#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \ + ALT_RODATA_DEVICE, \ + ALT_RWDATA_DEVICE, \ + ALT_EXCEPTIONS_DEVICE) + +/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */ +#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS +#define CALL_ALT_LOAD +#endif + +#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * When the legacy build tools define a macro called ALT_NO_BOOTLOADER, + * it indicates that initialization code is allowed at the reset address. + * The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for + * the same purpose. + */ +#ifdef ALT_NO_BOOTLOADER +#define ALT_ALLOW_CODE_AT_RESET +#endif + +/*************************************************************************\ +| EXTERNAL REFERENCES | +\*************************************************************************/ + +/* + * The entry point for user code is either "main" in hosted mode, or + * "alt_main" in standalone mode. These are explicitly referenced here, + * to ensure they are built into the executable. This allows the user + * to build them into libraries, rather than supplying them in object + * files at link time. + */ + .globl main + .globl alt_main + +/* + * Create a reference to the software multiply/divide and trap handers, + * so that if they are provided, they will appear in the executable. + */ +#ifndef ALT_NO_INSTRUCTION_EMULATION + .globl alt_exception_muldiv +#endif +#ifdef ALT_TRAP_HANDLER + .globl alt_exception_trap +#endif + +/* + * Linker defined symbols used to initialize bss. + */ +.globl __bss_start +.globl __bss_end + +/*************************************************************************\ +| RESET SECTION (.entry) | +\*************************************************************************/ + +/* + * This is the reset entry point for Nios II. + * + * At reset, only the cache line which contain the reset vector is + * initialized by the hardware. The code within the first cache line + * initializes the remainder of the instruction cache. + */ + + .section .entry, "xa" + .align 5 + +/* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + +/* + * Some tools want to know where the reset vector is. + * Code isn't always provided at the reset vector but at least the + * __reset label always contains the reset vector address because + * it is defined at the start of the .entry section. + */ + + .globl __reset + .type __reset, @function +__reset: + +/* + * Initialize the instruction cache if present (i.e. size > 0) and + * reset code is allowed unless optimizing for RTL simulation. + * RTL simulations can ensure the instruction cache is already initialized + * so skipping this loop speeds up RTL simulation. + */ + +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE +#endif + +0: + initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 1, 1, 0b, 1b + .popsection +#endif /* Initialize Instruction Cache */ + +/* + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + ori r1, r1, %lo(_start) + jmp r1 + + .size __reset, . - __reset +#endif /* Jump to _start */ + +/* + * When not using exit, provide an _exit symbol to prevent unresolved + * references to _exit from the linker script. + */ +#ifdef ALT_NO_EXIT + .globl _exit +_exit: +#endif + +/*************************************************************************\ +| TEXT SECTION (.text) | +\*************************************************************************/ + +/* + * Start of the .text section, and also the code entry point when + * the code is executed by a bootloader rather than directly from reset. + */ + .section .text + .align 2 + + .globl _start + .type _start, @function +_start: + +/* + * Initialize the data cache if present (i.e. size > 0) and not + * optimizing for RTL simulation. + * RTL simulations can ensure the data cache is already initialized + * so skipping this loop speeds up RTL simulation. + */ + +#if NIOS2_DCACHE_SIZE > 0 && !defined(ALT_SIM_OPTIMIZE) + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE +#endif + +0: + initd 0(r2) + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 2, 1, 0b, 1b + .popsection + +#endif /* Initialize Data Cache */ + + /* Log that caches have been initialized. */ + ALT_LOG_PUTS(alt_log_msg_cache) + + /* Log that the stack pointer is about to be setup. */ + ALT_LOG_PUTS(alt_log_msg_stackpointer) + +#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) + /* + * Now that the caches are initialized, set up the stack pointer. + * The value provided by the linker is assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + + /* Set up the global pointer. */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +#else /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */ + + /* + * Set up the GP and SP in all shadow register sets. + */ + + /* + * Check current register set number, if CPU resets into a shadow register + * set, switch register set to 0 by writing zero to SSTATUS register and + * execute an ERET instruction that just jumps to the next PC address + * (use the NEXTPC instruction to get this). + */ + + rdctl r2, status + + /* Get the current register set number (STATUS.CRS). */ + andi r3, r2, NIOS2_STATUS_CRS_MSK + + /* Skip switch register set if STATUS.CRS is 0. */ + beq r3, zero, .Lskip_switch_reg_set + + .set nobreak + + /* Current register set is non-zero, set SSTATUS to 0. */ + mov sstatus, zero + + /* Get next pc and store in ea. */ + nextpc ea + + /* Point to instruction after eret. */ + addi ea, ea, 8 + + /* + * Execute ERET instruction that just jumps to the next PC address + */ + eret + +.Lskip_switch_reg_set: + mov r2, zero + + /* Reset STATUS register */ + wrctl status, r2 + + movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS + + /* Set up the stack pointer in register set 0. */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + + /* Set up the global pointer in register set 0. */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +.Lsetup_sp_and_gp_loop: + /* + * Setup GP and SP for shadow register set + * from NIOS2_NUM_OF_SHADOW_REG_SETS to 0 + */ + + /* Skip if number of register sets is 0. */ + beq r3, zero, .Lno_shadow_register_set + + + /* Add previous register set STATUS.PRS by 1 */ + movhi r4, 1 + add r2, r2, r4 + + /* Write STATUS */ + wrctl status, r2 + + /* Clear r0 in the shadow register set (not done by hardware) */ + wrprs r0, r0 + + /* Write the GP in previous register set */ + wrprs gp, gp + + /* Only write the SP in previous register set + * if using the seperate exception stack. For normal case (single stack), + * funnel code would read the SP from previous register set. + */ +#ifdef ALT_INTERRUPT_STACK + + movhi et, %hiadj(__alt_interrupt_stack_pointer) + addi et, et, %lo(__alt_interrupt_stack_pointer) + wrprs sp, et + +#endif /* ALT_INTERRUPT_STACK */ + + /* Decrease number of register set counter by 1 */ + addi r3, r3, -1 + + br .Lsetup_sp_and_gp_loop +.Lno_shadow_register_set: + +#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS */ +/* + * Clear the BSS if not optimizing for RTL simulation. + * + * This uses the symbols: __bss_start and __bss_end, which are defined + * by the linker script. They mark the begining and the end of the bss + * region. The linker script guarantees that these values are word aligned. + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + ori r2, r2, %lo(__bss_start) + + movhi r3, %hi(__bss_end) + ori r3, r3, %lo(__bss_end) + + beq r2, r3, 1f + +0: + stw zero, (r2) + addi r2, r2, 4 + bltu r2, r3, 0b + +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 3, 1, 0b, 1b + .popsection +#endif /* ALT_SIM_OPTIMIZE */ + +/* + * The alt_load() facility is normally used when there is no bootloader. + * It copies some sections into RAM so it acts like a mini-bootloader. + */ +#ifdef CALL_ALT_LOAD + +#ifdef ALT_STACK_CHECK + /* + * If the user has selected stack checking then we need to set up a safe + * value in the stack limit register so that the relocation functions + * don't think the stack has overflowed (the contents of the rwdata + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + +#endif /* CALL_ALT_LOAD */ + +#ifdef ALT_STACK_CHECK + /* + * Set up the stack limit (if required). The linker has set up the + * copy of the variable which is in memory. + */ + + ldw et, %gprel(alt_stack_limit_value)(gp) +#endif + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + + .size _start, . - _start + +/* + * Add information about the stack base if stack overflow checking is enabled. + */ +#ifdef ALT_STACK_CHECK + .globl alt_stack_limit_value + .section .sdata,"aws",@progbits + .align 2 + .type alt_stack_limit_value, @object + .size alt_stack_limit_value, 4 +alt_stack_limit_value: + .long __alt_stack_limit +#endif diff --git a/software/qsys_tutorial_lcd4_bsp/Makefile b/software/qsys_tutorial_lcd4_bsp/Makefile index 168b158..0e63d38 100644 --- a/software/qsys_tutorial_lcd4_bsp/Makefile +++ b/software/qsys_tutorial_lcd4_bsp/Makefile @@ -1,161 +1,161 @@ -#------------------------------------------------------------------------------ -# BSP MAKEFILE -# -# This makefile was automatically generated by the nios2-bsp-generate-files -# command. Its purpose is to build a custom Board Support Package (BSP) -# targeting a specific Nios II processor in an SOPC Builder-based design. -# -# To create an application or library Makefile which uses this BSP, try the -# nios2-app-generate-makefile or nios2-lib-generate-makefile commands. -#------------------------------------------------------------------------------ - -#------------------------------------------------------------------------------ -# TOOLS -#------------------------------------------------------------------------------ - -MKDIR := mkdir -p -ECHO := echo -SPACE := $(empty) $(empty) - -#------------------------------------------------------------------------------ -# The adjust-path macro -# -# If COMSPEC is defined, Make is launched from Windows through -# Cygwin. This adjust-path macro will call 'cygpath -u' on all -# paths to ensure they are readable by Make. -# -# If COMSPEC is not defined, Make is launched from *nix, and no adjustment -# is necessary -#------------------------------------------------------------------------------ - -ifndef COMSPEC -ifdef ComSpec -COMSPEC = $(ComSpec) -endif # ComSpec -endif # !COMSPEC - -ifdef COMSPEC - adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1")) - adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1")) -else - adjust-path = $(subst $(SPACE),\$(SPACE),$1) - adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1) -endif - -#------------------------------------------------------------------------------ -# DEFAULT TARGET -# -# The default target, "all", must appear before any other target in the -# Makefile. Note that extra prerequisites are added to the "all" rule later. -#------------------------------------------------------------------------------ -.PHONY: all -all: - @$(ECHO) [BSP build complete] - - -#------------------------------------------------------------------------------ -# PATHS & DIRECTORY NAMES -# -# Explicitly locate absolute path of the BSP root -#------------------------------------------------------------------------------ - -BSP_ROOT_DIR := . - -# Define absolute path to the root of the BSP. -ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd)) - -# Stash all BSP object files here -OBJ_DIR := ./obj - -NEWLIB_DIR = $(BSP_ROOT_DIR)/newlib - - -#------------------------------------------------------------------------------ -# MANAGED CONTENT -# -# All content between the lines "START MANAGED" and "END MANAGED" below is -# generated based on variables in the BSP settings file when the -# nios2-bsp-generate-files command is invoked. If you wish to persist any -# information pertaining to the build process, it is recomended that you -# utilize the BSP settings mechanism to do so. -# -# Note that most variable assignments in this section have a corresponding BSP -# setting that can be changed by using the nios2-bsp-create-settings or -# nios2-bsp-update-settings command before nios2-bsp-generate-files; if you -# want any variable set to a specific value when this Makefile is re-generated -# (to prevent hand-edits from being over-written), use the BSP settings -# facilities above. -#------------------------------------------------------------------------------ - -#START MANAGED - -# The following TYPE comment allows tools to identify the 'type' of target this -# makefile is associated with. -# TYPE: BSP_PRIVATE_MAKEFILE - -# This following VERSION comment indicates the version of the tool used to -# generate this makefile. A makefile variable is provided for VERSION as well. -# ACDS_VERSION: 13.0sp1 -ACDS_VERSION := 13.0sp1 - -# This following BUILD_NUMBER comment indicates the build number of the tool -# used to generate this makefile. -# BUILD_NUMBER: 232 - -SETTINGS_FILE := settings.bsp -SOPC_FILE := C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo - +#------------------------------------------------------------------------------ +# BSP MAKEFILE +# +# This makefile was automatically generated by the nios2-bsp-generate-files +# command. Its purpose is to build a custom Board Support Package (BSP) +# targeting a specific Nios II processor in an SOPC Builder-based design. +# +# To create an application or library Makefile which uses this BSP, try the +# nios2-app-generate-makefile or nios2-lib-generate-makefile commands. +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +MKDIR := mkdir -p +ECHO := echo +SPACE := $(empty) $(empty) + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC is defined, Make is launched from Windows through +# Cygwin. This adjust-path macro will call 'cygpath -u' on all +# paths to ensure they are readable by Make. +# +# If COMSPEC is not defined, Make is launched from *nix, and no adjustment +# is necessary +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # !COMSPEC + +ifdef COMSPEC + adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1")) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1")) +else + adjust-path = $(subst $(SPACE),\$(SPACE),$1) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1) +endif + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +# +# The default target, "all", must appear before any other target in the +# Makefile. Note that extra prerequisites are added to the "all" rule later. +#------------------------------------------------------------------------------ +.PHONY: all +all: + @$(ECHO) [BSP build complete] + + +#------------------------------------------------------------------------------ +# PATHS & DIRECTORY NAMES +# +# Explicitly locate absolute path of the BSP root +#------------------------------------------------------------------------------ + +BSP_ROOT_DIR := . + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd)) + +# Stash all BSP object files here +OBJ_DIR := ./obj + +NEWLIB_DIR = $(BSP_ROOT_DIR)/newlib + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +# +# Note that most variable assignments in this section have a corresponding BSP +# setting that can be changed by using the nios2-bsp-create-settings or +# nios2-bsp-update-settings command before nios2-bsp-generate-files; if you +# want any variable set to a specific value when this Makefile is re-generated +# (to prevent hand-edits from being over-written), use the BSP settings +# facilities above. +#------------------------------------------------------------------------------ + +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PRIVATE_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +SETTINGS_FILE := settings.bsp +SOPC_FILE := C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + #------------------------------------------------------------------------------- # TOOL & COMMAND DEFINITIONS # # The base command for each build operation are expressed here. Additional # switches may be expressed here. They will run for all instances of the # utility. -#------------------------------------------------------------------------------- - -# Archiver command. Creates library files. -AR = nios2-elf-ar - -# Assembler command. Note that CC is used for .S files. -AS = nios2-elf-gcc - -# Custom flags only passed to the archiver. This content of this variable is -# directly passed to the archiver rather than the more standard "ARFLAGS". The -# reason for this is that GNU Make assumes some default content in ARFLAGS. -# This setting defines the value of BSP_ARFLAGS in Makefile. -BSP_ARFLAGS = -src - -# Custom flags only passed to the assembler. This setting defines the value of -# BSP_ASFLAGS in Makefile. -BSP_ASFLAGS = -Wa,-gdwarf2 - -# C/C++ compiler debug level. '-g' provides the default set of debug symbols -# typically required to debug a typical application. Omitting '-g' removes -# debug symbols from the ELF. This setting defines the value of -# BSP_CFLAGS_DEBUG in Makefile. -BSP_CFLAGS_DEBUG = -g - -# C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" -# optimization, etc. "-O0" is recommended for code that you want to debug since -# compiler optimization can remove variables and produce non-sequential -# execution of code while debugging. This setting defines the value of -# BSP_CFLAGS_OPTIMIZATION in Makefile. -BSP_CFLAGS_OPTIMIZATION = -O0 - -# C/C++ compiler warning level. "-Wall" is commonly used.This setting defines -# the value of BSP_CFLAGS_WARNINGS in Makefile. -BSP_CFLAGS_WARNINGS = -Wall - -# C compiler command. -CC = nios2-elf-gcc -xc - -# C++ compiler command. -CXX = nios2-elf-gcc -xc++ - -# Command used to remove files during 'clean' target. -RM = rm -f - - +#------------------------------------------------------------------------------- + +# Archiver command. Creates library files. +AR = nios2-elf-ar + +# Assembler command. Note that CC is used for .S files. +AS = nios2-elf-gcc + +# Custom flags only passed to the archiver. This content of this variable is +# directly passed to the archiver rather than the more standard "ARFLAGS". The +# reason for this is that GNU Make assumes some default content in ARFLAGS. +# This setting defines the value of BSP_ARFLAGS in Makefile. +BSP_ARFLAGS = -src + +# Custom flags only passed to the assembler. This setting defines the value of +# BSP_ASFLAGS in Makefile. +BSP_ASFLAGS = -Wa,-gdwarf2 + +# C/C++ compiler debug level. '-g' provides the default set of debug symbols +# typically required to debug a typical application. Omitting '-g' removes +# debug symbols from the ELF. This setting defines the value of +# BSP_CFLAGS_DEBUG in Makefile. +BSP_CFLAGS_DEBUG = -g + +# C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" +# optimization, etc. "-O0" is recommended for code that you want to debug since +# compiler optimization can remove variables and produce non-sequential +# execution of code while debugging. This setting defines the value of +# BSP_CFLAGS_OPTIMIZATION in Makefile. +BSP_CFLAGS_OPTIMIZATION = -O0 + +# C/C++ compiler warning level. "-Wall" is commonly used.This setting defines +# the value of BSP_CFLAGS_WARNINGS in Makefile. +BSP_CFLAGS_WARNINGS = -Wall + +# C compiler command. +CC = nios2-elf-gcc -xc + +# C++ compiler command. +CXX = nios2-elf-gcc -xc++ + +# Command used to remove files during 'clean' target. +RM = rm -f + + #------------------------------------------------------------------------------- # BUILD PRE & POST PROCESS COMMANDS # @@ -170,9 +170,9 @@ # You can view each pre/post-process command in the "Build Rules: All & # Clean", "Pattern Rules to Build Objects", and "Library Rules" sections of # this Makefile. -#------------------------------------------------------------------------------- - - +#------------------------------------------------------------------------------- + + #------------------------------------------------------------------------------- # BSP SOURCE BUILD SETTINGS (FLAG GENERATION) # @@ -189,13 +189,13 @@ # # Unless indicated otherwise, multiple entries in each variable should be # space-separated. -#------------------------------------------------------------------------------- - -# Altera HAL alt_sys_init.c generated source file -GENERATED_C_FILES := $(ABS_BSP_ROOT)/alt_sys_init.c -GENERATED_C_LIB_SRCS += alt_sys_init.c - - +#------------------------------------------------------------------------------- + +# Altera HAL alt_sys_init.c generated source file +GENERATED_C_FILES := $(ABS_BSP_ROOT)/alt_sys_init.c +GENERATED_C_LIB_SRCS += alt_sys_init.c + + #------------------------------------------------------------------------------- # BSP SOURCE FILE LISTING # @@ -208,568 +208,568 @@ # each source file type (C, assembly, etc.) is concatenated together and used # to construct a list of objects. Pattern rules to build each object are then # used to build each file. -#------------------------------------------------------------------------------- - -# altera_avalon_jtag_uart_driver sources root -altera_avalon_jtag_uart_driver_SRCS_ROOT := drivers - -# altera_avalon_jtag_uart_driver sources -altera_avalon_jtag_uart_driver_C_LIB_SRCS := \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_init.c \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_read.c \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_write.c \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_ioctl.c \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_fd.c - -# altera_avalon_lcd_16207_driver sources root -altera_avalon_lcd_16207_driver_SRCS_ROOT := drivers - -# altera_avalon_lcd_16207_driver sources -altera_avalon_lcd_16207_driver_C_LIB_SRCS := \ - $(altera_avalon_lcd_16207_driver_SRCS_ROOT)/src/altera_avalon_lcd_16207.c \ - $(altera_avalon_lcd_16207_driver_SRCS_ROOT)/src/altera_avalon_lcd_16207_fd.c - -# altera_avalon_pio_driver sources root -altera_avalon_pio_driver_SRCS_ROOT := drivers - -# altera_avalon_pio_driver sources -# altera_nios2_qsys_hal_driver sources root -altera_nios2_qsys_hal_driver_SRCS_ROOT := HAL - -# altera_nios2_qsys_hal_driver sources -altera_nios2_qsys_hal_driver_C_LIB_SRCS := \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/altera_nios2_qsys_irq.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_usleep.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_busy_sleep.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_vars.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_icache_flush.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_icache_flush_all.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush_all.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush_no_writeback.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_instruction_exception_entry.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_register.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_iic.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_remap_cached.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_remap_uncached.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_uncached_free.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_uncached_malloc.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_do_ctors.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_do_dtors.c \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_gmon.c - -altera_nios2_qsys_hal_driver_ASM_LIB_SRCS := \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_entry.S \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_trap.S \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_muldiv.S \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_entry.S \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_software_exception.S \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_mcount.S \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_log_macro.S \ - $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/crt0.S - -# hal sources root -hal_SRCS_ROOT := HAL - -# hal sources -hal_C_LIB_SRCS := \ - $(hal_SRCS_ROOT)/src/alt_alarm_start.c \ - $(hal_SRCS_ROOT)/src/alt_close.c \ - $(hal_SRCS_ROOT)/src/alt_dev.c \ - $(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \ - $(hal_SRCS_ROOT)/src/alt_dma_rxchan_open.c \ - $(hal_SRCS_ROOT)/src/alt_dma_txchan_open.c \ - $(hal_SRCS_ROOT)/src/alt_environ.c \ - $(hal_SRCS_ROOT)/src/alt_env_lock.c \ - $(hal_SRCS_ROOT)/src/alt_errno.c \ - $(hal_SRCS_ROOT)/src/alt_execve.c \ - $(hal_SRCS_ROOT)/src/alt_exit.c \ - $(hal_SRCS_ROOT)/src/alt_fcntl.c \ - $(hal_SRCS_ROOT)/src/alt_fd_lock.c \ - $(hal_SRCS_ROOT)/src/alt_fd_unlock.c \ - $(hal_SRCS_ROOT)/src/alt_find_dev.c \ - $(hal_SRCS_ROOT)/src/alt_find_file.c \ - $(hal_SRCS_ROOT)/src/alt_flash_dev.c \ - $(hal_SRCS_ROOT)/src/alt_fork.c \ - $(hal_SRCS_ROOT)/src/alt_fs_reg.c \ - $(hal_SRCS_ROOT)/src/alt_fstat.c \ - $(hal_SRCS_ROOT)/src/alt_get_fd.c \ - $(hal_SRCS_ROOT)/src/alt_getchar.c \ - $(hal_SRCS_ROOT)/src/alt_getpid.c \ - $(hal_SRCS_ROOT)/src/alt_gettod.c \ - $(hal_SRCS_ROOT)/src/alt_iic_isr_register.c \ - $(hal_SRCS_ROOT)/src/alt_instruction_exception_register.c \ - $(hal_SRCS_ROOT)/src/alt_ioctl.c \ - $(hal_SRCS_ROOT)/src/alt_io_redirect.c \ - $(hal_SRCS_ROOT)/src/alt_irq_handler.c \ - $(hal_SRCS_ROOT)/src/alt_isatty.c \ - $(hal_SRCS_ROOT)/src/alt_kill.c \ - $(hal_SRCS_ROOT)/src/alt_link.c \ - $(hal_SRCS_ROOT)/src/alt_load.c \ - $(hal_SRCS_ROOT)/src/alt_log_printf.c \ - $(hal_SRCS_ROOT)/src/alt_lseek.c \ - $(hal_SRCS_ROOT)/src/alt_main.c \ - $(hal_SRCS_ROOT)/src/alt_malloc_lock.c \ - $(hal_SRCS_ROOT)/src/alt_open.c \ - $(hal_SRCS_ROOT)/src/alt_printf.c \ - $(hal_SRCS_ROOT)/src/alt_putchar.c \ - $(hal_SRCS_ROOT)/src/alt_putstr.c \ - $(hal_SRCS_ROOT)/src/alt_read.c \ - $(hal_SRCS_ROOT)/src/alt_release_fd.c \ - $(hal_SRCS_ROOT)/src/alt_rename.c \ - $(hal_SRCS_ROOT)/src/alt_sbrk.c \ - $(hal_SRCS_ROOT)/src/alt_settod.c \ - $(hal_SRCS_ROOT)/src/alt_stat.c \ - $(hal_SRCS_ROOT)/src/alt_tick.c \ - $(hal_SRCS_ROOT)/src/alt_times.c \ - $(hal_SRCS_ROOT)/src/alt_unlink.c \ - $(hal_SRCS_ROOT)/src/alt_wait.c \ - $(hal_SRCS_ROOT)/src/alt_write.c - - -# Assemble all component C source files -COMPONENT_C_LIB_SRCS += \ - $(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \ - $(altera_avalon_lcd_16207_driver_C_LIB_SRCS) \ - $(altera_nios2_qsys_hal_driver_C_LIB_SRCS) \ - $(hal_C_LIB_SRCS) - -# Assemble all component assembly source files -COMPONENT_ASM_LIB_SRCS += \ - $(altera_nios2_qsys_hal_driver_ASM_LIB_SRCS) - -# Assemble all component C++ source files -COMPONENT_CPP_LIB_SRCS += \ - -#END MANAGED - -#------------------------------------------------------------------------------ -# PUBLIC.MK -# -# The generated public.mk file contains BSP information that is shared with -# other external makefiles, such as a Nios II application makefile. System- -# dependent information such as hardware-specific compiler flags and -# simulation file generation are stored here. -# -# In addition, public.mk contains include paths that various software, -# such as a device driver, may need for the C compiler. These paths are -# written to public.mk with respect to the BSP root. In public.mk, each -# path is prefixed with a special variable, $(ALT_LIBRARY_ROOT_DIR). The -# purpose of this variable is to allow an external Makefile to append on -# path information to precisely locate paths expressed in public.mk -# Since this is the BSP Makefile, we set ALT_LIBRARY_ROOT_DIR to point right -# here ("."), at the BSP root. -# -# ALT_LIBRARY_ROOT_DIR must always be set before public.mk is included. -#------------------------------------------------------------------------------ -ALT_LIBRARY_ROOT_DIR := . -include public.mk - - -#------------------------------------------------------------------------------ -# FLAGS -# -# Include paths for BSP files are written into the public.mk file and must -# be added to the existing list of pre-processor flags. In addition, "hooks" -# for standard flags left intentionally empty (CFLAGS, CPPFLAGS, ASFLAGS, -# and CXXFLAGS) are provided for conveniently adding to the relevant flags -# on the command-line or via script that calls make. -#------------------------------------------------------------------------------ -# Assemble final list of compiler flags from generated content -BSP_CFLAGS += \ - $(BSP_CFLAGS_DEFINED_SYMBOLS) \ - $(BSP_CFLAGS_UNDEFINED_SYMBOLS) \ - $(BSP_CFLAGS_OPTIMIZATION) \ - $(BSP_CFLAGS_DEBUG) \ - $(BSP_CFLAGS_WARNINGS) \ - $(BSP_CFLAGS_USER_FLAGS) \ - $(ALT_CFLAGS) \ - $(CFLAGS) - -# Make ready the final list of include directories and other C pre-processor -# flags. Each include path is made ready by prefixing it with "-I". -BSP_CPPFLAGS += \ - $(addprefix -I, $(BSP_INC_DIRS)) \ - $(addprefix -I, $(ALT_INCLUDE_DIRS)) \ - $(ALT_CPPFLAGS) \ - $(CPPFLAGS) - -# Finish off assembler flags with any user-provided flags -BSP_ASFLAGS += $(ASFLAGS) - -# Finish off C++ flags with any user-provided flags -BSP_CXXFLAGS += $(CXXFLAGS) - -# And finally, the ordered list -C_SRCS += $(GENERATED_C_LIB_SRCS) \ - $(COMPONENT_C_LIB_SRCS) - -CXX_SRCS += $(GENERATED_CPP_LIB_SRCS) \ - $(COMPONENT_CPP_LIB_SRCS) - -ASM_SRCS += $(GENERATED_ASM_LIB_SRCS) \ - $(COMPONENT_ASM_LIB_SRCS) - - -#------------------------------------------------------------------------------ -# LIST OF GENERATED FILES -# -# A Nios II BSP relies on the generation of several source files used -# by both the BSP and any applications referencing the BSP. -#------------------------------------------------------------------------------ - - -GENERATED_H_FILES := $(ABS_BSP_ROOT)/system.h - -GENERATED_LINKER_SCRIPT := $(ABS_BSP_ROOT)/linker.x - -GENERATED_FILES += $(GENERATED_H_FILES) \ - $(GENERATED_LINKER_SCRIPT) - - -#------------------------------------------------------------------------------ -# SETUP TO BUILD OBJECTS -# -# List of object files which are to be built. This is constructed from the input -# list of C source files (C_SRCS), C++ source files (CXX_SRCS), and assembler -# source file (ASM_SRCS). The permitted file extensions are: -# -# .c .C - for C files -# .cxx .cc .cpp .CXX .CC .CPP - for C++ files -# .S .s - for assembly files -# -# Extended description: The list of objects is a sorted list (duplicates -# removed) of all possible objects, placed beneath the ./obj directory, -# including any path information stored in the "*_SRCS" variable. The -# "patsubst" commands are used to concatenate together multiple file suffix -# types for common files (i.e. c++ as .cxx, .cc, .cpp). -# -# File extensions are case-insensitive in build rules with the exception of -# assembly sources. Nios II assembly sources with the ".S" extension are first -# run through the C preprocessor. Sources with the ".s" extension are not. -#------------------------------------------------------------------------------ -OBJS = $(sort $(addprefix $(OBJ_DIR)/, \ - $(patsubst %.c, %.o, $(patsubst %.C, %.o, $(C_SRCS))) \ - $(patsubst %.cxx, %.o, $(patsubst %.CXX, %.o, \ - $(patsubst %.cc, %.o, $(patsubst %.CC, %.o, \ - $(patsubst %.cpp, %.o, $(patsubst %.CPP, %.o, \ - $(CXX_SRCS) )))))) \ - $(patsubst %.S, %.o, $(patsubst %.s, %.o, $(ASM_SRCS))) )) - -# List of dependancy files for each object file. -DEPS = $(OBJS:.o=.d) - - -# Rules to force your project to rebuild or relink -# .force_relink file will cause any application that depends on this project to relink -# .force_rebuild file will cause this project to rebuild object files -# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files - -FORCE_RELINK_DEP := .force_relink -FORCE_REBUILD_DEP := .force_rebuild -FORCE_REBUILD_ALL_DEP := .force_rebuild_all -FORCE_REBUILD_DEP_LIST := $(FORCE_RELINK_DEP) $(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) - -$(FORCE_REBUILD_DEP_LIST): - -$(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP)) - - -#------------------------------------------------------------------------------ -# BUILD RULES: ALL & CLEAN -#------------------------------------------------------------------------------ -.DELETE_ON_ERROR: - -.PHONY: all -all: build_pre_process -all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR) -all: build_post_process - - -# clean: remove .o/.a/.d -.PHONY: clean -clean: - @$(RM) -r $(BSP_LIB) $(OBJ_DIR) $(FORCE_REBUILD_DEP_LIST) -ifneq ($(wildcard $(NEWLIB_DIR)),) - @$(RM) -r $(NEWLIB_DIR) -endif - @$(ECHO) [BSP clean complete] - - -#------------------------------------------------------------------------------ -# BUILD PRE/POST PROCESS -#------------------------------------------------------------------------------ -build_pre_process : - $(BUILD_PRE_PROCESS) - -build_post_process : - $(BUILD_POST_PROCESS) - -.PHONY: build_pre_process build_post_process - - - -#------------------------------------------------------------------------------ -# MAKEFILE UP TO DATE? -# -# Is this very Makefile up to date? Someone may have changed the BSP settings -# file or the associated target hardware. -#------------------------------------------------------------------------------ -# Skip this check when clean is the only target -ifneq ($(MAKECMDGOALS),clean) - -ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE)) -$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.) -endif - -Makefile: $(wildcard $(SETTINGS_FILE)) - @$(ECHO) Makefile not up to date. - @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated. - @$(ECHO) - @$(ECHO) Generate the BSP to update the Makefile, and then build again. - @$(ECHO) - @$(ECHO) To generate from Eclipse: - @$(ECHO) " 1. Right-click the BSP project." - @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." - @$(ECHO) - @$(ECHO) To generate from the command line: - @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" - @$(ECHO) - @exit 1 - -ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE)) -$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) -endif - -public.mk: $(wildcard $(SOPC_FILE)) - @$(ECHO) Makefile not up to date. - @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated. - @$(ECHO) - @$(ECHO) Generate the BSP to update the Makefile, and then build again. - @$(ECHO) - @$(ECHO) To generate from Eclipse: - @$(ECHO) " 1. Right-click the BSP project." - @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." - @$(ECHO) - @$(ECHO) To generate from the command line: - @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" - @$(ECHO) - @exit 1 - -endif # $(MAKECMDGOALS) != clean - -#------------------------------------------------------------------------------ -# PATTERN RULES TO BUILD OBJECTS -#------------------------------------------------------------------------------ -$(OBJ_DIR)/%.o: %.c - @$(ECHO) Compiling $( --bsp-dir=" + @$(ECHO) + @exit 1 + +ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE)) +$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) +endif + +public.mk: $(wildcard $(SOPC_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +endif # $(MAKECMDGOALS) != clean + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ +$(OBJ_DIR)/%.o: %.c + @$(ECHO) Compiling $( - -#include "sys/alt_alarm.h" -#include "sys/alt_warning.h" - -#include "os/alt_sem.h" -#include "os/alt_flag.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * If the user wants all drivers to be small rather than fast then make sure - * this one is marked as needing to be small. - */ -#if defined ALT_USE_SMALL_DRIVERS && !defined ALTERA_AVALON_JTAG_UART_SMALL -#define ALTERA_AVALON_JTAG_UART_SMALL -#endif - -/* - * If the user wants to ignore FIFO full error after timeout - */ -#if defined ALT_JTAG_UART_IGNORE_FIFO_FULL_ERROR && !defined ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR -#define ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR -#endif - -/* - * Constants that can be overriden. - */ -#ifndef ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT -#define ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT 10 -#endif - -#ifndef ALTERA_AVALON_JTAG_UART_BUF_LEN -#define ALTERA_AVALON_JTAG_UART_BUF_LEN 2048 -#endif - -/* - * ALT_JTAG_UART_READ_RDY and ALT_JTAG_UART_WRITE_RDY are the bitmasks - * that define uC/OS-II event flags that are releated to this device. - * - * ALT_JTAG_UART_READ_RDY indicates that there is read data in the buffer - * ready to be processed. ALT_JTAG_UART_WRITE_RDY indicates that the transmitter is - * ready for more data. - */ -#define ALT_JTAG_UART_READ_RDY 0x1 -#define ALT_JTAG_UART_WRITE_RDY 0x2 -#define ALT_JTAG_UART_TIMEOUT 0x4 - -/* - * State structure definition. Each instance of the driver uses one - * of these structures to hold its associated state. - */ - -typedef struct altera_avalon_jtag_uart_state_s -{ - unsigned int base; - -#ifndef ALTERA_AVALON_JTAG_UART_SMALL - - unsigned int timeout; /* Timeout until host is assumed inactive */ - alt_alarm alarm; - unsigned int irq_enable; - unsigned int host_inactive; - - ALT_SEM (read_lock) - ALT_SEM (write_lock) - ALT_FLAG_GRP (events) - - /* The variables below are volatile because they are modified by the - * interrupt routine. Making them volatile and reading them atomically - * means that we don't need any large critical sections. - */ - volatile unsigned int rx_in; - unsigned int rx_out; - unsigned int tx_in; - volatile unsigned int tx_out; - char rx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; - char tx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; - -#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ - -} altera_avalon_jtag_uart_state; - -/* - * Macros used by alt_sys_init when the ALT file descriptor facility isn't used. - */ - -#ifdef ALTERA_AVALON_JTAG_UART_SMALL - -#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ - altera_avalon_jtag_uart_state state = \ - { \ - name##_BASE, \ - } - -#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) - -#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ - -#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ - altera_avalon_jtag_uart_state state = \ - { \ - name##_BASE, \ - ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ - } - -/* - * Externally referenced routines - */ -extern void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, - int irq_controller_id, int irq); - -#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) \ - { \ - if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ - { \ - ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". " \ - "You have selected the interrupt driven version of " \ - "the ALTERA Avalon JTAG UART driver, but the " \ - "interrupt is not connected for this device. You can " \ - "select a polled mode driver by checking the 'small " \ - "driver' option in the HAL configuration window, or " \ - "by using the -DALTERA_AVALON_JTAG_UART_SMALL " \ - "preprocessor flag."); \ - } \ - else \ - altera_avalon_jtag_uart_init(&state, \ - name##_IRQ_INTERRUPT_CONTROLLER_ID, \ - name##_IRQ); \ - } - -#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ - -/* - * Include in case non-direct version of driver required. - */ -#include "altera_avalon_jtag_uart_fd.h" - -/* - * Map alt_sys_init macros to direct or non-direct versions. - */ -#ifdef ALT_USE_DIRECT_DRIVERS - -#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, state) \ - ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) -#define ALTERA_AVALON_JTAG_UART_INIT(name, state) \ - ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, dev) \ - ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, dev) -#define ALTERA_AVALON_JTAG_UART_INIT(name, dev) \ - ALTERA_AVALON_JTAG_UART_DEV_INIT(name, dev) - -#endif /* ALT_USE_DIRECT_DRIVERS */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_AVALON_JTAG_UART_H__ */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_JTAG_UART_H__ +#define __ALT_AVALON_JTAG_UART_H__ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_warning.h" + +#include "os/alt_sem.h" +#include "os/alt_flag.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * If the user wants all drivers to be small rather than fast then make sure + * this one is marked as needing to be small. + */ +#if defined ALT_USE_SMALL_DRIVERS && !defined ALTERA_AVALON_JTAG_UART_SMALL +#define ALTERA_AVALON_JTAG_UART_SMALL +#endif + +/* + * If the user wants to ignore FIFO full error after timeout + */ +#if defined ALT_JTAG_UART_IGNORE_FIFO_FULL_ERROR && !defined ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR +#define ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR +#endif + +/* + * Constants that can be overriden. + */ +#ifndef ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT +#define ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT 10 +#endif + +#ifndef ALTERA_AVALON_JTAG_UART_BUF_LEN +#define ALTERA_AVALON_JTAG_UART_BUF_LEN 2048 +#endif + +/* + * ALT_JTAG_UART_READ_RDY and ALT_JTAG_UART_WRITE_RDY are the bitmasks + * that define uC/OS-II event flags that are releated to this device. + * + * ALT_JTAG_UART_READ_RDY indicates that there is read data in the buffer + * ready to be processed. ALT_JTAG_UART_WRITE_RDY indicates that the transmitter is + * ready for more data. + */ +#define ALT_JTAG_UART_READ_RDY 0x1 +#define ALT_JTAG_UART_WRITE_RDY 0x2 +#define ALT_JTAG_UART_TIMEOUT 0x4 + +/* + * State structure definition. Each instance of the driver uses one + * of these structures to hold its associated state. + */ + +typedef struct altera_avalon_jtag_uart_state_s +{ + unsigned int base; + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + + unsigned int timeout; /* Timeout until host is assumed inactive */ + alt_alarm alarm; + unsigned int irq_enable; + unsigned int host_inactive; + + ALT_SEM (read_lock) + ALT_SEM (write_lock) + ALT_FLAG_GRP (events) + + /* The variables below are volatile because they are modified by the + * interrupt routine. Making them volatile and reading them atomically + * means that we don't need any large critical sections. + */ + volatile unsigned int rx_in; + unsigned int rx_out; + unsigned int tx_in; + volatile unsigned int tx_out; + char rx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; + char tx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +} altera_avalon_jtag_uart_state; + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility isn't used. + */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ + altera_avalon_jtag_uart_state state = \ + { \ + name##_BASE, \ + } + +#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ + altera_avalon_jtag_uart_state state = \ + { \ + name##_BASE, \ + ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ + } + +/* + * Externally referenced routines + */ +extern void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq); + +#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) \ + { \ + if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ + { \ + ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". " \ + "You have selected the interrupt driven version of " \ + "the ALTERA Avalon JTAG UART driver, but the " \ + "interrupt is not connected for this device. You can " \ + "select a polled mode driver by checking the 'small " \ + "driver' option in the HAL configuration window, or " \ + "by using the -DALTERA_AVALON_JTAG_UART_SMALL " \ + "preprocessor flag."); \ + } \ + else \ + altera_avalon_jtag_uart_init(&state, \ + name##_IRQ_INTERRUPT_CONTROLLER_ID, \ + name##_IRQ); \ + } + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_jtag_uart_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, state) \ + ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_JTAG_UART_INIT(name, state) \ + ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, dev) \ + ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_JTAG_UART_INIT(name, dev) \ + ALTERA_AVALON_JTAG_UART_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_JTAG_UART_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h index b3c3200..183bd3f 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h +++ b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h @@ -1,125 +1,125 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#ifndef __ALT_AVALON_JTAG_UART_FD_H__ -#define __ALT_AVALON_JTAG_UART_FD_H__ - -#include "sys/alt_dev.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Externally referenced routines - */ -extern int altera_avalon_jtag_uart_read_fd (alt_fd* fd, char* ptr, int len); -extern int altera_avalon_jtag_uart_write_fd (alt_fd* fd, const char* ptr, - int len); - -/* - * Device structure definition. This is needed by alt_sys_init in order to - * reserve memory for the device instance. - */ - -typedef struct altera_avalon_jtag_uart_dev_s -{ - alt_dev dev; - altera_avalon_jtag_uart_state state; -} altera_avalon_jtag_uart_dev; - -/* - * Macros used by alt_sys_init when the ALT file descriptor facility is used. - */ - -#ifdef ALTERA_AVALON_JTAG_UART_SMALL - -#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ - static altera_avalon_jtag_uart_dev d = \ - { \ - { \ - ALT_LLIST_ENTRY, \ - name##_NAME, \ - NULL, /* open */ \ - NULL, /* close */ \ - altera_avalon_jtag_uart_read_fd, \ - altera_avalon_jtag_uart_write_fd, \ - NULL, /* lseek */ \ - NULL, /* fstat */ \ - NULL, /* ioctl */ \ - }, \ - { \ - name##_BASE, \ - } \ - } - -#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev) - -#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ - -extern int altera_avalon_jtag_uart_close_fd(alt_fd* fd); -extern int altera_avalon_jtag_uart_ioctl_fd (alt_fd* fd, int req, void* arg); - -#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ - static altera_avalon_jtag_uart_dev d = \ - { \ - { \ - ALT_LLIST_ENTRY, \ - name##_NAME, \ - NULL, /* open */ \ - altera_avalon_jtag_uart_close_fd, \ - altera_avalon_jtag_uart_read_fd, \ - altera_avalon_jtag_uart_write_fd, \ - NULL, /* lseek */ \ - NULL, /* fstat */ \ - altera_avalon_jtag_uart_ioctl_fd, \ - }, \ - { \ - name##_BASE, \ - ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ - } \ - } - -#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) \ - { \ - ALTERA_AVALON_JTAG_UART_STATE_INIT(name, d.state); \ - \ - /* make the device available to the system */ \ - alt_dev_reg(&d.dev); \ - } - -#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALT_AVALON_JTAG_UART_FD_H__ */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_JTAG_UART_FD_H__ +#define __ALT_AVALON_JTAG_UART_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_jtag_uart_read_fd (alt_fd* fd, char* ptr, int len); +extern int altera_avalon_jtag_uart_write_fd (alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ + +typedef struct altera_avalon_jtag_uart_dev_s +{ + alt_dev dev; + altera_avalon_jtag_uart_state state; +} altera_avalon_jtag_uart_dev; + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_jtag_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + altera_avalon_jtag_uart_read_fd, \ + altera_avalon_jtag_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE, \ + } \ + } + +#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev) + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +extern int altera_avalon_jtag_uart_close_fd(alt_fd* fd); +extern int altera_avalon_jtag_uart_ioctl_fd (alt_fd* fd, int req, void* arg); + +#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_jtag_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + altera_avalon_jtag_uart_close_fd, \ + altera_avalon_jtag_uart_read_fd, \ + altera_avalon_jtag_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + altera_avalon_jtag_uart_ioctl_fd, \ + }, \ + { \ + name##_BASE, \ + ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ + } \ + } + +#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_JTAG_UART_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_JTAG_UART_FD_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h index 7f97160..8fe6b80 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h +++ b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h @@ -1,73 +1,73 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#ifndef __ALTERA_AVALON_JTAG_UART_REGS_H__ -#define __ALTERA_AVALON_JTAG_UART_REGS_H__ - -#include - -#define ALTERA_AVALON_JTAG_UART_DATA_REG 0 -#define IOADDR_ALTERA_AVALON_JTAG_UART_DATA(base) \ - __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_DATA_REG) -#define IORD_ALTERA_AVALON_JTAG_UART_DATA(base) \ - IORD(base, ALTERA_AVALON_JTAG_UART_DATA_REG) -#define IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, data) \ - IOWR(base, ALTERA_AVALON_JTAG_UART_DATA_REG, data) - -#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FF) -#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0) -#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000) -#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15) -#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000) -#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16) - - -#define ALTERA_AVALON_JTAG_UART_CONTROL_REG 1 -#define IOADDR_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ - __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) -#define IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ - IORD(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) -#define IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, data) \ - IOWR(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG, data) - -#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001) -#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1) -#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100) -#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9) -#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400) -#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000) -#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16) - -#endif /* __ALTERA_AVALON_JTAG_UART_REGS_H__ */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_JTAG_UART_REGS_H__ +#define __ALTERA_AVALON_JTAG_UART_REGS_H__ + +#include + +#define ALTERA_AVALON_JTAG_UART_DATA_REG 0 +#define IOADDR_ALTERA_AVALON_JTAG_UART_DATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_DATA_REG) +#define IORD_ALTERA_AVALON_JTAG_UART_DATA(base) \ + IORD(base, ALTERA_AVALON_JTAG_UART_DATA_REG) +#define IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, data) \ + IOWR(base, ALTERA_AVALON_JTAG_UART_DATA_REG, data) + +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FF) +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16) + + +#define ALTERA_AVALON_JTAG_UART_CONTROL_REG 1 +#define IOADDR_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) +#define IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ + IORD(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) +#define IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, data) \ + IOWR(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG, data) + +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16) + +#endif /* __ALTERA_AVALON_JTAG_UART_REGS_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207.h b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207.h index 2024b9a..526ef17 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207.h +++ b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207.h @@ -1,158 +1,158 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#ifndef __ALTERA_AVALON_LCD_16207_H__ -#define __ALTERA_AVALON_LCD_16207_H__ - -#include - -#include "sys/alt_alarm.h" -#include "os/alt_sem.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * The altera_avalon_lcd_16207_dev structure is used to hold device specific - * data. This includes the transmit and receive buffers. - * - * An instance of this structure is created in the auto-generated - * alt_sys_init.c file for each UART listed in the systems PTF file. This is - * done using the ALTERA_AVALON_LCD_16207_STATE_INSTANCE macro given below. - */ - -#define ALT_LCD_HEIGHT 2 -#define ALT_LCD_WIDTH 16 -#define ALT_LCD_VIRTUAL_WIDTH 80 - -typedef struct altera_avalon_lcd_16207_state_s -{ - int base; - - alt_alarm alarm; - int period; - - char broken; - - unsigned char x; - unsigned char y; - char address; - char esccount; - - char scrollpos; - char scrollmax; - char active; /* If non-zero then the foreground routines are - * active so the timer call must not update the - * display. */ - - char escape[8]; - - struct - { - char visible[ALT_LCD_WIDTH]; - char data[ALT_LCD_VIRTUAL_WIDTH+1]; - char width; - unsigned char speed; - - } line[ALT_LCD_HEIGHT]; - - ALT_SEM (write_lock)/* Semaphore used to control access to the - * write buffer in multi-threaded mode */ -} altera_avalon_lcd_16207_state; - -/* - * Called by alt_sys_init.c to initialize the driver. - */ -extern void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp); - -/* - * The LCD panel driver is not trivial, so leave it out in the small - * drivers case. Also leave it out in simulation because there is no - * simulated hardware for the LCD panel. These two can be overridden - * by defining ALT_USE_LCE_16207 if you really want it. - */ - -#if (!defined(ALT_USE_SMALL_DRIVERS) && !defined(ALT_SIM_OPTIMIZE)) || defined ALT_USE_LCD_16207 - -/* - * Used by the auto-generated file - * alt_sys_init.c to create an instance of this device driver. - */ -#define ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) \ - altera_avalon_lcd_16207_state state = \ - { \ - name##_BASE \ - } - -/* - * The macro ALTERA_AVALON_LCD_16207_INIT is used by the auto-generated file - * alt_sys_init.c to initialize an instance of the device driver. - */ -#define ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) \ - altera_avalon_lcd_16207_init(&state) - -#else /* exclude driver */ - -#define ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) extern int alt_no_storage -#define ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) while (0) - -#endif /* exclude driver */ - -/* - * Include in case non-direct version of driver required. - */ -#include "altera_avalon_lcd_16207_fd.h" - -/* - * Map alt_sys_init macros to direct or non-direct versions. - */ -#ifdef ALT_USE_DIRECT_DRIVERS - -#define ALTERA_AVALON_LCD_16207_INSTANCE(name, state) \ - ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) -#define ALTERA_AVALON_LCD_16207_INIT(name, state) \ - ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -#define ALTERA_AVALON_LCD_16207_INSTANCE(name, dev) \ - ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, dev) -#define ALTERA_AVALON_LCD_16207_INIT(name, dev) \ - ALTERA_AVALON_LCD_16207_DEV_INIT(name, dev) - -#endif /* ALT_USE_DIRECT_DRIVERS */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALTERA_AVALON_LCD_16207_H__ */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_H__ +#define __ALTERA_AVALON_LCD_16207_H__ + +#include + +#include "sys/alt_alarm.h" +#include "os/alt_sem.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The altera_avalon_lcd_16207_dev structure is used to hold device specific + * data. This includes the transmit and receive buffers. + * + * An instance of this structure is created in the auto-generated + * alt_sys_init.c file for each UART listed in the systems PTF file. This is + * done using the ALTERA_AVALON_LCD_16207_STATE_INSTANCE macro given below. + */ + +#define ALT_LCD_HEIGHT 2 +#define ALT_LCD_WIDTH 16 +#define ALT_LCD_VIRTUAL_WIDTH 80 + +typedef struct altera_avalon_lcd_16207_state_s +{ + int base; + + alt_alarm alarm; + int period; + + char broken; + + unsigned char x; + unsigned char y; + char address; + char esccount; + + char scrollpos; + char scrollmax; + char active; /* If non-zero then the foreground routines are + * active so the timer call must not update the + * display. */ + + char escape[8]; + + struct + { + char visible[ALT_LCD_WIDTH]; + char data[ALT_LCD_VIRTUAL_WIDTH+1]; + char width; + unsigned char speed; + + } line[ALT_LCD_HEIGHT]; + + ALT_SEM (write_lock)/* Semaphore used to control access to the + * write buffer in multi-threaded mode */ +} altera_avalon_lcd_16207_state; + +/* + * Called by alt_sys_init.c to initialize the driver. + */ +extern void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp); + +/* + * The LCD panel driver is not trivial, so leave it out in the small + * drivers case. Also leave it out in simulation because there is no + * simulated hardware for the LCD panel. These two can be overridden + * by defining ALT_USE_LCE_16207 if you really want it. + */ + +#if (!defined(ALT_USE_SMALL_DRIVERS) && !defined(ALT_SIM_OPTIMIZE)) || defined ALT_USE_LCD_16207 + +/* + * Used by the auto-generated file + * alt_sys_init.c to create an instance of this device driver. + */ +#define ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) \ + altera_avalon_lcd_16207_state state = \ + { \ + name##_BASE \ + } + +/* + * The macro ALTERA_AVALON_LCD_16207_INIT is used by the auto-generated file + * alt_sys_init.c to initialize an instance of the device driver. + */ +#define ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) \ + altera_avalon_lcd_16207_init(&state) + +#else /* exclude driver */ + +#define ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) extern int alt_no_storage +#define ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) while (0) + +#endif /* exclude driver */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_lcd_16207_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_LCD_16207_INSTANCE(name, state) \ + ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_LCD_16207_INIT(name, state) \ + ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_LCD_16207_INSTANCE(name, dev) \ + ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_LCD_16207_INIT(name, dev) \ + ALTERA_AVALON_LCD_16207_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_AVALON_LCD_16207_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h index 370927b..88436c0 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h +++ b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h @@ -1,108 +1,108 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#ifndef __ALTERA_AVALON_LCD_16207_FD_H__ -#define __ALTERA_AVALON_LCD_16207_FD_H__ - -#include "sys/alt_dev.h" - -#ifdef __cplusplus -extern "C" -{ -#endif /* __cplusplus */ - -/* - * Externally referenced routines - */ -extern int altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* ptr, - int len); - -/* - * Device structure definition. This is needed by alt_sys_init in order to - * reserve memory for the device instance. - */ - -typedef struct altera_avalon_lcd_16207_dev_s -{ - alt_dev dev; - altera_avalon_lcd_16207_state state; -} altera_avalon_lcd_16207_dev; - -/* - * The LCD panel driver is not trivial, so leave it out in the small - * drivers case. Also leave it out in simulation because there is no - * simulated hardware for the LCD panel. These two can be overridden - * by defining ALT_USE_LCE_16207 if you really want it. - */ - -#if (!defined(ALT_USE_SMALL_DRIVERS) && !defined(ALT_SIM_OPTIMIZE)) || defined ALT_USE_LCD_16207 - -/* - * Macros used by alt_sys_init when the ALT file descriptor facility is used. - */ -#define ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, d) \ - static altera_avalon_lcd_16207_dev d = \ - { \ - { \ - ALT_LLIST_ENTRY, \ - name##_NAME, \ - NULL, /* open */ \ - NULL, /* close */ \ - NULL, /* read */ \ - altera_avalon_lcd_16207_write_fd, \ - NULL, /* lseek */ \ - NULL, /* fstat */ \ - NULL, /* ioctl */ \ - }, \ - { \ - name##_BASE \ - }, \ - } - -#define ALTERA_AVALON_LCD_16207_DEV_INIT(name, d) \ - { \ - ALTERA_AVALON_LCD_16207_STATE_INIT(name, d.state); \ - \ - /* make the device available to the system */ \ - alt_dev_reg(&d.dev); \ - } - -#else /* exclude driver */ - -#define ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, d) extern int alt_no_storage -#define ALTERA_AVALON_LCD_16207_DEV_INIT(name, d) while (0) - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ALTERA_AVALON_LCD_16207_FD_H__ */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_FD_H__ +#define __ALTERA_AVALON_LCD_16207_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ + +typedef struct altera_avalon_lcd_16207_dev_s +{ + alt_dev dev; + altera_avalon_lcd_16207_state state; +} altera_avalon_lcd_16207_dev; + +/* + * The LCD panel driver is not trivial, so leave it out in the small + * drivers case. Also leave it out in simulation because there is no + * simulated hardware for the LCD panel. These two can be overridden + * by defining ALT_USE_LCE_16207 if you really want it. + */ + +#if (!defined(ALT_USE_SMALL_DRIVERS) && !defined(ALT_SIM_OPTIMIZE)) || defined ALT_USE_LCD_16207 + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ +#define ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, d) \ + static altera_avalon_lcd_16207_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + NULL, /* read */ \ + altera_avalon_lcd_16207_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE \ + }, \ + } + +#define ALTERA_AVALON_LCD_16207_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_LCD_16207_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#else /* exclude driver */ + +#define ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, d) extern int alt_no_storage +#define ALTERA_AVALON_LCD_16207_DEV_INIT(name, d) while (0) + +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_AVALON_LCD_16207_FD_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h index 79e29a6..bc35f1a 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h +++ b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h @@ -1,83 +1,83 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#ifndef __ALTERA_AVALON_LCD_16207_REGS_H__ -#define __ALTERA_AVALON_LCD_16207_REGS_H__ - -/* -/////////////////////////////////////////////////////////////////////////// -// -// ALTERA_AVALON_LCD_16207 PERIPHERAL -// -// Provides a hardware interface that allows software to -// access the two (2) internal 8-bit registers in an Optrex -// model 16207 (or equivalent) character LCD display (the kind -// shipped with the Nios Development Kit, 2 rows x 16 columns). -// -// Because the interface to the LCD module is "not quite Avalon," -// the hardware in this module ends-up mapping the module's -// two physical read-write registers into four Avalon-visible -// registers: Two read-only registers and two write-only registers. -// A picture is worth a thousand words: -// -// THE REGISTER MAP -// -// 7 6 5 4 3 2 1 0 Offset -// +-----+-----+-----+-----+-----+-----+-----+-----+ -// RS = 0 | Command Register (WRITE-Only) | 0 -// +-----+-----+-----+-----+-----+-----+-----+-----+ -// RS = 0 | Status Register (READ -Only) | 1 -// +-----+-----+-----+-----+-----+-----+-----+-----+ -// RS = 1 | Data Register (WRITE-Only) | 2 -// +-----+-----+-----+-----+-----+-----+-----+-----+ -// RS = 1 | Data Register (READ -Only) | 3 -// +-----+-----+-----+-----+-----+-----+-----+-----+ -// -/////////////////////////////////////////////////////////////////////////// -*/ - -#include - -#define IOADDR_ALTERA_AVALON_LCD_16207_COMMAND(base) __IO_CALC_ADDRESS_NATIVE(base, 0) -#define IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, data) IOWR(base, 0, data) - -#define IOADDR_ALTERA_AVALON_LCD_16207_STATUS(base) __IO_CALC_ADDRESS_NATIVE(base, 1) -#define IORD_ALTERA_AVALON_LCD_16207_STATUS(base) IORD(base, 1) - -#define ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK (0x00000080u) -#define ALTERA_AVALON_LCD_16207_STATUS_BUSY_OFST (7) - -#define IOADDR_ALTERA_AVALON_LCD_16207_DATA_WR(base) __IO_CALC_ADDRESS_NATIVE(base, 2) -#define IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data) IOWR(base, 2, data) - -#define IOADDR_ALTERA_AVALON_LCD_16207_DATA_RD(base) __IO_CALC_ADDRESS_NATIVE(base, 3) -#define IORD_ALTERA_AVALON_LCD_16207_DATA(base) IORD(base, 3) - -#endif +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_REGS_H__ +#define __ALTERA_AVALON_LCD_16207_REGS_H__ + +/* +/////////////////////////////////////////////////////////////////////////// +// +// ALTERA_AVALON_LCD_16207 PERIPHERAL +// +// Provides a hardware interface that allows software to +// access the two (2) internal 8-bit registers in an Optrex +// model 16207 (or equivalent) character LCD display (the kind +// shipped with the Nios Development Kit, 2 rows x 16 columns). +// +// Because the interface to the LCD module is "not quite Avalon," +// the hardware in this module ends-up mapping the module's +// two physical read-write registers into four Avalon-visible +// registers: Two read-only registers and two write-only registers. +// A picture is worth a thousand words: +// +// THE REGISTER MAP +// +// 7 6 5 4 3 2 1 0 Offset +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 0 | Command Register (WRITE-Only) | 0 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 0 | Status Register (READ -Only) | 1 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 1 | Data Register (WRITE-Only) | 2 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 1 | Data Register (READ -Only) | 3 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// +/////////////////////////////////////////////////////////////////////////// +*/ + +#include + +#define IOADDR_ALTERA_AVALON_LCD_16207_COMMAND(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, data) IOWR(base, 0, data) + +#define IOADDR_ALTERA_AVALON_LCD_16207_STATUS(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_LCD_16207_STATUS(base) IORD(base, 1) + +#define ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK (0x00000080u) +#define ALTERA_AVALON_LCD_16207_STATUS_BUSY_OFST (7) + +#define IOADDR_ALTERA_AVALON_LCD_16207_DATA_WR(base) __IO_CALC_ADDRESS_NATIVE(base, 2) +#define IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data) IOWR(base, 2, data) + +#define IOADDR_ALTERA_AVALON_LCD_16207_DATA_RD(base) __IO_CALC_ADDRESS_NATIVE(base, 3) +#define IORD_ALTERA_AVALON_LCD_16207_DATA(base) IORD(base, 3) + +#endif diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_pio_regs.h b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_pio_regs.h index 052439f..a829ddd 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_pio_regs.h +++ b/software/qsys_tutorial_lcd4_bsp/drivers/inc/altera_avalon_pio_regs.h @@ -1,67 +1,67 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#ifndef __ALTERA_AVALON_PIO_REGS_H__ -#define __ALTERA_AVALON_PIO_REGS_H__ - -#include - -#define IOADDR_ALTERA_AVALON_PIO_DATA(base) __IO_CALC_ADDRESS_NATIVE(base, 0) -#define IORD_ALTERA_AVALON_PIO_DATA(base) IORD(base, 0) -#define IOWR_ALTERA_AVALON_PIO_DATA(base, data) IOWR(base, 0, data) - -#define IOADDR_ALTERA_AVALON_PIO_DIRECTION(base) __IO_CALC_ADDRESS_NATIVE(base, 1) -#define IORD_ALTERA_AVALON_PIO_DIRECTION(base) IORD(base, 1) -#define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data) IOWR(base, 1, data) - -#define IOADDR_ALTERA_AVALON_PIO_IRQ_MASK(base) __IO_CALC_ADDRESS_NATIVE(base, 2) -#define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base) IORD(base, 2) -#define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data) - -#define IOADDR_ALTERA_AVALON_PIO_EDGE_CAP(base) __IO_CALC_ADDRESS_NATIVE(base, 3) -#define IORD_ALTERA_AVALON_PIO_EDGE_CAP(base) IORD(base, 3) -#define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data) IOWR(base, 3, data) - - -#define IOADDR_ALTERA_AVALON_PIO_SET_BIT(base) __IO_CALC_ADDRESS_NATIVE(base, 4) -#define IORD_ALTERA_AVALON_PIO_SET_BITS(base) IORD(base, 4) -#define IOWR_ALTERA_AVALON_PIO_SET_BITS(base, data) IOWR(base, 4, data) - -#define IOADDR_ALTERA_AVALON_PIO_CLEAR_BITS(base) __IO_CALC_ADDRESS_NATIVE(base, 5) -#define IORD_ALTERA_AVALON_PIO_CLEAR_BITS(base) IORD(base, 5) -#define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(base, data) IOWR(base, 5, data) - - - -/* Defintions for direction-register operation with bi-directional PIOs */ -#define ALTERA_AVALON_PIO_DIRECTION_INPUT 0 -#define ALTERA_AVALON_PIO_DIRECTION_OUTPUT 1 - -#endif /* __ALTERA_AVALON_PIO_REGS_H__ */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_PIO_REGS_H__ +#define __ALTERA_AVALON_PIO_REGS_H__ + +#include + +#define IOADDR_ALTERA_AVALON_PIO_DATA(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IORD_ALTERA_AVALON_PIO_DATA(base) IORD(base, 0) +#define IOWR_ALTERA_AVALON_PIO_DATA(base, data) IOWR(base, 0, data) + +#define IOADDR_ALTERA_AVALON_PIO_DIRECTION(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_PIO_DIRECTION(base) IORD(base, 1) +#define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data) IOWR(base, 1, data) + +#define IOADDR_ALTERA_AVALON_PIO_IRQ_MASK(base) __IO_CALC_ADDRESS_NATIVE(base, 2) +#define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base) IORD(base, 2) +#define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data) + +#define IOADDR_ALTERA_AVALON_PIO_EDGE_CAP(base) __IO_CALC_ADDRESS_NATIVE(base, 3) +#define IORD_ALTERA_AVALON_PIO_EDGE_CAP(base) IORD(base, 3) +#define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data) IOWR(base, 3, data) + + +#define IOADDR_ALTERA_AVALON_PIO_SET_BIT(base) __IO_CALC_ADDRESS_NATIVE(base, 4) +#define IORD_ALTERA_AVALON_PIO_SET_BITS(base) IORD(base, 4) +#define IOWR_ALTERA_AVALON_PIO_SET_BITS(base, data) IOWR(base, 4, data) + +#define IOADDR_ALTERA_AVALON_PIO_CLEAR_BITS(base) __IO_CALC_ADDRESS_NATIVE(base, 5) +#define IORD_ALTERA_AVALON_PIO_CLEAR_BITS(base) IORD(base, 5) +#define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(base, data) IOWR(base, 5, data) + + + +/* Defintions for direction-register operation with bi-directional PIOs */ +#define ALTERA_AVALON_PIO_DIRECTION_INPUT 0 +#define ALTERA_AVALON_PIO_DIRECTION_OUTPUT 1 + +#endif /* __ALTERA_AVALON_PIO_REGS_H__ */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_fd.c b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_fd.c index 53dfc3b..c2a882a 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_fd.c +++ b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_fd.c @@ -1,86 +1,86 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "alt_types.h" -#include "sys/alt_dev.h" -#include "altera_avalon_jtag_uart.h" - -extern int altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, - char* buffer, int space, int flags); -extern int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, - const char* ptr, int count, int flags); -extern int altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, - int req, void* arg); -extern int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, - int flags); - -/* ----------------------------------------------------------------------- */ -/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */ -/* - * - */ - -int -altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) -{ - altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; - - return altera_avalon_jtag_uart_read(&dev->state, buffer, space, - fd->fd_flags); -} - -int -altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) -{ - altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; - - return altera_avalon_jtag_uart_write(&dev->state, buffer, space, - fd->fd_flags); -} - -#ifndef ALTERA_AVALON_JTAG_UART_SMALL - -int -altera_avalon_jtag_uart_close_fd(alt_fd* fd) -{ - altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; - - return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); -} - -int -altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) -{ - altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; - - return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); -} - -#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_jtag_uart.h" + +extern int altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char* buffer, int space, int flags); +extern int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char* ptr, int count, int flags); +extern int altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, + int req, void* arg); +extern int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, + int flags); + +/* ----------------------------------------------------------------------- */ +/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */ +/* + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + fd->fd_flags); +} + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + fd->fd_flags); +} + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); +} + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_init.c b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_init.c index 7317bec..16376e3 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_init.c +++ b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_init.c @@ -1,256 +1,256 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include -#include -#include -#include - -#include - -#include "sys/alt_irq.h" -#include "sys/alt_alarm.h" -#include "sys/ioctl.h" -#include "alt_types.h" - -#include "altera_avalon_jtag_uart_regs.h" -#include "altera_avalon_jtag_uart.h" - -#include "sys/alt_log_printf.h" - -#ifndef ALTERA_AVALON_JTAG_UART_SMALL - -/* ----------------------------------------------------------- */ -/* ------------------------- FAST DRIVER --------------------- */ -/* ----------------------------------------------------------- */ -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT -static void altera_avalon_jtag_uart_irq(void* context); -#else -static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id); -#endif -static alt_u32 altera_avalon_jtag_uart_timeout(void* context); - -/* - * Driver initialization code. Register interrupts and start a timer - * which we can use to check whether the host is there. - * Return 1 on sucessful IRQ register and 0 on failure. - */ - -void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, - int irq_controller_id, int irq) -{ - ALT_FLAG_CREATE(&sp->events, 0); - ALT_SEM_CREATE(&sp->read_lock, 1); - ALT_SEM_CREATE(&sp->write_lock, 1); - - /* enable read interrupts at the device */ - sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; - - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); - - /* register the interrupt handler */ -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, - sp, NULL); -#else - alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); -#endif - - /* Register an alarm to go off every second to check for presence of host */ - sp->host_inactive = 0; - - if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), - &altera_avalon_jtag_uart_timeout, sp) < 0) - { - /* If we can't set the alarm then record "don't know if host present" - * and behave as though the host is present. - */ - sp->timeout = INT_MAX; - } - - /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ - ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); -} - -/* - * Interrupt routine - */ -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT -static void altera_avalon_jtag_uart_irq(void* context) -#else -static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) -#endif -{ - altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; - unsigned int base = sp->base; - - /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ - ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); - - for ( ; ; ) - { - unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); - - /* Return once nothing more to do */ - if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) - break; - - if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) - { - /* process a read irq. Start by assuming that there is data in the - * receive FIFO (otherwise why would we have been interrupted?) - */ - unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; - - for ( ; ; ) - { - /* Check whether there is space in the buffer. If not then we must not - * read any characters from the buffer as they will be lost. - */ - unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - if (next == sp->rx_out) - break; - - /* Try to remove a character from the FIFO and find out whether there - * are any more characters remaining. - */ - data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); - - if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) - break; - - sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; - sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - - /* Post an event to notify jtag_uart_read that a character has been read */ - ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); - } - - if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) - { - /* If there is still data available here then the buffer is full - * so turn off receive interrupts until some space becomes available. - */ - sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); - - /* Dummy read to ensure IRQ is cleared prior to ISR completion */ - IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); - } - } - - if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) - { - /* process a write irq */ - unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; - - while (space > 0 && sp->tx_out != sp->tx_in) - { - IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); - - sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - - /* Post an event to notify jtag_uart_write that a character has been written */ - ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); - - space--; - } - - if (space > 0) - { - /* If we don't have any more data available then turn off the TX interrupt */ - sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); - - /* Dummy read to ensure IRQ is cleared prior to ISR completion */ - IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); - } - } - } -} - -/* - * Timeout routine is called every second - */ - -static alt_u32 -altera_avalon_jtag_uart_timeout(void* context) -{ - altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; - - unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); - - if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) - { - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); - sp->host_inactive = 0; - } - else if (sp->host_inactive < INT_MAX - 2) { - sp->host_inactive++; - - if (sp->host_inactive >= sp->timeout) { - /* Post an event to indicate host is inactive (for jtag_uart_read */ - ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); - } - } - - return alt_ticks_per_second(); -} - -/* - * The close() routine is implemented to drain the JTAG UART transmit buffer - * when not in "small" mode. This routine will wait for transimt data to be - * emptied unless a timeout from host-activity occurs. If the driver flags - * have been set to non-blocking mode, this routine will exit immediately if - * any data remains. This routine should be called indirectly (i.e. though - * the C library close() routine) so that the file descriptor associated - * with the relevant stream (i.e. stdout) can be closed as well. This routine - * does not manage file descriptors. - * - * The close routine is not implemented for the small driver; instead it will - * map to null. This is because the small driver simply waits while characters - * are transmitted; there is no interrupt-serviced buffer to empty - */ -int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) -{ - /* - * Wait for all transmit data to be emptied by the JTAG UART ISR, or - * for a host-inactivity timeout, in which case transmit data will be lost - */ - while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { - if (flags & O_NONBLOCK) { - return -EWOULDBLOCK; - } - } - - return 0; -} - -#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context); +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id); +#endif +static alt_u32 altera_avalon_jtag_uart_timeout(void* context); + +/* + * Driver initialization code. Register interrupts and start a timer + * which we can use to check whether the host is there. + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + ALT_FLAG_CREATE(&sp->events, 0); + ALT_SEM_CREATE(&sp->read_lock, 1); + ALT_SEM_CREATE(&sp->write_lock, 1); + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + sp, NULL); +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + +/* + * Interrupt routine + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + unsigned int base = sp->base; + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + if (next == sp->rx_out) + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + } + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + } +} + +/* + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + sp->host_inactive = 0; + } + else if (sp->host_inactive < INT_MAX - 2) { + sp->host_inactive++; + + if (sp->host_inactive >= sp->timeout) { + /* Post an event to indicate host is inactive (for jtag_uart_read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + } + } + + return alt_ticks_per_second(); +} + +/* + * The close() routine is implemented to drain the JTAG UART transmit buffer + * when not in "small" mode. This routine will wait for transimt data to be + * emptied unless a timeout from host-activity occurs. If the driver flags + * have been set to non-blocking mode, this routine will exit immediately if + * any data remains. This routine should be called indirectly (i.e. though + * the C library close() routine) so that the file descriptor associated + * with the relevant stream (i.e. stdout) can be closed as well. This routine + * does not manage file descriptors. + * + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; +} + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c index cf71e6f..15d97a6 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c +++ b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c @@ -1,86 +1,86 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include -#include -#include -#include - -#include - -#include "sys/ioctl.h" -#include "alt_types.h" - -#include "altera_avalon_jtag_uart_regs.h" -#include "altera_avalon_jtag_uart.h" - -#include "sys/alt_log_printf.h" - -#ifndef ALTERA_AVALON_JTAG_UART_SMALL - -/* ----------------------------------------------------------- */ -/* ------------------------- FAST DRIVER --------------------- */ -/* ----------------------------------------------------------- */ - -int -altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, - void* arg) -{ - int rc = -ENOTTY; - - switch (req) - { - case TIOCSTIMEOUT: - /* Set the time to wait until assuming host is not connected */ - if (sp->timeout != INT_MAX) - { - int timeout = *((int *)arg); - sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; - rc = 0; - } - break; - - case TIOCGCONNECTED: - /* Find out whether host is connected */ - if (sp->timeout != INT_MAX) - { - *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; - rc = 0; - } - break; - - default: - break; - } - - return rc; -} - -#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + int rc = -ENOTTY; + + switch (req) + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + { + int timeout = *((int *)arg); + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + rc = 0; + } + break; + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + rc = 0; + } + break; + + default: + break; + } + + return rc; +} + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_read.c b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_read.c index 5657adb..f97baa8 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_read.c +++ b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_read.c @@ -1,205 +1,205 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include -#include -#include -#include - -#include - -#include "sys/alt_irq.h" -#include "sys/alt_alarm.h" -#include "sys/ioctl.h" -#include "alt_types.h" - -#include "altera_avalon_jtag_uart_regs.h" -#include "altera_avalon_jtag_uart.h" - -#include "sys/alt_log_printf.h" - -#ifdef __ucosii__ -#include "includes.h" -#endif /* __ucosii__ */ - -#ifdef ALTERA_AVALON_JTAG_UART_SMALL - -/* ----------------------------------------------------------- */ -/* ----------------------- SMALL DRIVER ---------------------- */ -/* ----------------------------------------------------------- */ - -/* Read routine. The small version blocks until it has at least one byte - * available, it then returns as much as is immediately available without - * waiting any more. It's performance will be very poor without - * interrupts. - */ - -int -altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, - char* buffer, int space, int flags) -{ - unsigned int base = sp->base; - - char * ptr = buffer; - char * end = buffer + space; - - while (ptr < end) - { - unsigned int data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); - - if (data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) - *ptr++ = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; - else if (ptr != buffer) - break; - else if(flags & O_NONBLOCK) - break; - - } - - if (ptr != buffer) - return ptr - buffer; - else if (flags & O_NONBLOCK) - return -EWOULDBLOCK; - else - return -EIO; -} - -#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ - -/* ----------------------------------------------------------- */ -/* ----------------------- FAST DRIVER ----------------------- */ -/* ----------------------------------------------------------- */ - -int -altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, - char * buffer, int space, int flags) -{ - char * ptr = buffer; - - alt_irq_context context; - unsigned int n; - - /* - * When running in a multi threaded environment, obtain the "read_lock" - * semaphore. This ensures that reading from the device is thread-safe. - */ - ALT_SEM_PEND (sp->read_lock, 0); - - while (space > 0) - { - unsigned int in, out; - - /* Read as much data as possible */ - do - { - in = sp->rx_in; - out = sp->rx_out; - - if (in >= out) - n = in - out; - else - n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; - - if (n == 0) - break; /* No more data available */ - - if (n > space) - n = space; - - memcpy(ptr, sp->rx_buf + out, n); - ptr += n; - space -= n; - - sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - } - while (space > 0); - - /* If we read any data then return it */ - if (ptr != buffer) - break; - - /* If in non-blocking mode then return error */ - if (flags & O_NONBLOCK) - break; - -#ifdef __ucosii__ - /* OS Present: Pend on a flag if the OS is running, otherwise spin */ - if(OSRunning == OS_TRUE) { - /* - * When running in a multi-threaded mode, we pend on the read event - * flag set and timeout event flag set in the isr. This avoids wasting CPU - * cycles waiting in this thread, when we could be doing something more - * profitable elsewhere. - */ - ALT_FLAG_PEND (sp->events, - ALT_JTAG_UART_READ_RDY | ALT_JTAG_UART_TIMEOUT, - OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, - 0); - } - else { - /* Spin until more data arrives or until host disconnects */ - while (in == sp->rx_in && sp->host_inactive < sp->timeout) - ; - } -#else - /* No OS: Always spin */ - while (in == sp->rx_in && sp->host_inactive < sp->timeout) - ; -#endif /* __ucosii__ */ - - if (in == sp->rx_in) - break; - } - - /* - * Now that access to the circular buffer is complete, release the read - * semaphore so that other threads can access the buffer. - */ - - ALT_SEM_POST (sp->read_lock); - - if (ptr != buffer) - { - /* If we read any data then there is space in the buffer so enable interrupts */ - context = alt_irq_disable_all(); - sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); - alt_irq_enable_all(context); - } - - if (ptr != buffer) - return ptr - buffer; - else if (flags & O_NONBLOCK) - return -EWOULDBLOCK; - else - return -EIO; -} - -#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifdef __ucosii__ +#include "includes.h" +#endif /* __ucosii__ */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ----------------------- SMALL DRIVER ---------------------- */ +/* ----------------------------------------------------------- */ + +/* Read routine. The small version blocks until it has at least one byte + * available, it then returns as much as is immediately available without + * waiting any more. It's performance will be very poor without + * interrupts. + */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char* buffer, int space, int flags) +{ + unsigned int base = sp->base; + + char * ptr = buffer; + char * end = buffer + space; + + while (ptr < end) + { + unsigned int data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) + *ptr++ = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + else if (ptr != buffer) + break; + else if(flags & O_NONBLOCK) + break; + + } + + if (ptr != buffer) + return ptr - buffer; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; +} + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +/* ----------------------------------------------------------- */ +/* ----------------------- FAST DRIVER ----------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + char * ptr = buffer; + + alt_irq_context context; + unsigned int n; + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + { + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + out = sp->rx_out; + + if (in >= out) + n = in - out; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + + if (n == 0) + break; /* No more data available */ + + if (n > space) + n = space; + + memcpy(ptr, sp->rx_buf + out, n); + ptr += n; + space -= n; + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + while (space > 0); + + /* If we read any data then return it */ + if (ptr != buffer) + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + /* + * When running in a multi-threaded mode, we pend on the read event + * flag set and timeout event flag set in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + ALT_JTAG_UART_READ_RDY | ALT_JTAG_UART_TIMEOUT, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* Spin until more data arrives or until host disconnects */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; + } +#else + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + break; + } + + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + + if (ptr != buffer) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + alt_irq_enable_all(context); + } + + if (ptr != buffer) + return ptr - buffer; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_write.c b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_write.c index 11aeca1..9562562 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_write.c +++ b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_jtag_uart_write.c @@ -1,217 +1,217 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include -#include -#include -#include - -#include - -#include "sys/alt_irq.h" -#include "sys/alt_alarm.h" -#include "sys/ioctl.h" -#include "alt_types.h" - -#include "altera_avalon_jtag_uart_regs.h" -#include "altera_avalon_jtag_uart.h" - -#include "sys/alt_log_printf.h" - -#ifdef __ucosii__ -#include "includes.h" -#endif /* __ucosii__ */ - -#ifdef ALTERA_AVALON_JTAG_UART_SMALL - -/* ----------------------------------------------------------- */ -/* ------------------------ SMALL DRIVER --------------------- */ -/* ----------------------------------------------------------- */ - -/* Write routine. The small version blocks when there is no space to write - * into, so it's performance will be very bad if you are writing more than - * one FIFOs worth of data. But you said you didn't want to use interrupts :-) - */ - -int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, - const char * ptr, int count, int flags) -{ - unsigned int base = sp->base; - - const char * end = ptr + count; - - while (ptr < end) - if ((IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) != 0) - IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, *ptr++); - - return count; -} - -#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ - -/* ----------------------------------------------------------- */ -/* ------------------------- FAST DRIVER --------------------- */ -/* ----------------------------------------------------------- */ - -int -altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, - const char * ptr, int count, int flags) -{ - /* Remove warning at optimisation level 03 by seting out to 0 */ - unsigned int in, out=0; - unsigned int n; - alt_irq_context context; - - const char * start = ptr; - - /* - * When running in a multi threaded environment, obtain the "write_lock" - * semaphore. This ensures that writing to the device is thread-safe. - */ - ALT_SEM_PEND (sp->write_lock, 0); - - do - { - /* Copy as much as we can into the transmit buffer */ - while (count > 0) - { - /* We need a stable value of the out pointer to calculate the space available */ - in = sp->tx_in; - out = sp->tx_out; - - if (in < out) - n = out - 1 - in; - else if (out > 0) - n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; - else - n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; - - if (n == 0) - break; - - if (n > count) - n = count; - - memcpy(sp->tx_buf + in, ptr, n); - ptr += n; - count -= n; - - sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - } - - /* - * If interrupts are disabled then we could transmit here, we only need - * to enable interrupts if there is no space left in the FIFO - * - * For now kick the interrupt routine every time to make it transmit - * the data - */ - context = alt_irq_disable_all(); - sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); - alt_irq_enable_all(context); - - /* - * If there is any data left then either return now or block until - * some has been sent - */ - /* consider: test whether there is anything there while doing this and delay for at most 2s. */ - if (count > 0) - { - if (flags & O_NONBLOCK) - break; - -#ifdef __ucosii__ - /* OS Present: Pend on a flag if the OS is running, otherwise spin */ - if(OSRunning == OS_TRUE) { - /* - * When running in a multi-threaded mode, we pend on the write event - * flag set or the timeout flag in the isr. This avoids wasting CPU - * cycles waiting in this thread, when we could be doing something - * more profitable elsewhere. - */ -#ifdef ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR - if(!sp->host_inactive) -#endif - ALT_FLAG_PEND (sp->events, - ALT_JTAG_UART_WRITE_RDY | ALT_JTAG_UART_TIMEOUT, - OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, - 0); - } - else { - /* - * OS not running: Wait for data to be removed from buffer. - * Once the interrupt routine has removed some data then we - * will be able to insert some more. - */ - while (out == sp->tx_out && sp->host_inactive < sp->timeout) - ; - } -#else - /* - * No OS present: Always wait for data to be removed from buffer. Once - * the interrupt routine has removed some data then we will be able to - * insert some more. - */ - while (out == sp->tx_out && sp->host_inactive < sp->timeout) - ; -#endif /* __ucosii__ */ - - if (out == sp->tx_out) - break; - } - } - while (count > 0); - - /* - * Now that access to the circular buffer is complete, release the write - * semaphore so that other threads can access the buffer. - */ - ALT_SEM_POST (sp->write_lock); - - if (ptr != start) - return ptr - start; - else if (flags & O_NONBLOCK) - return -EWOULDBLOCK; -#ifdef ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR - else if (sp->host_inactive >= sp->timeout) { - /* - * Reset the software FIFO, hardware FIFO could not be reset. - * Just throw away characters without reporting error. - */ - sp->tx_out = sp->tx_in = 0; - return ptr - start + count; - } -#endif - else - return -EIO; /* Host not connected */ -} - -#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifdef __ucosii__ +#include "includes.h" +#endif /* __ucosii__ */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------ SMALL DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* Write routine. The small version blocks when there is no space to write + * into, so it's performance will be very bad if you are writing more than + * one FIFOs worth of data. But you said you didn't want to use interrupts :-) + */ + +int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + unsigned int base = sp->base; + + const char * end = ptr + count; + + while (ptr < end) + if ((IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) != 0) + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, *ptr++); + + return count; +} + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + out = sp->tx_out; + + if (in < out) + n = out - 1 - in; + else if (out > 0) + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + + if (n == 0) + break; + + if (n > count) + n = count; + + memcpy(sp->tx_buf + in, ptr, n); + ptr += n; + count -= n; + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + + /* + * If interrupts are disabled then we could transmit here, we only need + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + alt_irq_enable_all(context); + + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + { + if (flags & O_NONBLOCK) + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + /* + * When running in a multi-threaded mode, we pend on the write event + * flag set or the timeout flag in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ +#ifdef ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + if(!sp->host_inactive) +#endif + ALT_FLAG_PEND (sp->events, + ALT_JTAG_UART_WRITE_RDY | ALT_JTAG_UART_TIMEOUT, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* + * OS not running: Wait for data to be removed from buffer. + * Once the interrupt routine has removed some data then we + * will be able to insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; + } +#else + /* + * No OS present: Always wait for data to be removed from buffer. Once + * the interrupt routine has removed some data then we will be able to + * insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (out == sp->tx_out) + break; + } + } + while (count > 0); + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + + if (ptr != start) + return ptr - start; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; +#ifdef ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + else if (sp->host_inactive >= sp->timeout) { + /* + * Reset the software FIFO, hardware FIFO could not be reset. + * Just throw away characters without reporting error. + */ + sp->tx_out = sp->tx_in = 0; + return ptr - start + count; + } +#endif + else + return -EIO; /* Host not connected */ +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_lcd_16207.c b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_lcd_16207.c index 1fefba3..102e202 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_lcd_16207.c +++ b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_lcd_16207.c @@ -1,605 +1,605 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -/* ===================================================================== */ - -/* - * This file provides the implementation of the functions used to drive a - * LCD panel. - * - * Characters written to the device will appear on the LCD panel as though - * it is a very small terminal. If the lines written to the terminal are - * longer than the number of characters on the terminal then it will scroll - * the lines of text automatically to display them all. - * - * If more lines are written than will fit on the terminal then it will scroll - * when characters are written to the line "below" the last displayed one - - * the cursor is allowed to sit below the visible area of the screen providing - * that this line is entirely blank. - * - * The following control sequences may be used to move around and do useful - * stuff: - * CR Moves back to the start of the current line - * LF Moves down a line and back to the start - * BS Moves back a character without erasing - * ESC Starts a VT100 style escape sequence - * - * The following escape sequences are recognised: - * ESC [ ; H Move to row and column specified (positions are - * counted from the top left which is 1;1) - * ESC [ K Clear from current position to end of line - * ESC [ 2 J Clear screen and go to top left - * - */ - -/* ===================================================================== */ - -#include -#include - -#include -#include -#include - -#include "sys/alt_alarm.h" - -#include "altera_avalon_lcd_16207_regs.h" -#include "altera_avalon_lcd_16207.h" - -/* --------------------------------------------------------------------- */ - -/* Commands which can be written to the COMMAND register */ - -enum /* Write to character RAM */ -{ - LCD_CMD_WRITE_DATA = 0x80 - /* Bits 6:0 hold character RAM address */ -}; - -enum /* Write to character generator RAM */ -{ - LCD_CMD_WRITE_CGR = 0x40 - /* Bits 5:0 hold character generator RAM address */ -}; - -enum /* Function Set command */ -{ - LCD_CMD_FUNCTION_SET = 0x20, - LCD_CMD_8BIT = 0x10, - LCD_CMD_TWO_LINE = 0x08, - LCD_CMD_BIGFONT = 0x04 -}; - -enum /* Shift command */ -{ - LCD_CMD_SHIFT = 0x10, - LCD_CMD_SHIFT_DISPLAY = 0x08, - LCD_CMD_SHIFT_RIGHT = 0x04 -}; - -enum /* On/Off command */ -{ - LCD_CMD_ONOFF = 0x08, - LCD_CMD_ENABLE_DISP = 0x04, - LCD_CMD_ENABLE_CURSOR = 0x02, - LCD_CMD_ENABLE_BLINK = 0x01 -}; - -enum /* Entry Mode command */ -{ - LCD_CMD_MODES = 0x04, - LCD_CMD_MODE_INC = 0x02, - LCD_CMD_MODE_SHIFT = 0x01 -}; - -enum /* Home command */ -{ - LCD_CMD_HOME = 0x02 -}; - -enum /* Clear command */ -{ - LCD_CMD_CLEAR = 0x01 -}; - -/* Where in LCD character space do the rows start */ -static char colstart[4] = { 0x00, 0x40, 0x20, 0x60 }; - -/* --------------------------------------------------------------------- */ - -static void lcd_write_command(altera_avalon_lcd_16207_state* sp, - unsigned char command) -{ - unsigned int base = sp->base; - - /* We impose a timeout on the driver in case the LCD panel isn't connected. - * The first time we call this function the timeout is approx 25ms - * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems - * with slower clocks, or debug builds, or slower memory will take longer. - */ - int i = 1000000; - - /* Don't bother if the LCD panel didn't work before */ - if (sp->broken) - return; - - /* Wait until LCD isn't busy. */ - while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) - if (--i == 0) - { - sp->broken = 1; - return; - } - - /* Despite what it says in the datasheet, the LCD isn't ready to accept - * a write immediately after it returns BUSY=0. Wait for 100us more. - */ - usleep(100); - - IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, command); -} - -/* --------------------------------------------------------------------- */ - -static void lcd_write_data(altera_avalon_lcd_16207_state* sp, - unsigned char data) -{ - unsigned int base = sp->base; - - /* We impose a timeout on the driver in case the LCD panel isn't connected. - * The first time we call this function the timeout is approx 25ms - * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems - * with slower clocks, or debug builds, or slower memory will take longer. - */ - int i = 1000000; - - /* Don't bother if the LCD panel didn't work before */ - if (sp->broken) - return; - - /* Wait until LCD isn't busy. */ - while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) - if (--i == 0) - { - sp->broken = 1; - return; - } - - /* Despite what it says in the datasheet, the LCD isn't ready to accept - * a write immediately after it returns BUSY=0. Wait for 100us more. - */ - usleep(100); - - IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data); - - sp->address++; -} - -/* --------------------------------------------------------------------- */ - -static void lcd_clear_screen(altera_avalon_lcd_16207_state* sp) -{ - int y; - - lcd_write_command(sp, LCD_CMD_CLEAR); - - sp->x = 0; - sp->y = 0; - sp->address = 0; - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - { - memset(sp->line[y].data, ' ', sizeof(sp->line[0].data)); - memset(sp->line[y].visible, ' ', sizeof(sp->line[0].visible)); - sp->line[y].width = 0; - } -} - -/* --------------------------------------------------------------------- */ - -static void lcd_repaint_screen(altera_avalon_lcd_16207_state* sp) -{ - int y, x; - - /* scrollpos controls how much the lines have scrolled round. The speed - * each line scrolls at is controlled by its speed variable - while - * scrolline lines will wrap at the position set by width - */ - - int scrollpos = sp->scrollpos; - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - { - int width = sp->line[y].width; - int offset = (scrollpos * sp->line[y].speed) >> 8; - if (offset >= width) - offset = 0; - - for (x = 0 ; x < ALT_LCD_WIDTH ; x++) - { - char c = sp->line[y].data[(x + offset) % width]; - - /* Writing data takes 40us, so don't do it unless required */ - if (sp->line[y].visible[x] != c) - { - unsigned char address = x + colstart[y]; - - if (address != sp->address) - { - lcd_write_command(sp, LCD_CMD_WRITE_DATA | address); - sp->address = address; - } - - lcd_write_data(sp, c); - sp->line[y].visible[x] = c; - } - } - } -} - -/* --------------------------------------------------------------------- */ - -static void lcd_scroll_up(altera_avalon_lcd_16207_state* sp) -{ - int y; - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - { - if (y < ALT_LCD_HEIGHT-1) - memcpy(sp->line[y].data, sp->line[y+1].data, ALT_LCD_VIRTUAL_WIDTH); - else - memset(sp->line[y].data, ' ', ALT_LCD_VIRTUAL_WIDTH); - } - - sp->y--; -} - -/* --------------------------------------------------------------------- */ - -static void lcd_handle_escape(altera_avalon_lcd_16207_state* sp, char c) -{ - int parm1 = 0, parm2 = 0; - - if (sp->escape[0] == '[') - { - char * ptr = sp->escape+1; - while (isdigit(*ptr)) - parm1 = (parm1 * 10) + (*ptr++ - '0'); - - if (*ptr == ';') - { - ptr++; - while (isdigit(*ptr)) - parm2 = (parm2 * 10) + (*ptr++ - '0'); - } - } - else - parm1 = -1; - - switch (c) - { - case 'H': /* ESC '[' ';' 'H' : Move cursor to location */ - case 'f': /* Same as above */ - if (parm2 > 0) - sp->x = parm2 - 1; - if (parm1 > 0) - { - sp->y = parm1 - 1; - if (sp->y > ALT_LCD_HEIGHT * 2) - sp->y = ALT_LCD_HEIGHT * 2; - while (sp->y > ALT_LCD_HEIGHT) - lcd_scroll_up(sp); - } - break; - - case 'J': - /* ESC J is clear to beginning of line [unimplemented] - * ESC [ 0 J is clear to bottom of screen [unimplemented] - * ESC [ 1 J is clear to beginning of screen [unimplemented] - * ESC [ 2 J is clear screen - */ - if (parm1 == 2) - lcd_clear_screen(sp); - break; - - case 'K': - /* ESC K is clear to end of line - * ESC [ 0 K is clear to end of line - * ESC [ 1 K is clear to beginning of line [unimplemented] - * ESC [ 2 K is clear line [unimplemented] - */ - if (parm1 < 1) - { - if (sp->x < ALT_LCD_VIRTUAL_WIDTH) - memset(sp->line[sp->y].data + sp->x, ' ', ALT_LCD_VIRTUAL_WIDTH - sp->x); - } - break; - } -} - -/* --------------------------------------------------------------------- */ - -int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, - const char* ptr, int len, int flags) -{ - const char* end = ptr + len; - - int y; - int widthmax; - - /* When running in a multi threaded environment, obtain the "write_lock" - * semaphore. This ensures that writing to the device is thread-safe. - */ - - ALT_SEM_PEND (sp->write_lock, 0); - - /* Tell the routine which is called off the timer interrupt that the - * foreground routines are active so it must not repaint the display. */ - sp->active = 1; - - for ( ; ptr < end ; ptr++) - { - char c = *ptr; - - if (sp->esccount >= 0) - { - unsigned int esccount = sp->esccount; - - /* Single character escape sequences can end with any character - * Multi character escape sequences start with '[' and contain - * digits and semicolons before terminating - */ - if ((esccount == 0 && c != '[') || - (esccount > 0 && !isdigit(c) && c != ';')) - { - sp->escape[esccount] = 0; - - lcd_handle_escape(sp, c); - - sp->esccount = -1; - } - else if (sp->esccount < sizeof(sp->escape)-1) - { - sp->escape[esccount] = c; - sp->esccount++; - } - } - else if (c == 27) /* ESC */ - { - sp->esccount = 0; - } - else if (c == '\r') - { - sp->x = 0; - } - else if (c == '\n') - { - sp->x = 0; - sp->y++; - - /* Let the cursor sit at X=0, Y=HEIGHT without scrolling so the user - * can print two lines of data without losing one. - */ - if (sp->y > ALT_LCD_HEIGHT) - lcd_scroll_up(sp); - } - else if (c == '\b') - { - if (sp->x > 0) - sp->x--; - } - else if (isprint(c)) - { - /* If we didn't scroll on the last linefeed then we might need to do - * it now. */ - if (sp->y >= ALT_LCD_HEIGHT) - lcd_scroll_up(sp); - - if (sp->x < ALT_LCD_VIRTUAL_WIDTH) - sp->line[sp->y].data[sp->x] = c; - - sp->x++; - } - } - - /* Recalculate the scrolling parameters */ - widthmax = ALT_LCD_WIDTH; - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - { - int width; - for (width = ALT_LCD_VIRTUAL_WIDTH ; width > 0 ; width--) - if (sp->line[y].data[width-1] != ' ') - break; - - /* The minimum width is the size of the LCD panel. If the real width - * is long enough to require scrolling then add an extra space so the - * end of the message doesn't run into the beginning of it. - */ - if (width <= ALT_LCD_WIDTH) - width = ALT_LCD_WIDTH; - else - width++; - - sp->line[y].width = width; - if (widthmax < width) - widthmax = width; - sp->line[y].speed = 0; /* By default lines don't scroll */ - } - - if (widthmax <= ALT_LCD_WIDTH) - sp->scrollmax = 0; - else - { - widthmax *= 2; - sp->scrollmax = widthmax; - - /* Now calculate how fast each of the other lines should go */ - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - if (sp->line[y].width > ALT_LCD_WIDTH) - { - /* You have three options for how to make the display scroll, chosen - * using the preprocessor directives below - */ -#if 1 - /* This option makes all the lines scroll round at different speeds - * which are chosen so that all the scrolls finish at the same time. - */ - sp->line[y].speed = 256 * sp->line[y].width / widthmax; -#elif 1 - /* This option pads the shorter lines with spaces so that they all - * scroll together. - */ - sp->line[y].width = widthmax / 2; - sp->line[y].speed = 256/2; -#else - /* This option makes the shorter lines stop after they have rotated - * and waits for the longer lines to catch up - */ - sp->line[y].speed = 256/2; -#endif - } - } - - /* Repaint once, then check whether there has been a missed repaint - * (because active was set when the timer interrupt occurred). If there - * has been a missed repaint then paint again. And again. etc. - */ - for ( ; ; ) - { - int old_scrollpos = sp->scrollpos; - - lcd_repaint_screen(sp); - - /* Let the timer routines repaint the display again */ - sp->active = 0; - - /* Have the timer routines tried to scroll while we were painting? - * If not then we can exit */ - if (sp->scrollpos == old_scrollpos) - break; - - /* We need to repaint again since the display scrolled while we were - * painting last time */ - sp->active = 1; - } - - /* Now that access to the display is complete, release the write - * semaphore so that other threads can access the buffer. - */ - - ALT_SEM_POST (sp->write_lock); - - return len; -} - -/* --------------------------------------------------------------------- */ - -/* This should be in a top level header file really */ -#define container_of(ptr, type, member) ((type *)((char *)ptr - offsetof(type, member))) - -/* - * Timeout routine is called every second - */ - -static alt_u32 alt_lcd_16207_timeout(void* context) -{ - altera_avalon_lcd_16207_state* sp = (altera_avalon_lcd_16207_state*)context; - - /* Update the scrolling position */ - if (sp->scrollpos + 1 >= sp->scrollmax) - sp->scrollpos = 0; - else - sp->scrollpos = sp->scrollpos + 1; - - /* Repaint the panel unless the foreground will do it again soon */ - if (sp->scrollmax > 0 && !sp->active) - lcd_repaint_screen(sp); - - return sp->period; -} - -/* --------------------------------------------------------------------- */ - -/* - * Called at boot time to initialise the LCD driver - */ -void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp) -{ - unsigned int base = sp->base; - - /* Mark the device as functional */ - sp->broken = 0; - - ALT_SEM_CREATE (&sp->write_lock, 1); - - /* The initialisation sequence below is copied from the datasheet for - * the 16207 LCD display. The first commands need to be timed because - * the BUSY bit in the status register doesn't work until the display - * has been reset three times. - */ - - /* Wait for 15 ms then reset */ - usleep(15000); - IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); - - /* Wait for another 4.1ms and reset again */ - usleep(4100); - IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); - - /* Wait a further 1 ms and reset a third time */ - usleep(1000); - IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); - - /* Setup interface parameters: 8 bit bus, 2 rows, 5x7 font */ - lcd_write_command(sp, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT | LCD_CMD_TWO_LINE); - - /* Turn display off */ - lcd_write_command(sp, LCD_CMD_ONOFF); - - /* Clear display */ - lcd_clear_screen(sp); - - /* Set mode: increment after writing, don't shift display */ - lcd_write_command(sp, LCD_CMD_MODES | LCD_CMD_MODE_INC); - - /* Turn display on */ - lcd_write_command(sp, LCD_CMD_ONOFF | LCD_CMD_ENABLE_DISP); - - sp->esccount = -1; - memset(sp->escape, 0, sizeof(sp->escape)); - - sp->scrollpos = 0; - sp->scrollmax = 0; - sp->active = 0; - - sp->period = alt_ticks_per_second() / 10; /* Call every 100ms */ - - alt_alarm_start(&sp->alarm, sp->period, &alt_lcd_16207_timeout, sp); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* ===================================================================== */ + +/* + * This file provides the implementation of the functions used to drive a + * LCD panel. + * + * Characters written to the device will appear on the LCD panel as though + * it is a very small terminal. If the lines written to the terminal are + * longer than the number of characters on the terminal then it will scroll + * the lines of text automatically to display them all. + * + * If more lines are written than will fit on the terminal then it will scroll + * when characters are written to the line "below" the last displayed one - + * the cursor is allowed to sit below the visible area of the screen providing + * that this line is entirely blank. + * + * The following control sequences may be used to move around and do useful + * stuff: + * CR Moves back to the start of the current line + * LF Moves down a line and back to the start + * BS Moves back a character without erasing + * ESC Starts a VT100 style escape sequence + * + * The following escape sequences are recognised: + * ESC [ ; H Move to row and column specified (positions are + * counted from the top left which is 1;1) + * ESC [ K Clear from current position to end of line + * ESC [ 2 J Clear screen and go to top left + * + */ + +/* ===================================================================== */ + +#include +#include + +#include +#include +#include + +#include "sys/alt_alarm.h" + +#include "altera_avalon_lcd_16207_regs.h" +#include "altera_avalon_lcd_16207.h" + +/* --------------------------------------------------------------------- */ + +/* Commands which can be written to the COMMAND register */ + +enum /* Write to character RAM */ +{ + LCD_CMD_WRITE_DATA = 0x80 + /* Bits 6:0 hold character RAM address */ +}; + +enum /* Write to character generator RAM */ +{ + LCD_CMD_WRITE_CGR = 0x40 + /* Bits 5:0 hold character generator RAM address */ +}; + +enum /* Function Set command */ +{ + LCD_CMD_FUNCTION_SET = 0x20, + LCD_CMD_8BIT = 0x10, + LCD_CMD_TWO_LINE = 0x08, + LCD_CMD_BIGFONT = 0x04 +}; + +enum /* Shift command */ +{ + LCD_CMD_SHIFT = 0x10, + LCD_CMD_SHIFT_DISPLAY = 0x08, + LCD_CMD_SHIFT_RIGHT = 0x04 +}; + +enum /* On/Off command */ +{ + LCD_CMD_ONOFF = 0x08, + LCD_CMD_ENABLE_DISP = 0x04, + LCD_CMD_ENABLE_CURSOR = 0x02, + LCD_CMD_ENABLE_BLINK = 0x01 +}; + +enum /* Entry Mode command */ +{ + LCD_CMD_MODES = 0x04, + LCD_CMD_MODE_INC = 0x02, + LCD_CMD_MODE_SHIFT = 0x01 +}; + +enum /* Home command */ +{ + LCD_CMD_HOME = 0x02 +}; + +enum /* Clear command */ +{ + LCD_CMD_CLEAR = 0x01 +}; + +/* Where in LCD character space do the rows start */ +static char colstart[4] = { 0x00, 0x40, 0x20, 0x60 }; + +/* --------------------------------------------------------------------- */ + +static void lcd_write_command(altera_avalon_lcd_16207_state* sp, + unsigned char command) +{ + unsigned int base = sp->base; + + /* We impose a timeout on the driver in case the LCD panel isn't connected. + * The first time we call this function the timeout is approx 25ms + * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems + * with slower clocks, or debug builds, or slower memory will take longer. + */ + int i = 1000000; + + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + if (--i == 0) + { + sp->broken = 1; + return; + } + + /* Despite what it says in the datasheet, the LCD isn't ready to accept + * a write immediately after it returns BUSY=0. Wait for 100us more. + */ + usleep(100); + + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, command); +} + +/* --------------------------------------------------------------------- */ + +static void lcd_write_data(altera_avalon_lcd_16207_state* sp, + unsigned char data) +{ + unsigned int base = sp->base; + + /* We impose a timeout on the driver in case the LCD panel isn't connected. + * The first time we call this function the timeout is approx 25ms + * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems + * with slower clocks, or debug builds, or slower memory will take longer. + */ + int i = 1000000; + + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + if (--i == 0) + { + sp->broken = 1; + return; + } + + /* Despite what it says in the datasheet, the LCD isn't ready to accept + * a write immediately after it returns BUSY=0. Wait for 100us more. + */ + usleep(100); + + IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data); + + sp->address++; +} + +/* --------------------------------------------------------------------- */ + +static void lcd_clear_screen(altera_avalon_lcd_16207_state* sp) +{ + int y; + + lcd_write_command(sp, LCD_CMD_CLEAR); + + sp->x = 0; + sp->y = 0; + sp->address = 0; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + memset(sp->line[y].data, ' ', sizeof(sp->line[0].data)); + memset(sp->line[y].visible, ' ', sizeof(sp->line[0].visible)); + sp->line[y].width = 0; + } +} + +/* --------------------------------------------------------------------- */ + +static void lcd_repaint_screen(altera_avalon_lcd_16207_state* sp) +{ + int y, x; + + /* scrollpos controls how much the lines have scrolled round. The speed + * each line scrolls at is controlled by its speed variable - while + * scrolline lines will wrap at the position set by width + */ + + int scrollpos = sp->scrollpos; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + int width = sp->line[y].width; + int offset = (scrollpos * sp->line[y].speed) >> 8; + if (offset >= width) + offset = 0; + + for (x = 0 ; x < ALT_LCD_WIDTH ; x++) + { + char c = sp->line[y].data[(x + offset) % width]; + + /* Writing data takes 40us, so don't do it unless required */ + if (sp->line[y].visible[x] != c) + { + unsigned char address = x + colstart[y]; + + if (address != sp->address) + { + lcd_write_command(sp, LCD_CMD_WRITE_DATA | address); + sp->address = address; + } + + lcd_write_data(sp, c); + sp->line[y].visible[x] = c; + } + } + } +} + +/* --------------------------------------------------------------------- */ + +static void lcd_scroll_up(altera_avalon_lcd_16207_state* sp) +{ + int y; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + if (y < ALT_LCD_HEIGHT-1) + memcpy(sp->line[y].data, sp->line[y+1].data, ALT_LCD_VIRTUAL_WIDTH); + else + memset(sp->line[y].data, ' ', ALT_LCD_VIRTUAL_WIDTH); + } + + sp->y--; +} + +/* --------------------------------------------------------------------- */ + +static void lcd_handle_escape(altera_avalon_lcd_16207_state* sp, char c) +{ + int parm1 = 0, parm2 = 0; + + if (sp->escape[0] == '[') + { + char * ptr = sp->escape+1; + while (isdigit(*ptr)) + parm1 = (parm1 * 10) + (*ptr++ - '0'); + + if (*ptr == ';') + { + ptr++; + while (isdigit(*ptr)) + parm2 = (parm2 * 10) + (*ptr++ - '0'); + } + } + else + parm1 = -1; + + switch (c) + { + case 'H': /* ESC '[' ';' 'H' : Move cursor to location */ + case 'f': /* Same as above */ + if (parm2 > 0) + sp->x = parm2 - 1; + if (parm1 > 0) + { + sp->y = parm1 - 1; + if (sp->y > ALT_LCD_HEIGHT * 2) + sp->y = ALT_LCD_HEIGHT * 2; + while (sp->y > ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + } + break; + + case 'J': + /* ESC J is clear to beginning of line [unimplemented] + * ESC [ 0 J is clear to bottom of screen [unimplemented] + * ESC [ 1 J is clear to beginning of screen [unimplemented] + * ESC [ 2 J is clear screen + */ + if (parm1 == 2) + lcd_clear_screen(sp); + break; + + case 'K': + /* ESC K is clear to end of line + * ESC [ 0 K is clear to end of line + * ESC [ 1 K is clear to beginning of line [unimplemented] + * ESC [ 2 K is clear line [unimplemented] + */ + if (parm1 < 1) + { + if (sp->x < ALT_LCD_VIRTUAL_WIDTH) + memset(sp->line[sp->y].data + sp->x, ' ', ALT_LCD_VIRTUAL_WIDTH - sp->x); + } + break; + } +} + +/* --------------------------------------------------------------------- */ + +int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, + const char* ptr, int len, int flags) +{ + const char* end = ptr + len; + + int y; + int widthmax; + + /* When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + + /* Tell the routine which is called off the timer interrupt that the + * foreground routines are active so it must not repaint the display. */ + sp->active = 1; + + for ( ; ptr < end ; ptr++) + { + char c = *ptr; + + if (sp->esccount >= 0) + { + unsigned int esccount = sp->esccount; + + /* Single character escape sequences can end with any character + * Multi character escape sequences start with '[' and contain + * digits and semicolons before terminating + */ + if ((esccount == 0 && c != '[') || + (esccount > 0 && !isdigit(c) && c != ';')) + { + sp->escape[esccount] = 0; + + lcd_handle_escape(sp, c); + + sp->esccount = -1; + } + else if (sp->esccount < sizeof(sp->escape)-1) + { + sp->escape[esccount] = c; + sp->esccount++; + } + } + else if (c == 27) /* ESC */ + { + sp->esccount = 0; + } + else if (c == '\r') + { + sp->x = 0; + } + else if (c == '\n') + { + sp->x = 0; + sp->y++; + + /* Let the cursor sit at X=0, Y=HEIGHT without scrolling so the user + * can print two lines of data without losing one. + */ + if (sp->y > ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + } + else if (c == '\b') + { + if (sp->x > 0) + sp->x--; + } + else if (isprint(c)) + { + /* If we didn't scroll on the last linefeed then we might need to do + * it now. */ + if (sp->y >= ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + + if (sp->x < ALT_LCD_VIRTUAL_WIDTH) + sp->line[sp->y].data[sp->x] = c; + + sp->x++; + } + } + + /* Recalculate the scrolling parameters */ + widthmax = ALT_LCD_WIDTH; + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + int width; + for (width = ALT_LCD_VIRTUAL_WIDTH ; width > 0 ; width--) + if (sp->line[y].data[width-1] != ' ') + break; + + /* The minimum width is the size of the LCD panel. If the real width + * is long enough to require scrolling then add an extra space so the + * end of the message doesn't run into the beginning of it. + */ + if (width <= ALT_LCD_WIDTH) + width = ALT_LCD_WIDTH; + else + width++; + + sp->line[y].width = width; + if (widthmax < width) + widthmax = width; + sp->line[y].speed = 0; /* By default lines don't scroll */ + } + + if (widthmax <= ALT_LCD_WIDTH) + sp->scrollmax = 0; + else + { + widthmax *= 2; + sp->scrollmax = widthmax; + + /* Now calculate how fast each of the other lines should go */ + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + if (sp->line[y].width > ALT_LCD_WIDTH) + { + /* You have three options for how to make the display scroll, chosen + * using the preprocessor directives below + */ +#if 1 + /* This option makes all the lines scroll round at different speeds + * which are chosen so that all the scrolls finish at the same time. + */ + sp->line[y].speed = 256 * sp->line[y].width / widthmax; +#elif 1 + /* This option pads the shorter lines with spaces so that they all + * scroll together. + */ + sp->line[y].width = widthmax / 2; + sp->line[y].speed = 256/2; +#else + /* This option makes the shorter lines stop after they have rotated + * and waits for the longer lines to catch up + */ + sp->line[y].speed = 256/2; +#endif + } + } + + /* Repaint once, then check whether there has been a missed repaint + * (because active was set when the timer interrupt occurred). If there + * has been a missed repaint then paint again. And again. etc. + */ + for ( ; ; ) + { + int old_scrollpos = sp->scrollpos; + + lcd_repaint_screen(sp); + + /* Let the timer routines repaint the display again */ + sp->active = 0; + + /* Have the timer routines tried to scroll while we were painting? + * If not then we can exit */ + if (sp->scrollpos == old_scrollpos) + break; + + /* We need to repaint again since the display scrolled while we were + * painting last time */ + sp->active = 1; + } + + /* Now that access to the display is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + + return len; +} + +/* --------------------------------------------------------------------- */ + +/* This should be in a top level header file really */ +#define container_of(ptr, type, member) ((type *)((char *)ptr - offsetof(type, member))) + +/* + * Timeout routine is called every second + */ + +static alt_u32 alt_lcd_16207_timeout(void* context) +{ + altera_avalon_lcd_16207_state* sp = (altera_avalon_lcd_16207_state*)context; + + /* Update the scrolling position */ + if (sp->scrollpos + 1 >= sp->scrollmax) + sp->scrollpos = 0; + else + sp->scrollpos = sp->scrollpos + 1; + + /* Repaint the panel unless the foreground will do it again soon */ + if (sp->scrollmax > 0 && !sp->active) + lcd_repaint_screen(sp); + + return sp->period; +} + +/* --------------------------------------------------------------------- */ + +/* + * Called at boot time to initialise the LCD driver + */ +void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp) +{ + unsigned int base = sp->base; + + /* Mark the device as functional */ + sp->broken = 0; + + ALT_SEM_CREATE (&sp->write_lock, 1); + + /* The initialisation sequence below is copied from the datasheet for + * the 16207 LCD display. The first commands need to be timed because + * the BUSY bit in the status register doesn't work until the display + * has been reset three times. + */ + + /* Wait for 15 ms then reset */ + usleep(15000); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Wait for another 4.1ms and reset again */ + usleep(4100); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Wait a further 1 ms and reset a third time */ + usleep(1000); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Setup interface parameters: 8 bit bus, 2 rows, 5x7 font */ + lcd_write_command(sp, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT | LCD_CMD_TWO_LINE); + + /* Turn display off */ + lcd_write_command(sp, LCD_CMD_ONOFF); + + /* Clear display */ + lcd_clear_screen(sp); + + /* Set mode: increment after writing, don't shift display */ + lcd_write_command(sp, LCD_CMD_MODES | LCD_CMD_MODE_INC); + + /* Turn display on */ + lcd_write_command(sp, LCD_CMD_ONOFF | LCD_CMD_ENABLE_DISP); + + sp->esccount = -1; + memset(sp->escape, 0, sizeof(sp->escape)); + + sp->scrollpos = 0; + sp->scrollmax = 0; + sp->active = 0; + + sp->period = alt_ticks_per_second() / 10; /* Call every 100ms */ + + alt_alarm_start(&sp->alarm, sp->period, &alt_lcd_16207_timeout, sp); +} diff --git a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_lcd_16207_fd.c b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_lcd_16207_fd.c index 431b094..08c9371 100644 --- a/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_lcd_16207_fd.c +++ b/software/qsys_tutorial_lcd4_bsp/drivers/src/altera_avalon_lcd_16207_fd.c @@ -1,45 +1,45 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* * -******************************************************************************/ - -#include "alt_types.h" -#include "sys/alt_dev.h" -#include "altera_avalon_lcd_16207.h" - -extern int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, - const char* ptr, int count, int flags); - -int -altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* buffer, int space) -{ - altera_avalon_lcd_16207_dev* dev = (altera_avalon_lcd_16207_dev*) fd->dev; - - return altera_avalon_lcd_16207_write(&dev->state, buffer, space, - fd->fd_flags); -} +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_lcd_16207.h" + +extern int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, + const char* ptr, int count, int flags); + +int +altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_lcd_16207_dev* dev = (altera_avalon_lcd_16207_dev*) fd->dev; + + return altera_avalon_lcd_16207_write(&dev->state, buffer, space, + fd->fd_flags); +} diff --git a/software/qsys_tutorial_lcd4_bsp/mem_init.mk b/software/qsys_tutorial_lcd4_bsp/mem_init.mk index 1f2a48f..4bdd7f1 100644 --- a/software/qsys_tutorial_lcd4_bsp/mem_init.mk +++ b/software/qsys_tutorial_lcd4_bsp/mem_init.mk @@ -1,322 +1,322 @@ - -######################################################################### -####### M E M I N I T M A K E F I L E C O N T E N T ###### -######################################################################### - -######################################################################### -# This file is intended to be included by public.mk -# -# -# The following variables must be defined before including this file: -# - ELF -# -# The following variables may be defined to override the default behavior: -# - HDL_SIM_DIR -# - HDL_SIM_INSTALL_DIR -# - MEM_INIT_DIR -# - MEM_INIT_INSTALL_DIR -# - QUARTUS_PROJECT_DIR -# - SOPC_NAME -# - SIM_OPTIMIZE -# - RESET_ADDRESS -# -######################################################################### - -ifeq ($(MEM_INIT_FILE),) -# MEM_INIT_FILE should be set equal to the working relative path to this -# mem_init.mk makefile fragment -MEM_INIT_FILE := $(wildcard $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))) -endif - -ifeq ($(ELF2DAT),) -ELF2DAT := elf2dat -endif - -ifeq ($(ELF2HEX),) -ELF2HEX := elf2hex -endif - -ifeq ($(ELF2FLASH),) -ELF2FLASH := elf2flash -endif - -ifeq ($(FLASH2DAT),) -FLASH2DAT := flash2dat -endif - -ifeq ($(NM),) -NM := nios2-elf-nm -endif - -ifeq ($(MKDIR),) -MKDIR := mkdir -p -endif - -ifeq ($(RM),) -RM := rm -f -endif - -ifeq ($(CP),) -CP := cp -endif - -ifeq ($(ECHO),) -ECHO := echo -endif - -MEM_INIT_DIR ?= mem_init -HDL_SIM_DIR ?= $(MEM_INIT_DIR)/hdl_sim - -ifdef QUARTUS_PROJECT_DIR -MEM_INIT_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR)) -ifdef SOPC_NAME -HDL_SIM_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))/$(SOPC_NAME)_sim -endif -endif - -MEM_INIT_DESCRIPTOR_FILE ?= $(MEM_INIT_DIR)/meminit.spd - -MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip - -#------------------------------------- -# Default Flash Boot Loaders -#------------------------------------- - -BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2 -BOOT_LOADER_CFI ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec -BOOT_LOADER_CFI_BE ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec - - -#------------------------------------- -# Default Target -#------------------------------------- - -.PHONY: default_mem_init -ifeq ($(QSYS),1) -default_mem_init: mem_init_generate -else -default_mem_init: mem_init_install -endif -#------------------------------------- -# Runtime Macros -#------------------------------------- - -define post-process-info - @echo Post-processing to create $@... -endef - -target_stem = $(notdir $(basename $@)) - -mem_start_address = $($(target_stem)_START) -mem_end_address = $($(target_stem)_END) -mem_width = $($(target_stem)_WIDTH) -mem_endianness = $($(target_stem)_ENDIANNESS) -mem_create_lanes = $($(target_stem)_CREATE_LANES) - -mem_pad_flag = $($(target_stem)_PAD_FLAG) -mem_reloc_input_flag = $($(target_stem)_RELOC_INPUT_FLAG) -mem_no_zero_fill_flag = $($(target_stem)_NO_ZERO_FILL_FLAG) - -flash_mem_epcs_flag = $($(target_stem)_EPCS_FLAGS) -flash_mem_cfi_flag = $($(target_stem)_CFI_FLAGS) -flash_mem_boot_loader_flag = $($(target_stem)_BOOT_LOADER_FLAG) - -elf2dat_extra_args = $(mem_pad_flag) -elf2hex_extra_args = $(mem_no_zero_fill_flag) -elf2flash_extra_args = $(flash_mem_cfi_flag) $(flash_mem_epcs_flag) $(flash_mem_boot_loader_flag) -flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag) - -#------------------------------------------------------------------------------ -# BSP SPECIFIC CONTENT -# -# The content below is controlled by the BSP and SOPC System -#------------------------------------------------------------------------------ -#START OF BSP SPECIFIC - -#------------------------------------- -# Global Settings -#------------------------------------- - - -# The following TYPE comment allows tools to identify the 'type' of target this -# makefile is associated with. -# TYPE: BSP_MEMINIT_MAKEFILE - -# This following VERSION comment indicates the version of the tool used to -# generate this makefile. A makefile variable is provided for VERSION as well. -# ACDS_VERSION: 13.0sp1 -ACDS_VERSION := 13.0sp1 - -# This following BUILD_NUMBER comment indicates the build number of the tool -# used to generate this makefile. -# BUILD_NUMBER: 232 - -# Optimize for simulation -SIM_OPTIMIZE ?= 0 - -# The CPU reset address as needed by elf2flash -RESET_ADDRESS ?= 0x00000000 - -#------------------------------------- -# Pre-Initialized Memory Descriptions -#------------------------------------- - -# Memory: onchip_memory -MEM_0 := nios_system_onchip_memory -$(MEM_0)_NAME := onchip_memory -$(MEM_0)_MEM_INIT_FILE_PARAM_NAME := INIT_FILE -HEX_FILES += $(MEM_INIT_DIR)/$(MEM_0).hex -MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_0).hex -DAT_FILES += $(HDL_SIM_DIR)/$(MEM_0).dat -HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat -SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym -HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym -$(MEM_0)_START := 0x00000000 -$(MEM_0)_END := 0x00031fff -$(MEM_0)_HIERARCHICAL_PATH := onchip_memory -$(MEM_0)_WIDTH := 32 -$(MEM_0)_ENDIANNESS := --little-endian-mem -$(MEM_0)_CREATE_LANES := 0 - -.PHONY: onchip_memory -onchip_memory: check_elf_exists $(MEM_INIT_DIR)/$(MEM_0).hex $(HDL_SIM_DIR)/$(MEM_0).dat $(HDL_SIM_DIR)/$(MEM_0).sym - - -#END OF BSP SPECIFIC - -#------------------------------------- -# Pre-Initialized Memory Targets -#------------------------------------- - -.PHONY: mem_init_install mem_init_generate mem_init_clean - -ifeq ($(QSYS),1) -# Target mem_init_install is deprecated for QSys based systems -# To initialize onchip memories for Quartus II Synthesis with Qsys based systems: -# 1) Use "make mem_init_genearate" -# 2) Add the generated mem_init/meminit.qip file to your Quartus II Project -# -mem_init_install: - $(error Deprecated Makefile Target: '$@'. Use target 'mem_init_generate' and then add $(MEM_INIT_QIP_FILE) to your Quartus II Project) - -else # QSYS != 1, if SopcBuilder based system - -ifneq ($(MEM_INIT_INSTALL_DIR),) -mem_init_install: $(MEM_INIT_INSTALL_FILES) -endif - -ifneq ($(HDL_SIM_INSTALL_DIR),) -mem_init_install: $(HDL_SIM_INSTALL_FILES) -endif - -mem_init_install: mem_init_generate -ifeq ($(MEM_INIT_INSTALL_DIR),) - @echo "WARNING: MEM_INIT_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR environment variable." -endif -ifeq ($(HDL_SIM_INSTALL_DIR),) - @echo "WARNING: HDL_SIM_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR and SOPC_NAME environment variable." -endif - -$(MEM_INIT_INSTALL_FILES): $(MEM_INIT_INSTALL_DIR)/%: $(MEM_INIT_DIR)/% - @$(MKDIR) $(@D) - @$(CP) -v $< $@ - -$(HDL_SIM_INSTALL_FILES): $(HDL_SIM_INSTALL_DIR)/%: $(HDL_SIM_DIR)/% - @$(MKDIR) $(@D) - @$(CP) -v $< $@ - -endif # QSYS == 1 - - -mem_init_generate: hex dat sym flash $(MEM_INIT_DESCRIPTOR_FILE) $(MEM_INIT_QIP_FILE) - -mem_init_clean: - @$(RM) -r $(MEM_INIT_DIR) $(HDL_SIM_DIR) $(FLASH_FILES) - -.PHONY: hex dat sym flash - -hex: check_elf_exists $(HEX_FILES) - -dat: check_elf_exists $(DAT_FILES) - -sym: check_elf_exists $(SYM_FILES) - -flash: check_elf_exists $(FLASH_FILES) - -#------------------------------------- -# Pre-Initialized Memory Rules -#------------------------------------- - -.PHONY: check_elf_exists -check_elf_exists: $(ELF) -ifeq ($(ELF),) - $(error ELF var not set in mem_init.mk) -endif - -$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(ELF) - $(post-process-info) - @$(MKDIR) $(@D) - bash -c '$(ELF2DAT) --infile=$< --outfile=$@ \ - --base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \ - $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)' - -$(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat - @true - -$(HEX_FILES): %.hex: $(ELF) - $(post-process-info) - @$(MKDIR) $(@D) - bash -c '$(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_width) \ - $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@' - -$(SYM_FILES): %.sym: $(ELF) - $(post-process-info) - @$(MKDIR) $(@D) - $(NM) -n $< > $@ - -$(FLASH_FILES): %.flash: $(ELF) - $(post-process-info) - @$(MKDIR) $(@D) - bash -c '$(ELF2FLASH) --input=$< --outfile=$@ --sim_optimize=$(SIM_OPTIMIZE) $(mem_endianness) \ - $(elf2flash_extra_args)' - -# -# Function generate_spd_entry -# Arg1: path to the memory initialization file -# Arg2: Type HEX or DAT -# Arg3: Output spd file to append -gen_spd_entry.BASE_FILE = $(basename $(notdir $1)) -gen_spd_entry.PARAM_NAME = $($(gen_spd_entry.BASE_FILE)_MEM_INIT_FILE_PARAM_NAME) -gen_spd_entry.MEM_PATH = $($(gen_spd_entry.BASE_FILE)_HIERARCHICAL_PATH) -gen_spd_entry.SETTINGS = $(strip \ - path=\"$1\" \ - type=\"$2\" \ - $(if $(gen_spd_entry.PARAM_NAME),initParamName=\"$(gen_spd_entry.PARAM_NAME)\") \ - $(if $(gen_spd_entry.MEM_PATH),memoryPath=\"$(gen_spd_entry.MEM_PATH)\") \ -) -define gen_spd_entry -$(ECHO) "" >> $3 -endef - -$(MEM_INIT_DESCRIPTOR_FILE).DAT_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(DAT_FILES)) -$(MEM_INIT_DESCRIPTOR_FILE).HEX_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(HEX_FILES)) - -$(MEM_INIT_DESCRIPTOR_FILE): %.spd: $(MEM_INIT_FILE) - $(post-process-info) - @$(MKDIR) $(@D) - @$(RM) $@ - @$(ECHO) "" > $@ - @$(ECHO) "" >> $@ - @$(foreach dat_file,$($@.DAT_FILESET),$(call gen_spd_entry,$(dat_file),DAT,$@) &&)true - @$(foreach hex_file,$($@.HEX_FILESET),$(call gen_spd_entry,$(hex_file),HEX,$@) &&)true - @$(ECHO) "" >> $@ - -.DELETE_ON_ERROR: $(MEM_INIT_DESCRIPTOR_FILE) - -$(MEM_INIT_QIP_FILE): %.qip: $(MEM_INIT_FILE) - $(post-process-info) - @$(MKDIR) $(@D) - @$(RM) $@ - @$(ECHO) "set_global_assignment -name SEARCH_PATH $$::quartus(qip_path)" > $@ - -.DELETE_ON_ERROR: $(MEM_INIT_QIP_FILE) + +######################################################################### +####### M E M I N I T M A K E F I L E C O N T E N T ###### +######################################################################### + +######################################################################### +# This file is intended to be included by public.mk +# +# +# The following variables must be defined before including this file: +# - ELF +# +# The following variables may be defined to override the default behavior: +# - HDL_SIM_DIR +# - HDL_SIM_INSTALL_DIR +# - MEM_INIT_DIR +# - MEM_INIT_INSTALL_DIR +# - QUARTUS_PROJECT_DIR +# - SOPC_NAME +# - SIM_OPTIMIZE +# - RESET_ADDRESS +# +######################################################################### + +ifeq ($(MEM_INIT_FILE),) +# MEM_INIT_FILE should be set equal to the working relative path to this +# mem_init.mk makefile fragment +MEM_INIT_FILE := $(wildcard $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))) +endif + +ifeq ($(ELF2DAT),) +ELF2DAT := elf2dat +endif + +ifeq ($(ELF2HEX),) +ELF2HEX := elf2hex +endif + +ifeq ($(ELF2FLASH),) +ELF2FLASH := elf2flash +endif + +ifeq ($(FLASH2DAT),) +FLASH2DAT := flash2dat +endif + +ifeq ($(NM),) +NM := nios2-elf-nm +endif + +ifeq ($(MKDIR),) +MKDIR := mkdir -p +endif + +ifeq ($(RM),) +RM := rm -f +endif + +ifeq ($(CP),) +CP := cp +endif + +ifeq ($(ECHO),) +ECHO := echo +endif + +MEM_INIT_DIR ?= mem_init +HDL_SIM_DIR ?= $(MEM_INIT_DIR)/hdl_sim + +ifdef QUARTUS_PROJECT_DIR +MEM_INIT_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR)) +ifdef SOPC_NAME +HDL_SIM_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))/$(SOPC_NAME)_sim +endif +endif + +MEM_INIT_DESCRIPTOR_FILE ?= $(MEM_INIT_DIR)/meminit.spd + +MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip + +#------------------------------------- +# Default Flash Boot Loaders +#------------------------------------- + +BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2 +BOOT_LOADER_CFI ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec +BOOT_LOADER_CFI_BE ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec + + +#------------------------------------- +# Default Target +#------------------------------------- + +.PHONY: default_mem_init +ifeq ($(QSYS),1) +default_mem_init: mem_init_generate +else +default_mem_init: mem_init_install +endif +#------------------------------------- +# Runtime Macros +#------------------------------------- + +define post-process-info + @echo Post-processing to create $@... +endef + +target_stem = $(notdir $(basename $@)) + +mem_start_address = $($(target_stem)_START) +mem_end_address = $($(target_stem)_END) +mem_width = $($(target_stem)_WIDTH) +mem_endianness = $($(target_stem)_ENDIANNESS) +mem_create_lanes = $($(target_stem)_CREATE_LANES) + +mem_pad_flag = $($(target_stem)_PAD_FLAG) +mem_reloc_input_flag = $($(target_stem)_RELOC_INPUT_FLAG) +mem_no_zero_fill_flag = $($(target_stem)_NO_ZERO_FILL_FLAG) + +flash_mem_epcs_flag = $($(target_stem)_EPCS_FLAGS) +flash_mem_cfi_flag = $($(target_stem)_CFI_FLAGS) +flash_mem_boot_loader_flag = $($(target_stem)_BOOT_LOADER_FLAG) + +elf2dat_extra_args = $(mem_pad_flag) +elf2hex_extra_args = $(mem_no_zero_fill_flag) +elf2flash_extra_args = $(flash_mem_cfi_flag) $(flash_mem_epcs_flag) $(flash_mem_boot_loader_flag) +flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag) + +#------------------------------------------------------------------------------ +# BSP SPECIFIC CONTENT +# +# The content below is controlled by the BSP and SOPC System +#------------------------------------------------------------------------------ +#START OF BSP SPECIFIC + +#------------------------------------- +# Global Settings +#------------------------------------- + + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_MEMINIT_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +# Optimize for simulation +SIM_OPTIMIZE ?= 0 + +# The CPU reset address as needed by elf2flash +RESET_ADDRESS ?= 0x00000000 + +#------------------------------------- +# Pre-Initialized Memory Descriptions +#------------------------------------- + +# Memory: onchip_memory +MEM_0 := nios_system_onchip_memory +$(MEM_0)_NAME := onchip_memory +$(MEM_0)_MEM_INIT_FILE_PARAM_NAME := INIT_FILE +HEX_FILES += $(MEM_INIT_DIR)/$(MEM_0).hex +MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_0).hex +DAT_FILES += $(HDL_SIM_DIR)/$(MEM_0).dat +HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat +SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym +HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym +$(MEM_0)_START := 0x00000000 +$(MEM_0)_END := 0x00031fff +$(MEM_0)_HIERARCHICAL_PATH := onchip_memory +$(MEM_0)_WIDTH := 32 +$(MEM_0)_ENDIANNESS := --little-endian-mem +$(MEM_0)_CREATE_LANES := 0 + +.PHONY: onchip_memory +onchip_memory: check_elf_exists $(MEM_INIT_DIR)/$(MEM_0).hex $(HDL_SIM_DIR)/$(MEM_0).dat $(HDL_SIM_DIR)/$(MEM_0).sym + + +#END OF BSP SPECIFIC + +#------------------------------------- +# Pre-Initialized Memory Targets +#------------------------------------- + +.PHONY: mem_init_install mem_init_generate mem_init_clean + +ifeq ($(QSYS),1) +# Target mem_init_install is deprecated for QSys based systems +# To initialize onchip memories for Quartus II Synthesis with Qsys based systems: +# 1) Use "make mem_init_genearate" +# 2) Add the generated mem_init/meminit.qip file to your Quartus II Project +# +mem_init_install: + $(error Deprecated Makefile Target: '$@'. Use target 'mem_init_generate' and then add $(MEM_INIT_QIP_FILE) to your Quartus II Project) + +else # QSYS != 1, if SopcBuilder based system + +ifneq ($(MEM_INIT_INSTALL_DIR),) +mem_init_install: $(MEM_INIT_INSTALL_FILES) +endif + +ifneq ($(HDL_SIM_INSTALL_DIR),) +mem_init_install: $(HDL_SIM_INSTALL_FILES) +endif + +mem_init_install: mem_init_generate +ifeq ($(MEM_INIT_INSTALL_DIR),) + @echo "WARNING: MEM_INIT_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR environment variable." +endif +ifeq ($(HDL_SIM_INSTALL_DIR),) + @echo "WARNING: HDL_SIM_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR and SOPC_NAME environment variable." +endif + +$(MEM_INIT_INSTALL_FILES): $(MEM_INIT_INSTALL_DIR)/%: $(MEM_INIT_DIR)/% + @$(MKDIR) $(@D) + @$(CP) -v $< $@ + +$(HDL_SIM_INSTALL_FILES): $(HDL_SIM_INSTALL_DIR)/%: $(HDL_SIM_DIR)/% + @$(MKDIR) $(@D) + @$(CP) -v $< $@ + +endif # QSYS == 1 + + +mem_init_generate: hex dat sym flash $(MEM_INIT_DESCRIPTOR_FILE) $(MEM_INIT_QIP_FILE) + +mem_init_clean: + @$(RM) -r $(MEM_INIT_DIR) $(HDL_SIM_DIR) $(FLASH_FILES) + +.PHONY: hex dat sym flash + +hex: check_elf_exists $(HEX_FILES) + +dat: check_elf_exists $(DAT_FILES) + +sym: check_elf_exists $(SYM_FILES) + +flash: check_elf_exists $(FLASH_FILES) + +#------------------------------------- +# Pre-Initialized Memory Rules +#------------------------------------- + +.PHONY: check_elf_exists +check_elf_exists: $(ELF) +ifeq ($(ELF),) + $(error ELF var not set in mem_init.mk) +endif + +$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2DAT) --infile=$< --outfile=$@ \ + --base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \ + $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)' + +$(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat + @true + +$(HEX_FILES): %.hex: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_width) \ + $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@' + +$(SYM_FILES): %.sym: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + $(NM) -n $< > $@ + +$(FLASH_FILES): %.flash: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2FLASH) --input=$< --outfile=$@ --sim_optimize=$(SIM_OPTIMIZE) $(mem_endianness) \ + $(elf2flash_extra_args)' + +# +# Function generate_spd_entry +# Arg1: path to the memory initialization file +# Arg2: Type HEX or DAT +# Arg3: Output spd file to append +gen_spd_entry.BASE_FILE = $(basename $(notdir $1)) +gen_spd_entry.PARAM_NAME = $($(gen_spd_entry.BASE_FILE)_MEM_INIT_FILE_PARAM_NAME) +gen_spd_entry.MEM_PATH = $($(gen_spd_entry.BASE_FILE)_HIERARCHICAL_PATH) +gen_spd_entry.SETTINGS = $(strip \ + path=\"$1\" \ + type=\"$2\" \ + $(if $(gen_spd_entry.PARAM_NAME),initParamName=\"$(gen_spd_entry.PARAM_NAME)\") \ + $(if $(gen_spd_entry.MEM_PATH),memoryPath=\"$(gen_spd_entry.MEM_PATH)\") \ +) +define gen_spd_entry +$(ECHO) "" >> $3 +endef + +$(MEM_INIT_DESCRIPTOR_FILE).DAT_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(DAT_FILES)) +$(MEM_INIT_DESCRIPTOR_FILE).HEX_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(HEX_FILES)) + +$(MEM_INIT_DESCRIPTOR_FILE): %.spd: $(MEM_INIT_FILE) + $(post-process-info) + @$(MKDIR) $(@D) + @$(RM) $@ + @$(ECHO) "" > $@ + @$(ECHO) "" >> $@ + @$(foreach dat_file,$($@.DAT_FILESET),$(call gen_spd_entry,$(dat_file),DAT,$@) &&)true + @$(foreach hex_file,$($@.HEX_FILESET),$(call gen_spd_entry,$(hex_file),HEX,$@) &&)true + @$(ECHO) "" >> $@ + +.DELETE_ON_ERROR: $(MEM_INIT_DESCRIPTOR_FILE) + +$(MEM_INIT_QIP_FILE): %.qip: $(MEM_INIT_FILE) + $(post-process-info) + @$(MKDIR) $(@D) + @$(RM) $@ + @$(ECHO) "set_global_assignment -name SEARCH_PATH $$::quartus(qip_path)" > $@ + +.DELETE_ON_ERROR: $(MEM_INIT_QIP_FILE) diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_alarm_start.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_alarm_start.d index 3bb20ea..a293917 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_alarm_start.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_alarm_start.d @@ -1,22 +1,22 @@ -obj/HAL/src/alt_alarm_start.o: HAL/src/alt_alarm_start.c \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ - HAL/inc/nios2.h system.h linker.h - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -system.h: - -linker.h: +obj/HAL/src/alt_alarm_start.o: HAL/src/alt_alarm_start.c \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h linker.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_busy_sleep.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_busy_sleep.d index e93e80c..0441737 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_busy_sleep.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_busy_sleep.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_busy_sleep.o: HAL/src/alt_busy_sleep.c system.h linker.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_busy_sleep.h - -system.h: - -linker.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_busy_sleep.h: +obj/HAL/src/alt_busy_sleep.o: HAL/src/alt_busy_sleep.c system.h linker.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_busy_sleep.h + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_busy_sleep.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_close.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_close.d index fbbab9c..c678dc5 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_close.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_close.d @@ -1,34 +1,34 @@ -obj/HAL/src/alt_close.o: HAL/src/alt_close.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ - HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_close.o: HAL/src/alt_close.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush.d index a0eaf8a..cc01756 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush.d @@ -1,15 +1,15 @@ -obj/HAL/src/alt_dcache_flush.o: HAL/src/alt_dcache_flush.c \ - HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ - HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h - -HAL/inc/nios2.h: - -system.h: - -linker.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_dcache_flush.o: HAL/src/alt_dcache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush_all.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush_all.d index 792c3e4..9b4b55d 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush_all.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush_all.d @@ -1,15 +1,15 @@ -obj/HAL/src/alt_dcache_flush_all.o: HAL/src/alt_dcache_flush_all.c \ - HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ - HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h - -HAL/inc/nios2.h: - -system.h: - -linker.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_dcache_flush_all.o: HAL/src/alt_dcache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d index 867c42b..a1291f0 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d @@ -1,16 +1,16 @@ -obj/HAL/src/alt_dcache_flush_no_writeback.o: \ - HAL/src/alt_dcache_flush_no_writeback.c HAL/inc/nios2.h system.h \ - linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h \ - HAL/inc/alt_types.h - -HAL/inc/nios2.h: - -system.h: - -linker.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_dcache_flush_no_writeback.o: \ + HAL/src/alt_dcache_flush_no_writeback.c HAL/inc/nios2.h system.h \ + linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h \ + HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dev.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dev.d index cd9b1d4..89b9883 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dev.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dev.d @@ -1,34 +1,34 @@ -obj/HAL/src/alt_dev.o: HAL/src/alt_dev.c HAL/inc/sys/alt_dev.h system.h \ - linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ - HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ - system.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/alt_types.h: - -system.h: +obj/HAL/src/alt_dev.o: HAL/src/alt_dev.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dev_llist_insert.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dev_llist_insert.d index 344d065..f23980f 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dev_llist_insert.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dev_llist_insert.d @@ -1,13 +1,13 @@ -obj/HAL/src/alt_dev_llist_insert.o: HAL/src/alt_dev_llist_insert.c \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_errno.h: +obj/HAL/src/alt_dev_llist_insert.o: HAL/src/alt_dev_llist_insert.c \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dma_rxchan_open.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dma_rxchan_open.d index fb21fed..71aa62d 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dma_rxchan_open.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dma_rxchan_open.d @@ -1,35 +1,35 @@ -obj/HAL/src/alt_dma_rxchan_open.o: HAL/src/alt_dma_rxchan_open.c \ - HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ - HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ - HAL/inc/sys/alt_llist.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h - -HAL/inc/sys/alt_dma.h: - -HAL/inc/sys/alt_dma_dev.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_errno.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: +obj/HAL/src/alt_dma_rxchan_open.o: HAL/src/alt_dma_rxchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dma_txchan_open.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dma_txchan_open.d index 500b95c..2a33dba 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dma_txchan_open.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_dma_txchan_open.d @@ -1,35 +1,35 @@ -obj/HAL/src/alt_dma_txchan_open.o: HAL/src/alt_dma_txchan_open.c \ - HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ - HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ - HAL/inc/sys/alt_llist.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h - -HAL/inc/sys/alt_dma.h: - -HAL/inc/sys/alt_dma_dev.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_errno.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: +obj/HAL/src/alt_dma_txchan_open.o: HAL/src/alt_dma_txchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_do_ctors.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_do_ctors.d index daf8baf..0898fbc 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_do_ctors.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_do_ctors.d @@ -1 +1 @@ -obj/HAL/src/alt_do_ctors.o: HAL/src/alt_do_ctors.c +obj/HAL/src/alt_do_ctors.o: HAL/src/alt_do_ctors.c diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_do_dtors.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_do_dtors.d index c3471eb..abdadfa 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_do_dtors.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_do_dtors.d @@ -1 +1 @@ -obj/HAL/src/alt_do_dtors.o: HAL/src/alt_do_dtors.c +obj/HAL/src/alt_do_dtors.o: HAL/src/alt_do_dtors.c diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_env_lock.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_env_lock.d index 634d7b0..fd8a733 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_env_lock.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_env_lock.d @@ -1 +1 @@ -obj/HAL/src/alt_env_lock.o: HAL/src/alt_env_lock.c +obj/HAL/src/alt_env_lock.o: HAL/src/alt_env_lock.c diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_environ.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_environ.d index e9ca295..b622e4b 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_environ.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_environ.d @@ -1,3 +1,3 @@ -obj/HAL/src/alt_environ.o: HAL/src/alt_environ.c HAL/inc/os/alt_syscall.h - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_environ.o: HAL/src/alt_environ.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_errno.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_errno.d index 29ca544..51c7dcd 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_errno.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_errno.d @@ -1,8 +1,8 @@ -obj/HAL/src/alt_errno.o: HAL/src/alt_errno.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/alt_types.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_errno.o: HAL/src/alt_errno.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_entry.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_entry.d index 540567e..7960631 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_entry.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_entry.d @@ -1,6 +1,6 @@ -obj/HAL/src/alt_exception_entry.o: HAL/src/alt_exception_entry.S system.h \ - linker.h - -system.h: - -linker.h: +obj/HAL/src/alt_exception_entry.o: HAL/src/alt_exception_entry.S system.h \ + linker.h + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_muldiv.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_muldiv.d index 63d66a7..a1e5556 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_muldiv.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_muldiv.d @@ -1 +1 @@ -obj/HAL/src/alt_exception_muldiv.o: HAL/src/alt_exception_muldiv.S +obj/HAL/src/alt_exception_muldiv.o: HAL/src/alt_exception_muldiv.S diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_trap.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_trap.d index 6e18488..ef4edc6 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_trap.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exception_trap.d @@ -1 +1 @@ -obj/HAL/src/alt_exception_trap.o: HAL/src/alt_exception_trap.S +obj/HAL/src/alt_exception_trap.o: HAL/src/alt_exception_trap.S diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_execve.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_execve.d index 9cef7d2..0060a9d 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_execve.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_execve.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_execve.o: HAL/src/alt_execve.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_execve.o: HAL/src/alt_execve.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exit.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exit.d index a779da8..09ed618 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exit.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_exit.d @@ -1,26 +1,26 @@ -obj/HAL/src/alt_exit.o: HAL/src/alt_exit.c HAL/inc/sys/alt_irq.h \ - HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ - HAL/inc/sys/alt_sim.h HAL/inc/os/alt_hooks.h HAL/inc/os/alt_syscall.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_log_printf.h system.h - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_sim.h: - -HAL/inc/os/alt_hooks.h: - -HAL/inc/os/alt_syscall.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_log_printf.h: - -system.h: +obj/HAL/src/alt_exit.o: HAL/src/alt_exit.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_sim.h HAL/inc/os/alt_hooks.h HAL/inc/os/alt_syscall.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_sim.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fcntl.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fcntl.d index 527f242..b8835a6 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fcntl.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fcntl.d @@ -1,34 +1,34 @@ -obj/HAL/src/alt_fcntl.o: HAL/src/alt_fcntl.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ - system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ - HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_fcntl.o: HAL/src/alt_fcntl.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fd_lock.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fd_lock.d index 93daeac..f6d94e1 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fd_lock.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fd_lock.d @@ -1,27 +1,27 @@ -obj/HAL/src/alt_fd_lock.o: HAL/src/alt_fd_lock.c HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: +obj/HAL/src/alt_fd_lock.o: HAL/src/alt_fd_lock.c HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fd_unlock.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fd_unlock.d index 45a3207..9778463 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fd_unlock.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fd_unlock.d @@ -1,27 +1,27 @@ -obj/HAL/src/alt_fd_unlock.o: HAL/src/alt_fd_unlock.c \ - HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: +obj/HAL/src/alt_fd_unlock.o: HAL/src/alt_fd_unlock.c \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_find_dev.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_find_dev.d index 98336f8..7b37308 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_find_dev.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_find_dev.d @@ -1,31 +1,31 @@ -obj/HAL/src/alt_find_dev.o: HAL/src/alt_find_dev.c HAL/inc/sys/alt_dev.h \ - system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ - HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_find_dev.o: HAL/src/alt_find_dev.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_find_file.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_find_file.d index d1150ca..4f15c6d 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_find_file.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_find_file.d @@ -1,32 +1,32 @@ -obj/HAL/src/alt_find_file.o: HAL/src/alt_find_file.c \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ - HAL/inc/alt_types.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_find_file.o: HAL/src/alt_find_file.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_flash_dev.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_flash_dev.d index 8835e8f..e665b37 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_flash_dev.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_flash_dev.d @@ -1,34 +1,34 @@ -obj/HAL/src/alt_flash_dev.o: HAL/src/alt_flash_dev.c \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/sys/alt_flash_dev.h \ - HAL/inc/sys/alt_flash_types.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ - system.h linker.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_flash_dev.h: - -HAL/inc/sys/alt_flash_types.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: +obj/HAL/src/alt_flash_dev.o: HAL/src/alt_flash_dev.c \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/sys/alt_flash_dev.h \ + HAL/inc/sys/alt_flash_types.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_flash_dev.h: + +HAL/inc/sys/alt_flash_types.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fork.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fork.d index 492be65..ef5b637 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fork.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fork.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_fork.o: HAL/src/alt_fork.c HAL/inc/sys/alt_warning.h \ - HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_warning.h: - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_fork.o: HAL/src/alt_fork.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fs_reg.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fs_reg.d index d8f95ab..f56b56f 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fs_reg.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fs_reg.d @@ -1,29 +1,29 @@ -obj/HAL/src/alt_fs_reg.o: HAL/src/alt_fs_reg.c HAL/inc/sys/alt_dev.h \ - system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ - HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: +obj/HAL/src/alt_fs_reg.o: HAL/src/alt_fs_reg.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fstat.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fstat.d index 0d021b8..b1c4a1e 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fstat.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_fstat.d @@ -1,36 +1,36 @@ -obj/HAL/src/alt_fstat.o: HAL/src/alt_fstat.c HAL/inc/sys/alt_dev.h \ - system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_errno.h \ - HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/sys/alt_errno.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_fstat.o: HAL/src/alt_fstat.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_get_fd.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_get_fd.d index 9a4daaa..5524f68 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_get_fd.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_get_fd.d @@ -1,34 +1,34 @@ -obj/HAL/src/alt_get_fd.o: HAL/src/alt_get_fd.c HAL/inc/sys/alt_dev.h \ - system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ - HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ - system.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/alt_types.h: - -system.h: +obj/HAL/src/alt_get_fd.o: HAL/src/alt_get_fd.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_getchar.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_getchar.d index 2a468de..aa88591 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_getchar.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_getchar.d @@ -1 +1 @@ -obj/HAL/src/alt_getchar.o: HAL/src/alt_getchar.c +obj/HAL/src/alt_getchar.o: HAL/src/alt_getchar.c diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_getpid.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_getpid.d index d9499b9..365651b 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_getpid.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_getpid.d @@ -1,3 +1,3 @@ -obj/HAL/src/alt_getpid.o: HAL/src/alt_getpid.c HAL/inc/os/alt_syscall.h - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_getpid.o: HAL/src/alt_getpid.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_gettod.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_gettod.d index cf3cf34..ffd23b8 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_gettod.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_gettod.d @@ -1,17 +1,17 @@ -obj/HAL/src/alt_gettod.o: HAL/src/alt_gettod.c HAL/inc/sys/alt_alarm.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ - HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_gettod.o: HAL/src/alt_gettod.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_gmon.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_gmon.d index e9469ab..6a213bf 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_gmon.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_gmon.d @@ -1,24 +1,24 @@ -obj/HAL/src/alt_gmon.o: HAL/src/alt_gmon.c HAL/inc/priv/nios2_gmon_data.h \ - HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ - linker.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h - -HAL/inc/priv/nios2_gmon_data.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_gmon.o: HAL/src/alt_gmon.c HAL/inc/priv/nios2_gmon_data.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h + +HAL/inc/priv/nios2_gmon_data.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_icache_flush.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_icache_flush.d index 2e4ddd1..a6048d7 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_icache_flush.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_icache_flush.d @@ -1,15 +1,15 @@ -obj/HAL/src/alt_icache_flush.o: HAL/src/alt_icache_flush.c \ - HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ - HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h - -HAL/inc/nios2.h: - -system.h: - -linker.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_icache_flush.o: HAL/src/alt_icache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_icache_flush_all.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_icache_flush_all.d index 47cfbf3..19ee42e 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_icache_flush_all.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_icache_flush_all.d @@ -1,15 +1,15 @@ -obj/HAL/src/alt_icache_flush_all.o: HAL/src/alt_icache_flush_all.c \ - HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ - HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h - -HAL/inc/nios2.h: - -system.h: - -linker.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_icache_flush_all.o: HAL/src/alt_icache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_iic.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_iic.d index a709e0c..444ca68 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_iic.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_iic.d @@ -1,29 +1,29 @@ -obj/HAL/src/alt_iic.o: HAL/src/alt_iic.c system.h linker.h \ - HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ - HAL/inc/priv/alt_iic_isr_register.h HAL/inc/alt_types.h \ - HAL/inc/sys/alt_irq.h HAL/inc/priv/alt_legacy_irq.h system.h \ - HAL/inc/nios2.h - -system.h: - -linker.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -HAL/inc/priv/alt_iic_isr_register.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/priv/alt_legacy_irq.h: - -system.h: - -HAL/inc/nios2.h: +obj/HAL/src/alt_iic.o: HAL/src/alt_iic.c system.h linker.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_iic_isr_register.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_irq.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_iic_isr_register.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_iic_isr_register.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_iic_isr_register.d index d0470ae..93b9138 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_iic_isr_register.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_iic_isr_register.d @@ -1,30 +1,30 @@ -obj/HAL/src/alt_iic_isr_register.o: HAL/src/alt_iic_isr_register.c \ - system.h linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ - HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ - HAL/inc/priv/alt_iic_isr_register.h HAL/inc/alt_types.h \ - HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_irq_entry.h \ - HAL/inc/priv/alt_irq_table.h - -system.h: - -linker.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -HAL/inc/priv/alt_iic_isr_register.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/sys/alt_irq_entry.h: - -HAL/inc/priv/alt_irq_table.h: +obj/HAL/src/alt_iic_isr_register.o: HAL/src/alt_iic_isr_register.c \ + system.h linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_iic_isr_register.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_irq_entry.h \ + HAL/inc/priv/alt_irq_table.h + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_iic_isr_register.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_irq_entry.h: + +HAL/inc/priv/alt_irq_table.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_instruction_exception_entry.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_instruction_exception_entry.d index 6d0705f..f91b75a 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_instruction_exception_entry.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_instruction_exception_entry.d @@ -1,18 +1,18 @@ -obj/HAL/src/alt_instruction_exception_entry.o: \ - HAL/src/alt_instruction_exception_entry.c HAL/inc/sys/alt_exceptions.h \ - HAL/inc/alt_types.h system.h linker.h HAL/inc/nios2.h \ - HAL/inc/alt_types.h system.h - -HAL/inc/sys/alt_exceptions.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: +obj/HAL/src/alt_instruction_exception_entry.o: \ + HAL/src/alt_instruction_exception_entry.c HAL/inc/sys/alt_exceptions.h \ + HAL/inc/alt_types.h system.h linker.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_instruction_exception_register.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_instruction_exception_register.d index d4fac04..24c4435 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_instruction_exception_register.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_instruction_exception_register.d @@ -1,16 +1,16 @@ -obj/HAL/src/alt_instruction_exception_register.o: \ - HAL/src/alt_instruction_exception_register.c \ - HAL/inc/sys/alt_exceptions.h HAL/inc/alt_types.h system.h linker.h \ - HAL/inc/alt_types.h system.h - -HAL/inc/sys/alt_exceptions.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/alt_types.h: - -system.h: +obj/HAL/src/alt_instruction_exception_register.o: \ + HAL/src/alt_instruction_exception_register.c \ + HAL/inc/sys/alt_exceptions.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_io_redirect.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_io_redirect.d index 8228365..d84ac28 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_io_redirect.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_io_redirect.d @@ -1,29 +1,29 @@ -obj/HAL/src/alt_io_redirect.o: HAL/src/alt_io_redirect.c \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: +obj/HAL/src/alt_io_redirect.o: HAL/src/alt_io_redirect.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_ioctl.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_ioctl.d index 5a705e4..0b46e82 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_ioctl.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_ioctl.d @@ -1,36 +1,36 @@ -obj/HAL/src/alt_ioctl.o: HAL/src/alt_ioctl.c HAL/inc/sys/ioctl.h \ - HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ - HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ - HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/ioctl.h: - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_ioctl.o: HAL/src/alt_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_entry.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_entry.d index 9ec3751..c2477c1 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_entry.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_entry.d @@ -1,5 +1,5 @@ -obj/HAL/src/alt_irq_entry.o: HAL/src/alt_irq_entry.S system.h linker.h - -system.h: - -linker.h: +obj/HAL/src/alt_irq_entry.o: HAL/src/alt_irq_entry.S system.h linker.h + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_handler.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_handler.d index 6fb668f..c6ee821 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_handler.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_handler.d @@ -1,19 +1,19 @@ -obj/HAL/src/alt_irq_handler.o: HAL/src/alt_irq_handler.c system.h \ - linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ - system.h HAL/inc/os/alt_hooks.h HAL/inc/alt_types.h - -system.h: - -linker.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -HAL/inc/os/alt_hooks.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_irq_handler.o: HAL/src/alt_irq_handler.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/os/alt_hooks.h HAL/inc/alt_types.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_register.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_register.d index 3df2f8a..ad1830e 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_register.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_register.d @@ -1,36 +1,36 @@ -obj/HAL/src/alt_irq_register.o: HAL/src/alt_irq_register.c system.h \ - linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ - system.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/os/alt_hooks.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_irq_entry.h \ - HAL/inc/priv/alt_irq_table.h - -system.h: - -linker.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -HAL/inc/priv/alt_legacy_irq.h: - -system.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/os/alt_hooks.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_irq_entry.h: - -HAL/inc/priv/alt_irq_table.h: +obj/HAL/src/alt_irq_register.o: HAL/src/alt_irq_register.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/os/alt_hooks.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq_entry.h \ + HAL/inc/priv/alt_irq_table.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq_entry.h: + +HAL/inc/priv/alt_irq_table.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_vars.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_vars.d index f316558..c339fc6 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_vars.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_irq_vars.d @@ -1,8 +1,8 @@ -obj/HAL/src/alt_irq_vars.o: HAL/src/alt_irq_vars.c HAL/inc/alt_types.h \ - system.h linker.h - -HAL/inc/alt_types.h: - -system.h: - -linker.h: +obj/HAL/src/alt_irq_vars.o: HAL/src/alt_irq_vars.c HAL/inc/alt_types.h \ + system.h linker.h + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_isatty.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_isatty.d index 4a21885..1b9868b 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_isatty.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_isatty.d @@ -1,36 +1,36 @@ -obj/HAL/src/alt_isatty.o: HAL/src/alt_isatty.c HAL/inc/sys/alt_dev.h \ - system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h HAL/inc/sys/alt_warning.h \ - HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_errno.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_isatty.o: HAL/src/alt_isatty.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_kill.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_kill.d index 0c14ae8..7ced1b6 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_kill.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_kill.d @@ -1,8 +1,8 @@ -obj/HAL/src/alt_kill.o: HAL/src/alt_kill.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_kill.o: HAL/src/alt_kill.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_link.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_link.d index dc844c6..2156c3d 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_link.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_link.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_link.o: HAL/src/alt_link.c HAL/inc/sys/alt_warning.h \ - HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_warning.h: - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_link.o: HAL/src/alt_link.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_load.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_load.d index d496ab8..ff64508 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_load.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_load.d @@ -1,8 +1,8 @@ -obj/HAL/src/alt_load.o: HAL/src/alt_load.c HAL/inc/sys/alt_load.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h - -HAL/inc/sys/alt_load.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_cache.h: +obj/HAL/src/alt_load.o: HAL/src/alt_load.c HAL/inc/sys/alt_load.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h + +HAL/inc/sys/alt_load.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_log_macro.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_log_macro.d index 9768c1f..b6c30c4 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_log_macro.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_log_macro.d @@ -1 +1 @@ -obj/HAL/src/alt_log_macro.o: HAL/src/alt_log_macro.S +obj/HAL/src/alt_log_macro.o: HAL/src/alt_log_macro.S diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_log_printf.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_log_printf.d index 251ff6d..ddd7cdb 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_log_printf.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_log_printf.d @@ -1 +1 @@ -obj/HAL/src/alt_log_printf.o: HAL/src/alt_log_printf.c +obj/HAL/src/alt_log_printf.o: HAL/src/alt_log_printf.c diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_lseek.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_lseek.d index 25ed783..a103673 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_lseek.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_lseek.d @@ -1,34 +1,34 @@ -obj/HAL/src/alt_lseek.o: HAL/src/alt_lseek.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ - HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_lseek.o: HAL/src/alt_lseek.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_main.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_main.d index afdfda0..67b6a7b 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_main.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_main.d @@ -1,47 +1,47 @@ -obj/HAL/src/alt_main.o: HAL/src/alt_main.c HAL/inc/sys/alt_dev.h system.h \ - linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_sys_init.h HAL/inc/sys/alt_irq.h \ - HAL/inc/nios2.h HAL/inc/os/alt_hooks.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ - HAL/inc/alt_types.h system.h HAL/inc/sys/alt_log_printf.h system.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_sys_init.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/os/alt_hooks.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/alt_types.h: - -system.h: - -HAL/inc/sys/alt_log_printf.h: - -system.h: +obj/HAL/src/alt_main.o: HAL/src/alt_main.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_sys_init.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/os/alt_hooks.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h system.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_malloc_lock.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_malloc_lock.d index 4ed35c2..981b056 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_malloc_lock.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_malloc_lock.d @@ -1 +1 @@ -obj/HAL/src/alt_malloc_lock.o: HAL/src/alt_malloc_lock.c +obj/HAL/src/alt_malloc_lock.o: HAL/src/alt_malloc_lock.c diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_mcount.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_mcount.d index 1203efc..4fa3643 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_mcount.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_mcount.d @@ -1 +1 @@ -obj/HAL/src/alt_mcount.o: HAL/src/alt_mcount.S +obj/HAL/src/alt_mcount.o: HAL/src/alt_mcount.S diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_open.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_open.d index a2aacd9..a5c2358 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_open.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_open.d @@ -1,36 +1,36 @@ -obj/HAL/src/alt_open.o: HAL/src/alt_open.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_open.o: HAL/src/alt_open.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_printf.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_printf.d index 3ce68a4..0fe3550 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_printf.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_printf.d @@ -1,3 +1,3 @@ -obj/HAL/src/alt_printf.o: HAL/src/alt_printf.c HAL/inc/sys/alt_stdio.h - -HAL/inc/sys/alt_stdio.h: +obj/HAL/src/alt_printf.o: HAL/src/alt_printf.c HAL/inc/sys/alt_stdio.h + +HAL/inc/sys/alt_stdio.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_putchar.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_putchar.d index 0f19fb8..fa6d19f 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_putchar.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_putchar.d @@ -1 +1 @@ -obj/HAL/src/alt_putchar.o: HAL/src/alt_putchar.c +obj/HAL/src/alt_putchar.o: HAL/src/alt_putchar.c diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_putstr.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_putstr.d index ed03fdc..a28ce55 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_putstr.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_putstr.d @@ -1 +1 @@ -obj/HAL/src/alt_putstr.o: HAL/src/alt_putstr.c +obj/HAL/src/alt_putstr.o: HAL/src/alt_putstr.c diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_read.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_read.d index 4081a45..f5d459d 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_read.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_read.d @@ -1,34 +1,34 @@ -obj/HAL/src/alt_read.o: HAL/src/alt_read.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ - HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_read.o: HAL/src/alt_read.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_release_fd.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_release_fd.d index 0e3acb5..137f496 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_release_fd.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_release_fd.d @@ -1,29 +1,29 @@ -obj/HAL/src/alt_release_fd.o: HAL/src/alt_release_fd.c \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: +obj/HAL/src/alt_release_fd.o: HAL/src/alt_release_fd.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_remap_cached.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_remap_cached.d index b5fb151..abacaa4 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_remap_cached.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_remap_cached.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_remap_cached.o: HAL/src/alt_remap_cached.c \ - HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: +obj/HAL/src/alt_remap_cached.o: HAL/src/alt_remap_cached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_remap_uncached.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_remap_uncached.d index 0423405..19b8e4c 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_remap_uncached.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_remap_uncached.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_remap_uncached.o: HAL/src/alt_remap_uncached.c \ - HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: +obj/HAL/src/alt_remap_uncached.o: HAL/src/alt_remap_uncached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_rename.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_rename.d index b7af4b2..f16ad38 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_rename.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_rename.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_rename.o: HAL/src/alt_rename.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_rename.o: HAL/src/alt_rename.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_sbrk.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_sbrk.d index a0771ae..cc6de28 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_sbrk.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_sbrk.d @@ -1,19 +1,19 @@ -obj/HAL/src/alt_sbrk.o: HAL/src/alt_sbrk.c HAL/inc/os/alt_syscall.h \ - HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ - linker.h HAL/inc/sys/alt_stack.h system.h - -HAL/inc/os/alt_syscall.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_stack.h: - -system.h: +obj/HAL/src/alt_sbrk.o: HAL/src/alt_sbrk.c HAL/inc/os/alt_syscall.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/sys/alt_stack.h system.h + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_stack.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_settod.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_settod.d index 56718d5..f8e7109 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_settod.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_settod.d @@ -1,17 +1,17 @@ -obj/HAL/src/alt_settod.o: HAL/src/alt_settod.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_settod.o: HAL/src/alt_settod.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_software_exception.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_software_exception.d index fab4023..d17d10b 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_software_exception.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_software_exception.d @@ -1,6 +1,6 @@ -obj/HAL/src/alt_software_exception.o: HAL/src/alt_software_exception.S \ - system.h linker.h - -system.h: - -linker.h: +obj/HAL/src/alt_software_exception.o: HAL/src/alt_software_exception.S \ + system.h linker.h + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_stat.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_stat.d index 8a63c27..b66e05e 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_stat.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_stat.d @@ -1,3 +1,3 @@ -obj/HAL/src/alt_stat.o: HAL/src/alt_stat.c HAL/inc/os/alt_syscall.h - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_stat.o: HAL/src/alt_stat.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_tick.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_tick.d index ddbb281..88d8e2a 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_tick.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_tick.d @@ -1,27 +1,27 @@ -obj/HAL/src/alt_tick.o: HAL/src/alt_tick.c HAL/inc/sys/alt_irq.h \ - HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_hooks.h \ - HAL/inc/alt_types.h - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_hooks.h: - -HAL/inc/alt_types.h: +obj/HAL/src/alt_tick.o: HAL/src/alt_tick.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_hooks.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_times.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_times.d index 4bad83d..e0ded1e 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_times.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_times.d @@ -1,17 +1,17 @@ -obj/HAL/src/alt_times.o: HAL/src/alt_times.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_times.o: HAL/src/alt_times.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_uncached_free.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_uncached_free.d index d74ef4b..7d5ae2b 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_uncached_free.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_uncached_free.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_uncached_free.o: HAL/src/alt_uncached_free.c \ - HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: +obj/HAL/src/alt_uncached_free.o: HAL/src/alt_uncached_free.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_uncached_malloc.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_uncached_malloc.d index 16799fb..05d57d8 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_uncached_malloc.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_uncached_malloc.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_uncached_malloc.o: HAL/src/alt_uncached_malloc.c \ - HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h - -HAL/inc/sys/alt_cache.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: +obj/HAL/src/alt_uncached_malloc.o: HAL/src/alt_uncached_malloc.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_unlink.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_unlink.d index 0205f86..04b6dcd 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_unlink.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_unlink.d @@ -1,10 +1,10 @@ -obj/HAL/src/alt_unlink.o: HAL/src/alt_unlink.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_unlink.o: HAL/src/alt_unlink.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_usleep.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_usleep.d index b5eca45..c3ccee2 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_usleep.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_usleep.d @@ -1,6 +1,6 @@ -obj/HAL/src/alt_usleep.o: HAL/src/alt_usleep.c \ - HAL/inc/priv/alt_busy_sleep.h HAL/inc/os/alt_syscall.h - -HAL/inc/priv/alt_busy_sleep.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_usleep.o: HAL/src/alt_usleep.c \ + HAL/inc/priv/alt_busy_sleep.h HAL/inc/os/alt_syscall.h + +HAL/inc/priv/alt_busy_sleep.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_wait.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_wait.d index f47f5df..98bf5df 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_wait.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_wait.d @@ -1,8 +1,8 @@ -obj/HAL/src/alt_wait.o: HAL/src/alt_wait.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_syscall.h: +obj/HAL/src/alt_wait.o: HAL/src/alt_wait.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_write.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_write.d index 0bc4b7c..722e8bc 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_write.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/alt_write.d @@ -1,38 +1,38 @@ -obj/HAL/src/alt_write.o: HAL/src/alt_write.c HAL/inc/sys/alt_errno.h \ - HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ - HAL/inc/os/alt_syscall.h HAL/inc/sys/alt_log_printf.h system.h - -HAL/inc/sys/alt_errno.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/priv/alt_file.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_syscall.h: - -HAL/inc/sys/alt_log_printf.h: - -system.h: +obj/HAL/src/alt_write.o: HAL/src/alt_write.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/altera_nios2_qsys_irq.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/altera_nios2_qsys_irq.d index 47bdd9c..45223c8 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/altera_nios2_qsys_irq.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/altera_nios2_qsys_irq.d @@ -1,15 +1,15 @@ -obj/HAL/src/altera_nios2_qsys_irq.o: HAL/src/altera_nios2_qsys_irq.c \ - HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ - linker.h HAL/inc/altera_nios2_qsys_irq.h - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/altera_nios2_qsys_irq.h: +obj/HAL/src/altera_nios2_qsys_irq.o: HAL/src/altera_nios2_qsys_irq.c \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/altera_nios2_qsys_irq.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/altera_nios2_qsys_irq.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/crt0.d b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/crt0.d index 3af0bb0..c1049a0 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/crt0.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/HAL/src/crt0.d @@ -1,12 +1,12 @@ -obj/HAL/src/crt0.o: HAL/src/crt0.S system.h linker.h HAL/inc/nios2.h \ - HAL/inc/sys/alt_log_printf.h system.h - -system.h: - -linker.h: - -HAL/inc/nios2.h: - -HAL/inc/sys/alt_log_printf.h: - -system.h: +obj/HAL/src/crt0.o: HAL/src/crt0.S system.h linker.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_log_printf.h system.h + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/alt_sys_init.d b/software/qsys_tutorial_lcd4_bsp/obj/alt_sys_init.d index 029ebe0..df7e15a 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/alt_sys_init.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/alt_sys_init.d @@ -1,59 +1,59 @@ -obj/alt_sys_init.o: alt_sys_init.c system.h linker.h \ - HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ - HAL/inc/sys/alt_sys_init.h HAL/inc/altera_nios2_qsys_irq.h \ - drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ - HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ - HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ - drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ - HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h drivers/inc/altera_avalon_lcd_16207.h \ - drivers/inc/altera_avalon_lcd_16207_fd.h - -system.h: - -linker.h: - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -HAL/inc/sys/alt_sys_init.h: - -HAL/inc/altera_nios2_qsys_irq.h: - -drivers/inc/altera_avalon_jtag_uart.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_flag.h: - -drivers/inc/altera_avalon_jtag_uart_fd.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -drivers/inc/altera_avalon_lcd_16207.h: - -drivers/inc/altera_avalon_lcd_16207_fd.h: +obj/alt_sys_init.o: alt_sys_init.c system.h linker.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/sys/alt_sys_init.h HAL/inc/altera_nios2_qsys_irq.h \ + drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h drivers/inc/altera_avalon_lcd_16207.h \ + drivers/inc/altera_avalon_lcd_16207_fd.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/altera_nios2_qsys_irq.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d index b152697..5fd0251 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d @@ -1,48 +1,48 @@ -obj/drivers/src/altera_avalon_jtag_uart_fd.o: \ - drivers/src/altera_avalon_jtag_uart_fd.c HAL/inc/alt_types.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ - HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \ - HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ - drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_flag.h: - -drivers/inc/altera_avalon_jtag_uart_fd.h: - -HAL/inc/sys/alt_dev.h: +obj/drivers/src/altera_avalon_jtag_uart_fd.o: \ + drivers/src/altera_avalon_jtag_uart_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d index f9460a1..39101c1 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d @@ -1,66 +1,66 @@ -obj/drivers/src/altera_avalon_jtag_uart_init.o: \ - drivers/src/altera_avalon_jtag_uart_init.c HAL/inc/sys/alt_irq.h \ - HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ - HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ - HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ - drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ - HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/ioctl.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart_regs.h: - -HAL/inc/io.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_flag.h: - -drivers/inc/altera_avalon_jtag_uart_fd.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/sys/alt_log_printf.h: - -system.h: +obj/drivers/src/altera_avalon_jtag_uart_init.o: \ + drivers/src/altera_avalon_jtag_uart_init.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d index d75a559..39508a1 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d @@ -1,58 +1,58 @@ -obj/drivers/src/altera_avalon_jtag_uart_ioctl.o: \ - drivers/src/altera_avalon_jtag_uart_ioctl.c HAL/inc/sys/ioctl.h \ - HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ - HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ - HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ - drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h system.h \ - linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h - -HAL/inc/sys/ioctl.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart_regs.h: - -HAL/inc/io.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_flag.h: - -drivers/inc/altera_avalon_jtag_uart_fd.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/sys/alt_log_printf.h: - -system.h: +obj/drivers/src/altera_avalon_jtag_uart_ioctl.o: \ + drivers/src/altera_avalon_jtag_uart_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d index 9a4846a..915c27a 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d @@ -1,66 +1,66 @@ -obj/drivers/src/altera_avalon_jtag_uart_read.o: \ - drivers/src/altera_avalon_jtag_uart_read.c HAL/inc/sys/alt_irq.h \ - HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ - HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ - HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ - drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ - HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/ioctl.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart_regs.h: - -HAL/inc/io.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_flag.h: - -drivers/inc/altera_avalon_jtag_uart_fd.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/sys/alt_log_printf.h: - -system.h: +obj/drivers/src/altera_avalon_jtag_uart_read.o: \ + drivers/src/altera_avalon_jtag_uart_read.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d index 5518b7f..4e67aaa 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d @@ -1,66 +1,66 @@ -obj/drivers/src/altera_avalon_jtag_uart_write.o: \ - drivers/src/altera_avalon_jtag_uart_write.c HAL/inc/sys/alt_irq.h \ - HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ - HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ - HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ - drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ - HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h - -HAL/inc/sys/alt_irq.h: - -HAL/inc/nios2.h: - -HAL/inc/alt_types.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -HAL/inc/sys/ioctl.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart_regs.h: - -HAL/inc/io.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_jtag_uart.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_warning.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -HAL/inc/os/alt_flag.h: - -drivers/inc/altera_avalon_jtag_uart_fd.h: - -HAL/inc/sys/alt_dev.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/sys/alt_log_printf.h: - -system.h: +obj/drivers/src/altera_avalon_jtag_uart_write.o: \ + drivers/src/altera_avalon_jtag_uart_write.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_lcd_16207.d b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_lcd_16207.d index dfd0adb..238baea 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_lcd_16207.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_lcd_16207.d @@ -1,47 +1,47 @@ -obj/drivers/src/altera_avalon_lcd_16207.o: \ - drivers/src/altera_avalon_lcd_16207.c HAL/inc/sys/alt_alarm.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ - HAL/inc/alt_types.h drivers/inc/altera_avalon_lcd_16207_regs.h \ - HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_lcd_16207.h \ - HAL/inc/sys/alt_alarm.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h drivers/inc/altera_avalon_lcd_16207_fd.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_lcd_16207_regs.h: - -HAL/inc/io.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_lcd_16207.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -drivers/inc/altera_avalon_lcd_16207_fd.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: +obj/drivers/src/altera_avalon_lcd_16207.o: \ + drivers/src/altera_avalon_lcd_16207.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_lcd_16207_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_lcd_16207.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h drivers/inc/altera_avalon_lcd_16207_fd.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: diff --git a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d index b39dc1d..d45be02 100644 --- a/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d +++ b/software/qsys_tutorial_lcd4_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d @@ -1,43 +1,43 @@ -obj/drivers/src/altera_avalon_lcd_16207_fd.o: \ - drivers/src/altera_avalon_lcd_16207_fd.c HAL/inc/alt_types.h \ - HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ - HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ - HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ - drivers/inc/altera_avalon_lcd_16207.h HAL/inc/sys/alt_alarm.h \ - HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/os/alt_sem.h \ - HAL/inc/priv/alt_no_error.h drivers/inc/altera_avalon_lcd_16207_fd.h \ - HAL/inc/sys/alt_dev.h - -HAL/inc/alt_types.h: - -HAL/inc/sys/alt_dev.h: - -system.h: - -linker.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -HAL/inc/priv/alt_dev_llist.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/alt_types.h: - -drivers/inc/altera_avalon_lcd_16207.h: - -HAL/inc/sys/alt_alarm.h: - -HAL/inc/sys/alt_llist.h: - -HAL/inc/priv/alt_alarm.h: - -HAL/inc/os/alt_sem.h: - -HAL/inc/priv/alt_no_error.h: - -drivers/inc/altera_avalon_lcd_16207_fd.h: - -HAL/inc/sys/alt_dev.h: +obj/drivers/src/altera_avalon_lcd_16207_fd.o: \ + drivers/src/altera_avalon_lcd_16207_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_lcd_16207.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h drivers/inc/altera_avalon_lcd_16207_fd.h \ + HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/software/qsys_tutorial_lcd4_bsp/public.mk b/software/qsys_tutorial_lcd4_bsp/public.mk index 2fd6fc6..a8f9076 100644 --- a/software/qsys_tutorial_lcd4_bsp/public.mk +++ b/software/qsys_tutorial_lcd4_bsp/public.mk @@ -1,377 +1,377 @@ -#------------------------------------------------------------------------------ -# BSP "PUBLIC" MAKEFILE CONTENT -# -# This file is intended to be included in an application or library -# Makefile that is using this BSP. You can create such a Makefile with -# the nios2-app-generate-makefile or nios2-lib-generate-makefile -# commands. -# -# The following variables must be defined before including this file: -# -# ALT_LIBRARY_ROOT_DIR -# Contains the path to the BSP top-level (aka root) directory -#------------------------------------------------------------------------------ - -#------------------------------------------------------------------------------ -# PATHS -#------------------------------------------------------------------------------ - - - -# Path to the provided linker script. -BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x - -# Include paths: -# The path to root of all header files that a library wishes to make -# available for an application's use is specified here. Note that this -# may not be *all* folders within a hierarchy. For example, if it is -# desired that the application developer type: -# #include -# #include -# With files laid out like this: -# /inc/sockets.h -# /inc/ip/tcpip.h -# -# Then, only /inc need be added to the list of include -# directories. Alternatively, if you wish to be able to directly include -# all files in a hierarchy, separate paths to each folder in that -# hierarchy must be defined. - -# The following are the "base" set of include paths for a BSP. -# These paths are appended to the list that individual software -# components, drivers, etc., add in the generated portion of this -# file (below). -ALT_INCLUDE_DIRS_TO_APPEND += \ - $(ALT_LIBRARY_ROOT_DIR) \ - $(ALT_LIBRARY_ROOT_DIR)/drivers/inc - -# Additions to linker library search-path: -# Here we provide a path to "our self" for the application to construct a -# "-L " out of. This should contain a list of directories, -# relative to the library root, of all directories with .a files to link -# against. -ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) - - -#------------------------------------------------------------------------------ -# COMPILATION FLAGS -#------------------------------------------------------------------------------ -# Default C pre-processor flags for a BSP: -ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ - -pipe - - -#------------------------------------------------------------------------------ -# MANAGED CONTENT -# -# All content between the lines "START MANAGED" and "END MANAGED" below is -# generated based on variables in the BSP settings file when the -# nios2-bsp-generate-files command is invoked. If you wish to persist any -# information pertaining to the build process, it is recomended that you -# utilize the BSP settings mechanism to do so. -#------------------------------------------------------------------------------ -#START MANAGED - -# The following TYPE comment allows tools to identify the 'type' of target this -# makefile is associated with. -# TYPE: BSP_PUBLIC_MAKEFILE - -# This following VERSION comment indicates the version of the tool used to -# generate this makefile. A makefile variable is provided for VERSION as well. -# ACDS_VERSION: 13.0sp1 -ACDS_VERSION := 13.0sp1 - -# This following BUILD_NUMBER comment indicates the build number of the tool -# used to generate this makefile. -# BUILD_NUMBER: 232 - -# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with -# design component names. -SOPCINFO_FILE := C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo - -# Big-Endian operation. +#------------------------------------------------------------------------------ +# BSP "PUBLIC" MAKEFILE CONTENT +# +# This file is intended to be included in an application or library +# Makefile that is using this BSP. You can create such a Makefile with +# the nios2-app-generate-makefile or nios2-lib-generate-makefile +# commands. +# +# The following variables must be defined before including this file: +# +# ALT_LIBRARY_ROOT_DIR +# Contains the path to the BSP top-level (aka root) directory +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# PATHS +#------------------------------------------------------------------------------ + + + +# Path to the provided linker script. +BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x + +# Include paths: +# The path to root of all header files that a library wishes to make +# available for an application's use is specified here. Note that this +# may not be *all* folders within a hierarchy. For example, if it is +# desired that the application developer type: +# #include +# #include +# With files laid out like this: +# /inc/sockets.h +# /inc/ip/tcpip.h +# +# Then, only /inc need be added to the list of include +# directories. Alternatively, if you wish to be able to directly include +# all files in a hierarchy, separate paths to each folder in that +# hierarchy must be defined. + +# The following are the "base" set of include paths for a BSP. +# These paths are appended to the list that individual software +# components, drivers, etc., add in the generated portion of this +# file (below). +ALT_INCLUDE_DIRS_TO_APPEND += \ + $(ALT_LIBRARY_ROOT_DIR) \ + $(ALT_LIBRARY_ROOT_DIR)/drivers/inc + +# Additions to linker library search-path: +# Here we provide a path to "our self" for the application to construct a +# "-L " out of. This should contain a list of directories, +# relative to the library root, of all directories with .a files to link +# against. +ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) + + +#------------------------------------------------------------------------------ +# COMPILATION FLAGS +#------------------------------------------------------------------------------ +# Default C pre-processor flags for a BSP: +ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ + -pipe + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +#------------------------------------------------------------------------------ +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PUBLIC_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with +# design component names. +SOPCINFO_FILE := C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + +# Big-Endian operation. # setting BIG_ENDIAN is false -ALT_CFLAGS += -EL - -# Path to the provided C language runtime initialization code. -BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o - -# Name of BSP library as provided to linker using the "-msys-lib" flag or -# linker script GROUP command. +ALT_CFLAGS += -EL + +# Path to the provided C language runtime initialization code. +BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o + +# Name of BSP library as provided to linker using the "-msys-lib" flag or +# linker script GROUP command. # setting BSP_SYS_LIB is hal_bsp -BSP_SYS_LIB := hal_bsp -ELF_PATCH_FLAG += --thread_model hal - -# Type identifier of the BSP library +BSP_SYS_LIB := hal_bsp +ELF_PATCH_FLAG += --thread_model hal + +# Type identifier of the BSP library # setting BSP_TYPE is hal -ALT_CPPFLAGS += -D__hal__ -BSP_TYPE := hal - -# CPU Name +ALT_CPPFLAGS += -D__hal__ +BSP_TYPE := hal + +# CPU Name # setting CPU_NAME is nios2_processor -CPU_NAME = nios2_processor -ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) - -# Hardware Divider present. +CPU_NAME = nios2_processor +ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) + +# Hardware Divider present. # setting HARDWARE_DIVIDE is false -ALT_CFLAGS += -mno-hw-div - -# Hardware Multiplier present. +ALT_CFLAGS += -mno-hw-div + +# Hardware Multiplier present. # setting HARDWARE_MULTIPLY is false -ALT_CFLAGS += -mno-hw-mul - -# Hardware Mulx present. +ALT_CFLAGS += -mno-hw-mul + +# Hardware Mulx present. # setting HARDWARE_MULX is false -ALT_CFLAGS += -mno-hw-mulx - -# Debug Core present. +ALT_CFLAGS += -mno-hw-mulx + +# Debug Core present. # setting HAS_DEBUG_CORE is true -CPU_HAS_DEBUG_CORE = 1 - -# Qsys generated design +CPU_HAS_DEBUG_CORE = 1 + +# Qsys generated design # setting QSYS is 1 -QSYS := 1 -ELF_PATCH_FLAG += --qsys true - -# Design Name +QSYS := 1 +ELF_PATCH_FLAG += --qsys true + +# Design Name # setting SOPC_NAME is nios_system -SOPC_NAME := nios_system - -# SopcBuilder Simulation Enabled +SOPC_NAME := nios_system + +# SopcBuilder Simulation Enabled # setting SOPC_SIMULATION_ENABLED is false -ELF_PATCH_FLAG += --simulation_enabled false - -# Enable JTAG UART driver to recover when host is inactive causing buffer to -# full without returning error. Printf will not fail with this recovery. none +ELF_PATCH_FLAG += --simulation_enabled false + +# Enable JTAG UART driver to recover when host is inactive causing buffer to +# full without returning error. Printf will not fail with this recovery. none # setting altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error is false - -# Small-footprint (polled mode) driver none + +# Small-footprint (polled mode) driver none # setting altera_avalon_jtag_uart_driver.enable_small_driver is false - -# Build a custom version of newlib with the specified space-separated compiler -# flags. The custom newlib build will be placed in the <bsp root>/newlib -# directory, and will be used only for applications that utilize this BSP. + +# Build a custom version of newlib with the specified space-separated compiler +# flags. The custom newlib build will be placed in the <bsp root>/newlib +# directory, and will be used only for applications that utilize this BSP. # setting hal.custom_newlib_flags is none - -# Enable support for a subset of the C++ language. This option increases code -# footprint by adding support for C++ constructors. Certain features, such as -# multiple inheritance and exceptions are not supported. If false, adds -# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code -# footprint. none + +# Enable support for a subset of the C++ language. This option increases code +# footprint by adding support for C++ constructors. Certain features, such as +# multiple inheritance and exceptions are not supported. If false, adds +# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code +# footprint. none # setting hal.enable_c_plus_plus is true - -# When your application exits, close file descriptors, call C++ destructors, -# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to -# ALT_LDFLAGS in public.mk. none + +# When your application exits, close file descriptors, call C++ destructors, +# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds +# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to +# ALT_LDFLAGS in public.mk. none # setting hal.enable_clean_exit is true - -# Add exit() support. This option increases code footprint if your "main()" -# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to -# ALT_CPPFLAGS in public.mk, and reduces footprint none + +# Add exit() support. This option increases code footprint if your "main()" +# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to +# ALT_CPPFLAGS in public.mk, and reduces footprint none # setting hal.enable_exit is true - -# Causes code to be compiled with gprof profiling enabled and the application -# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to -# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none + +# Causes code to be compiled with gprof profiling enabled and the application +# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to +# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none # setting hal.enable_gprof is false - -# Enables lightweight device driver API. This reduces code and data footprint -# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file -# descriptors. Instead, driver routines are called directly. The open(), -# close(), and lseek() routines will always fail if called. The read(), -# write(), fstat(), ioctl(), and isatty() routines only work for the stdio -# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. -# The Altera Host and read-only ZIP file systems can't be used if -# hal.enable_lightweight_device_driver_api is true. + +# Enables lightweight device driver API. This reduces code and data footprint +# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file +# descriptors. Instead, driver routines are called directly. The open(), +# close(), and lseek() routines will always fail if called. The read(), +# write(), fstat(), ioctl(), and isatty() routines only work for the stdio +# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. +# The Altera Host and read-only ZIP file systems can't be used if +# hal.enable_lightweight_device_driver_api is true. # setting hal.enable_lightweight_device_driver_api is false - -# Adds code to emulate multiply and divide instructions in case they are -# executed but aren't present in the CPU. Normally this isn't required because -# the compiler won't use multiply and divide instructions that aren't present -# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in -# public.mk. none + +# Adds code to emulate multiply and divide instructions in case they are +# executed but aren't present in the CPU. Normally this isn't required because +# the compiler won't use multiply and divide instructions that aren't present +# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in +# public.mk. none # setting hal.enable_mul_div_emulation is false -ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION - -# Certain drivers are compiled with reduced functionality to reduce code -# footprint. Not all drivers observe this setting. The altera_avalon_uart and -# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled -# operation. CAUTION: Several device drivers are disabled entirely. These -# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and -# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash -# access routines) to fail. You can define a symbol provided by each driver to -# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to -# ALT_CPPFLAGS in public.mk. none +ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION + +# Certain drivers are compiled with reduced functionality to reduce code +# footprint. Not all drivers observe this setting. The altera_avalon_uart and +# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled +# operation. CAUTION: Several device drivers are disabled entirely. These +# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and +# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash +# access routines) to fail. You can define a symbol provided by each driver to +# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to +# ALT_CPPFLAGS in public.mk. none # setting hal.enable_reduced_device_drivers is false - -# Turns on HAL runtime stack checking feature. Enabling this setting causes -# additional code to be placed into each subroutine call to generate an -# exception if a stack collision occurs with the heap or statically allocated -# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in -# public.mk. none + +# Turns on HAL runtime stack checking feature. Enabling this setting causes +# additional code to be placed into each subroutine call to generate an +# exception if a stack collision occurs with the heap or statically allocated +# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in +# public.mk. none # setting hal.enable_runtime_stack_checking is false - -# The BSP is compiled with optimizations to speedup HDL simulation such as -# initializing the cache, clearing the .bss section, and skipping long delay -# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When -# this setting is true, the BSP shouldn't be used to build applications that -# are expected to run real hardware. + +# The BSP is compiled with optimizations to speedup HDL simulation such as +# initializing the cache, clearing the .bss section, and skipping long delay +# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When +# this setting is true, the BSP shouldn't be used to build applications that +# are expected to run real hardware. # setting hal.enable_sim_optimize is false - -# Causes the small newlib (C library) to be used. This reduces code and data -# footprint at the expense of reduced functionality. Several newlib features -# are removed such as floating-point support in printf(), stdin input routines, -# and buffered I/O. The small C library is not compatible with Micrium -# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none + +# Causes the small newlib (C library) to be used. This reduces code and data +# footprint at the expense of reduced functionality. Several newlib features +# are removed such as floating-point support in printf(), stdin input routines, +# and buffered I/O. The small C library is not compatible with Micrium +# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none # setting hal.enable_small_c_library is false - -# Enable SOPC Builder System ID. If a System ID SOPC Builder component is -# connected to the CPU associated with this BSP, it will be enabled in the -# creation of command-line arguments to download an ELF to the target. -# Otherwise, system ID and timestamp values are left out of public.mk for -# application Makefile "download-elf" target definition. With the system ID -# check disabled, the Nios II EDS tools will not automatically ensure that the -# application .elf file (and BSP it is linked against) corresponds to the -# hardware design on the target. If false, adds --accept-bad-sysid to -# SOPC_SYSID_FLAG in public.mk. none + +# Enable SOPC Builder System ID. If a System ID SOPC Builder component is +# connected to the CPU associated with this BSP, it will be enabled in the +# creation of command-line arguments to download an ELF to the target. +# Otherwise, system ID and timestamp values are left out of public.mk for +# application Makefile "download-elf" target definition. With the system ID +# check disabled, the Nios II EDS tools will not automatically ensure that the +# application .elf file (and BSP it is linked against) corresponds to the +# hardware design on the target. If false, adds --accept-bad-sysid to +# SOPC_SYSID_FLAG in public.mk. none # setting hal.enable_sopc_sysid_check is true - -# Enable BSP generation to query if SOPC system is big endian. If true ignores -# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true -# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none + +# Enable BSP generation to query if SOPC system is big endian. If true ignores +# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true +# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none # setting hal.make.ignore_system_derived.big_endian is false - -# Enable BSP generation to query if SOPC system has a debug core present. If -# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core -# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if -# no debug core is found in the system. none + +# Enable BSP generation to query if SOPC system has a debug core present. If +# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core +# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if +# no debug core is found in the system. none # setting hal.make.ignore_system_derived.debug_core_present is false - -# Enable BSP generation to query if SOPC system has FPU present. If true -# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found -# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU -# is not found in the system. none + +# Enable BSP generation to query if SOPC system has FPU present. If true +# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found +# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU +# is not found in the system. none # setting hal.make.ignore_system_derived.fpu_present is false - -# Enable BSP generation to query if SOPC system has hardware divide present. If -# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no -# division is found in system. If true ignores export of 'ALT_CFLAGS += -# -mhw-div' if division is found in the system. none + +# Enable BSP generation to query if SOPC system has hardware divide present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no +# division is found in system. If true ignores export of 'ALT_CFLAGS += +# -mhw-div' if division is found in the system. none # setting hal.make.ignore_system_derived.hardware_divide_present is false - -# Enable BSP generation to query if SOPC system floating point custom -# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS -# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to -# public.mk if the custom instruction is found in the system. none + +# Enable BSP generation to query if SOPC system floating point custom +# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS +# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to +# public.mk if the custom instruction is found in the system. none # setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is false - -# Enable BSP generation to query if SOPC system floating point custom -# instruction without a divider is present. If true ignores export of -# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the -# system. none + +# Enable BSP generation to query if SOPC system floating point custom +# instruction without a divider is present. If true ignores export of +# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += +# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the +# system. none # setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is false - -# Enable BSP generation to query if SOPC system has multiplier present. If true -# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier -# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if -# multiplier is found in the system. none + +# Enable BSP generation to query if SOPC system has multiplier present. If true +# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if +# multiplier is found in the system. none # setting hal.make.ignore_system_derived.hardware_multiplier_present is false - -# Enable BSP generation to query if SOPC system has hardware mulx present. If -# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx -# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' -# if mulx is found in the system. none + +# Enable BSP generation to query if SOPC system has hardware mulx present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' +# if mulx is found in the system. none # setting hal.make.ignore_system_derived.hardware_mulx_present is false - -# Enable BSP generation to query if SOPC system has simulation enabled. If true -# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none + +# Enable BSP generation to query if SOPC system has simulation enabled. If true +# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none # setting hal.make.ignore_system_derived.sopc_simulation_enabled is false - -# Enable BSP generation to query SOPC system for system ID base address. If -# true ignores export of 'SOPC_SYSID_FLAG += --sidp=

' and -# 'ELF_PATCH_FLAG += --sidp=

' to public.mk. none + +# Enable BSP generation to query SOPC system for system ID base address. If +# true ignores export of 'SOPC_SYSID_FLAG += --sidp=

' and +# 'ELF_PATCH_FLAG += --sidp=

' to public.mk. none # setting hal.make.ignore_system_derived.sopc_system_base_address is false - -# Enable BSP generation to query SOPC system for system ID. If true ignores -# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += -# --id=' to public.mk. none + +# Enable BSP generation to query SOPC system for system ID. If true ignores +# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += +# --id=' to public.mk. none # setting hal.make.ignore_system_derived.sopc_system_id is false - -# Enable BSP generation to query SOPC system for system timestamp. If true -# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and -# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none + +# Enable BSP generation to query SOPC system for system timestamp. If true +# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and +# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none # setting hal.make.ignore_system_derived.sopc_system_timestamp is false - -# Slave descriptor of STDERR character-mode device. This setting is used by the -# ALT_STDERR family of defines in system.h. none + +# Slave descriptor of STDERR character-mode device. This setting is used by the +# ALT_STDERR family of defines in system.h. none # setting hal.stderr is jtag_uart -ELF_PATCH_FLAG += --stderr_dev jtag_uart - -# Slave descriptor of STDIN character-mode device. This setting is used by the -# ALT_STDIN family of defines in system.h. none +ELF_PATCH_FLAG += --stderr_dev jtag_uart + +# Slave descriptor of STDIN character-mode device. This setting is used by the +# ALT_STDIN family of defines in system.h. none # setting hal.stdin is jtag_uart -ELF_PATCH_FLAG += --stdin_dev jtag_uart - -# Slave descriptor of STDOUT character-mode device. This setting is used by the -# ALT_STDOUT family of defines in system.h. none +ELF_PATCH_FLAG += --stdin_dev jtag_uart + +# Slave descriptor of STDOUT character-mode device. This setting is used by the +# ALT_STDOUT family of defines in system.h. none # setting hal.stdout is jtag_uart -ELF_PATCH_FLAG += --stdout_dev jtag_uart - - -#------------------------------------------------------------------------------ -# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS -#------------------------------------------------------------------------------ - -ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc - -#------------------------------------------------------------------------------ -# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS -#------------------------------------------------------------------------------ - -ALT_CPPFLAGS += -DALT_SINGLE_THREADED - -#END MANAGED - - -#------------------------------------------------------------------------------ -# LIBRARY INFORMATION -#------------------------------------------------------------------------------ -# Assemble the name of the BSP *.a file using the BSP library name -# (BSP_SYS_LIB) in generated content above. -BSP_LIB := lib$(BSP_SYS_LIB).a - -# Additional libraries to link against: -# An application including this file will prefix each library with "-l". -# For example, to include the Newlib math library "m" is included, which -# becomes "-lm" when linking the application. -ALT_LIBRARY_NAMES += m - -# Additions to linker dependencies: -# An application Makefile will typically add these directly to the list -# of dependencies required to build the executable target(s). The BSP -# library (*.a) file is specified here. -ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) - -# Is this library "Makeable"? -# Add to list of root library directories that support running 'make' -# to build them. Because libraries may or may not have a Makefile in their -# root, appending to this variable tells an application to run 'make' in -# the library root to build/update this library. -MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) - -# Additional Assembler Flags -# -gdwarf2 flag is required for stepping through assembly code -ALT_ASFLAGS += -gdwarf2 - -#------------------------------------------------------------------------------ -# FINAL INCLUDE PATH LIST -#------------------------------------------------------------------------------ -# Append static include paths to paths specified by OS/driver/sw package -# additions to the BSP thus giving them precedence in case a BSP addition -# is attempting to override BSP sources. -ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) - - - +ELF_PATCH_FLAG += --stdout_dev jtag_uart + + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS +#------------------------------------------------------------------------------ + +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS +#------------------------------------------------------------------------------ + +ALT_CPPFLAGS += -DALT_SINGLE_THREADED + +#END MANAGED + + +#------------------------------------------------------------------------------ +# LIBRARY INFORMATION +#------------------------------------------------------------------------------ +# Assemble the name of the BSP *.a file using the BSP library name +# (BSP_SYS_LIB) in generated content above. +BSP_LIB := lib$(BSP_SYS_LIB).a + +# Additional libraries to link against: +# An application including this file will prefix each library with "-l". +# For example, to include the Newlib math library "m" is included, which +# becomes "-lm" when linking the application. +ALT_LIBRARY_NAMES += m + +# Additions to linker dependencies: +# An application Makefile will typically add these directly to the list +# of dependencies required to build the executable target(s). The BSP +# library (*.a) file is specified here. +ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) + +# Is this library "Makeable"? +# Add to list of root library directories that support running 'make' +# to build them. Because libraries may or may not have a Makefile in their +# root, appending to this variable tells an application to run 'make' in +# the library root to build/update this library. +MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) + +# Additional Assembler Flags +# -gdwarf2 flag is required for stepping through assembly code +ALT_ASFLAGS += -gdwarf2 + +#------------------------------------------------------------------------------ +# FINAL INCLUDE PATH LIST +#------------------------------------------------------------------------------ +# Append static include paths to paths specified by OS/driver/sw package +# additions to the BSP thus giving them precedence in case a BSP addition +# is attempting to override BSP sources. +ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) + + + diff --git a/software/qsys_tutorial_lcd4_bsp/settings.bsp b/software/qsys_tutorial_lcd4_bsp/settings.bsp index 94ddcfd..20806eb 100644 --- a/software/qsys_tutorial_lcd4_bsp/settings.bsp +++ b/software/qsys_tutorial_lcd4_bsp/settings.bsp @@ -1,991 +1,991 @@ - - - hal - default - 2016/12/02 1:35:13 - 1480610113326 - C:\Users\takayun\Documents\DE2-115\qsys_tutorial\software\qsys_tutorial_lcd4_bsp - .\settings.bsp - C:\Users\takayun\Documents\DE2-115\qsys_tutorial\nios_system.sopcinfo - default - nios2_processor - 1.9 - - hal.sys_clk_timer - ALT_SYS_CLK - UnquotedString - none - none - system_h_define - Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. - none - false - common - - - hal.timestamp_timer - ALT_TIMESTAMP_CLK - UnquotedString - none - none - system_h_define - Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. - none - false - common - - - hal.max_file_descriptors - ALT_MAX_FD - DecimalNumber - 32 - 32 - system_h_define - Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. - If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. - false - - - - hal.enable_instruction_related_exceptions_api - ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API - BooleanDefineOnly - false - false - system_h_define - Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. - These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. - false - - - - hal.linker.allow_code_at_reset - ALT_ALLOW_CODE_AT_RESET - Boolean - 1 - 0 - none - Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. - If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. - false - - - - hal.linker.enable_alt_load - NONE - Boolean - 1 - 0 - none - Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. - This setting is typically false if an external bootloader (e.g. flash bootloader) is present. - false - - - - hal.linker.enable_alt_load_copy_rodata - NONE - Boolean - 0 - 0 - none - Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. - none - false - - - - hal.linker.enable_alt_load_copy_rwdata - NONE - Boolean - 1 - 0 - none - Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. - none - false - - - - hal.linker.enable_alt_load_copy_exceptions - NONE - Boolean - 0 - 0 - none - Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. - none - false - - - - hal.linker.enable_exception_stack - NONE - Boolean - 0 - 0 - none - Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. - The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. - false - common - - - hal.linker.exception_stack_size - NONE - DecimalNumber - 1024 - 1024 - none - Size of the exception stack in bytes. - Only used if hal.linker.enable_exception_stack is true. - false - common - - - hal.linker.exception_stack_memory_region_name - NONE - UnquotedString - onchip_memory - none - none - Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. - Only used if hal.linker.enable_exception_stack is true. - false - common - - - hal.linker.enable_interrupt_stack - NONE - Boolean - 0 - 0 - none - Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. - The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. - false - common - - - hal.linker.interrupt_stack_size - NONE - DecimalNumber - 1024 - 1024 - none - Size of the interrupt stack in bytes. - Only used if hal.linker.enable_interrupt_stack is true. - false - common - - - hal.linker.interrupt_stack_memory_region_name - NONE - UnquotedString - onchip_memory - none - none - Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. - Only used if hal.linker.enable_interrupt_stack is true. - false - common - - - hal.stdin - NONE - UnquotedString - jtag_uart - none - system_h_define - Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. - none - false - common - - - hal.stdout - NONE - UnquotedString - jtag_uart - none - system_h_define - Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. - none - false - common - - - hal.stderr - NONE - UnquotedString - jtag_uart - none - system_h_define - Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. - none - false - common - - - hal.log_port - NONE - UnquotedString - none - none - public_mk_define - Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. - none - false - none - - - hal.make.build_pre_process - BUILD_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before BSP built. - none - false - none - - - hal.make.ar_pre_process - AR_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before archiver execution. - none - false - none - - - hal.make.bsp_cflags_defined_symbols - BSP_CFLAGS_DEFINED_SYMBOLS - UnquotedString - none - none - makefile_variable - Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. - none - false - none - - - hal.make.ar_post_process - AR_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after archiver execution. - none - false - none - - - hal.make.as - AS - UnquotedString - nios2-elf-gcc - nios2-elf-gcc - makefile_variable - Assembler command. Note that CC is used for .S files. - none - false - none - - - hal.make.build_post_process - BUILD_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after BSP built. - none - false - none - - - hal.make.bsp_cflags_debug - BSP_CFLAGS_DEBUG - UnquotedString - -g - -g - makefile_variable - C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. - none - false - common - - - hal.make.ar - AR - UnquotedString - nios2-elf-ar - nios2-elf-ar - makefile_variable - Archiver command. Creates library files. - none - false - none - - - hal.make.rm - RM - UnquotedString - rm -f - rm -f - makefile_variable - Command used to remove files during 'clean' target. - none - false - none - - - hal.make.cxx_pre_process - CXX_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each C++ file is compiled. - none - false - none - - - hal.make.bsp_cflags_warnings - BSP_CFLAGS_WARNINGS - UnquotedString - -Wall - -Wall - makefile_variable - C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. - none - false - none - - - hal.make.bsp_arflags - BSP_ARFLAGS - UnquotedString - -src - -src - makefile_variable - Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. - none - false - none - - - hal.make.bsp_cflags_optimization - BSP_CFLAGS_OPTIMIZATION - UnquotedString - -O0 - -O0 - makefile_variable - C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. - none - false - common - - - hal.make.as_post_process - AS_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after each assembly file is compiled. - none - false - none - - - hal.make.cc_pre_process - CC_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each .c/.S file is compiled. - none - false - none - - - hal.make.bsp_asflags - BSP_ASFLAGS - UnquotedString - -Wa,-gdwarf2 - -Wa,-gdwarf2 - makefile_variable - Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. - none - false - none - - - hal.make.as_pre_process - AS_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each assembly file is compiled. - none - false - none - - - hal.make.bsp_cflags_undefined_symbols - BSP_CFLAGS_UNDEFINED_SYMBOLS - UnquotedString - none - none - makefile_variable - Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. - none - false - none - - - hal.make.cc_post_process - CC_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after each .c/.S file is compiled. - none - false - none - - - hal.make.cxx_post_process - CXX_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each C++ file is compiled. - none - false - none - - - hal.make.cc - CC - UnquotedString - nios2-elf-gcc -xc - nios2-elf-gcc -xc - makefile_variable - C compiler command. - none - false - none - - - hal.make.bsp_cxx_flags - BSP_CXXFLAGS - UnquotedString - none - none - makefile_variable - Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. - none - false - none - - - hal.make.bsp_inc_dirs - BSP_INC_DIRS - UnquotedString - none - none - makefile_variable - Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. - none - false - none - - - hal.make.cxx - CXX - UnquotedString - nios2-elf-gcc -xc++ - nios2-elf-gcc -xc++ - makefile_variable - C++ compiler command. - none - false - none - - - hal.make.bsp_cflags_user_flags - BSP_CFLAGS_USER_FLAGS - UnquotedString - none - none - makefile_variable - Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_id - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_timestamp - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_base_address - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_simulation_enabled - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.fpu_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_multiplier_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_mulx_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_divide_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. - none - false - none - - - hal.make.ignore_system_derived.debug_core_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. - none - false - none - - - hal.make.ignore_system_derived.big_endian - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. - none - false - none - - - hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. - none - false - none - - - hal.enable_exit - ALT_NO_EXIT - Boolean - 1 - 1 - public_mk_define - Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint - none - false - none - - - hal.enable_small_c_library - NONE - Boolean - 0 - 0 - public_mk_define - Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. - none - false - common - - - hal.enable_clean_exit - ALT_NO_CLEAN_EXIT - Boolean - 1 - 1 - public_mk_define - When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. - none - false - none - - - hal.enable_runtime_stack_checking - ALT_STACK_CHECK - Boolean - 0 - 0 - public_mk_define - Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. - none - false - none - - - hal.enable_gprof - ALT_PROVIDE_GMON - Boolean - 0 - 0 - public_mk_define - Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. - none - false - common - - - hal.enable_c_plus_plus - ALT_NO_C_PLUS_PLUS - Boolean - 1 - 1 - public_mk_define - Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. - none - false - none - - - hal.enable_reduced_device_drivers - ALT_USE_SMALL_DRIVERS - Boolean - 0 - 0 - public_mk_define - Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. - none - false - common - - - hal.enable_lightweight_device_driver_api - ALT_USE_DIRECT_DRIVERS - Boolean - 0 - 0 - public_mk_define - Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. - The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. - false - none - - - hal.enable_mul_div_emulation - ALT_NO_INSTRUCTION_EMULATION - Boolean - 0 - 0 - public_mk_define - Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. - none - false - none - - - hal.enable_sim_optimize - ALT_SIM_OPTIMIZE - Boolean - 0 - 0 - public_mk_define - The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. - When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. - false - common - - - hal.enable_sopc_sysid_check - NONE - Boolean - 1 - 1 - public_mk_define - Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. - none - false - none - - - hal.custom_newlib_flags - CUSTOM_NEWLIB_FLAGS - UnquotedString - none - none - public_mk_define - Build a custom version of newlib with the specified space-separated compiler flags. - The custom newlib build will be placed in the <bsp root>/newlib directory, and will be used only for applications that utilize this BSP. - false - none - - - hal.log_flags - ALT_LOG_FLAGS - DecimalNumber - 0 - 0 - public_mk_define - The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. - hal.log_port must be set for this to be used. - false - none - - - altera_avalon_jtag_uart_driver.enable_small_driver - ALTERA_AVALON_JTAG_UART_SMALL - BooleanDefineOnly - false - false - public_mk_define - Small-footprint (polled mode) driver - none - false - - - - altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error - ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR - BooleanDefineOnly - false - false - public_mk_define - Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery. - none - false - - - - onchip_memory - 0x00000000 - 0x00031FFF - 204800 - memory - - - lcd_on - 0x00041010 - 0x0004101F - 16 - - - - lcd_blon - 0x00041020 - 0x0004102F - 16 - - - - lcd_16207_0 - 0x00041030 - 0x0004103F - 16 - printable - - - hex7 - 0x00041040 - 0x0004104F - 16 - - - - hex6 - 0x00041050 - 0x0004105F - 16 - - - - hex5 - 0x00041060 - 0x0004106F - 16 - - - - hex4 - 0x00041070 - 0x0004107F - 16 - - - - hex3 - 0x00041080 - 0x0004108F - 16 - - - - hex2 - 0x00041090 - 0x0004109F - 16 - - - - hex1 - 0x000410A0 - 0x000410AF - 16 - - - - hex0 - 0x000410B0 - 0x000410BF - 16 - - - - push_switches - 0x000410C0 - 0x000410CF - 16 - - - - switches - 0x000410D0 - 0x000410DF - 16 - - - - LEDRs - 0x000410E0 - 0x000410EF - 16 - - - - LEDs - 0x000410F0 - 0x000410FF - 16 - - - - jtag_uart - 0x00041100 - 0x00041107 - 8 - printable - - - .text - onchip_memory - - - .rodata - onchip_memory - - - .rwdata - onchip_memory - - - .bss - onchip_memory - - - .heap - onchip_memory - - - .stack - onchip_memory - + + + hal + default + 2016/12/02 1:35:13 + 1480610113326 + C:\Users\takayun\Documents\DE2-115\qsys_tutorial\software\qsys_tutorial_lcd4_bsp + .\settings.bsp + C:\Users\takayun\Documents\DE2-115\qsys_tutorial\nios_system.sopcinfo + default + nios2_processor + 1.9 + + hal.sys_clk_timer + ALT_SYS_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. + none + false + common + + + hal.timestamp_timer + ALT_TIMESTAMP_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. + none + false + common + + + hal.max_file_descriptors + ALT_MAX_FD + DecimalNumber + 32 + 32 + system_h_define + Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. + If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. + false + + + + hal.enable_instruction_related_exceptions_api + ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + BooleanDefineOnly + false + false + system_h_define + Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. + These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. + false + + + + hal.linker.allow_code_at_reset + ALT_ALLOW_CODE_AT_RESET + Boolean + 1 + 0 + none + Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. + If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load + NONE + Boolean + 1 + 0 + none + Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. + This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load_copy_rodata + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_rwdata + NONE + Boolean + 1 + 0 + none + Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_exceptions + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. + none + false + + + + hal.linker.enable_exception_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. + The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.exception_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the exception stack in bytes. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.exception_stack_memory_region_name + NONE + UnquotedString + onchip_memory + none + none + Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.enable_interrupt_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. + The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.interrupt_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the interrupt stack in bytes. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.linker.interrupt_stack_memory_region_name + NONE + UnquotedString + onchip_memory + none + none + Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.stdin + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. + none + false + common + + + hal.stdout + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. + none + false + common + + + hal.stderr + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. + none + false + common + + + hal.log_port + NONE + UnquotedString + none + none + public_mk_define + Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. + none + false + none + + + hal.make.build_pre_process + BUILD_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before BSP built. + none + false + none + + + hal.make.ar_pre_process + AR_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before archiver execution. + none + false + none + + + hal.make.bsp_cflags_defined_symbols + BSP_CFLAGS_DEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.ar_post_process + AR_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after archiver execution. + none + false + none + + + hal.make.as + AS + UnquotedString + nios2-elf-gcc + nios2-elf-gcc + makefile_variable + Assembler command. Note that CC is used for .S files. + none + false + none + + + hal.make.build_post_process + BUILD_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after BSP built. + none + false + none + + + hal.make.bsp_cflags_debug + BSP_CFLAGS_DEBUG + UnquotedString + -g + -g + makefile_variable + C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. + none + false + common + + + hal.make.ar + AR + UnquotedString + nios2-elf-ar + nios2-elf-ar + makefile_variable + Archiver command. Creates library files. + none + false + none + + + hal.make.rm + RM + UnquotedString + rm -f + rm -f + makefile_variable + Command used to remove files during 'clean' target. + none + false + none + + + hal.make.cxx_pre_process + CXX_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.bsp_cflags_warnings + BSP_CFLAGS_WARNINGS + UnquotedString + -Wall + -Wall + makefile_variable + C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. + none + false + none + + + hal.make.bsp_arflags + BSP_ARFLAGS + UnquotedString + -src + -src + makefile_variable + Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. + none + false + none + + + hal.make.bsp_cflags_optimization + BSP_CFLAGS_OPTIMIZATION + UnquotedString + -O0 + -O0 + makefile_variable + C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. + none + false + common + + + hal.make.as_post_process + AS_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each assembly file is compiled. + none + false + none + + + hal.make.cc_pre_process + CC_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each .c/.S file is compiled. + none + false + none + + + hal.make.bsp_asflags + BSP_ASFLAGS + UnquotedString + -Wa,-gdwarf2 + -Wa,-gdwarf2 + makefile_variable + Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. + none + false + none + + + hal.make.as_pre_process + AS_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each assembly file is compiled. + none + false + none + + + hal.make.bsp_cflags_undefined_symbols + BSP_CFLAGS_UNDEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.cc_post_process + CC_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each .c/.S file is compiled. + none + false + none + + + hal.make.cxx_post_process + CXX_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.cc + CC + UnquotedString + nios2-elf-gcc -xc + nios2-elf-gcc -xc + makefile_variable + C compiler command. + none + false + none + + + hal.make.bsp_cxx_flags + BSP_CXXFLAGS + UnquotedString + none + none + makefile_variable + Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. + none + false + none + + + hal.make.bsp_inc_dirs + BSP_INC_DIRS + UnquotedString + none + none + makefile_variable + Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. + none + false + none + + + hal.make.cxx + CXX + UnquotedString + nios2-elf-gcc -xc++ + nios2-elf-gcc -xc++ + makefile_variable + C++ compiler command. + none + false + none + + + hal.make.bsp_cflags_user_flags + BSP_CFLAGS_USER_FLAGS + UnquotedString + none + none + makefile_variable + Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_id + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_timestamp + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_base_address + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_simulation_enabled + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.fpu_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_multiplier_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_mulx_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_divide_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. + none + false + none + + + hal.make.ignore_system_derived.debug_core_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. + none + false + none + + + hal.make.ignore_system_derived.big_endian + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.enable_exit + ALT_NO_EXIT + Boolean + 1 + 1 + public_mk_define + Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint + none + false + none + + + hal.enable_small_c_library + NONE + Boolean + 0 + 0 + public_mk_define + Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. + none + false + common + + + hal.enable_clean_exit + ALT_NO_CLEAN_EXIT + Boolean + 1 + 1 + public_mk_define + When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. + none + false + none + + + hal.enable_runtime_stack_checking + ALT_STACK_CHECK + Boolean + 0 + 0 + public_mk_define + Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_gprof + ALT_PROVIDE_GMON + Boolean + 0 + 0 + public_mk_define + Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. + none + false + common + + + hal.enable_c_plus_plus + ALT_NO_C_PLUS_PLUS + Boolean + 1 + 1 + public_mk_define + Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. + none + false + none + + + hal.enable_reduced_device_drivers + ALT_USE_SMALL_DRIVERS + Boolean + 0 + 0 + public_mk_define + Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. + none + false + common + + + hal.enable_lightweight_device_driver_api + ALT_USE_DIRECT_DRIVERS + Boolean + 0 + 0 + public_mk_define + Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. + The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. + false + none + + + hal.enable_mul_div_emulation + ALT_NO_INSTRUCTION_EMULATION + Boolean + 0 + 0 + public_mk_define + Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_sim_optimize + ALT_SIM_OPTIMIZE + Boolean + 0 + 0 + public_mk_define + The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. + When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. + false + common + + + hal.enable_sopc_sysid_check + NONE + Boolean + 1 + 1 + public_mk_define + Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. + none + false + none + + + hal.custom_newlib_flags + CUSTOM_NEWLIB_FLAGS + UnquotedString + none + none + public_mk_define + Build a custom version of newlib with the specified space-separated compiler flags. + The custom newlib build will be placed in the <bsp root>/newlib directory, and will be used only for applications that utilize this BSP. + false + none + + + hal.log_flags + ALT_LOG_FLAGS + DecimalNumber + 0 + 0 + public_mk_define + The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. + hal.log_port must be set for this to be used. + false + none + + + altera_avalon_jtag_uart_driver.enable_small_driver + ALTERA_AVALON_JTAG_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error + ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + BooleanDefineOnly + false + false + public_mk_define + Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery. + none + false + + + + onchip_memory + 0x00000000 - 0x00031FFF + 204800 + memory + + + lcd_on + 0x00041010 - 0x0004101F + 16 + + + + lcd_blon + 0x00041020 - 0x0004102F + 16 + + + + lcd_16207_0 + 0x00041030 - 0x0004103F + 16 + printable + + + hex7 + 0x00041040 - 0x0004104F + 16 + + + + hex6 + 0x00041050 - 0x0004105F + 16 + + + + hex5 + 0x00041060 - 0x0004106F + 16 + + + + hex4 + 0x00041070 - 0x0004107F + 16 + + + + hex3 + 0x00041080 - 0x0004108F + 16 + + + + hex2 + 0x00041090 - 0x0004109F + 16 + + + + hex1 + 0x000410A0 - 0x000410AF + 16 + + + + hex0 + 0x000410B0 - 0x000410BF + 16 + + + + push_switches + 0x000410C0 - 0x000410CF + 16 + + + + switches + 0x000410D0 - 0x000410DF + 16 + + + + LEDRs + 0x000410E0 - 0x000410EF + 16 + + + + LEDs + 0x000410F0 - 0x000410FF + 16 + + + + jtag_uart + 0x00041100 - 0x00041107 + 8 + printable + + + .text + onchip_memory + + + .rodata + onchip_memory + + + .rwdata + onchip_memory + + + .bss + onchip_memory + + + .heap + onchip_memory + + + .stack + onchip_memory + \ No newline at end of file diff --git a/software/qsys_tutorial_lcd4_bsp/summary.html b/software/qsys_tutorial_lcd4_bsp/summary.html index 1ae83c4..9f86bf3 100644 --- a/software/qsys_tutorial_lcd4_bsp/summary.html +++ b/software/qsys_tutorial_lcd4_bsp/summary.html @@ -1,2047 +1,2047 @@ - -Altera Nios II BSP Summary - -

BSP Description

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BSP Type:	hal
SOPC Design File:	C:\Users\takayun\Documents\DE2-115\qsys_tutorial\nios_system.sopcinfo
Quartus JDI File:	default
CPU:	nios2_processor
BSP Settings File:	.\settings.bsp
BSP Version:	default
BSP Generated On:	2016/12/02 1:35:13
BSP Generated Timestamp:	1480610113326
BSP Generated Location:	C:\Users\takayun\Documents\DE2-115\qsys_tutorial\software\qsys_tutorial_lcd4_bsp

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Nios II Memory Map

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Slave Descriptor	Address Range	Size	Attributes
jtag_uart	0x00041100 - 0x00041107	8	printable
LEDs	0x000410F0 - 0x000410FF	16
LEDRs	0x000410E0 - 0x000410EF	16
switches	0x000410D0 - 0x000410DF	16
push_switches	0x000410C0 - 0x000410CF	16
hex0	0x000410B0 - 0x000410BF	16
hex1	0x000410A0 - 0x000410AF	16
hex2	0x00041090 - 0x0004109F	16
hex3	0x00041080 - 0x0004108F	16
hex4	0x00041070 - 0x0004107F	16
hex5	0x00041060 - 0x0004106F	16
hex6	0x00041050 - 0x0004105F	16
hex7	0x00041040 - 0x0004104F	16
lcd_16207_0	0x00041030 - 0x0004103F	16	printable
lcd_blon	0x00041020 - 0x0004102F	16
lcd_on	0x00041010 - 0x0004101F	16
onchip_memory	0x00000000 - 0x00031FFF	204800	memory

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Linker Regions

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Region	Address Range	Size	Memory	Offset

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Linker Section Mappings

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Section	Region
.text	onchip_memory
.rodata	onchip_memory
.rwdata	onchip_memory
.bss	onchip_memory
.heap	onchip_memory
.stack	onchip_memory

Settings

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Setting Name:	altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error
Identifier:	ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	public_mk_define
Description:	Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery.
Restrictions:	none

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Setting Name:	altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:	ALTERA_AVALON_JTAG_UART_SMALL
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	public_mk_define
Description:	Small-footprint (polled mode) driver
Restrictions:	none

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Setting Name:	hal.custom_newlib_flags
Identifier:	CUSTOM_NEWLIB_FLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	public_mk_define
Description:	Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:	The custom newlib build will be placed in the <bsp root>/newlib directory, and will be used only for applications that utilize this BSP.

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Setting Name:	hal.enable_c_plus_plus
Identifier:	ALT_NO_C_PLUS_PLUS
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:	none

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Setting Name:	hal.enable_clean_exit
Identifier:	ALT_NO_CLEAN_EXIT
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_exit
Identifier:	ALT_NO_EXIT
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:	none

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Setting Name:	hal.enable_gprof
Identifier:	ALT_PROVIDE_GMON
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_instruction_related_exceptions_api
Identifier:	ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	system_h_define
Description:	Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:	These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.

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Setting Name:	hal.enable_lightweight_device_driver_api
Identifier:	ALT_USE_DIRECT_DRIVERS
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:	The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.

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Setting Name:	hal.enable_mul_div_emulation
Identifier:	ALT_NO_INSTRUCTION_EMULATION
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_reduced_device_drivers
Identifier:	ALT_USE_SMALL_DRIVERS
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_runtime_stack_checking
Identifier:	ALT_STACK_CHECK
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_sim_optimize
Identifier:	ALT_SIM_OPTIMIZE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:	When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.

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Setting Name:	hal.enable_small_c_library
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_sopc_sysid_check
Identifier:	NONE
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:	none

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Setting Name:	hal.linker.allow_code_at_reset
Identifier:	ALT_ALLOW_CODE_AT_RESET
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:	If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.

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Setting Name:	hal.linker.enable_alt_load
Identifier:	NONE
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:	This setting is typically false if an external bootloader (e.g. flash bootloader) is present.

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Setting Name:	hal.linker.enable_alt_load_copy_exceptions
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_alt_load_copy_rodata
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_alt_load_copy_rwdata
Identifier:	NONE
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_exception_stack
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:	The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is not used.

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Setting Name:	hal.linker.enable_interrupt_stack
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:	The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is not used.

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Setting Name:	hal.linker.exception_stack_memory_region_name
Identifier:	NONE
Default Value:	none
Value:	onchip_memory
Type:	UnquotedString
Destination:	none
Description:	Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:	Only used if hal.linker.enable_exception_stack is true.

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Setting Name:	hal.linker.exception_stack_size
Identifier:	NONE
Default Value:	1024
Value:	1024
Type:	DecimalNumber
Destination:	none
Description:	Size of the exception stack in bytes.
Restrictions:	Only used if hal.linker.enable_exception_stack is true.

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Setting Name:	hal.linker.interrupt_stack_memory_region_name
Identifier:	NONE
Default Value:	none
Value:	onchip_memory
Type:	UnquotedString
Destination:	none
Description:	Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:	Only used if hal.linker.enable_interrupt_stack is true.

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Setting Name:	hal.linker.interrupt_stack_size
Identifier:	NONE
Default Value:	1024
Value:	1024
Type:	DecimalNumber
Destination:	none
Description:	Size of the interrupt stack in bytes.
Restrictions:	Only used if hal.linker.enable_interrupt_stack is true.

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Setting Name:	hal.log_flags
Identifier:	ALT_LOG_FLAGS
Default Value:	0
Value:	0
Type:	DecimalNumber
Destination:	public_mk_define
Description:	The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:	hal.log_port must be set for this to be used.

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Setting Name:	hal.log_port
Identifier:	NONE
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	public_mk_define
Description:	Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:	none

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Setting Name:	hal.make.ar
Identifier:	AR
Default Value:	nios2-elf-ar
Value:	nios2-elf-ar
Type:	UnquotedString
Destination:	makefile_variable
Description:	Archiver command. Creates library files.
Restrictions:	none

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Setting Name:	hal.make.ar_post_process
Identifier:	AR_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after archiver execution.
Restrictions:	none

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Setting Name:	hal.make.ar_pre_process
Identifier:	AR_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before archiver execution.
Restrictions:	none

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Setting Name:	hal.make.as
Identifier:	AS
Default Value:	nios2-elf-gcc
Value:	nios2-elf-gcc
Type:	UnquotedString
Destination:	makefile_variable
Description:	Assembler command. Note that CC is used for .S files.
Restrictions:	none

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Setting Name:	hal.make.as_post_process
Identifier:	AS_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after each assembly file is compiled.
Restrictions:	none

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Setting Name:	hal.make.as_pre_process
Identifier:	AS_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each assembly file is compiled.
Restrictions:	none

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Setting Name:	hal.make.bsp_arflags
Identifier:	BSP_ARFLAGS
Default Value:	-src
Value:	-src
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_asflags
Identifier:	BSP_ASFLAGS
Default Value:	-Wa,-gdwarf2
Value:	-Wa,-gdwarf2
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_debug
Identifier:	BSP_CFLAGS_DEBUG
Default Value:	-g
Value:	-g
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_defined_symbols
Identifier:	BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_optimization
Identifier:	BSP_CFLAGS_OPTIMIZATION
Default Value:	-O0
Value:	-O0
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_undefined_symbols
Identifier:	BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_user_flags
Identifier:	BSP_CFLAGS_USER_FLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_warnings
Identifier:	BSP_CFLAGS_WARNINGS
Default Value:	-Wall
Value:	-Wall
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cxx_flags
Identifier:	BSP_CXXFLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_inc_dirs
Identifier:	BSP_INC_DIRS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.build_post_process
Identifier:	BUILD_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after BSP built.
Restrictions:	none

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Setting Name:	hal.make.build_pre_process
Identifier:	BUILD_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before BSP built.
Restrictions:	none

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Setting Name:	hal.make.cc
Identifier:	CC
Default Value:	nios2-elf-gcc -xc
Value:	nios2-elf-gcc -xc
Type:	UnquotedString
Destination:	makefile_variable
Description:	C compiler command.
Restrictions:	none

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Setting Name:	hal.make.cc_post_process
Identifier:	CC_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after each .c/.S file is compiled.
Restrictions:	none

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Setting Name:	hal.make.cc_pre_process
Identifier:	CC_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each .c/.S file is compiled.
Restrictions:	none

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Setting Name:	hal.make.cxx
Identifier:	CXX
Default Value:	nios2-elf-gcc -xc++
Value:	nios2-elf-gcc -xc++
Type:	UnquotedString
Destination:	makefile_variable
Description:	C++ compiler command.
Restrictions:	none

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Setting Name:	hal.make.cxx_post_process
Identifier:	CXX_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each C++ file is compiled.
Restrictions:	none

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Setting Name:	hal.make.cxx_pre_process
Identifier:	CXX_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each C++ file is compiled.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.big_endian
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.debug_core_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.fpu_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.hardware_divide_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.hardware_mulx_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.sopc_system_base_address
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.sopc_system_id
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:	none

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Setting Name:	hal.make.rm
Identifier:	RM
Default Value:	rm -f
Value:	rm -f
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command used to remove files during 'clean' target.
Restrictions:	none

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Setting Name:	hal.max_file_descriptors
Identifier:	ALT_MAX_FD
Default Value:	32
Value:	32
Type:	DecimalNumber
Destination:	system_h_define
Description:	Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:	If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.

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Setting Name:	hal.stderr
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:	none

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Setting Name:	hal.stdin
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:	none

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Setting Name:	hal.stdout
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:	none

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Setting Name:	hal.sys_clk_timer
Identifier:	ALT_SYS_CLK
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:	none

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Setting Name:	hal.timestamp_timer
Identifier:	ALT_TIMESTAMP_CLK
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:	none

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BSP Description

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BSP Type:	hal
SOPC Design File:	C:\Users\takayun\Documents\DE2-115\qsys_tutorial\nios_system.sopcinfo
Quartus JDI File:	default
CPU:	nios2_processor
BSP Settings File:	.\settings.bsp
BSP Version:	default
BSP Generated On:	2016/12/02 1:35:13
BSP Generated Timestamp:	1480610113326
BSP Generated Location:	C:\Users\takayun\Documents\DE2-115\qsys_tutorial\software\qsys_tutorial_lcd4_bsp

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Nios II Memory Map

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Slave Descriptor	Address Range	Size	Attributes
jtag_uart	0x00041100 - 0x00041107	8	printable
LEDs	0x000410F0 - 0x000410FF	16
LEDRs	0x000410E0 - 0x000410EF	16
switches	0x000410D0 - 0x000410DF	16
push_switches	0x000410C0 - 0x000410CF	16
hex0	0x000410B0 - 0x000410BF	16
hex1	0x000410A0 - 0x000410AF	16
hex2	0x00041090 - 0x0004109F	16
hex3	0x00041080 - 0x0004108F	16
hex4	0x00041070 - 0x0004107F	16
hex5	0x00041060 - 0x0004106F	16
hex6	0x00041050 - 0x0004105F	16
hex7	0x00041040 - 0x0004104F	16
lcd_16207_0	0x00041030 - 0x0004103F	16	printable
lcd_blon	0x00041020 - 0x0004102F	16
lcd_on	0x00041010 - 0x0004101F	16
onchip_memory	0x00000000 - 0x00031FFF	204800	memory

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Linker Regions

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Region	Address Range	Size	Memory	Offset

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Linker Section Mappings

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Section	Region
.text	onchip_memory
.rodata	onchip_memory
.rwdata	onchip_memory
.bss	onchip_memory
.heap	onchip_memory
.stack	onchip_memory

Settings

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Setting Name:	altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error
Identifier:	ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	public_mk_define
Description:	Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery.
Restrictions:	none

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Setting Name:	altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:	ALTERA_AVALON_JTAG_UART_SMALL
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	public_mk_define
Description:	Small-footprint (polled mode) driver
Restrictions:	none

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Setting Name:	hal.custom_newlib_flags
Identifier:	CUSTOM_NEWLIB_FLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	public_mk_define
Description:	Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:	The custom newlib build will be placed in the <bsp root>/newlib directory, and will be used only for applications that utilize this BSP.

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Setting Name:	hal.enable_c_plus_plus
Identifier:	ALT_NO_C_PLUS_PLUS
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:	none

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Setting Name:	hal.enable_clean_exit
Identifier:	ALT_NO_CLEAN_EXIT
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_exit
Identifier:	ALT_NO_EXIT
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:	none

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Setting Name:	hal.enable_gprof
Identifier:	ALT_PROVIDE_GMON
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_instruction_related_exceptions_api
Identifier:	ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:	false
Value:	false
Type:	BooleanDefineOnly
Destination:	system_h_define
Description:	Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:	These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.

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Setting Name:	hal.enable_lightweight_device_driver_api
Identifier:	ALT_USE_DIRECT_DRIVERS
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:	The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.

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Setting Name:	hal.enable_mul_div_emulation
Identifier:	ALT_NO_INSTRUCTION_EMULATION
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_reduced_device_drivers
Identifier:	ALT_USE_SMALL_DRIVERS
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_runtime_stack_checking
Identifier:	ALT_STACK_CHECK
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_sim_optimize
Identifier:	ALT_SIM_OPTIMIZE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:	When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.

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Setting Name:	hal.enable_small_c_library
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:	none

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Setting Name:	hal.enable_sopc_sysid_check
Identifier:	NONE
Default Value:	1
Value:	1
Type:	Boolean
Destination:	public_mk_define
Description:	Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:	none

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Setting Name:	hal.linker.allow_code_at_reset
Identifier:	ALT_ALLOW_CODE_AT_RESET
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:	If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.

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Setting Name:	hal.linker.enable_alt_load
Identifier:	NONE
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:	This setting is typically false if an external bootloader (e.g. flash bootloader) is present.

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Setting Name:	hal.linker.enable_alt_load_copy_exceptions
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_alt_load_copy_rodata
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_alt_load_copy_rwdata
Identifier:	NONE
Default Value:	0
Value:	1
Type:	Boolean
Destination:	none
Description:	Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:	none

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Setting Name:	hal.linker.enable_exception_stack
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:	The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is not used.

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Setting Name:	hal.linker.enable_interrupt_stack
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	none
Description:	Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:	The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is not used.

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Setting Name:	hal.linker.exception_stack_memory_region_name
Identifier:	NONE
Default Value:	none
Value:	onchip_memory
Type:	UnquotedString
Destination:	none
Description:	Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:	Only used if hal.linker.enable_exception_stack is true.

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Setting Name:	hal.linker.exception_stack_size
Identifier:	NONE
Default Value:	1024
Value:	1024
Type:	DecimalNumber
Destination:	none
Description:	Size of the exception stack in bytes.
Restrictions:	Only used if hal.linker.enable_exception_stack is true.

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Setting Name:	hal.linker.interrupt_stack_memory_region_name
Identifier:	NONE
Default Value:	none
Value:	onchip_memory
Type:	UnquotedString
Destination:	none
Description:	Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:	Only used if hal.linker.enable_interrupt_stack is true.

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Setting Name:	hal.linker.interrupt_stack_size
Identifier:	NONE
Default Value:	1024
Value:	1024
Type:	DecimalNumber
Destination:	none
Description:	Size of the interrupt stack in bytes.
Restrictions:	Only used if hal.linker.enable_interrupt_stack is true.

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Setting Name:	hal.log_flags
Identifier:	ALT_LOG_FLAGS
Default Value:	0
Value:	0
Type:	DecimalNumber
Destination:	public_mk_define
Description:	The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:	hal.log_port must be set for this to be used.

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Setting Name:	hal.log_port
Identifier:	NONE
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	public_mk_define
Description:	Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:	none

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Setting Name:	hal.make.ar
Identifier:	AR
Default Value:	nios2-elf-ar
Value:	nios2-elf-ar
Type:	UnquotedString
Destination:	makefile_variable
Description:	Archiver command. Creates library files.
Restrictions:	none

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Setting Name:	hal.make.ar_post_process
Identifier:	AR_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after archiver execution.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ar_pre_process
Identifier:	AR_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before archiver execution.
Restrictions:	none

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Setting Name:	hal.make.as
Identifier:	AS
Default Value:	nios2-elf-gcc
Value:	nios2-elf-gcc
Type:	UnquotedString
Destination:	makefile_variable
Description:	Assembler command. Note that CC is used for .S files.
Restrictions:	none

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Setting Name:	hal.make.as_post_process
Identifier:	AS_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after each assembly file is compiled.
Restrictions:	none

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Setting Name:	hal.make.as_pre_process
Identifier:	AS_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each assembly file is compiled.
Restrictions:	none

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Setting Name:	hal.make.bsp_arflags
Identifier:	BSP_ARFLAGS
Default Value:	-src
Value:	-src
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_asflags
Identifier:	BSP_ASFLAGS
Default Value:	-Wa,-gdwarf2
Value:	-Wa,-gdwarf2
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_debug
Identifier:	BSP_CFLAGS_DEBUG
Default Value:	-g
Value:	-g
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:	none

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Setting Name:	hal.make.bsp_cflags_defined_symbols
Identifier:	BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.bsp_cflags_optimization
Identifier:	BSP_CFLAGS_OPTIMIZATION
Default Value:	-O0
Value:	-O0
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.bsp_cflags_undefined_symbols
Identifier:	BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.bsp_cflags_user_flags
Identifier:	BSP_CFLAGS_USER_FLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.bsp_cflags_warnings
Identifier:	BSP_CFLAGS_WARNINGS
Default Value:	-Wall
Value:	-Wall
Type:	UnquotedString
Destination:	makefile_variable
Description:	C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.bsp_cxx_flags
Identifier:	BSP_CXXFLAGS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.bsp_inc_dirs
Identifier:	BSP_INC_DIRS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.build_post_process
Identifier:	BUILD_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after BSP built.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.build_pre_process
Identifier:	BUILD_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before BSP built.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cc
Identifier:	CC
Default Value:	nios2-elf-gcc -xc
Value:	nios2-elf-gcc -xc
Type:	UnquotedString
Destination:	makefile_variable
Description:	C compiler command.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cc_post_process
Identifier:	CC_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed after each .c/.S file is compiled.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cc_pre_process
Identifier:	CC_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each .c/.S file is compiled.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cxx
Identifier:	CXX
Default Value:	nios2-elf-gcc -xc++
Value:	nios2-elf-gcc -xc++
Type:	UnquotedString
Destination:	makefile_variable
Description:	C++ compiler command.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cxx_post_process
Identifier:	CXX_POST_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each C++ file is compiled.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.cxx_pre_process
Identifier:	CXX_PRE_PROCESS
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command executed before each C++ file is compiled.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.big_endian
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.debug_core_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.fpu_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.hardware_divide_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:	none

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Setting Name:	hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.hardware_mulx_present
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.sopc_system_base_address
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.sopc_system_id
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:	NONE
Default Value:	0
Value:	0
Type:	Boolean
Destination:	public_mk_define
Description:	Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.make.rm
Identifier:	RM
Default Value:	rm -f
Value:	rm -f
Type:	UnquotedString
Destination:	makefile_variable
Description:	Command used to remove files during 'clean' target.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.max_file_descriptors
Identifier:	ALT_MAX_FD
Default Value:	32
Value:	32
Type:	DecimalNumber
Destination:	system_h_define
Description:	Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:	If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.stderr
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.stdin
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.stdout
Identifier:	NONE
Default Value:	none
Value:	jtag_uart
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.sys_clk_timer
Identifier:	ALT_SYS_CLK
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:	none

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+ + + + + + + + + + + + + + + + + + + + + + + + + +

Setting Name:	hal.timestamp_timer
Identifier:	ALT_TIMESTAMP_CLK
Default Value:	none
Value:	none
Type:	UnquotedString
Destination:	system_h_define
Description:	Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:	none

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